1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/platform_device.h> 9 10 #include "pinctrl-msm.h" 11 12 static const char * const sm6115_tiles[] = { 13 "south", 14 "east", 15 "west" 16 }; 17 18 enum { 19 SOUTH, 20 EAST, 21 WEST 22 }; 23 24 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 25 { \ 26 .grp = PINCTRL_PINGROUP("gpio" #id, \ 27 gpio##id##_pins, \ 28 ARRAY_SIZE(gpio##id##_pins)), \ 29 .funcs = (int[]){ \ 30 msm_mux_gpio, /* gpio mode */ \ 31 msm_mux_##f1, \ 32 msm_mux_##f2, \ 33 msm_mux_##f3, \ 34 msm_mux_##f4, \ 35 msm_mux_##f5, \ 36 msm_mux_##f6, \ 37 msm_mux_##f7, \ 38 msm_mux_##f8, \ 39 msm_mux_##f9 \ 40 }, \ 41 .nfuncs = 10, \ 42 .ctl_reg = 0x1000 * id, \ 43 .io_reg = 0x4 + 0x1000 * id, \ 44 .intr_cfg_reg = 0x8 + 0x1000 * id, \ 45 .intr_status_reg = 0xc + 0x1000 * id, \ 46 .tile = _tile, \ 47 .mux_bit = 2, \ 48 .pull_bit = 0, \ 49 .drv_bit = 6, \ 50 .egpio_enable = 12, \ 51 .egpio_present = 11, \ 52 .oe_bit = 9, \ 53 .in_bit = 0, \ 54 .out_bit = 1, \ 55 .intr_enable_bit = 0, \ 56 .intr_status_bit = 0, \ 57 .intr_target_bit = 5, \ 58 .intr_target_kpss_val = 3, \ 59 .intr_raw_status_bit = 4, \ 60 .intr_polarity_bit = 1, \ 61 .intr_detection_bit = 2, \ 62 .intr_detection_width = 2, \ 63 } 64 65 #define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \ 66 { \ 67 .grp = PINCTRL_PINGROUP(#pg_name, \ 68 pg_name##_pins, \ 69 ARRAY_SIZE(pg_name##_pins)), \ 70 .ctl_reg = ctl, \ 71 .io_reg = 0, \ 72 .intr_cfg_reg = 0, \ 73 .intr_status_reg = 0, \ 74 .tile = _tile, \ 75 .mux_bit = -1, \ 76 .pull_bit = pull, \ 77 .drv_bit = drv, \ 78 .oe_bit = -1, \ 79 .in_bit = -1, \ 80 .out_bit = -1, \ 81 .intr_enable_bit = -1, \ 82 .intr_status_bit = -1, \ 83 .intr_target_bit = -1, \ 84 .intr_raw_status_bit = -1, \ 85 .intr_polarity_bit = -1, \ 86 .intr_detection_bit = -1, \ 87 .intr_detection_width = -1, \ 88 } 89 90 #define UFS_RESET(pg_name, offset) \ 91 { \ 92 .grp = PINCTRL_PINGROUP(#pg_name, \ 93 pg_name##_pins, \ 94 ARRAY_SIZE(pg_name##_pins)), \ 95 .ctl_reg = offset, \ 96 .io_reg = offset + 0x4, \ 97 .intr_cfg_reg = 0, \ 98 .intr_status_reg = 0, \ 99 .tile = WEST, \ 100 .mux_bit = -1, \ 101 .pull_bit = 3, \ 102 .drv_bit = 0, \ 103 .oe_bit = -1, \ 104 .in_bit = -1, \ 105 .out_bit = 0, \ 106 .intr_enable_bit = -1, \ 107 .intr_status_bit = -1, \ 108 .intr_target_bit = -1, \ 109 .intr_raw_status_bit = -1, \ 110 .intr_polarity_bit = -1, \ 111 .intr_detection_bit = -1, \ 112 .intr_detection_width = -1, \ 113 } 114 static const struct pinctrl_pin_desc sm6115_pins[] = { 115 PINCTRL_PIN(0, "GPIO_0"), 116 PINCTRL_PIN(1, "GPIO_1"), 117 PINCTRL_PIN(2, "GPIO_2"), 118 PINCTRL_PIN(3, "GPIO_3"), 119 PINCTRL_PIN(4, "GPIO_4"), 120 PINCTRL_PIN(5, "GPIO_5"), 121 PINCTRL_PIN(6, "GPIO_6"), 122 PINCTRL_PIN(7, "GPIO_7"), 123 PINCTRL_PIN(8, "GPIO_8"), 124 PINCTRL_PIN(9, "GPIO_9"), 125 PINCTRL_PIN(10, "GPIO_10"), 126 PINCTRL_PIN(11, "GPIO_11"), 127 PINCTRL_PIN(12, "GPIO_12"), 128 PINCTRL_PIN(13, "GPIO_13"), 129 PINCTRL_PIN(14, "GPIO_14"), 130 PINCTRL_PIN(15, "GPIO_15"), 131 PINCTRL_PIN(16, "GPIO_16"), 132 PINCTRL_PIN(17, "GPIO_17"), 133 PINCTRL_PIN(18, "GPIO_18"), 134 PINCTRL_PIN(19, "GPIO_19"), 135 PINCTRL_PIN(20, "GPIO_20"), 136 PINCTRL_PIN(21, "GPIO_21"), 137 PINCTRL_PIN(22, "GPIO_22"), 138 PINCTRL_PIN(23, "GPIO_23"), 139 PINCTRL_PIN(24, "GPIO_24"), 140 PINCTRL_PIN(25, "GPIO_25"), 141 PINCTRL_PIN(26, "GPIO_26"), 142 PINCTRL_PIN(27, "GPIO_27"), 143 PINCTRL_PIN(28, "GPIO_28"), 144 PINCTRL_PIN(29, "GPIO_29"), 145 PINCTRL_PIN(30, "GPIO_30"), 146 PINCTRL_PIN(31, "GPIO_31"), 147 PINCTRL_PIN(32, "GPIO_32"), 148 PINCTRL_PIN(33, "GPIO_33"), 149 PINCTRL_PIN(34, "GPIO_34"), 150 PINCTRL_PIN(35, "GPIO_35"), 151 PINCTRL_PIN(36, "GPIO_36"), 152 PINCTRL_PIN(37, "GPIO_37"), 153 PINCTRL_PIN(38, "GPIO_38"), 154 PINCTRL_PIN(39, "GPIO_39"), 155 PINCTRL_PIN(40, "GPIO_40"), 156 PINCTRL_PIN(41, "GPIO_41"), 157 PINCTRL_PIN(42, "GPIO_42"), 158 PINCTRL_PIN(43, "GPIO_43"), 159 PINCTRL_PIN(44, "GPIO_44"), 160 PINCTRL_PIN(45, "GPIO_45"), 161 PINCTRL_PIN(46, "GPIO_46"), 162 PINCTRL_PIN(47, "GPIO_47"), 163 PINCTRL_PIN(48, "GPIO_48"), 164 PINCTRL_PIN(49, "GPIO_49"), 165 PINCTRL_PIN(50, "GPIO_50"), 166 PINCTRL_PIN(51, "GPIO_51"), 167 PINCTRL_PIN(52, "GPIO_52"), 168 PINCTRL_PIN(53, "GPIO_53"), 169 PINCTRL_PIN(54, "GPIO_54"), 170 PINCTRL_PIN(55, "GPIO_55"), 171 PINCTRL_PIN(56, "GPIO_56"), 172 PINCTRL_PIN(57, "GPIO_57"), 173 PINCTRL_PIN(58, "GPIO_58"), 174 PINCTRL_PIN(59, "GPIO_59"), 175 PINCTRL_PIN(60, "GPIO_60"), 176 PINCTRL_PIN(61, "GPIO_61"), 177 PINCTRL_PIN(62, "GPIO_62"), 178 PINCTRL_PIN(63, "GPIO_63"), 179 PINCTRL_PIN(64, "GPIO_64"), 180 PINCTRL_PIN(65, "GPIO_65"), 181 PINCTRL_PIN(66, "GPIO_66"), 182 PINCTRL_PIN(67, "GPIO_67"), 183 PINCTRL_PIN(68, "GPIO_68"), 184 PINCTRL_PIN(69, "GPIO_69"), 185 PINCTRL_PIN(70, "GPIO_70"), 186 PINCTRL_PIN(71, "GPIO_71"), 187 PINCTRL_PIN(72, "GPIO_72"), 188 PINCTRL_PIN(73, "GPIO_73"), 189 PINCTRL_PIN(74, "GPIO_74"), 190 PINCTRL_PIN(75, "GPIO_75"), 191 PINCTRL_PIN(76, "GPIO_76"), 192 PINCTRL_PIN(77, "GPIO_77"), 193 PINCTRL_PIN(78, "GPIO_78"), 194 PINCTRL_PIN(79, "GPIO_79"), 195 PINCTRL_PIN(80, "GPIO_80"), 196 PINCTRL_PIN(81, "GPIO_81"), 197 PINCTRL_PIN(82, "GPIO_82"), 198 PINCTRL_PIN(83, "GPIO_83"), 199 PINCTRL_PIN(84, "GPIO_84"), 200 PINCTRL_PIN(85, "GPIO_85"), 201 PINCTRL_PIN(86, "GPIO_86"), 202 PINCTRL_PIN(87, "GPIO_87"), 203 PINCTRL_PIN(88, "GPIO_88"), 204 PINCTRL_PIN(89, "GPIO_89"), 205 PINCTRL_PIN(90, "GPIO_90"), 206 PINCTRL_PIN(91, "GPIO_91"), 207 PINCTRL_PIN(92, "GPIO_92"), 208 PINCTRL_PIN(93, "GPIO_93"), 209 PINCTRL_PIN(94, "GPIO_94"), 210 PINCTRL_PIN(95, "GPIO_95"), 211 PINCTRL_PIN(96, "GPIO_96"), 212 PINCTRL_PIN(97, "GPIO_97"), 213 PINCTRL_PIN(98, "GPIO_98"), 214 PINCTRL_PIN(99, "GPIO_99"), 215 PINCTRL_PIN(100, "GPIO_100"), 216 PINCTRL_PIN(101, "GPIO_101"), 217 PINCTRL_PIN(102, "GPIO_102"), 218 PINCTRL_PIN(103, "GPIO_103"), 219 PINCTRL_PIN(104, "GPIO_104"), 220 PINCTRL_PIN(105, "GPIO_105"), 221 PINCTRL_PIN(106, "GPIO_106"), 222 PINCTRL_PIN(107, "GPIO_107"), 223 PINCTRL_PIN(108, "GPIO_108"), 224 PINCTRL_PIN(109, "GPIO_109"), 225 PINCTRL_PIN(110, "GPIO_110"), 226 PINCTRL_PIN(111, "GPIO_111"), 227 PINCTRL_PIN(112, "GPIO_112"), 228 PINCTRL_PIN(113, "UFS_RESET"), 229 PINCTRL_PIN(114, "SDC1_RCLK"), 230 PINCTRL_PIN(115, "SDC1_CLK"), 231 PINCTRL_PIN(116, "SDC1_CMD"), 232 PINCTRL_PIN(117, "SDC1_DATA"), 233 PINCTRL_PIN(118, "SDC2_CLK"), 234 PINCTRL_PIN(119, "SDC2_CMD"), 235 PINCTRL_PIN(120, "SDC2_DATA"), 236 }; 237 238 #define DECLARE_MSM_GPIO_PINS(pin) \ 239 static const unsigned int gpio##pin##_pins[] = { pin } 240 DECLARE_MSM_GPIO_PINS(0); 241 DECLARE_MSM_GPIO_PINS(1); 242 DECLARE_MSM_GPIO_PINS(2); 243 DECLARE_MSM_GPIO_PINS(3); 244 DECLARE_MSM_GPIO_PINS(4); 245 DECLARE_MSM_GPIO_PINS(5); 246 DECLARE_MSM_GPIO_PINS(6); 247 DECLARE_MSM_GPIO_PINS(7); 248 DECLARE_MSM_GPIO_PINS(8); 249 DECLARE_MSM_GPIO_PINS(9); 250 DECLARE_MSM_GPIO_PINS(10); 251 DECLARE_MSM_GPIO_PINS(11); 252 DECLARE_MSM_GPIO_PINS(12); 253 DECLARE_MSM_GPIO_PINS(13); 254 DECLARE_MSM_GPIO_PINS(14); 255 DECLARE_MSM_GPIO_PINS(15); 256 DECLARE_MSM_GPIO_PINS(16); 257 DECLARE_MSM_GPIO_PINS(17); 258 DECLARE_MSM_GPIO_PINS(18); 259 DECLARE_MSM_GPIO_PINS(19); 260 DECLARE_MSM_GPIO_PINS(20); 261 DECLARE_MSM_GPIO_PINS(21); 262 DECLARE_MSM_GPIO_PINS(22); 263 DECLARE_MSM_GPIO_PINS(23); 264 DECLARE_MSM_GPIO_PINS(24); 265 DECLARE_MSM_GPIO_PINS(25); 266 DECLARE_MSM_GPIO_PINS(26); 267 DECLARE_MSM_GPIO_PINS(27); 268 DECLARE_MSM_GPIO_PINS(28); 269 DECLARE_MSM_GPIO_PINS(29); 270 DECLARE_MSM_GPIO_PINS(30); 271 DECLARE_MSM_GPIO_PINS(31); 272 DECLARE_MSM_GPIO_PINS(32); 273 DECLARE_MSM_GPIO_PINS(33); 274 DECLARE_MSM_GPIO_PINS(34); 275 DECLARE_MSM_GPIO_PINS(35); 276 DECLARE_MSM_GPIO_PINS(36); 277 DECLARE_MSM_GPIO_PINS(37); 278 DECLARE_MSM_GPIO_PINS(38); 279 DECLARE_MSM_GPIO_PINS(39); 280 DECLARE_MSM_GPIO_PINS(40); 281 DECLARE_MSM_GPIO_PINS(41); 282 DECLARE_MSM_GPIO_PINS(42); 283 DECLARE_MSM_GPIO_PINS(43); 284 DECLARE_MSM_GPIO_PINS(44); 285 DECLARE_MSM_GPIO_PINS(45); 286 DECLARE_MSM_GPIO_PINS(46); 287 DECLARE_MSM_GPIO_PINS(47); 288 DECLARE_MSM_GPIO_PINS(48); 289 DECLARE_MSM_GPIO_PINS(49); 290 DECLARE_MSM_GPIO_PINS(50); 291 DECLARE_MSM_GPIO_PINS(51); 292 DECLARE_MSM_GPIO_PINS(52); 293 DECLARE_MSM_GPIO_PINS(53); 294 DECLARE_MSM_GPIO_PINS(54); 295 DECLARE_MSM_GPIO_PINS(55); 296 DECLARE_MSM_GPIO_PINS(56); 297 DECLARE_MSM_GPIO_PINS(57); 298 DECLARE_MSM_GPIO_PINS(58); 299 DECLARE_MSM_GPIO_PINS(59); 300 DECLARE_MSM_GPIO_PINS(60); 301 DECLARE_MSM_GPIO_PINS(61); 302 DECLARE_MSM_GPIO_PINS(62); 303 DECLARE_MSM_GPIO_PINS(63); 304 DECLARE_MSM_GPIO_PINS(64); 305 DECLARE_MSM_GPIO_PINS(65); 306 DECLARE_MSM_GPIO_PINS(66); 307 DECLARE_MSM_GPIO_PINS(67); 308 DECLARE_MSM_GPIO_PINS(68); 309 DECLARE_MSM_GPIO_PINS(69); 310 DECLARE_MSM_GPIO_PINS(70); 311 DECLARE_MSM_GPIO_PINS(71); 312 DECLARE_MSM_GPIO_PINS(72); 313 DECLARE_MSM_GPIO_PINS(73); 314 DECLARE_MSM_GPIO_PINS(74); 315 DECLARE_MSM_GPIO_PINS(75); 316 DECLARE_MSM_GPIO_PINS(76); 317 DECLARE_MSM_GPIO_PINS(77); 318 DECLARE_MSM_GPIO_PINS(78); 319 DECLARE_MSM_GPIO_PINS(79); 320 DECLARE_MSM_GPIO_PINS(80); 321 DECLARE_MSM_GPIO_PINS(81); 322 DECLARE_MSM_GPIO_PINS(82); 323 DECLARE_MSM_GPIO_PINS(83); 324 DECLARE_MSM_GPIO_PINS(84); 325 DECLARE_MSM_GPIO_PINS(85); 326 DECLARE_MSM_GPIO_PINS(86); 327 DECLARE_MSM_GPIO_PINS(87); 328 DECLARE_MSM_GPIO_PINS(88); 329 DECLARE_MSM_GPIO_PINS(89); 330 DECLARE_MSM_GPIO_PINS(90); 331 DECLARE_MSM_GPIO_PINS(91); 332 DECLARE_MSM_GPIO_PINS(92); 333 DECLARE_MSM_GPIO_PINS(93); 334 DECLARE_MSM_GPIO_PINS(94); 335 DECLARE_MSM_GPIO_PINS(95); 336 DECLARE_MSM_GPIO_PINS(96); 337 DECLARE_MSM_GPIO_PINS(97); 338 DECLARE_MSM_GPIO_PINS(98); 339 DECLARE_MSM_GPIO_PINS(99); 340 DECLARE_MSM_GPIO_PINS(100); 341 DECLARE_MSM_GPIO_PINS(101); 342 DECLARE_MSM_GPIO_PINS(102); 343 DECLARE_MSM_GPIO_PINS(103); 344 DECLARE_MSM_GPIO_PINS(104); 345 DECLARE_MSM_GPIO_PINS(105); 346 DECLARE_MSM_GPIO_PINS(106); 347 DECLARE_MSM_GPIO_PINS(107); 348 DECLARE_MSM_GPIO_PINS(108); 349 DECLARE_MSM_GPIO_PINS(109); 350 DECLARE_MSM_GPIO_PINS(110); 351 DECLARE_MSM_GPIO_PINS(111); 352 DECLARE_MSM_GPIO_PINS(112); 353 354 static const unsigned int ufs_reset_pins[] = { 113 }; 355 static const unsigned int sdc1_rclk_pins[] = { 114 }; 356 static const unsigned int sdc1_clk_pins[] = { 115 }; 357 static const unsigned int sdc1_cmd_pins[] = { 116 }; 358 static const unsigned int sdc1_data_pins[] = { 117 }; 359 static const unsigned int sdc2_clk_pins[] = { 118 }; 360 static const unsigned int sdc2_cmd_pins[] = { 119 }; 361 static const unsigned int sdc2_data_pins[] = { 120 }; 362 363 enum sm6115_functions { 364 msm_mux_adsp_ext, 365 msm_mux_agera_pll, 366 msm_mux_atest, 367 msm_mux_cam_mclk, 368 msm_mux_cci_async, 369 msm_mux_cci_i2c, 370 msm_mux_cci_timer, 371 msm_mux_cri_trng, 372 msm_mux_dac_calib, 373 msm_mux_dbg_out, 374 msm_mux_ddr_bist, 375 msm_mux_ddr_pxi0, 376 msm_mux_ddr_pxi1, 377 msm_mux_ddr_pxi2, 378 msm_mux_ddr_pxi3, 379 msm_mux_egpio, 380 msm_mux_gcc_gp1, 381 msm_mux_gcc_gp2, 382 msm_mux_gcc_gp3, 383 msm_mux_gpio, 384 msm_mux_gp_pdm0, 385 msm_mux_gp_pdm1, 386 msm_mux_gp_pdm2, 387 msm_mux_gsm0_tx, 388 msm_mux_gsm1_tx, 389 msm_mux_jitter_bist, 390 msm_mux_mdp_vsync, 391 msm_mux_mdp_vsync_out_0, 392 msm_mux_mdp_vsync_out_1, 393 msm_mux_mpm_pwr, 394 msm_mux_mss_lte, 395 msm_mux_m_voc, 396 msm_mux_nav_gpio, 397 msm_mux_pa_indicator, 398 msm_mux_pbs, 399 msm_mux_pbs_out, 400 msm_mux_phase_flag, 401 msm_mux_pll_bist, 402 msm_mux_pll_bypassnl, 403 msm_mux_pll_reset, 404 msm_mux_prng_rosc, 405 msm_mux_qdss_cti, 406 msm_mux_qdss_gpio, 407 msm_mux_qup0, 408 msm_mux_qup1, 409 msm_mux_qup2, 410 msm_mux_qup3, 411 msm_mux_qup4, 412 msm_mux_qup5, 413 msm_mux_sdc1_tb, 414 msm_mux_sdc2_tb, 415 msm_mux_sd_write, 416 msm_mux_ssbi_wtr1, 417 msm_mux_tgu, 418 msm_mux_tsense_pwm, 419 msm_mux_uim1_clk, 420 msm_mux_uim1_data, 421 msm_mux_uim1_present, 422 msm_mux_uim1_reset, 423 msm_mux_uim2_clk, 424 msm_mux_uim2_data, 425 msm_mux_uim2_present, 426 msm_mux_uim2_reset, 427 msm_mux_usb_phy, 428 msm_mux_vfr_1, 429 msm_mux_vsense_trigger, 430 msm_mux_wlan1_adc0, 431 msm_mux_wlan1_adc1, 432 msm_mux__, 433 }; 434 435 static const char * const qup0_groups[] = { 436 "gpio0", "gpio1", "gpio2", "gpio3", "gpio82", "gpio86", 437 }; 438 static const char * const gpio_groups[] = { 439 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 440 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 441 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 442 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 443 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 444 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 445 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 446 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 447 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 448 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 449 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 450 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 451 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 452 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 453 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 454 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 455 "gpio111", "gpio112", 456 }; 457 static const char * const egpio_groups[] = { 458 "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", 459 "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", 460 "gpio110", "gpio111", "gpio112", 461 }; 462 static const char * const ddr_bist_groups[] = { 463 "gpio0", "gpio1", "gpio2", "gpio3", 464 }; 465 static const char * const phase_flag_groups[] = { 466 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", 467 "gpio14", "gpio15", "gpio16", "gpio17", "gpio22", "gpio23", "gpio24", 468 "gpio25", "gpio26", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", 469 "gpio35", "gpio36", "gpio43", "gpio44", "gpio45", "gpio63", "gpio64", 470 "gpio102", "gpio103", "gpio104", "gpio105", 471 }; 472 static const char * const qdss_gpio_groups[] = { 473 "gpio0", "gpio1", "gpio2", "gpio3", "gpio8", "gpio9", "gpio10", 474 "gpio11", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", 475 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", 476 "gpio47", "gpio48", "gpio69", "gpio70", "gpio87", "gpio90", "gpio91", 477 "gpio94", "gpio95", "gpio104", "gpio105", "gpio106", "gpio107", 478 "gpio109", "gpio110", 479 }; 480 static const char * const atest_groups[] = { 481 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", 482 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio29", "gpio30", 483 "gpio31", "gpio32", "gpio33", "gpio86", "gpio87", "gpio88", "gpio89", 484 "gpio100", "gpio101", 485 }; 486 static const char * const mpm_pwr_groups[] = { 487 "gpio1", 488 }; 489 static const char * const m_voc_groups[] = { 490 "gpio0", 491 }; 492 static const char * const dac_calib_groups[] = { 493 "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio14", "gpio15", 494 "gpio16", "gpio17", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", 495 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio80", "gpio81", 496 "gpio82", "gpio102", "gpio103", "gpio104", "gpio105" 497 }; 498 static const char * const qup1_groups[] = { 499 "gpio4", "gpio5", "gpio69", "gpio70", 500 }; 501 static const char * const cri_trng_groups[] = { 502 "gpio4", "gpio5", "gpio18", 503 }; 504 static const char * const qup2_groups[] = { 505 "gpio6", "gpio7", "gpio71", "gpio80", 506 }; 507 static const char * const qup3_groups[] = { 508 "gpio8", "gpio9", "gpio10", "gpio11", 509 }; 510 static const char * const pbs_out_groups[] = { 511 "gpio8", "gpio9", "gpio52", 512 }; 513 static const char * const pll_bist_groups[] = { 514 "gpio8", "gpio9", 515 }; 516 static const char * const tsense_pwm_groups[] = { 517 "gpio8", 518 }; 519 static const char * const agera_pll_groups[] = { 520 "gpio10", "gpio11", 521 }; 522 static const char * const pbs_groups[] = { 523 "gpio10", "gpio11", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", 524 "gpio23", "gpio24", "gpio25", "gpio26", "gpio47", "gpio48", "gpio87", 525 "gpio90", "gpio91", 526 }; 527 static const char * const qup4_groups[] = { 528 "gpio12", "gpio13", "gpio96", "gpio97", 529 }; 530 static const char * const tgu_groups[] = { 531 "gpio12", "gpio13", "gpio14", "gpio15", 532 }; 533 static const char * const qup5_groups[] = { 534 "gpio14", "gpio15", "gpio16", "gpio17", 535 }; 536 static const char * const sdc2_tb_groups[] = { 537 "gpio18", 538 }; 539 static const char * const sdc1_tb_groups[] = { 540 "gpio19", 541 }; 542 static const char * const cam_mclk_groups[] = { 543 "gpio20", "gpio21", "gpio27", "gpio28", 544 }; 545 static const char * const adsp_ext_groups[] = { 546 "gpio21", 547 }; 548 static const char * const cci_i2c_groups[] = { 549 "gpio22", "gpio23", "gpio29", "gpio30", 550 }; 551 static const char * const prng_rosc_groups[] = { 552 "gpio22", "gpio23", 553 }; 554 static const char * const cci_timer_groups[] = { 555 "gpio24", "gpio25", "gpio28", "gpio32", 556 }; 557 static const char * const gcc_gp1_groups[] = { 558 "gpio24", "gpio86", 559 }; 560 static const char * const cci_async_groups[] = { 561 "gpio25", 562 }; 563 static const char * const vsense_trigger_groups[] = { 564 "gpio26", 565 }; 566 static const char * const qdss_cti_groups[] = { 567 "gpio27", "gpio28", "gpio72", "gpio73", "gpio96", "gpio97", 568 }; 569 static const char * const gp_pdm0_groups[] = { 570 "gpio31", "gpio95", 571 }; 572 static const char * const gp_pdm1_groups[] = { 573 "gpio32", "gpio96", 574 }; 575 static const char * const gp_pdm2_groups[] = { 576 "gpio33", "gpio97", 577 }; 578 static const char * const nav_gpio_groups[] = { 579 "gpio42", "gpio47", "gpio52", "gpio95", "gpio96", "gpio97", "gpio106", 580 "gpio107", "gpio108", 581 }; 582 static const char * const vfr_1_groups[] = { 583 "gpio48", 584 }; 585 static const char * const pa_indicator_groups[] = { 586 "gpio49", 587 }; 588 static const char * const gsm1_tx_groups[] = { 589 "gpio53", 590 }; 591 static const char * const ssbi_wtr1_groups[] = { 592 "gpio59", "gpio60", 593 }; 594 static const char * const pll_bypassnl_groups[] = { 595 "gpio62", 596 }; 597 static const char * const pll_reset_groups[] = { 598 "gpio63", 599 }; 600 static const char * const ddr_pxi0_groups[] = { 601 "gpio63", "gpio64", 602 }; 603 static const char * const gsm0_tx_groups[] = { 604 "gpio64", 605 }; 606 static const char * const gcc_gp2_groups[] = { 607 "gpio69", "gpio107", 608 }; 609 static const char * const ddr_pxi1_groups[] = { 610 "gpio69", "gpio70", 611 }; 612 static const char * const gcc_gp3_groups[] = { 613 "gpio70", "gpio106", 614 }; 615 static const char * const dbg_out_groups[] = { 616 "gpio71", 617 }; 618 static const char * const uim2_data_groups[] = { 619 "gpio72", 620 }; 621 static const char * const uim2_clk_groups[] = { 622 "gpio73", 623 }; 624 static const char * const uim2_reset_groups[] = { 625 "gpio74", 626 }; 627 static const char * const uim2_present_groups[] = { 628 "gpio75", 629 }; 630 static const char * const uim1_data_groups[] = { 631 "gpio76", 632 }; 633 static const char * const uim1_clk_groups[] = { 634 "gpio77", 635 }; 636 static const char * const uim1_reset_groups[] = { 637 "gpio78", 638 }; 639 static const char * const uim1_present_groups[] = { 640 "gpio79", 641 }; 642 static const char * const mdp_vsync_groups[] = { 643 "gpio81", "gpio96", "gpio97", 644 }; 645 static const char * const mdp_vsync_out_0_groups[] = { 646 "gpio81", 647 }; 648 static const char * const mdp_vsync_out_1_groups[] = { 649 "gpio81", 650 }; 651 static const char * const usb_phy_groups[] = { 652 "gpio89", 653 }; 654 static const char * const mss_lte_groups[] = { 655 "gpio90", "gpio91", 656 }; 657 static const char * const wlan1_adc0_groups[] = { 658 "gpio94", 659 }; 660 static const char * const wlan1_adc1_groups[] = { 661 "gpio95", 662 }; 663 static const char * const sd_write_groups[] = { 664 "gpio96", 665 }; 666 static const char * const jitter_bist_groups[] = { 667 "gpio96", "gpio97", 668 }; 669 static const char * const ddr_pxi2_groups[] = { 670 "gpio102", "gpio103", 671 }; 672 static const char * const ddr_pxi3_groups[] = { 673 "gpio104", "gpio105", 674 }; 675 676 static const struct pinfunction sm6115_functions[] = { 677 MSM_PIN_FUNCTION(adsp_ext), 678 MSM_PIN_FUNCTION(agera_pll), 679 MSM_PIN_FUNCTION(atest), 680 MSM_PIN_FUNCTION(cam_mclk), 681 MSM_PIN_FUNCTION(cci_async), 682 MSM_PIN_FUNCTION(cci_i2c), 683 MSM_PIN_FUNCTION(cci_timer), 684 MSM_PIN_FUNCTION(cri_trng), 685 MSM_PIN_FUNCTION(dac_calib), 686 MSM_PIN_FUNCTION(dbg_out), 687 MSM_PIN_FUNCTION(ddr_bist), 688 MSM_PIN_FUNCTION(ddr_pxi0), 689 MSM_PIN_FUNCTION(ddr_pxi1), 690 MSM_PIN_FUNCTION(ddr_pxi2), 691 MSM_PIN_FUNCTION(ddr_pxi3), 692 MSM_PIN_FUNCTION(egpio), 693 MSM_PIN_FUNCTION(gcc_gp1), 694 MSM_PIN_FUNCTION(gcc_gp2), 695 MSM_PIN_FUNCTION(gcc_gp3), 696 MSM_GPIO_PIN_FUNCTION(gpio), 697 MSM_PIN_FUNCTION(gp_pdm0), 698 MSM_PIN_FUNCTION(gp_pdm1), 699 MSM_PIN_FUNCTION(gp_pdm2), 700 MSM_PIN_FUNCTION(gsm0_tx), 701 MSM_PIN_FUNCTION(gsm1_tx), 702 MSM_PIN_FUNCTION(jitter_bist), 703 MSM_PIN_FUNCTION(mdp_vsync), 704 MSM_PIN_FUNCTION(mdp_vsync_out_0), 705 MSM_PIN_FUNCTION(mdp_vsync_out_1), 706 MSM_PIN_FUNCTION(mpm_pwr), 707 MSM_PIN_FUNCTION(mss_lte), 708 MSM_PIN_FUNCTION(m_voc), 709 MSM_PIN_FUNCTION(nav_gpio), 710 MSM_PIN_FUNCTION(pa_indicator), 711 MSM_PIN_FUNCTION(pbs), 712 MSM_PIN_FUNCTION(pbs_out), 713 MSM_PIN_FUNCTION(phase_flag), 714 MSM_PIN_FUNCTION(pll_bist), 715 MSM_PIN_FUNCTION(pll_bypassnl), 716 MSM_PIN_FUNCTION(pll_reset), 717 MSM_PIN_FUNCTION(prng_rosc), 718 MSM_PIN_FUNCTION(qdss_cti), 719 MSM_PIN_FUNCTION(qdss_gpio), 720 MSM_PIN_FUNCTION(qup0), 721 MSM_PIN_FUNCTION(qup1), 722 MSM_PIN_FUNCTION(qup2), 723 MSM_PIN_FUNCTION(qup3), 724 MSM_PIN_FUNCTION(qup4), 725 MSM_PIN_FUNCTION(qup5), 726 MSM_PIN_FUNCTION(sdc1_tb), 727 MSM_PIN_FUNCTION(sdc2_tb), 728 MSM_PIN_FUNCTION(sd_write), 729 MSM_PIN_FUNCTION(ssbi_wtr1), 730 MSM_PIN_FUNCTION(tgu), 731 MSM_PIN_FUNCTION(tsense_pwm), 732 MSM_PIN_FUNCTION(uim1_clk), 733 MSM_PIN_FUNCTION(uim1_data), 734 MSM_PIN_FUNCTION(uim1_present), 735 MSM_PIN_FUNCTION(uim1_reset), 736 MSM_PIN_FUNCTION(uim2_clk), 737 MSM_PIN_FUNCTION(uim2_data), 738 MSM_PIN_FUNCTION(uim2_present), 739 MSM_PIN_FUNCTION(uim2_reset), 740 MSM_PIN_FUNCTION(usb_phy), 741 MSM_PIN_FUNCTION(vfr_1), 742 MSM_PIN_FUNCTION(vsense_trigger), 743 MSM_PIN_FUNCTION(wlan1_adc0), 744 MSM_PIN_FUNCTION(wlan1_adc1), 745 }; 746 747 /* Every pin is maintained as a single group, and missing or non-existing pin 748 * would be maintained as dummy group to synchronize pin group index with 749 * pin descriptor registered with pinctrl core. 750 * Clients would not be able to request these dummy pin groups. 751 */ 752 static const struct msm_pingroup sm6115_groups[] = { 753 [0] = PINGROUP(0, WEST, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _), 754 [1] = PINGROUP(1, WEST, qup0, mpm_pwr, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _), 755 [2] = PINGROUP(2, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _), 756 [3] = PINGROUP(3, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _), 757 [4] = PINGROUP(4, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _), 758 [5] = PINGROUP(5, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _), 759 [6] = PINGROUP(6, WEST, qup2, _, phase_flag, dac_calib, atest, _, _, _, _), 760 [7] = PINGROUP(7, WEST, qup2, _, _, _, _, _, _, _, _), 761 [8] = PINGROUP(8, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, tsense_pwm, _, _), 762 [9] = PINGROUP(9, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, _, _, _), 763 [10] = PINGROUP(10, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _), 764 [11] = PINGROUP(11, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _), 765 [12] = PINGROUP(12, WEST, qup4, tgu, _, _, _, _, _, _, _), 766 [13] = PINGROUP(13, WEST, qup4, tgu, _, _, _, _, _, _, _), 767 [14] = PINGROUP(14, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _), 768 [15] = PINGROUP(15, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _), 769 [16] = PINGROUP(16, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _), 770 [17] = PINGROUP(17, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _), 771 [18] = PINGROUP(18, EAST, sdc2_tb, cri_trng, pbs, qdss_gpio, _, _, _, _, _), 772 [19] = PINGROUP(19, EAST, sdc1_tb, pbs, qdss_gpio, _, _, _, _, _, _), 773 [20] = PINGROUP(20, EAST, cam_mclk, pbs, qdss_gpio, _, _, _, _, _, _), 774 [21] = PINGROUP(21, EAST, cam_mclk, adsp_ext, pbs, qdss_gpio, _, _, _, _, _), 775 [22] = PINGROUP(22, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), 776 [23] = PINGROUP(23, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), 777 [24] = PINGROUP(24, EAST, cci_timer, gcc_gp1, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), 778 [25] = PINGROUP(25, EAST, cci_async, cci_timer, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), 779 [26] = PINGROUP(26, EAST, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, vsense_trigger, _, _), 780 [27] = PINGROUP(27, EAST, cam_mclk, qdss_cti, _, _, _, _, _, _, _), 781 [28] = PINGROUP(28, EAST, cam_mclk, cci_timer, qdss_cti, _, _, _, _, _, _), 782 [29] = PINGROUP(29, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _), 783 [30] = PINGROUP(30, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _), 784 [31] = PINGROUP(31, EAST, gp_pdm0, _, phase_flag, dac_calib, atest, _, _, _, _), 785 [32] = PINGROUP(32, EAST, cci_timer, gp_pdm1, _, phase_flag, dac_calib, atest, _, _, _), 786 [33] = PINGROUP(33, EAST, gp_pdm2, _, phase_flag, dac_calib, atest, _, _, _, _), 787 [34] = PINGROUP(34, EAST, _, _, _, _, _, _, _, _, _), 788 [35] = PINGROUP(35, EAST, _, phase_flag, _, _, _, _, _, _, _), 789 [36] = PINGROUP(36, EAST, _, phase_flag, _, _, _, _, _, _, _), 790 [37] = PINGROUP(37, EAST, _, _, _, _, _, _, _, _, _), 791 [38] = PINGROUP(38, EAST, _, _, _, _, _, _, _, _, _), 792 [39] = PINGROUP(39, EAST, _, _, _, _, _, _, _, _, _), 793 [40] = PINGROUP(40, EAST, _, _, _, _, _, _, _, _, _), 794 [41] = PINGROUP(41, EAST, _, _, _, _, _, _, _, _, _), 795 [42] = PINGROUP(42, EAST, _, nav_gpio, _, _, _, _, _, _, _), 796 [43] = PINGROUP(43, EAST, _, _, phase_flag, _, _, _, _, _, _), 797 [44] = PINGROUP(44, EAST, _, _, phase_flag, _, _, _, _, _, _), 798 [45] = PINGROUP(45, EAST, _, _, phase_flag, _, _, _, _, _, _), 799 [46] = PINGROUP(46, EAST, _, _, _, _, _, _, _, _, _), 800 [47] = PINGROUP(47, EAST, _, nav_gpio, pbs, qdss_gpio, _, _, _, _, _), 801 [48] = PINGROUP(48, EAST, _, vfr_1, _, pbs, qdss_gpio, _, _, _, _), 802 [49] = PINGROUP(49, EAST, _, pa_indicator, _, _, _, _, _, _, _), 803 [50] = PINGROUP(50, EAST, _, _, _, _, _, _, _, _, _), 804 [51] = PINGROUP(51, EAST, _, _, _, _, _, _, _, _, _), 805 [52] = PINGROUP(52, EAST, _, nav_gpio, pbs_out, _, _, _, _, _, _), 806 [53] = PINGROUP(53, EAST, _, gsm1_tx, _, _, _, _, _, _, _), 807 [54] = PINGROUP(54, EAST, _, _, _, _, _, _, _, _, _), 808 [55] = PINGROUP(55, EAST, _, _, _, _, _, _, _, _, _), 809 [56] = PINGROUP(56, EAST, _, _, _, _, _, _, _, _, _), 810 [57] = PINGROUP(57, EAST, _, _, _, _, _, _, _, _, _), 811 [58] = PINGROUP(58, EAST, _, _, _, _, _, _, _, _, _), 812 [59] = PINGROUP(59, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _), 813 [60] = PINGROUP(60, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _), 814 [61] = PINGROUP(61, EAST, _, _, _, _, _, _, _, _, _), 815 [62] = PINGROUP(62, EAST, _, pll_bypassnl, _, _, _, _, _, _, _), 816 [63] = PINGROUP(63, EAST, pll_reset, _, phase_flag, ddr_pxi0, _, _, _, _, _), 817 [64] = PINGROUP(64, EAST, gsm0_tx, _, phase_flag, ddr_pxi0, _, _, _, _, _), 818 [65] = PINGROUP(65, WEST, _, _, _, _, _, _, _, _, _), 819 [66] = PINGROUP(66, WEST, _, _, _, _, _, _, _, _, _), 820 [67] = PINGROUP(67, WEST, _, _, _, _, _, _, _, _, _), 821 [68] = PINGROUP(68, WEST, _, _, _, _, _, _, _, _, _), 822 [69] = PINGROUP(69, WEST, qup1, gcc_gp2, qdss_gpio, ddr_pxi1, _, _, _, _, _), 823 [70] = PINGROUP(70, WEST, qup1, gcc_gp3, qdss_gpio, ddr_pxi1, _, _, _, _, _), 824 [71] = PINGROUP(71, WEST, qup2, dbg_out, _, _, _, _, _, _, _), 825 [72] = PINGROUP(72, SOUTH, uim2_data, qdss_cti, _, _, _, _, _, _, _), 826 [73] = PINGROUP(73, SOUTH, uim2_clk, _, qdss_cti, _, _, _, _, _, _), 827 [74] = PINGROUP(74, SOUTH, uim2_reset, _, _, _, _, _, _, _, _), 828 [75] = PINGROUP(75, SOUTH, uim2_present, _, _, _, _, _, _, _, _), 829 [76] = PINGROUP(76, SOUTH, uim1_data, _, _, _, _, _, _, _, _), 830 [77] = PINGROUP(77, SOUTH, uim1_clk, _, _, _, _, _, _, _, _), 831 [78] = PINGROUP(78, SOUTH, uim1_reset, _, _, _, _, _, _, _, _), 832 [79] = PINGROUP(79, SOUTH, uim1_present, _, _, _, _, _, _, _, _), 833 [80] = PINGROUP(80, WEST, qup2, dac_calib, _, _, _, _, _, _, _), 834 [81] = PINGROUP(81, WEST, mdp_vsync_out_0, mdp_vsync_out_1, mdp_vsync, dac_calib, _, _, _, _, _), 835 [82] = PINGROUP(82, WEST, qup0, dac_calib, _, _, _, _, _, _, _), 836 [83] = PINGROUP(83, WEST, _, _, _, _, _, _, _, _, _), 837 [84] = PINGROUP(84, WEST, _, _, _, _, _, _, _, _, _), 838 [85] = PINGROUP(85, WEST, _, _, _, _, _, _, _, _, _), 839 [86] = PINGROUP(86, WEST, qup0, gcc_gp1, atest, _, _, _, _, _, _), 840 [87] = PINGROUP(87, EAST, pbs, qdss_gpio, _, _, _, _, _, _, _), 841 [88] = PINGROUP(88, EAST, _, _, _, _, _, _, _, _, _), 842 [89] = PINGROUP(89, WEST, usb_phy, atest, _, _, _, _, _, _, _), 843 [90] = PINGROUP(90, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _), 844 [91] = PINGROUP(91, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _), 845 [92] = PINGROUP(92, WEST, _, _, _, _, _, _, _, _, _), 846 [93] = PINGROUP(93, WEST, _, _, _, _, _, _, _, _, _), 847 [94] = PINGROUP(94, WEST, _, qdss_gpio, wlan1_adc0, _, _, _, _, _, _), 848 [95] = PINGROUP(95, WEST, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _), 849 [96] = PINGROUP(96, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _), 850 [97] = PINGROUP(97, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _), 851 [98] = PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, egpio), 852 [99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, egpio), 853 [100] = PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, egpio), 854 [101] = PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, egpio), 855 [102] = PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, egpio), 856 [103] = PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, egpio), 857 [104] = PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, egpio), 858 [105] = PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, egpio), 859 [106] = PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, egpio), 860 [107] = PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, egpio), 861 [108] = PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, egpio), 862 [109] = PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, egpio), 863 [110] = PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, egpio), 864 [111] = PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, egpio), 865 [112] = PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, egpio), 866 [113] = UFS_RESET(ufs_reset, 0x78000), 867 [114] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0), 868 [115] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6), 869 [116] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x75000, 11, 3), 870 [117] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x75000, 9, 0), 871 [118] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x73000, 14, 6), 872 [119] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x73000, 11, 3), 873 [120] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x73000, 9, 0), 874 }; 875 876 static const struct msm_gpio_wakeirq_map sm6115_mpm_map[] = { 877 { 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 }, { 13, 18 }, 878 { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 }, { 25, 71 }, { 27, 73 }, 879 { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 }, { 34, 56 }, { 35, 57 }, { 36, 58 }, 880 { 39, 28 }, { 46, 29 }, { 62, 60 }, { 63, 61 }, { 64, 62 }, { 65, 30 }, { 66, 31 }, 881 { 67, 32 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 }, { 79, 36 }, { 80, 21 }, 882 { 81, 38 }, { 83, 9 }, { 84, 39 }, { 85, 40 }, { 86, 19 }, { 87, 42 }, { 88, 43 }, 883 { 89, 45 }, { 91, 74 }, { 93, 46 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 }, 884 }; 885 886 static const struct msm_pinctrl_soc_data sm6115_tlmm = { 887 .pins = sm6115_pins, 888 .npins = ARRAY_SIZE(sm6115_pins), 889 .functions = sm6115_functions, 890 .nfunctions = ARRAY_SIZE(sm6115_functions), 891 .groups = sm6115_groups, 892 .ngroups = ARRAY_SIZE(sm6115_groups), 893 .ngpios = 114, 894 .tiles = sm6115_tiles, 895 .ntiles = ARRAY_SIZE(sm6115_tiles), 896 .wakeirq_map = sm6115_mpm_map, 897 .nwakeirq_map = ARRAY_SIZE(sm6115_mpm_map), 898 .egpio_func = 9, 899 }; 900 901 static int sm6115_tlmm_probe(struct platform_device *pdev) 902 { 903 return msm_pinctrl_probe(pdev, &sm6115_tlmm); 904 } 905 906 static const struct of_device_id sm6115_tlmm_of_match[] = { 907 { .compatible = "qcom,sm6115-tlmm", }, 908 { } 909 }; 910 MODULE_DEVICE_TABLE(of, sm6115_tlmm_of_match); 911 912 static struct platform_driver sm6115_tlmm_driver = { 913 .driver = { 914 .name = "sm6115-tlmm", 915 .of_match_table = sm6115_tlmm_of_match, 916 }, 917 .probe = sm6115_tlmm_probe, 918 }; 919 920 static int __init sm6115_tlmm_init(void) 921 { 922 return platform_driver_register(&sm6115_tlmm_driver); 923 } 924 arch_initcall(sm6115_tlmm_init); 925 926 static void __exit sm6115_tlmm_exit(void) 927 { 928 platform_driver_unregister(&sm6115_tlmm_driver); 929 } 930 module_exit(sm6115_tlmm_exit); 931 932 MODULE_DESCRIPTION("QTI sm6115 tlmm driver"); 933 MODULE_LICENSE("GPL v2"); 934