1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/platform_device.h> 9 10 #include "pinctrl-msm.h" 11 12 #define REG_SIZE 0x1000 13 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ 14 { \ 15 .grp = PINCTRL_PINGROUP("gpio" #id, \ 16 gpio##id##_pins, \ 17 ARRAY_SIZE(gpio##id##_pins)), \ 18 .funcs = (int[]){ \ 19 msm_mux_gpio, /* gpio mode */ \ 20 msm_mux_##f1, \ 21 msm_mux_##f2, \ 22 msm_mux_##f3, \ 23 msm_mux_##f4, \ 24 msm_mux_##f5, \ 25 msm_mux_##f6, \ 26 msm_mux_##f7, \ 27 msm_mux_##f8, \ 28 msm_mux_##f9, \ 29 msm_mux_##f10, \ 30 msm_mux_##f11 \ 31 }, \ 32 .nfuncs = 12, \ 33 .ctl_reg = REG_SIZE * id, \ 34 .io_reg = 0x4 + REG_SIZE * id, \ 35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 36 .intr_status_reg = 0xc + REG_SIZE * id, \ 37 .mux_bit = 2, \ 38 .pull_bit = 0, \ 39 .drv_bit = 6, \ 40 .oe_bit = 9, \ 41 .in_bit = 0, \ 42 .out_bit = 1, \ 43 .intr_enable_bit = 0, \ 44 .intr_status_bit = 0, \ 45 .intr_wakeup_enable_bit = 7, \ 46 .intr_wakeup_present_bit = 6, \ 47 .intr_target_bit = 8, \ 48 .intr_target_kpss_val = 3, \ 49 .intr_raw_status_bit = 4, \ 50 .intr_polarity_bit = 1, \ 51 .intr_detection_bit = 2, \ 52 .intr_detection_width = 2, \ 53 } 54 55 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 56 { \ 57 .grp = PINCTRL_PINGROUP(#pg_name, \ 58 pg_name##_pins, \ 59 ARRAY_SIZE(pg_name##_pins)), \ 60 .ctl_reg = ctl, \ 61 .io_reg = 0, \ 62 .intr_cfg_reg = 0, \ 63 .intr_status_reg = 0, \ 64 .mux_bit = -1, \ 65 .pull_bit = pull, \ 66 .drv_bit = drv, \ 67 .oe_bit = -1, \ 68 .in_bit = -1, \ 69 .out_bit = -1, \ 70 .intr_enable_bit = -1, \ 71 .intr_status_bit = -1, \ 72 .intr_target_bit = -1, \ 73 .intr_raw_status_bit = -1, \ 74 .intr_polarity_bit = -1, \ 75 .intr_detection_bit = -1, \ 76 .intr_detection_width = -1, \ 77 } 78 79 static const struct pinctrl_pin_desc shikra_pins[] = { 80 PINCTRL_PIN(0, "GPIO_0"), 81 PINCTRL_PIN(1, "GPIO_1"), 82 PINCTRL_PIN(2, "GPIO_2"), 83 PINCTRL_PIN(3, "GPIO_3"), 84 PINCTRL_PIN(4, "GPIO_4"), 85 PINCTRL_PIN(5, "GPIO_5"), 86 PINCTRL_PIN(6, "GPIO_6"), 87 PINCTRL_PIN(7, "GPIO_7"), 88 PINCTRL_PIN(8, "GPIO_8"), 89 PINCTRL_PIN(9, "GPIO_9"), 90 PINCTRL_PIN(10, "GPIO_10"), 91 PINCTRL_PIN(11, "GPIO_11"), 92 PINCTRL_PIN(12, "GPIO_12"), 93 PINCTRL_PIN(13, "GPIO_13"), 94 PINCTRL_PIN(14, "GPIO_14"), 95 PINCTRL_PIN(15, "GPIO_15"), 96 PINCTRL_PIN(16, "GPIO_16"), 97 PINCTRL_PIN(17, "GPIO_17"), 98 PINCTRL_PIN(18, "GPIO_18"), 99 PINCTRL_PIN(19, "GPIO_19"), 100 PINCTRL_PIN(20, "GPIO_20"), 101 PINCTRL_PIN(21, "GPIO_21"), 102 PINCTRL_PIN(22, "GPIO_22"), 103 PINCTRL_PIN(23, "GPIO_23"), 104 PINCTRL_PIN(24, "GPIO_24"), 105 PINCTRL_PIN(25, "GPIO_25"), 106 PINCTRL_PIN(26, "GPIO_26"), 107 PINCTRL_PIN(27, "GPIO_27"), 108 PINCTRL_PIN(28, "GPIO_28"), 109 PINCTRL_PIN(29, "GPIO_29"), 110 PINCTRL_PIN(30, "GPIO_30"), 111 PINCTRL_PIN(31, "GPIO_31"), 112 PINCTRL_PIN(32, "GPIO_32"), 113 PINCTRL_PIN(33, "GPIO_33"), 114 PINCTRL_PIN(34, "GPIO_34"), 115 PINCTRL_PIN(35, "GPIO_35"), 116 PINCTRL_PIN(36, "GPIO_36"), 117 PINCTRL_PIN(37, "GPIO_37"), 118 PINCTRL_PIN(38, "GPIO_38"), 119 PINCTRL_PIN(39, "GPIO_39"), 120 PINCTRL_PIN(40, "GPIO_40"), 121 PINCTRL_PIN(41, "GPIO_41"), 122 PINCTRL_PIN(42, "GPIO_42"), 123 PINCTRL_PIN(43, "GPIO_43"), 124 PINCTRL_PIN(44, "GPIO_44"), 125 PINCTRL_PIN(45, "GPIO_45"), 126 PINCTRL_PIN(46, "GPIO_46"), 127 PINCTRL_PIN(47, "GPIO_47"), 128 PINCTRL_PIN(48, "GPIO_48"), 129 PINCTRL_PIN(49, "GPIO_49"), 130 PINCTRL_PIN(50, "GPIO_50"), 131 PINCTRL_PIN(51, "GPIO_51"), 132 PINCTRL_PIN(52, "GPIO_52"), 133 PINCTRL_PIN(53, "GPIO_53"), 134 PINCTRL_PIN(54, "GPIO_54"), 135 PINCTRL_PIN(55, "GPIO_55"), 136 PINCTRL_PIN(56, "GPIO_56"), 137 PINCTRL_PIN(57, "GPIO_57"), 138 PINCTRL_PIN(58, "GPIO_58"), 139 PINCTRL_PIN(59, "GPIO_59"), 140 PINCTRL_PIN(60, "GPIO_60"), 141 PINCTRL_PIN(61, "GPIO_61"), 142 PINCTRL_PIN(62, "GPIO_62"), 143 PINCTRL_PIN(63, "GPIO_63"), 144 PINCTRL_PIN(64, "GPIO_64"), 145 PINCTRL_PIN(65, "GPIO_65"), 146 PINCTRL_PIN(66, "GPIO_66"), 147 PINCTRL_PIN(67, "GPIO_67"), 148 PINCTRL_PIN(68, "GPIO_68"), 149 PINCTRL_PIN(69, "GPIO_69"), 150 PINCTRL_PIN(70, "GPIO_70"), 151 PINCTRL_PIN(71, "GPIO_71"), 152 PINCTRL_PIN(72, "GPIO_72"), 153 PINCTRL_PIN(73, "GPIO_73"), 154 PINCTRL_PIN(74, "GPIO_74"), 155 PINCTRL_PIN(75, "GPIO_75"), 156 PINCTRL_PIN(76, "GPIO_76"), 157 PINCTRL_PIN(77, "GPIO_77"), 158 PINCTRL_PIN(78, "GPIO_78"), 159 PINCTRL_PIN(79, "GPIO_79"), 160 PINCTRL_PIN(80, "GPIO_80"), 161 PINCTRL_PIN(81, "GPIO_81"), 162 PINCTRL_PIN(82, "GPIO_82"), 163 PINCTRL_PIN(83, "GPIO_83"), 164 PINCTRL_PIN(84, "GPIO_84"), 165 PINCTRL_PIN(85, "GPIO_85"), 166 PINCTRL_PIN(86, "GPIO_86"), 167 PINCTRL_PIN(87, "GPIO_87"), 168 PINCTRL_PIN(88, "GPIO_88"), 169 PINCTRL_PIN(89, "GPIO_89"), 170 PINCTRL_PIN(90, "GPIO_90"), 171 PINCTRL_PIN(91, "GPIO_91"), 172 PINCTRL_PIN(92, "GPIO_92"), 173 PINCTRL_PIN(93, "GPIO_93"), 174 PINCTRL_PIN(94, "GPIO_94"), 175 PINCTRL_PIN(95, "GPIO_95"), 176 PINCTRL_PIN(96, "GPIO_96"), 177 PINCTRL_PIN(97, "GPIO_97"), 178 PINCTRL_PIN(98, "GPIO_98"), 179 PINCTRL_PIN(99, "GPIO_99"), 180 PINCTRL_PIN(100, "GPIO_100"), 181 PINCTRL_PIN(101, "GPIO_101"), 182 PINCTRL_PIN(102, "GPIO_102"), 183 PINCTRL_PIN(103, "GPIO_103"), 184 PINCTRL_PIN(104, "GPIO_104"), 185 PINCTRL_PIN(105, "GPIO_105"), 186 PINCTRL_PIN(106, "GPIO_106"), 187 PINCTRL_PIN(107, "GPIO_107"), 188 PINCTRL_PIN(108, "GPIO_108"), 189 PINCTRL_PIN(109, "GPIO_109"), 190 PINCTRL_PIN(110, "GPIO_110"), 191 PINCTRL_PIN(111, "GPIO_111"), 192 PINCTRL_PIN(112, "GPIO_112"), 193 PINCTRL_PIN(113, "GPIO_113"), 194 PINCTRL_PIN(114, "GPIO_114"), 195 PINCTRL_PIN(115, "GPIO_115"), 196 PINCTRL_PIN(116, "GPIO_116"), 197 PINCTRL_PIN(117, "GPIO_117"), 198 PINCTRL_PIN(118, "GPIO_118"), 199 PINCTRL_PIN(119, "GPIO_119"), 200 PINCTRL_PIN(120, "GPIO_120"), 201 PINCTRL_PIN(121, "GPIO_121"), 202 PINCTRL_PIN(122, "GPIO_122"), 203 PINCTRL_PIN(123, "GPIO_123"), 204 PINCTRL_PIN(124, "GPIO_124"), 205 PINCTRL_PIN(125, "GPIO_125"), 206 PINCTRL_PIN(126, "GPIO_126"), 207 PINCTRL_PIN(127, "GPIO_127"), 208 PINCTRL_PIN(128, "GPIO_128"), 209 PINCTRL_PIN(129, "GPIO_129"), 210 PINCTRL_PIN(130, "GPIO_130"), 211 PINCTRL_PIN(131, "GPIO_131"), 212 PINCTRL_PIN(132, "GPIO_132"), 213 PINCTRL_PIN(133, "GPIO_133"), 214 PINCTRL_PIN(134, "GPIO_134"), 215 PINCTRL_PIN(135, "GPIO_135"), 216 PINCTRL_PIN(136, "GPIO_136"), 217 PINCTRL_PIN(137, "GPIO_137"), 218 PINCTRL_PIN(138, "GPIO_138"), 219 PINCTRL_PIN(139, "GPIO_139"), 220 PINCTRL_PIN(140, "GPIO_140"), 221 PINCTRL_PIN(141, "GPIO_141"), 222 PINCTRL_PIN(142, "GPIO_142"), 223 PINCTRL_PIN(143, "GPIO_143"), 224 PINCTRL_PIN(144, "GPIO_144"), 225 PINCTRL_PIN(145, "GPIO_145"), 226 PINCTRL_PIN(146, "GPIO_146"), 227 PINCTRL_PIN(147, "GPIO_147"), 228 PINCTRL_PIN(148, "GPIO_148"), 229 PINCTRL_PIN(149, "GPIO_149"), 230 PINCTRL_PIN(150, "GPIO_150"), 231 PINCTRL_PIN(151, "GPIO_151"), 232 PINCTRL_PIN(152, "GPIO_152"), 233 PINCTRL_PIN(153, "GPIO_153"), 234 PINCTRL_PIN(154, "GPIO_154"), 235 PINCTRL_PIN(155, "GPIO_155"), 236 PINCTRL_PIN(156, "GPIO_156"), 237 PINCTRL_PIN(157, "GPIO_157"), 238 PINCTRL_PIN(158, "GPIO_158"), 239 PINCTRL_PIN(159, "GPIO_159"), 240 PINCTRL_PIN(160, "GPIO_160"), 241 PINCTRL_PIN(161, "GPIO_161"), 242 PINCTRL_PIN(162, "GPIO_162"), 243 PINCTRL_PIN(163, "GPIO_163"), 244 PINCTRL_PIN(164, "GPIO_164"), 245 PINCTRL_PIN(165, "GPIO_165"), 246 PINCTRL_PIN(166, "SDC1_RCLK"), 247 PINCTRL_PIN(167, "SDC1_CLK"), 248 PINCTRL_PIN(168, "SDC1_CMD"), 249 PINCTRL_PIN(169, "SDC1_DATA"), 250 PINCTRL_PIN(170, "SDC2_CLK"), 251 PINCTRL_PIN(171, "SDC2_CMD"), 252 PINCTRL_PIN(172, "SDC2_DATA"), 253 }; 254 255 #define DECLARE_MSM_GPIO_PINS(pin) \ 256 static const unsigned int gpio##pin##_pins[] = { pin } 257 DECLARE_MSM_GPIO_PINS(0); 258 DECLARE_MSM_GPIO_PINS(1); 259 DECLARE_MSM_GPIO_PINS(2); 260 DECLARE_MSM_GPIO_PINS(3); 261 DECLARE_MSM_GPIO_PINS(4); 262 DECLARE_MSM_GPIO_PINS(5); 263 DECLARE_MSM_GPIO_PINS(6); 264 DECLARE_MSM_GPIO_PINS(7); 265 DECLARE_MSM_GPIO_PINS(8); 266 DECLARE_MSM_GPIO_PINS(9); 267 DECLARE_MSM_GPIO_PINS(10); 268 DECLARE_MSM_GPIO_PINS(11); 269 DECLARE_MSM_GPIO_PINS(12); 270 DECLARE_MSM_GPIO_PINS(13); 271 DECLARE_MSM_GPIO_PINS(14); 272 DECLARE_MSM_GPIO_PINS(15); 273 DECLARE_MSM_GPIO_PINS(16); 274 DECLARE_MSM_GPIO_PINS(17); 275 DECLARE_MSM_GPIO_PINS(18); 276 DECLARE_MSM_GPIO_PINS(19); 277 DECLARE_MSM_GPIO_PINS(20); 278 DECLARE_MSM_GPIO_PINS(21); 279 DECLARE_MSM_GPIO_PINS(22); 280 DECLARE_MSM_GPIO_PINS(23); 281 DECLARE_MSM_GPIO_PINS(24); 282 DECLARE_MSM_GPIO_PINS(25); 283 DECLARE_MSM_GPIO_PINS(26); 284 DECLARE_MSM_GPIO_PINS(27); 285 DECLARE_MSM_GPIO_PINS(28); 286 DECLARE_MSM_GPIO_PINS(29); 287 DECLARE_MSM_GPIO_PINS(30); 288 DECLARE_MSM_GPIO_PINS(31); 289 DECLARE_MSM_GPIO_PINS(32); 290 DECLARE_MSM_GPIO_PINS(33); 291 DECLARE_MSM_GPIO_PINS(34); 292 DECLARE_MSM_GPIO_PINS(35); 293 DECLARE_MSM_GPIO_PINS(36); 294 DECLARE_MSM_GPIO_PINS(37); 295 DECLARE_MSM_GPIO_PINS(38); 296 DECLARE_MSM_GPIO_PINS(39); 297 DECLARE_MSM_GPIO_PINS(40); 298 DECLARE_MSM_GPIO_PINS(41); 299 DECLARE_MSM_GPIO_PINS(42); 300 DECLARE_MSM_GPIO_PINS(43); 301 DECLARE_MSM_GPIO_PINS(44); 302 DECLARE_MSM_GPIO_PINS(45); 303 DECLARE_MSM_GPIO_PINS(46); 304 DECLARE_MSM_GPIO_PINS(47); 305 DECLARE_MSM_GPIO_PINS(48); 306 DECLARE_MSM_GPIO_PINS(49); 307 DECLARE_MSM_GPIO_PINS(50); 308 DECLARE_MSM_GPIO_PINS(51); 309 DECLARE_MSM_GPIO_PINS(52); 310 DECLARE_MSM_GPIO_PINS(53); 311 DECLARE_MSM_GPIO_PINS(54); 312 DECLARE_MSM_GPIO_PINS(55); 313 DECLARE_MSM_GPIO_PINS(56); 314 DECLARE_MSM_GPIO_PINS(57); 315 DECLARE_MSM_GPIO_PINS(58); 316 DECLARE_MSM_GPIO_PINS(59); 317 DECLARE_MSM_GPIO_PINS(60); 318 DECLARE_MSM_GPIO_PINS(61); 319 DECLARE_MSM_GPIO_PINS(62); 320 DECLARE_MSM_GPIO_PINS(63); 321 DECLARE_MSM_GPIO_PINS(64); 322 DECLARE_MSM_GPIO_PINS(65); 323 DECLARE_MSM_GPIO_PINS(66); 324 DECLARE_MSM_GPIO_PINS(67); 325 DECLARE_MSM_GPIO_PINS(68); 326 DECLARE_MSM_GPIO_PINS(69); 327 DECLARE_MSM_GPIO_PINS(70); 328 DECLARE_MSM_GPIO_PINS(71); 329 DECLARE_MSM_GPIO_PINS(72); 330 DECLARE_MSM_GPIO_PINS(73); 331 DECLARE_MSM_GPIO_PINS(74); 332 DECLARE_MSM_GPIO_PINS(75); 333 DECLARE_MSM_GPIO_PINS(76); 334 DECLARE_MSM_GPIO_PINS(77); 335 DECLARE_MSM_GPIO_PINS(78); 336 DECLARE_MSM_GPIO_PINS(79); 337 DECLARE_MSM_GPIO_PINS(80); 338 DECLARE_MSM_GPIO_PINS(81); 339 DECLARE_MSM_GPIO_PINS(82); 340 DECLARE_MSM_GPIO_PINS(83); 341 DECLARE_MSM_GPIO_PINS(84); 342 DECLARE_MSM_GPIO_PINS(85); 343 DECLARE_MSM_GPIO_PINS(86); 344 DECLARE_MSM_GPIO_PINS(87); 345 DECLARE_MSM_GPIO_PINS(88); 346 DECLARE_MSM_GPIO_PINS(89); 347 DECLARE_MSM_GPIO_PINS(90); 348 DECLARE_MSM_GPIO_PINS(91); 349 DECLARE_MSM_GPIO_PINS(92); 350 DECLARE_MSM_GPIO_PINS(93); 351 DECLARE_MSM_GPIO_PINS(94); 352 DECLARE_MSM_GPIO_PINS(95); 353 DECLARE_MSM_GPIO_PINS(96); 354 DECLARE_MSM_GPIO_PINS(97); 355 DECLARE_MSM_GPIO_PINS(98); 356 DECLARE_MSM_GPIO_PINS(99); 357 DECLARE_MSM_GPIO_PINS(100); 358 DECLARE_MSM_GPIO_PINS(101); 359 DECLARE_MSM_GPIO_PINS(102); 360 DECLARE_MSM_GPIO_PINS(103); 361 DECLARE_MSM_GPIO_PINS(104); 362 DECLARE_MSM_GPIO_PINS(105); 363 DECLARE_MSM_GPIO_PINS(106); 364 DECLARE_MSM_GPIO_PINS(107); 365 DECLARE_MSM_GPIO_PINS(108); 366 DECLARE_MSM_GPIO_PINS(109); 367 DECLARE_MSM_GPIO_PINS(110); 368 DECLARE_MSM_GPIO_PINS(111); 369 DECLARE_MSM_GPIO_PINS(112); 370 DECLARE_MSM_GPIO_PINS(113); 371 DECLARE_MSM_GPIO_PINS(114); 372 DECLARE_MSM_GPIO_PINS(115); 373 DECLARE_MSM_GPIO_PINS(116); 374 DECLARE_MSM_GPIO_PINS(117); 375 DECLARE_MSM_GPIO_PINS(118); 376 DECLARE_MSM_GPIO_PINS(119); 377 DECLARE_MSM_GPIO_PINS(120); 378 DECLARE_MSM_GPIO_PINS(121); 379 DECLARE_MSM_GPIO_PINS(122); 380 DECLARE_MSM_GPIO_PINS(123); 381 DECLARE_MSM_GPIO_PINS(124); 382 DECLARE_MSM_GPIO_PINS(125); 383 DECLARE_MSM_GPIO_PINS(126); 384 DECLARE_MSM_GPIO_PINS(127); 385 DECLARE_MSM_GPIO_PINS(128); 386 DECLARE_MSM_GPIO_PINS(129); 387 DECLARE_MSM_GPIO_PINS(130); 388 DECLARE_MSM_GPIO_PINS(131); 389 DECLARE_MSM_GPIO_PINS(132); 390 DECLARE_MSM_GPIO_PINS(133); 391 DECLARE_MSM_GPIO_PINS(134); 392 DECLARE_MSM_GPIO_PINS(135); 393 DECLARE_MSM_GPIO_PINS(136); 394 DECLARE_MSM_GPIO_PINS(137); 395 DECLARE_MSM_GPIO_PINS(138); 396 DECLARE_MSM_GPIO_PINS(139); 397 DECLARE_MSM_GPIO_PINS(140); 398 DECLARE_MSM_GPIO_PINS(141); 399 DECLARE_MSM_GPIO_PINS(142); 400 DECLARE_MSM_GPIO_PINS(143); 401 DECLARE_MSM_GPIO_PINS(144); 402 DECLARE_MSM_GPIO_PINS(145); 403 DECLARE_MSM_GPIO_PINS(146); 404 DECLARE_MSM_GPIO_PINS(147); 405 DECLARE_MSM_GPIO_PINS(148); 406 DECLARE_MSM_GPIO_PINS(149); 407 DECLARE_MSM_GPIO_PINS(150); 408 DECLARE_MSM_GPIO_PINS(151); 409 DECLARE_MSM_GPIO_PINS(152); 410 DECLARE_MSM_GPIO_PINS(153); 411 DECLARE_MSM_GPIO_PINS(154); 412 DECLARE_MSM_GPIO_PINS(155); 413 DECLARE_MSM_GPIO_PINS(156); 414 DECLARE_MSM_GPIO_PINS(157); 415 DECLARE_MSM_GPIO_PINS(158); 416 DECLARE_MSM_GPIO_PINS(159); 417 DECLARE_MSM_GPIO_PINS(160); 418 DECLARE_MSM_GPIO_PINS(161); 419 DECLARE_MSM_GPIO_PINS(162); 420 DECLARE_MSM_GPIO_PINS(163); 421 DECLARE_MSM_GPIO_PINS(164); 422 DECLARE_MSM_GPIO_PINS(165); 423 424 static const unsigned int sdc1_rclk_pins[] = { 166 }; 425 static const unsigned int sdc1_clk_pins[] = { 167 }; 426 static const unsigned int sdc1_cmd_pins[] = { 168 }; 427 static const unsigned int sdc1_data_pins[] = { 169 }; 428 static const unsigned int sdc2_clk_pins[] = { 170 }; 429 static const unsigned int sdc2_cmd_pins[] = { 171 }; 430 static const unsigned int sdc2_data_pins[] = { 172 }; 431 432 enum shikra_functions { 433 msm_mux_gpio, 434 msm_mux_agera_pll, 435 msm_mux_atest_bbrx, 436 msm_mux_atest_char, 437 msm_mux_atest_gpsadc, 438 msm_mux_atest_tsens, 439 msm_mux_atest_usb, 440 msm_mux_cam_mclk, 441 msm_mux_cci_async, 442 msm_mux_cci_i2c0, 443 msm_mux_cci_i2c1, 444 msm_mux_cci_timer, 445 msm_mux_char_exec, 446 msm_mux_cri_trng, 447 msm_mux_dac_calib, 448 msm_mux_dbg_out_clk, 449 msm_mux_ddr_bist, 450 msm_mux_ddr_pxi, 451 msm_mux_dmic, 452 msm_mux_emac_dll, 453 msm_mux_emac_mcg, 454 msm_mux_emac_phy, 455 msm_mux_emac0_ptp_aux, 456 msm_mux_emac0_ptp_pps, 457 msm_mux_emac1_ptp_aux, 458 msm_mux_emac1_ptp_pps, 459 msm_mux_ext_mclk, 460 msm_mux_gcc_gp, 461 msm_mux_gsm0_tx, 462 msm_mux_i2s0, 463 msm_mux_i2s1, 464 msm_mux_i2s2, 465 msm_mux_i2s3, 466 msm_mux_jitter_bist, 467 msm_mux_m_voc, 468 msm_mux_mdp_vsync_e, 469 msm_mux_mdp_vsync_out0, 470 msm_mux_mdp_vsync_out1, 471 msm_mux_mdp_vsync_p, 472 msm_mux_mdp_vsync_s, 473 msm_mux_mpm_pwr, 474 msm_mux_mss_lte, 475 msm_mux_nav_gpio, 476 msm_mux_pa_indicator_or, 477 msm_mux_pbs_in, 478 msm_mux_pbs_out, 479 msm_mux_pcie0_clk_req_n, 480 msm_mux_phase_flag, 481 msm_mux_pll, 482 msm_mux_prng_rosc, 483 msm_mux_pwm, 484 msm_mux_qdss_cti, 485 msm_mux_qup0_se0, 486 msm_mux_qup0_se1, 487 msm_mux_qup0_se1_01, 488 msm_mux_qup0_se1_23, 489 msm_mux_qup0_se2, 490 msm_mux_qup0_se3_01, 491 msm_mux_qup0_se3_23, 492 msm_mux_qup0_se4_01, 493 msm_mux_qup0_se4_23, 494 msm_mux_qup0_se5, 495 msm_mux_qup0_se6, 496 msm_mux_qup0_se7_01, 497 msm_mux_qup0_se7_23, 498 msm_mux_qup0_se8, 499 msm_mux_qup0_se9, 500 msm_mux_qup0_se9_01, 501 msm_mux_qup0_se9_23, 502 msm_mux_rgmii, 503 msm_mux_sd_write_protect, 504 msm_mux_sdc_cdc, 505 msm_mux_sdc_tb_trig, 506 msm_mux_ssbi_wtr, 507 msm_mux_swr0_rx, 508 msm_mux_swr0_tx, 509 msm_mux_tgu_ch_trigout, 510 msm_mux_tsc_async, 511 msm_mux_tsense_pwm, 512 msm_mux_uim1, 513 msm_mux_uim2, 514 msm_mux_unused_adsp, 515 msm_mux_unused_gsm1, 516 msm_mux_usb0_phy_ps, 517 msm_mux_vfr, 518 msm_mux_vsense_trigger_mirnat, 519 msm_mux_wlan, 520 msm_mux__, 521 }; 522 523 static const char *const gpio_groups[] = { 524 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 525 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", 526 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", 527 "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", 528 "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 529 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 530 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", 531 "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", 532 "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", 533 "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", 534 "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", 535 "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", 536 "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 537 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", 538 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", 539 "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", 540 "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", 541 "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", 542 "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", 543 "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", 544 "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", 545 "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", 546 "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", 547 "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", 548 "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", 549 "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", 550 "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", 551 "gpio162", "gpio163", "gpio164", "gpio165", 552 }; 553 554 static const char *const agera_pll_groups[] = { 555 "gpio22", "gpio23", 556 }; 557 558 static const char *const atest_bbrx_groups[] = { 559 "gpio58", "gpio59", 560 }; 561 562 static const char *const atest_char_groups[] = { 563 "gpio56", "gpio57", "gpio54", "gpio55", "gpio62", 564 }; 565 566 static const char *const atest_gpsadc_groups[] = { 567 "gpio60", "gpio96", 568 }; 569 570 static const char *const atest_tsens_groups[] = { 571 "gpio1", "gpio2", 572 }; 573 574 static const char *const atest_usb_groups[] = { 575 "gpio53", "gpio58", "gpio59", "gpio60", "gpio61", "gpio96", 576 "gpio98", "gpio99", "gpio100", "gpio101", 577 }; 578 579 static const char *const cam_mclk_groups[] = { 580 "gpio34", "gpio35", "gpio96", "gpio98", 581 }; 582 583 static const char *const cci_async_groups[] = { 584 "gpio39", 585 }; 586 587 static const char *const cci_i2c0_groups[] = { 588 "gpio36", "gpio37", 589 }; 590 591 static const char *const cci_i2c1_groups[] = { 592 "gpio41", "gpio42", 593 }; 594 595 static const char *const cci_timer_groups[] = { 596 "gpio38", "gpio40", "gpio43", "gpio47", 597 }; 598 599 static const char *const char_exec_groups[] = { 600 "gpio12", "gpio13", 601 }; 602 603 static const char *const cri_trng_groups[] = { 604 "gpio6", "gpio7", "gpio20", 605 }; 606 607 static const char *const dac_calib_groups[] = { 608 "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", 609 "gpio9", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", 610 "gpio19", "gpio63", "gpio64", "gpio66", "gpio68", "gpio69", 611 "gpio70", "gpio88", "gpio89", "gpio90", "gpio97", "gpio116", 612 "gpio117", "gpio118", 613 }; 614 615 static const char *const dbg_out_clk_groups[] = { 616 "gpio61", 617 }; 618 619 static const char *const ddr_bist_groups[] = { 620 "gpio1", "gpio2", "gpio3", "gpio4", 621 }; 622 623 static const char *const ddr_pxi_groups[] = { 624 "gpio98", "gpio99", "gpio100", "gpio101", 625 }; 626 627 static const char *const dmic_groups[] = { 628 "gpio96", "gpio97", "gpio98", "gpio99", 629 }; 630 631 static const char *const emac_dll_groups[] = { 632 "gpio58", "gpio59", "gpio60", "gpio61", 633 }; 634 635 static const char *const emac_mcg_groups[] = { 636 "gpio28", "gpio29", "gpio40", "gpio43", "gpio44", "gpio45", 637 "gpio46", "gpio47", 638 }; 639 640 static const char *const emac_phy_groups[] = { 641 "gpio120", "gpio136", 642 }; 643 644 static const char *const emac0_ptp_aux_groups[] = { 645 "gpio60", "gpio63", "gpio69", "gpio85", 646 }; 647 648 static const char *const emac0_ptp_pps_groups[] = { 649 "gpio60", "gpio63", "gpio69", "gpio85", 650 }; 651 652 static const char *const emac1_ptp_aux_groups[] = { 653 "gpio31", "gpio33", "gpio60", "gpio68", 654 }; 655 656 static const char *const emac1_ptp_pps_groups[] = { 657 "gpio31", "gpio33", "gpio60", "gpio68", 658 }; 659 660 static const char *const ext_mclk_groups[] = { 661 "gpio103", "gpio104", "gpio110", "gpio114", 662 }; 663 664 static const char *const gcc_gp_groups[] = { 665 "gpio45", "gpio53", "gpio61", "gpio88", "gpio89", "gpio110", 666 }; 667 668 static const char *const gsm0_tx_groups[] = { 669 "gpio75", 670 }; 671 672 static const char *const i2s0_groups[] = { 673 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 674 }; 675 676 static const char *const i2s1_groups[] = { 677 "gpio96", "gpio97", "gpio98", "gpio99", 678 }; 679 680 static const char *const i2s2_groups[] = { 681 "gpio100", "gpio101", "gpio102", "gpio103", 682 }; 683 684 static const char *const i2s3_groups[] = { 685 "gpio111", "gpio112", "gpio113", "gpio114", 686 }; 687 688 static const char *const jitter_bist_groups[] = { 689 "gpio96", "gpio99", 690 }; 691 692 static const char *const m_voc_groups[] = { 693 "gpio0", 694 }; 695 696 static const char *const mdp_vsync_e_groups[] = { 697 "gpio94", 698 }; 699 700 static const char *const mdp_vsync_out0_groups[] = { 701 "gpio86", 702 }; 703 704 static const char *const mdp_vsync_out1_groups[] = { 705 "gpio86", 706 }; 707 708 static const char *const mdp_vsync_p_groups[] = { 709 "gpio86", 710 }; 711 712 static const char *const mdp_vsync_s_groups[] = { 713 "gpio95", 714 }; 715 716 static const char *const mpm_pwr_groups[] = { 717 "gpio1", 718 }; 719 720 static const char *const mss_lte_groups[] = { 721 "gpio115", "gpio116", 722 }; 723 724 static const char *const nav_gpio_groups[] = { 725 "gpio53", "gpio58", "gpio63", "gpio71", "gpio91", "gpio92", 726 "gpio95", "gpio100", "gpio101", "gpio104", 727 }; 728 729 static const char *const pa_indicator_or_groups[] = { 730 "gpio61", 731 }; 732 733 static const char *const pbs_in_groups[] = { 734 "gpio48", "gpio49", "gpio50", "gpio51", "gpio53", "gpio54", 735 "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", 736 "gpio61", "gpio62", "gpio63", "gpio74", 737 }; 738 739 static const char *const pbs_out_groups[] = { 740 "gpio22", "gpio23", "gpio24", 741 }; 742 743 static const char *const pcie0_clk_req_n_groups[] = { 744 "gpio117", 745 }; 746 747 static const char *const phase_flag_groups[] = { 748 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 749 "gpio6", "gpio7", "gpio8", "gpio9", "gpio11", "gpio16", 750 "gpio17", "gpio28", "gpio29", "gpio30", "gpio31", "gpio48", 751 "gpio49", "gpio50", "gpio54", "gpio55", "gpio56", "gpio57", 752 "gpio62", "gpio63", "gpio64", "gpio69", "gpio70", "gpio71", 753 "gpio72", "gpio74", "gpio102", 754 }; 755 756 static const char *const pll_groups[] = { 757 "gpio14", "gpio22", "gpio43", "gpio44", "gpio74", "gpio76", 758 }; 759 760 static const char *const prng_rosc_groups[] = { 761 "gpio27", "gpio28", 762 }; 763 764 static const char *const pwm_groups[] = { 765 "gpio32", "gpio40", "gpio45", "gpio53", "gpio54", "gpio55", 766 "gpio56", "gpio57", "gpio58", "gpio61", "gpio62", "gpio68", 767 "gpio77", "gpio79", "gpio80", "gpio87", "gpio102" 768 }; 769 770 static const char *const qdss_cti_groups[] = { 771 "gpio28", "gpio29", "gpio30", "gpio31", "gpio94", "gpio95", 772 }; 773 774 static const char *const qup0_se0_groups[] = { 775 "gpio0", "gpio1", "gpio2", "gpio3", 776 }; 777 778 static const char *const qup0_se1_groups[] = { 779 "gpio28", "gpio29", 780 }; 781 782 static const char *const qup0_se1_01_groups[] = { 783 "gpio4", "gpio5", 784 }; 785 786 static const char *const qup0_se1_23_groups[] = { 787 "gpio4", "gpio5", 788 }; 789 790 static const char *const qup0_se2_groups[] = { 791 "gpio6", "gpio7", "gpio8", "gpio9", "gpio30", "gpio31", 792 }; 793 794 static const char *const qup0_se3_01_groups[] = { 795 "gpio10", "gpio11", 796 }; 797 798 static const char *const qup0_se3_23_groups[] = { 799 "gpio10", "gpio11", 800 }; 801 802 static const char *const qup0_se4_01_groups[] = { 803 "gpio12", "gpio13", 804 }; 805 806 static const char *const qup0_se4_23_groups[] = { 807 "gpio12", "gpio13", 808 }; 809 810 static const char *const qup0_se5_groups[] = { 811 "gpio14", "gpio15", "gpio16", "gpio17", 812 }; 813 814 static const char *const qup0_se6_groups[] = { 815 "gpio18", "gpio19", "gpio28", "gpio29", "gpio30", "gpio31", 816 }; 817 818 static const char *const qup0_se7_01_groups[] = { 819 "gpio20", "gpio21", 820 }; 821 822 static const char *const qup0_se7_23_groups[] = { 823 "gpio20", "gpio21", 824 }; 825 826 static const char *const qup0_se8_groups[] = { 827 "gpio22", "gpio23", "gpio24", "gpio25", 828 }; 829 830 static const char *const qup0_se9_groups[] = { 831 "gpio48", "gpio49", "gpio50", "gpio51", 832 }; 833 834 static const char *const qup0_se9_01_groups[] = { 835 "gpio26", "gpio27", 836 }; 837 838 static const char *const qup0_se9_23_groups[] = { 839 "gpio26", "gpio27", 840 }; 841 842 static const char *const rgmii_groups[] = { 843 "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", 844 "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", 845 "gpio133", "gpio134", "gpio137", "gpio138", "gpio139", "gpio140", 846 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", 847 "gpio147", "gpio148", "gpio149", "gpio150", 848 }; 849 850 static const char *const sd_write_protect_groups[] = { 851 "gpio109", 852 }; 853 854 static const char *const sdc_cdc_groups[] = { 855 "gpio98", "gpio99", "gpio100", "gpio101", 856 }; 857 858 static const char *const sdc_tb_trig_groups[] = { 859 "gpio32", "gpio33", 860 }; 861 862 static const char *const ssbi_wtr_groups[] = { 863 "gpio68", "gpio69", "gpio70", "gpio71", 864 }; 865 866 static const char *const swr0_rx_groups[] = { 867 "gpio107", "gpio108", "gpio109", 868 }; 869 870 static const char *const swr0_tx_groups[] = { 871 "gpio105", "gpio106", 872 }; 873 874 static const char *const tgu_ch_trigout_groups[] = { 875 "gpio14", "gpio15", "gpio16", "gpio17", 876 }; 877 878 static const char *const tsc_async_groups[] = { 879 "gpio45", "gpio46", 880 }; 881 882 static const char *const tsense_pwm_groups[] = { 883 "gpio21", 884 }; 885 886 static const char *const uim1_groups[] = { 887 "gpio81", "gpio82", "gpio83", "gpio84", 888 }; 889 890 static const char *const uim2_groups[] = { 891 "gpio77", "gpio78", "gpio79", "gpio80", 892 }; 893 894 static const char *const unused_adsp_groups[] = { 895 "gpio35", 896 }; 897 898 static const char *const unused_gsm1_groups[] = { 899 "gpio64", 900 }; 901 902 static const char *const usb0_phy_ps_groups[] = { 903 "gpio90", 904 }; 905 906 static const char *const vfr_groups[] = { 907 "gpio59", 908 }; 909 910 static const char *const vsense_trigger_mirnat_groups[] = { 911 "gpio58", 912 }; 913 914 static const char *const wlan_groups[] = { 915 "gpio14", "gpio15", 916 }; 917 918 static const struct pinfunction shikra_functions[] = { 919 MSM_GPIO_PIN_FUNCTION(gpio), 920 MSM_PIN_FUNCTION(agera_pll), 921 MSM_PIN_FUNCTION(atest_bbrx), 922 MSM_PIN_FUNCTION(atest_char), 923 MSM_PIN_FUNCTION(atest_gpsadc), 924 MSM_PIN_FUNCTION(atest_tsens), 925 MSM_PIN_FUNCTION(atest_usb), 926 MSM_PIN_FUNCTION(cam_mclk), 927 MSM_PIN_FUNCTION(cci_async), 928 MSM_PIN_FUNCTION(cci_i2c0), 929 MSM_PIN_FUNCTION(cci_i2c1), 930 MSM_PIN_FUNCTION(cci_timer), 931 MSM_PIN_FUNCTION(char_exec), 932 MSM_PIN_FUNCTION(cri_trng), 933 MSM_PIN_FUNCTION(dac_calib), 934 MSM_PIN_FUNCTION(dbg_out_clk), 935 MSM_PIN_FUNCTION(ddr_bist), 936 MSM_PIN_FUNCTION(ddr_pxi), 937 MSM_PIN_FUNCTION(dmic), 938 MSM_PIN_FUNCTION(emac_dll), 939 MSM_PIN_FUNCTION(emac_mcg), 940 MSM_PIN_FUNCTION(emac_phy), 941 MSM_PIN_FUNCTION(emac0_ptp_aux), 942 MSM_PIN_FUNCTION(emac0_ptp_pps), 943 MSM_PIN_FUNCTION(emac1_ptp_aux), 944 MSM_PIN_FUNCTION(emac1_ptp_pps), 945 MSM_PIN_FUNCTION(ext_mclk), 946 MSM_PIN_FUNCTION(gcc_gp), 947 MSM_PIN_FUNCTION(gsm0_tx), 948 MSM_PIN_FUNCTION(i2s0), 949 MSM_PIN_FUNCTION(i2s1), 950 MSM_PIN_FUNCTION(i2s2), 951 MSM_PIN_FUNCTION(i2s3), 952 MSM_PIN_FUNCTION(jitter_bist), 953 MSM_PIN_FUNCTION(m_voc), 954 MSM_PIN_FUNCTION(mdp_vsync_e), 955 MSM_PIN_FUNCTION(mdp_vsync_out0), 956 MSM_PIN_FUNCTION(mdp_vsync_out1), 957 MSM_PIN_FUNCTION(mdp_vsync_p), 958 MSM_PIN_FUNCTION(mdp_vsync_s), 959 MSM_PIN_FUNCTION(mpm_pwr), 960 MSM_PIN_FUNCTION(mss_lte), 961 MSM_PIN_FUNCTION(nav_gpio), 962 MSM_PIN_FUNCTION(pa_indicator_or), 963 MSM_PIN_FUNCTION(pbs_in), 964 MSM_PIN_FUNCTION(pbs_out), 965 MSM_PIN_FUNCTION(pcie0_clk_req_n), 966 MSM_PIN_FUNCTION(phase_flag), 967 MSM_PIN_FUNCTION(pll), 968 MSM_PIN_FUNCTION(prng_rosc), 969 MSM_PIN_FUNCTION(pwm), 970 MSM_PIN_FUNCTION(qdss_cti), 971 MSM_PIN_FUNCTION(qup0_se0), 972 MSM_PIN_FUNCTION(qup0_se1), 973 MSM_PIN_FUNCTION(qup0_se1_01), 974 MSM_PIN_FUNCTION(qup0_se1_23), 975 MSM_PIN_FUNCTION(qup0_se2), 976 MSM_PIN_FUNCTION(qup0_se3_01), 977 MSM_PIN_FUNCTION(qup0_se3_23), 978 MSM_PIN_FUNCTION(qup0_se4_01), 979 MSM_PIN_FUNCTION(qup0_se4_23), 980 MSM_PIN_FUNCTION(qup0_se5), 981 MSM_PIN_FUNCTION(qup0_se6), 982 MSM_PIN_FUNCTION(qup0_se7_01), 983 MSM_PIN_FUNCTION(qup0_se7_23), 984 MSM_PIN_FUNCTION(qup0_se8), 985 MSM_PIN_FUNCTION(qup0_se9), 986 MSM_PIN_FUNCTION(qup0_se9_01), 987 MSM_PIN_FUNCTION(qup0_se9_23), 988 MSM_PIN_FUNCTION(rgmii), 989 MSM_PIN_FUNCTION(sd_write_protect), 990 MSM_PIN_FUNCTION(sdc_cdc), 991 MSM_PIN_FUNCTION(sdc_tb_trig), 992 MSM_PIN_FUNCTION(ssbi_wtr), 993 MSM_PIN_FUNCTION(swr0_rx), 994 MSM_PIN_FUNCTION(swr0_tx), 995 MSM_PIN_FUNCTION(tgu_ch_trigout), 996 MSM_PIN_FUNCTION(tsc_async), 997 MSM_PIN_FUNCTION(tsense_pwm), 998 MSM_PIN_FUNCTION(uim1), 999 MSM_PIN_FUNCTION(uim2), 1000 MSM_PIN_FUNCTION(unused_adsp), 1001 MSM_PIN_FUNCTION(unused_gsm1), 1002 MSM_PIN_FUNCTION(usb0_phy_ps), 1003 MSM_PIN_FUNCTION(vfr), 1004 MSM_PIN_FUNCTION(vsense_trigger_mirnat), 1005 MSM_PIN_FUNCTION(wlan), 1006 }; 1007 1008 static const struct msm_pingroup shikra_groups[] = { 1009 [0] = PINGROUP(0, qup0_se0, m_voc, _, phase_flag, _, _, _, _, _, _, _), 1010 [1] = PINGROUP(1, qup0_se0, mpm_pwr, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _), 1011 [2] = PINGROUP(2, qup0_se0, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _, _), 1012 [3] = PINGROUP(3, qup0_se0, ddr_bist, _, phase_flag, dac_calib, _, _, _, _, _, _), 1013 [4] = PINGROUP(4, qup0_se1_23, qup0_se1_01, ddr_bist, _, phase_flag, dac_calib, _, _, _, 1014 _, _), 1015 [5] = PINGROUP(5, qup0_se1_23, qup0_se1_01, _, phase_flag, dac_calib, _, _, _, _, _, _), 1016 [6] = PINGROUP(6, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _), 1017 [7] = PINGROUP(7, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _), 1018 [8] = PINGROUP(8, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _), 1019 [9] = PINGROUP(9, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _), 1020 [10] = PINGROUP(10, qup0_se3_01, qup0_se3_23, _, _, _, _, _, _, _, _, _), 1021 [11] = PINGROUP(11, qup0_se3_01, qup0_se3_23, _, phase_flag, _, _, _, _, _, _, _), 1022 [12] = PINGROUP(12, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _), 1023 [13] = PINGROUP(13, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _), 1024 [14] = PINGROUP(14, qup0_se5, pll, tgu_ch_trigout, dac_calib, wlan, _, _, _, _, _, _), 1025 [15] = PINGROUP(15, qup0_se5, tgu_ch_trigout, _, dac_calib, wlan, _, _, _, _, _, _), 1026 [16] = PINGROUP(16, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _), 1027 [17] = PINGROUP(17, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _), 1028 [18] = PINGROUP(18, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _), 1029 [19] = PINGROUP(19, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _), 1030 [20] = PINGROUP(20, qup0_se7_01, qup0_se7_23, cri_trng, _, _, _, _, _, _, _, _), 1031 [21] = PINGROUP(21, qup0_se7_01, qup0_se7_23, tsense_pwm, _, _, _, _, _, _, _, _), 1032 [22] = PINGROUP(22, qup0_se8, pll, agera_pll, pbs_out, _, _, _, _, _, _, _), 1033 [23] = PINGROUP(23, qup0_se8, agera_pll, pbs_out, _, _, _, _, _, _, _, _), 1034 [24] = PINGROUP(24, qup0_se8, pbs_out, _, _, _, _, _, _, _, _, _), 1035 [25] = PINGROUP(25, qup0_se8, _, _, _, _, _, _, _, _, _, _), 1036 [26] = PINGROUP(26, qup0_se9_23, qup0_se9_01, _, _, _, _, _, _, _, _, _), 1037 [27] = PINGROUP(27, qup0_se9_23, qup0_se9_01, prng_rosc, _, _, _, _, _, _, _, _), 1038 [28] = PINGROUP(28, qup0_se1, qup0_se6, emac_mcg, prng_rosc, _, phase_flag, qdss_cti, 1039 _, _, _, _), 1040 [29] = PINGROUP(29, qup0_se1, qup0_se6, emac_mcg, _, phase_flag, qdss_cti, _, _, _, _, _), 1041 [30] = PINGROUP(30, qup0_se2, qup0_se6, _, phase_flag, qdss_cti, _, _, _, _, _, _), 1042 [31] = PINGROUP(31, qup0_se2, qup0_se6, emac1_ptp_aux, emac1_ptp_pps, _, phase_flag, 1043 qdss_cti, _, _, _, _), 1044 [32] = PINGROUP(32, pwm, sdc_tb_trig, _, _, _, _, _, _, _, _, _), 1045 [33] = PINGROUP(33, emac1_ptp_aux, emac1_ptp_pps, sdc_tb_trig, _, _, _, _, _, _, _, _), 1046 [34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _, _, _, _, _), 1047 [35] = PINGROUP(35, cam_mclk, unused_adsp, _, _, _, _, _, _, _, _, _), 1048 [36] = PINGROUP(36, cci_i2c0, _, _, _, _, _, _, _, _, _, _), 1049 [37] = PINGROUP(37, cci_i2c0, _, _, _, _, _, _, _, _, _, _), 1050 [38] = PINGROUP(38, cci_timer, _, _, _, _, _, _, _, _, _, _), 1051 [39] = PINGROUP(39, cci_async, _, _, _, _, _, _, _, _, _, _), 1052 [40] = PINGROUP(40, cci_timer, emac_mcg, pwm, _, _, _, _, _, _, _, _), 1053 [41] = PINGROUP(41, cci_i2c1, _, _, _, _, _, _, _, _, _, _), 1054 [42] = PINGROUP(42, cci_i2c1, _, _, _, _, _, _, _, _, _, _), 1055 [43] = PINGROUP(43, cci_timer, emac_mcg, pll, _, _, _, _, _, _, _, _), 1056 [44] = PINGROUP(44, emac_mcg, pll, _, _, _, _, _, _, _, _, _), 1057 [45] = PINGROUP(45, tsc_async, emac_mcg, pwm, gcc_gp, _, _, _, _, _, _, _), 1058 [46] = PINGROUP(46, tsc_async, emac_mcg, _, _, _, _, _, _, _, _, _), 1059 [47] = PINGROUP(47, cci_timer, emac_mcg, _, _, _, _, _, _, _, _, _), 1060 [48] = PINGROUP(48, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), 1061 [49] = PINGROUP(49, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), 1062 [50] = PINGROUP(50, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), 1063 [51] = PINGROUP(51, _, qup0_se9, pbs_in, _, _, _, _, _, _, _, _), 1064 [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _, _, _), 1065 [53] = PINGROUP(53, _, nav_gpio, gcc_gp, pwm, _, pbs_in, atest_usb, _, _, _, _), 1066 [54] = PINGROUP(54, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), 1067 [55] = PINGROUP(55, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), 1068 [56] = PINGROUP(56, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), 1069 [57] = PINGROUP(57, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), 1070 [58] = PINGROUP(58, _, nav_gpio, pwm, _, pbs_in, atest_bbrx, atest_usb, 1071 vsense_trigger_mirnat, emac_dll, _, _), 1072 [59] = PINGROUP(59, _, vfr, _, pbs_in, atest_bbrx, atest_usb, emac_dll, _, _, _, _), 1073 [60] = PINGROUP(60, _, emac1_ptp_aux, emac1_ptp_pps, emac0_ptp_aux, emac0_ptp_pps, _, 1074 pbs_in, atest_gpsadc, atest_usb, emac_dll, _), 1075 [61] = PINGROUP(61, _, pwm, gcc_gp, pa_indicator_or, dbg_out_clk, pbs_in, atest_usb, 1076 emac_dll, _, _, _), 1077 [62] = PINGROUP(62, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), 1078 [63] = PINGROUP(63, _, nav_gpio, emac0_ptp_aux, emac0_ptp_pps, _, pbs_in, phase_flag, 1079 dac_calib, _, _, _), 1080 [64] = PINGROUP(64, _, unused_gsm1, dac_calib, _, _, _, _, _, _, _, _), 1081 [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _, _, _), 1082 [66] = PINGROUP(66, _, dac_calib, _, _, _, _, _, _, _, _, _), 1083 [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _, _, _), 1084 [68] = PINGROUP(68, _, ssbi_wtr, emac1_ptp_aux, emac1_ptp_pps, pwm, dac_calib, _, _, _, 1085 _, _), 1086 [69] = PINGROUP(69, _, ssbi_wtr, emac0_ptp_aux, emac0_ptp_pps, _, phase_flag, dac_calib, 1087 _, _, _, _), 1088 [70] = PINGROUP(70, _, ssbi_wtr, _, phase_flag, dac_calib, _, _, _, _, _, _), 1089 [71] = PINGROUP(71, _, ssbi_wtr, nav_gpio, _, phase_flag, _, _, _, _, _, _), 1090 [72] = PINGROUP(72, _, _, phase_flag, _, _, _, _, _, _, _, _), 1091 [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _, _), 1092 [74] = PINGROUP(74, pll, _, pbs_in, phase_flag, _, _, _, _, _, _, _), 1093 [75] = PINGROUP(75, gsm0_tx, _, _, _, _, _, _, _, _, _, _), 1094 [76] = PINGROUP(76, pll, _, _, _, _, _, _, _, _, _, _), 1095 [77] = PINGROUP(77, uim2, pwm, _, _, _, _, _, _, _, _, _), 1096 [78] = PINGROUP(78, uim2, _, _, _, _, _, _, _, _, _, _), 1097 [79] = PINGROUP(79, uim2, pwm, _, _, _, _, _, _, _, _, _), 1098 [80] = PINGROUP(80, uim2, pwm, _, _, _, _, _, _, _, _, _), 1099 [81] = PINGROUP(81, uim1, _, _, _, _, _, _, _, _, _, _), 1100 [82] = PINGROUP(82, uim1, _, _, _, _, _, _, _, _, _, _), 1101 [83] = PINGROUP(83, uim1, _, _, _, _, _, _, _, _, _, _), 1102 [84] = PINGROUP(84, uim1, _, _, _, _, _, _, _, _, _, _), 1103 [85] = PINGROUP(85, emac0_ptp_aux, emac0_ptp_pps, _, _, _, _, _, _, _, _, _), 1104 [86] = PINGROUP(86, mdp_vsync_p, mdp_vsync_out0, mdp_vsync_out1, _, _, _, _, _, _, _, _), 1105 [87] = PINGROUP(87, _, pwm, _, _, _, _, _, _, _, _, _), 1106 [88] = PINGROUP(88, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _), 1107 [89] = PINGROUP(89, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _), 1108 [90] = PINGROUP(90, usb0_phy_ps, _, dac_calib, _, _, _, _, _, _, _, _), 1109 [91] = PINGROUP(91, nav_gpio, _, _, _, _, _, _, _, _, _, _), 1110 [92] = PINGROUP(92, nav_gpio, _, _, _, _, _, _, _, _, _, _), 1111 [93] = PINGROUP(93, _, _, _, _, _, _, _, _, _, _, _), 1112 [94] = PINGROUP(94, mdp_vsync_e, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), 1113 [95] = PINGROUP(95, nav_gpio, mdp_vsync_s, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 1114 [96] = PINGROUP(96, dmic, cam_mclk, i2s1, jitter_bist, atest_gpsadc, atest_usb, _, _, _, 1115 _, _), 1116 [97] = PINGROUP(97, dmic, i2s1, dac_calib, _, _, _, _, _, _, _, _), 1117 [98] = PINGROUP(98, dmic, cam_mclk, i2s1, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _), 1118 [99] = PINGROUP(99, dmic, i2s1, jitter_bist, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), 1119 [100] = PINGROUP(100, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), 1120 [101] = PINGROUP(101, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), 1121 [102] = PINGROUP(102, i2s2, pwm, _, phase_flag, _, _, _, _, _, _, _), 1122 [103] = PINGROUP(103, ext_mclk, i2s2, _, _, _, _, _, _, _, _, _), 1123 [104] = PINGROUP(104, ext_mclk, nav_gpio, _, _, _, _, _, _, _, _, _), 1124 [105] = PINGROUP(105, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _), 1125 [106] = PINGROUP(106, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _), 1126 [107] = PINGROUP(107, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _), 1127 [108] = PINGROUP(108, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _), 1128 [109] = PINGROUP(109, swr0_rx, i2s0, sd_write_protect, _, _, _, _, _, _, _, _), 1129 [110] = PINGROUP(110, ext_mclk, i2s0, _, gcc_gp, _, _, _, _, _, _, _), 1130 [111] = PINGROUP(111, i2s3, _, _, _, _, _, _, _, _, _, _), 1131 [112] = PINGROUP(112, i2s3, _, _, _, _, _, _, _, _, _, _), 1132 [113] = PINGROUP(113, i2s3, _, _, _, _, _, _, _, _, _, _), 1133 [114] = PINGROUP(114, ext_mclk, i2s3, _, _, _, _, _, _, _, _, _), 1134 [115] = PINGROUP(115, mss_lte, _, _, _, _, _, _, _, _, _, _), 1135 [116] = PINGROUP(116, mss_lte, _, dac_calib, _, _, _, _, _, _, _, _), 1136 [117] = PINGROUP(117, pcie0_clk_req_n, _, dac_calib, _, _, _, _, _, _, _, _), 1137 [118] = PINGROUP(118, _, dac_calib, _, _, _, _, _, _, _, _, _), 1138 [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, _), 1139 [120] = PINGROUP(120, emac_phy, _, _, _, _, _, _, _, _, _, _), 1140 [121] = PINGROUP(121, rgmii, _, _, _, _, _, _, _, _, _, _), 1141 [122] = PINGROUP(122, rgmii, _, _, _, _, _, _, _, _, _, _), 1142 [123] = PINGROUP(123, rgmii, _, _, _, _, _, _, _, _, _, _), 1143 [124] = PINGROUP(124, rgmii, _, _, _, _, _, _, _, _, _, _), 1144 [125] = PINGROUP(125, rgmii, _, _, _, _, _, _, _, _, _, _), 1145 [126] = PINGROUP(126, rgmii, _, _, _, _, _, _, _, _, _, _), 1146 [127] = PINGROUP(127, rgmii, _, _, _, _, _, _, _, _, _, _), 1147 [128] = PINGROUP(128, rgmii, _, _, _, _, _, _, _, _, _, _), 1148 [129] = PINGROUP(129, rgmii, _, _, _, _, _, _, _, _, _, _), 1149 [130] = PINGROUP(130, rgmii, _, _, _, _, _, _, _, _, _, _), 1150 [131] = PINGROUP(131, rgmii, _, _, _, _, _, _, _, _, _, _), 1151 [132] = PINGROUP(132, rgmii, _, _, _, _, _, _, _, _, _, _), 1152 [133] = PINGROUP(133, rgmii, _, _, _, _, _, _, _, _, _, _), 1153 [134] = PINGROUP(134, rgmii, _, _, _, _, _, _, _, _, _, _), 1154 [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, _), 1155 [136] = PINGROUP(136, emac_phy, _, _, _, _, _, _, _, _, _, _), 1156 [137] = PINGROUP(137, rgmii, _, _, _, _, _, _, _, _, _, _), 1157 [138] = PINGROUP(138, rgmii, _, _, _, _, _, _, _, _, _, _), 1158 [139] = PINGROUP(139, rgmii, _, _, _, _, _, _, _, _, _, _), 1159 [140] = PINGROUP(140, rgmii, _, _, _, _, _, _, _, _, _, _), 1160 [141] = PINGROUP(141, rgmii, _, _, _, _, _, _, _, _, _, _), 1161 [142] = PINGROUP(142, rgmii, _, _, _, _, _, _, _, _, _, _), 1162 [143] = PINGROUP(143, rgmii, _, _, _, _, _, _, _, _, _, _), 1163 [144] = PINGROUP(144, rgmii, _, _, _, _, _, _, _, _, _, _), 1164 [145] = PINGROUP(145, rgmii, _, _, _, _, _, _, _, _, _, _), 1165 [146] = PINGROUP(146, rgmii, _, _, _, _, _, _, _, _, _, _), 1166 [147] = PINGROUP(147, rgmii, _, _, _, _, _, _, _, _, _, _), 1167 [148] = PINGROUP(148, rgmii, _, _, _, _, _, _, _, _, _, _), 1168 [149] = PINGROUP(149, rgmii, _, _, _, _, _, _, _, _, _, _), 1169 [150] = PINGROUP(150, rgmii, _, _, _, _, _, _, _, _, _, _), 1170 [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, _), 1171 [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, _), 1172 [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, _), 1173 [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, _), 1174 [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _, _, _), 1175 [156] = PINGROUP(156, _, _, _, _, _, _, _, _, _, _, _), 1176 [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _), 1177 [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _), 1178 [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _, _, _), 1179 [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _, _, _), 1180 [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _, _, _), 1181 [162] = PINGROUP(162, _, _, _, _, _, _, _, _, _, _, _), 1182 [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, _), 1183 [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, _), 1184 [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, _), 1185 [166] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xac004, 0, 0), 1186 [167] = SDC_QDSD_PINGROUP(sdc1_clk, 0xac000, 13, 6), 1187 [168] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xac000, 11, 3), 1188 [169] = SDC_QDSD_PINGROUP(sdc1_data, 0xac000, 9, 0), 1189 [170] = SDC_QDSD_PINGROUP(sdc2_clk, 0xaa000, 14, 6), 1190 [171] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xaa000, 11, 3), 1191 [172] = SDC_QDSD_PINGROUP(sdc2_data, 0xaa000, 9, 0), 1192 }; 1193 1194 static const struct msm_gpio_wakeirq_map shikra_mpm_map[] = { 1195 {1, 9 }, {2, 31 }, {5, 49 }, {6, 53 }, {9, 72 }, {10, 10 }, 1196 {12, 22 }, {14, 26 }, {17, 29 }, {18, 24 }, {20, 32 }, {22, 33 }, 1197 {25, 34 }, {27, 35 }, {28, 36 }, {29, 37 }, {30, 38 }, {31, 39 }, 1198 {32, 40 }, {33, 41 }, {38, 42 }, {40, 43 }, {43, 44 }, {44, 45 }, 1199 {45, 46 }, {46, 47 }, {47, 48 }, {48, 60 }, {50, 50 }, {51, 51 }, 1200 {52, 61 }, {53, 62 }, {57, 52 }, {58, 63 }, {60, 54 }, {63, 64 }, 1201 {73, 55 }, {74, 56 }, {75, 57 }, {77, 3 }, {80, 4 }, {84, 5 }, 1202 {85, 67 }, {86, 69 }, {88, 70 }, {89, 71 }, {90, 73 }, {91, 74 }, 1203 {92, 75 }, {93, 76 }, {94, 77 }, {95, 78 }, {97, 79 }, {99, 80 }, 1204 {100, 11 }, {101, 13 }, {102, 14 }, {103, 15 }, {106, 16 }, {108, 17 }, 1205 {112, 18 }, {116, 19 }, {117, 20 }, {119, 21 }, {120, 23 }, {136, 25 }, 1206 {159, 27 }, {161, 28 }, 1207 }; 1208 1209 static const struct msm_pinctrl_soc_data shikra_tlmm = { 1210 .pins = shikra_pins, 1211 .npins = ARRAY_SIZE(shikra_pins), 1212 .functions = shikra_functions, 1213 .nfunctions = ARRAY_SIZE(shikra_functions), 1214 .groups = shikra_groups, 1215 .ngroups = ARRAY_SIZE(shikra_groups), 1216 .ngpios = 166, 1217 .wakeirq_map = shikra_mpm_map, 1218 .nwakeirq_map = ARRAY_SIZE(shikra_mpm_map), 1219 }; 1220 1221 static int shikra_tlmm_probe(struct platform_device *pdev) 1222 { 1223 return msm_pinctrl_probe(pdev, &shikra_tlmm); 1224 } 1225 1226 static const struct of_device_id shikra_tlmm_of_match[] = { 1227 { .compatible = "qcom,shikra-tlmm", .data = &shikra_tlmm }, 1228 {}, 1229 }; 1230 MODULE_DEVICE_TABLE(of, shikra_tlmm_of_match); 1231 1232 static struct platform_driver shikra_tlmm_driver = { 1233 .driver = { 1234 .name = "shikra-tlmm", 1235 .of_match_table = shikra_tlmm_of_match, 1236 }, 1237 .probe = shikra_tlmm_probe, 1238 }; 1239 1240 static int __init shikra_tlmm_init(void) 1241 { 1242 return platform_driver_register(&shikra_tlmm_driver); 1243 } 1244 arch_initcall(shikra_tlmm_init); 1245 1246 static void __exit shikra_tlmm_exit(void) 1247 { 1248 platform_driver_unregister(&shikra_tlmm_driver); 1249 } 1250 module_exit(shikra_tlmm_exit); 1251 1252 MODULE_DESCRIPTION("QTI Shikra TLMM driver"); 1253 MODULE_LICENSE("GPL"); 1254