1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/platform_device.h> 9 10 #include "pinctrl-msm.h" 11 12 #define REG_SIZE 0x1000 13 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ 14 { \ 15 .grp = PINCTRL_PINGROUP("gpio" #id, \ 16 gpio##id##_pins, \ 17 ARRAY_SIZE(gpio##id##_pins)), \ 18 .funcs = (int[]){ \ 19 msm_mux_gpio, /* gpio mode */ \ 20 msm_mux_##f1, \ 21 msm_mux_##f2, \ 22 msm_mux_##f3, \ 23 msm_mux_##f4, \ 24 msm_mux_##f5, \ 25 msm_mux_##f6, \ 26 msm_mux_##f7, \ 27 msm_mux_##f8, \ 28 msm_mux_##f9, \ 29 msm_mux_##f10, \ 30 msm_mux_##f11 \ 31 }, \ 32 .nfuncs = 12, \ 33 .ctl_reg = REG_SIZE * id, \ 34 .io_reg = 0x4 + REG_SIZE * id, \ 35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 36 .intr_status_reg = 0xc + REG_SIZE * id, \ 37 .mux_bit = 2, \ 38 .pull_bit = 0, \ 39 .drv_bit = 6, \ 40 .oe_bit = 9, \ 41 .in_bit = 0, \ 42 .out_bit = 1, \ 43 .intr_enable_bit = 0, \ 44 .intr_status_bit = 0, \ 45 .intr_wakeup_enable_bit = 7, \ 46 .intr_wakeup_present_bit = 6, \ 47 .intr_target_width = 4, \ 48 .intr_target_bit = 8, \ 49 .intr_target_kpss_val = 3, \ 50 .intr_raw_status_bit = 4, \ 51 .intr_polarity_bit = 1, \ 52 .intr_detection_bit = 2, \ 53 .intr_detection_width = 2, \ 54 } 55 56 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 57 { \ 58 .grp = PINCTRL_PINGROUP(#pg_name, \ 59 pg_name##_pins, \ 60 ARRAY_SIZE(pg_name##_pins)), \ 61 .ctl_reg = ctl, \ 62 .io_reg = 0, \ 63 .intr_cfg_reg = 0, \ 64 .intr_status_reg = 0, \ 65 .mux_bit = -1, \ 66 .pull_bit = pull, \ 67 .drv_bit = drv, \ 68 .oe_bit = -1, \ 69 .in_bit = -1, \ 70 .out_bit = -1, \ 71 .intr_enable_bit = -1, \ 72 .intr_status_bit = -1, \ 73 .intr_target_bit = -1, \ 74 .intr_raw_status_bit = -1, \ 75 .intr_polarity_bit = -1, \ 76 .intr_detection_bit = -1, \ 77 .intr_detection_width = -1, \ 78 } 79 80 static const struct pinctrl_pin_desc shikra_pins[] = { 81 PINCTRL_PIN(0, "GPIO_0"), 82 PINCTRL_PIN(1, "GPIO_1"), 83 PINCTRL_PIN(2, "GPIO_2"), 84 PINCTRL_PIN(3, "GPIO_3"), 85 PINCTRL_PIN(4, "GPIO_4"), 86 PINCTRL_PIN(5, "GPIO_5"), 87 PINCTRL_PIN(6, "GPIO_6"), 88 PINCTRL_PIN(7, "GPIO_7"), 89 PINCTRL_PIN(8, "GPIO_8"), 90 PINCTRL_PIN(9, "GPIO_9"), 91 PINCTRL_PIN(10, "GPIO_10"), 92 PINCTRL_PIN(11, "GPIO_11"), 93 PINCTRL_PIN(12, "GPIO_12"), 94 PINCTRL_PIN(13, "GPIO_13"), 95 PINCTRL_PIN(14, "GPIO_14"), 96 PINCTRL_PIN(15, "GPIO_15"), 97 PINCTRL_PIN(16, "GPIO_16"), 98 PINCTRL_PIN(17, "GPIO_17"), 99 PINCTRL_PIN(18, "GPIO_18"), 100 PINCTRL_PIN(19, "GPIO_19"), 101 PINCTRL_PIN(20, "GPIO_20"), 102 PINCTRL_PIN(21, "GPIO_21"), 103 PINCTRL_PIN(22, "GPIO_22"), 104 PINCTRL_PIN(23, "GPIO_23"), 105 PINCTRL_PIN(24, "GPIO_24"), 106 PINCTRL_PIN(25, "GPIO_25"), 107 PINCTRL_PIN(26, "GPIO_26"), 108 PINCTRL_PIN(27, "GPIO_27"), 109 PINCTRL_PIN(28, "GPIO_28"), 110 PINCTRL_PIN(29, "GPIO_29"), 111 PINCTRL_PIN(30, "GPIO_30"), 112 PINCTRL_PIN(31, "GPIO_31"), 113 PINCTRL_PIN(32, "GPIO_32"), 114 PINCTRL_PIN(33, "GPIO_33"), 115 PINCTRL_PIN(34, "GPIO_34"), 116 PINCTRL_PIN(35, "GPIO_35"), 117 PINCTRL_PIN(36, "GPIO_36"), 118 PINCTRL_PIN(37, "GPIO_37"), 119 PINCTRL_PIN(38, "GPIO_38"), 120 PINCTRL_PIN(39, "GPIO_39"), 121 PINCTRL_PIN(40, "GPIO_40"), 122 PINCTRL_PIN(41, "GPIO_41"), 123 PINCTRL_PIN(42, "GPIO_42"), 124 PINCTRL_PIN(43, "GPIO_43"), 125 PINCTRL_PIN(44, "GPIO_44"), 126 PINCTRL_PIN(45, "GPIO_45"), 127 PINCTRL_PIN(46, "GPIO_46"), 128 PINCTRL_PIN(47, "GPIO_47"), 129 PINCTRL_PIN(48, "GPIO_48"), 130 PINCTRL_PIN(49, "GPIO_49"), 131 PINCTRL_PIN(50, "GPIO_50"), 132 PINCTRL_PIN(51, "GPIO_51"), 133 PINCTRL_PIN(52, "GPIO_52"), 134 PINCTRL_PIN(53, "GPIO_53"), 135 PINCTRL_PIN(54, "GPIO_54"), 136 PINCTRL_PIN(55, "GPIO_55"), 137 PINCTRL_PIN(56, "GPIO_56"), 138 PINCTRL_PIN(57, "GPIO_57"), 139 PINCTRL_PIN(58, "GPIO_58"), 140 PINCTRL_PIN(59, "GPIO_59"), 141 PINCTRL_PIN(60, "GPIO_60"), 142 PINCTRL_PIN(61, "GPIO_61"), 143 PINCTRL_PIN(62, "GPIO_62"), 144 PINCTRL_PIN(63, "GPIO_63"), 145 PINCTRL_PIN(64, "GPIO_64"), 146 PINCTRL_PIN(65, "GPIO_65"), 147 PINCTRL_PIN(66, "GPIO_66"), 148 PINCTRL_PIN(67, "GPIO_67"), 149 PINCTRL_PIN(68, "GPIO_68"), 150 PINCTRL_PIN(69, "GPIO_69"), 151 PINCTRL_PIN(70, "GPIO_70"), 152 PINCTRL_PIN(71, "GPIO_71"), 153 PINCTRL_PIN(72, "GPIO_72"), 154 PINCTRL_PIN(73, "GPIO_73"), 155 PINCTRL_PIN(74, "GPIO_74"), 156 PINCTRL_PIN(75, "GPIO_75"), 157 PINCTRL_PIN(76, "GPIO_76"), 158 PINCTRL_PIN(77, "GPIO_77"), 159 PINCTRL_PIN(78, "GPIO_78"), 160 PINCTRL_PIN(79, "GPIO_79"), 161 PINCTRL_PIN(80, "GPIO_80"), 162 PINCTRL_PIN(81, "GPIO_81"), 163 PINCTRL_PIN(82, "GPIO_82"), 164 PINCTRL_PIN(83, "GPIO_83"), 165 PINCTRL_PIN(84, "GPIO_84"), 166 PINCTRL_PIN(85, "GPIO_85"), 167 PINCTRL_PIN(86, "GPIO_86"), 168 PINCTRL_PIN(87, "GPIO_87"), 169 PINCTRL_PIN(88, "GPIO_88"), 170 PINCTRL_PIN(89, "GPIO_89"), 171 PINCTRL_PIN(90, "GPIO_90"), 172 PINCTRL_PIN(91, "GPIO_91"), 173 PINCTRL_PIN(92, "GPIO_92"), 174 PINCTRL_PIN(93, "GPIO_93"), 175 PINCTRL_PIN(94, "GPIO_94"), 176 PINCTRL_PIN(95, "GPIO_95"), 177 PINCTRL_PIN(96, "GPIO_96"), 178 PINCTRL_PIN(97, "GPIO_97"), 179 PINCTRL_PIN(98, "GPIO_98"), 180 PINCTRL_PIN(99, "GPIO_99"), 181 PINCTRL_PIN(100, "GPIO_100"), 182 PINCTRL_PIN(101, "GPIO_101"), 183 PINCTRL_PIN(102, "GPIO_102"), 184 PINCTRL_PIN(103, "GPIO_103"), 185 PINCTRL_PIN(104, "GPIO_104"), 186 PINCTRL_PIN(105, "GPIO_105"), 187 PINCTRL_PIN(106, "GPIO_106"), 188 PINCTRL_PIN(107, "GPIO_107"), 189 PINCTRL_PIN(108, "GPIO_108"), 190 PINCTRL_PIN(109, "GPIO_109"), 191 PINCTRL_PIN(110, "GPIO_110"), 192 PINCTRL_PIN(111, "GPIO_111"), 193 PINCTRL_PIN(112, "GPIO_112"), 194 PINCTRL_PIN(113, "GPIO_113"), 195 PINCTRL_PIN(114, "GPIO_114"), 196 PINCTRL_PIN(115, "GPIO_115"), 197 PINCTRL_PIN(116, "GPIO_116"), 198 PINCTRL_PIN(117, "GPIO_117"), 199 PINCTRL_PIN(118, "GPIO_118"), 200 PINCTRL_PIN(119, "GPIO_119"), 201 PINCTRL_PIN(120, "GPIO_120"), 202 PINCTRL_PIN(121, "GPIO_121"), 203 PINCTRL_PIN(122, "GPIO_122"), 204 PINCTRL_PIN(123, "GPIO_123"), 205 PINCTRL_PIN(124, "GPIO_124"), 206 PINCTRL_PIN(125, "GPIO_125"), 207 PINCTRL_PIN(126, "GPIO_126"), 208 PINCTRL_PIN(127, "GPIO_127"), 209 PINCTRL_PIN(128, "GPIO_128"), 210 PINCTRL_PIN(129, "GPIO_129"), 211 PINCTRL_PIN(130, "GPIO_130"), 212 PINCTRL_PIN(131, "GPIO_131"), 213 PINCTRL_PIN(132, "GPIO_132"), 214 PINCTRL_PIN(133, "GPIO_133"), 215 PINCTRL_PIN(134, "GPIO_134"), 216 PINCTRL_PIN(135, "GPIO_135"), 217 PINCTRL_PIN(136, "GPIO_136"), 218 PINCTRL_PIN(137, "GPIO_137"), 219 PINCTRL_PIN(138, "GPIO_138"), 220 PINCTRL_PIN(139, "GPIO_139"), 221 PINCTRL_PIN(140, "GPIO_140"), 222 PINCTRL_PIN(141, "GPIO_141"), 223 PINCTRL_PIN(142, "GPIO_142"), 224 PINCTRL_PIN(143, "GPIO_143"), 225 PINCTRL_PIN(144, "GPIO_144"), 226 PINCTRL_PIN(145, "GPIO_145"), 227 PINCTRL_PIN(146, "GPIO_146"), 228 PINCTRL_PIN(147, "GPIO_147"), 229 PINCTRL_PIN(148, "GPIO_148"), 230 PINCTRL_PIN(149, "GPIO_149"), 231 PINCTRL_PIN(150, "GPIO_150"), 232 PINCTRL_PIN(151, "GPIO_151"), 233 PINCTRL_PIN(152, "GPIO_152"), 234 PINCTRL_PIN(153, "GPIO_153"), 235 PINCTRL_PIN(154, "GPIO_154"), 236 PINCTRL_PIN(155, "GPIO_155"), 237 PINCTRL_PIN(156, "GPIO_156"), 238 PINCTRL_PIN(157, "GPIO_157"), 239 PINCTRL_PIN(158, "GPIO_158"), 240 PINCTRL_PIN(159, "GPIO_159"), 241 PINCTRL_PIN(160, "GPIO_160"), 242 PINCTRL_PIN(161, "GPIO_161"), 243 PINCTRL_PIN(162, "GPIO_162"), 244 PINCTRL_PIN(163, "GPIO_163"), 245 PINCTRL_PIN(164, "GPIO_164"), 246 PINCTRL_PIN(165, "GPIO_165"), 247 PINCTRL_PIN(166, "SDC1_RCLK"), 248 PINCTRL_PIN(167, "SDC1_CLK"), 249 PINCTRL_PIN(168, "SDC1_CMD"), 250 PINCTRL_PIN(169, "SDC1_DATA"), 251 PINCTRL_PIN(170, "SDC2_CLK"), 252 PINCTRL_PIN(171, "SDC2_CMD"), 253 PINCTRL_PIN(172, "SDC2_DATA"), 254 }; 255 256 #define DECLARE_MSM_GPIO_PINS(pin) \ 257 static const unsigned int gpio##pin##_pins[] = { pin } 258 DECLARE_MSM_GPIO_PINS(0); 259 DECLARE_MSM_GPIO_PINS(1); 260 DECLARE_MSM_GPIO_PINS(2); 261 DECLARE_MSM_GPIO_PINS(3); 262 DECLARE_MSM_GPIO_PINS(4); 263 DECLARE_MSM_GPIO_PINS(5); 264 DECLARE_MSM_GPIO_PINS(6); 265 DECLARE_MSM_GPIO_PINS(7); 266 DECLARE_MSM_GPIO_PINS(8); 267 DECLARE_MSM_GPIO_PINS(9); 268 DECLARE_MSM_GPIO_PINS(10); 269 DECLARE_MSM_GPIO_PINS(11); 270 DECLARE_MSM_GPIO_PINS(12); 271 DECLARE_MSM_GPIO_PINS(13); 272 DECLARE_MSM_GPIO_PINS(14); 273 DECLARE_MSM_GPIO_PINS(15); 274 DECLARE_MSM_GPIO_PINS(16); 275 DECLARE_MSM_GPIO_PINS(17); 276 DECLARE_MSM_GPIO_PINS(18); 277 DECLARE_MSM_GPIO_PINS(19); 278 DECLARE_MSM_GPIO_PINS(20); 279 DECLARE_MSM_GPIO_PINS(21); 280 DECLARE_MSM_GPIO_PINS(22); 281 DECLARE_MSM_GPIO_PINS(23); 282 DECLARE_MSM_GPIO_PINS(24); 283 DECLARE_MSM_GPIO_PINS(25); 284 DECLARE_MSM_GPIO_PINS(26); 285 DECLARE_MSM_GPIO_PINS(27); 286 DECLARE_MSM_GPIO_PINS(28); 287 DECLARE_MSM_GPIO_PINS(29); 288 DECLARE_MSM_GPIO_PINS(30); 289 DECLARE_MSM_GPIO_PINS(31); 290 DECLARE_MSM_GPIO_PINS(32); 291 DECLARE_MSM_GPIO_PINS(33); 292 DECLARE_MSM_GPIO_PINS(34); 293 DECLARE_MSM_GPIO_PINS(35); 294 DECLARE_MSM_GPIO_PINS(36); 295 DECLARE_MSM_GPIO_PINS(37); 296 DECLARE_MSM_GPIO_PINS(38); 297 DECLARE_MSM_GPIO_PINS(39); 298 DECLARE_MSM_GPIO_PINS(40); 299 DECLARE_MSM_GPIO_PINS(41); 300 DECLARE_MSM_GPIO_PINS(42); 301 DECLARE_MSM_GPIO_PINS(43); 302 DECLARE_MSM_GPIO_PINS(44); 303 DECLARE_MSM_GPIO_PINS(45); 304 DECLARE_MSM_GPIO_PINS(46); 305 DECLARE_MSM_GPIO_PINS(47); 306 DECLARE_MSM_GPIO_PINS(48); 307 DECLARE_MSM_GPIO_PINS(49); 308 DECLARE_MSM_GPIO_PINS(50); 309 DECLARE_MSM_GPIO_PINS(51); 310 DECLARE_MSM_GPIO_PINS(52); 311 DECLARE_MSM_GPIO_PINS(53); 312 DECLARE_MSM_GPIO_PINS(54); 313 DECLARE_MSM_GPIO_PINS(55); 314 DECLARE_MSM_GPIO_PINS(56); 315 DECLARE_MSM_GPIO_PINS(57); 316 DECLARE_MSM_GPIO_PINS(58); 317 DECLARE_MSM_GPIO_PINS(59); 318 DECLARE_MSM_GPIO_PINS(60); 319 DECLARE_MSM_GPIO_PINS(61); 320 DECLARE_MSM_GPIO_PINS(62); 321 DECLARE_MSM_GPIO_PINS(63); 322 DECLARE_MSM_GPIO_PINS(64); 323 DECLARE_MSM_GPIO_PINS(65); 324 DECLARE_MSM_GPIO_PINS(66); 325 DECLARE_MSM_GPIO_PINS(67); 326 DECLARE_MSM_GPIO_PINS(68); 327 DECLARE_MSM_GPIO_PINS(69); 328 DECLARE_MSM_GPIO_PINS(70); 329 DECLARE_MSM_GPIO_PINS(71); 330 DECLARE_MSM_GPIO_PINS(72); 331 DECLARE_MSM_GPIO_PINS(73); 332 DECLARE_MSM_GPIO_PINS(74); 333 DECLARE_MSM_GPIO_PINS(75); 334 DECLARE_MSM_GPIO_PINS(76); 335 DECLARE_MSM_GPIO_PINS(77); 336 DECLARE_MSM_GPIO_PINS(78); 337 DECLARE_MSM_GPIO_PINS(79); 338 DECLARE_MSM_GPIO_PINS(80); 339 DECLARE_MSM_GPIO_PINS(81); 340 DECLARE_MSM_GPIO_PINS(82); 341 DECLARE_MSM_GPIO_PINS(83); 342 DECLARE_MSM_GPIO_PINS(84); 343 DECLARE_MSM_GPIO_PINS(85); 344 DECLARE_MSM_GPIO_PINS(86); 345 DECLARE_MSM_GPIO_PINS(87); 346 DECLARE_MSM_GPIO_PINS(88); 347 DECLARE_MSM_GPIO_PINS(89); 348 DECLARE_MSM_GPIO_PINS(90); 349 DECLARE_MSM_GPIO_PINS(91); 350 DECLARE_MSM_GPIO_PINS(92); 351 DECLARE_MSM_GPIO_PINS(93); 352 DECLARE_MSM_GPIO_PINS(94); 353 DECLARE_MSM_GPIO_PINS(95); 354 DECLARE_MSM_GPIO_PINS(96); 355 DECLARE_MSM_GPIO_PINS(97); 356 DECLARE_MSM_GPIO_PINS(98); 357 DECLARE_MSM_GPIO_PINS(99); 358 DECLARE_MSM_GPIO_PINS(100); 359 DECLARE_MSM_GPIO_PINS(101); 360 DECLARE_MSM_GPIO_PINS(102); 361 DECLARE_MSM_GPIO_PINS(103); 362 DECLARE_MSM_GPIO_PINS(104); 363 DECLARE_MSM_GPIO_PINS(105); 364 DECLARE_MSM_GPIO_PINS(106); 365 DECLARE_MSM_GPIO_PINS(107); 366 DECLARE_MSM_GPIO_PINS(108); 367 DECLARE_MSM_GPIO_PINS(109); 368 DECLARE_MSM_GPIO_PINS(110); 369 DECLARE_MSM_GPIO_PINS(111); 370 DECLARE_MSM_GPIO_PINS(112); 371 DECLARE_MSM_GPIO_PINS(113); 372 DECLARE_MSM_GPIO_PINS(114); 373 DECLARE_MSM_GPIO_PINS(115); 374 DECLARE_MSM_GPIO_PINS(116); 375 DECLARE_MSM_GPIO_PINS(117); 376 DECLARE_MSM_GPIO_PINS(118); 377 DECLARE_MSM_GPIO_PINS(119); 378 DECLARE_MSM_GPIO_PINS(120); 379 DECLARE_MSM_GPIO_PINS(121); 380 DECLARE_MSM_GPIO_PINS(122); 381 DECLARE_MSM_GPIO_PINS(123); 382 DECLARE_MSM_GPIO_PINS(124); 383 DECLARE_MSM_GPIO_PINS(125); 384 DECLARE_MSM_GPIO_PINS(126); 385 DECLARE_MSM_GPIO_PINS(127); 386 DECLARE_MSM_GPIO_PINS(128); 387 DECLARE_MSM_GPIO_PINS(129); 388 DECLARE_MSM_GPIO_PINS(130); 389 DECLARE_MSM_GPIO_PINS(131); 390 DECLARE_MSM_GPIO_PINS(132); 391 DECLARE_MSM_GPIO_PINS(133); 392 DECLARE_MSM_GPIO_PINS(134); 393 DECLARE_MSM_GPIO_PINS(135); 394 DECLARE_MSM_GPIO_PINS(136); 395 DECLARE_MSM_GPIO_PINS(137); 396 DECLARE_MSM_GPIO_PINS(138); 397 DECLARE_MSM_GPIO_PINS(139); 398 DECLARE_MSM_GPIO_PINS(140); 399 DECLARE_MSM_GPIO_PINS(141); 400 DECLARE_MSM_GPIO_PINS(142); 401 DECLARE_MSM_GPIO_PINS(143); 402 DECLARE_MSM_GPIO_PINS(144); 403 DECLARE_MSM_GPIO_PINS(145); 404 DECLARE_MSM_GPIO_PINS(146); 405 DECLARE_MSM_GPIO_PINS(147); 406 DECLARE_MSM_GPIO_PINS(148); 407 DECLARE_MSM_GPIO_PINS(149); 408 DECLARE_MSM_GPIO_PINS(150); 409 DECLARE_MSM_GPIO_PINS(151); 410 DECLARE_MSM_GPIO_PINS(152); 411 DECLARE_MSM_GPIO_PINS(153); 412 DECLARE_MSM_GPIO_PINS(154); 413 DECLARE_MSM_GPIO_PINS(155); 414 DECLARE_MSM_GPIO_PINS(156); 415 DECLARE_MSM_GPIO_PINS(157); 416 DECLARE_MSM_GPIO_PINS(158); 417 DECLARE_MSM_GPIO_PINS(159); 418 DECLARE_MSM_GPIO_PINS(160); 419 DECLARE_MSM_GPIO_PINS(161); 420 DECLARE_MSM_GPIO_PINS(162); 421 DECLARE_MSM_GPIO_PINS(163); 422 DECLARE_MSM_GPIO_PINS(164); 423 DECLARE_MSM_GPIO_PINS(165); 424 425 static const unsigned int sdc1_rclk_pins[] = { 166 }; 426 static const unsigned int sdc1_clk_pins[] = { 167 }; 427 static const unsigned int sdc1_cmd_pins[] = { 168 }; 428 static const unsigned int sdc1_data_pins[] = { 169 }; 429 static const unsigned int sdc2_clk_pins[] = { 170 }; 430 static const unsigned int sdc2_cmd_pins[] = { 171 }; 431 static const unsigned int sdc2_data_pins[] = { 172 }; 432 433 enum shikra_functions { 434 msm_mux_gpio, 435 msm_mux_agera_pll, 436 msm_mux_atest_bbrx, 437 msm_mux_atest_char, 438 msm_mux_atest_gpsadc, 439 msm_mux_atest_tsens, 440 msm_mux_atest_usb, 441 msm_mux_cam_mclk, 442 msm_mux_cci_async, 443 msm_mux_cci_i2c0, 444 msm_mux_cci_i2c1, 445 msm_mux_cci_timer, 446 msm_mux_char_exec, 447 msm_mux_cri_trng, 448 msm_mux_dac_calib, 449 msm_mux_dbg_out_clk, 450 msm_mux_ddr_bist, 451 msm_mux_ddr_pxi, 452 msm_mux_dmic, 453 msm_mux_emac_dll, 454 msm_mux_emac_mcg, 455 msm_mux_emac_phy, 456 msm_mux_emac0_ptp_aux, 457 msm_mux_emac0_ptp_pps, 458 msm_mux_emac1_ptp_aux, 459 msm_mux_emac1_ptp_pps, 460 msm_mux_ext_mclk, 461 msm_mux_gcc_gp, 462 msm_mux_gsm0_tx, 463 msm_mux_i2s0, 464 msm_mux_i2s1, 465 msm_mux_i2s2, 466 msm_mux_i2s3, 467 msm_mux_jitter_bist, 468 msm_mux_m_voc, 469 msm_mux_mdp_vsync_e, 470 msm_mux_mdp_vsync_out0, 471 msm_mux_mdp_vsync_out1, 472 msm_mux_mdp_vsync_p, 473 msm_mux_mdp_vsync_s, 474 msm_mux_mpm_pwr, 475 msm_mux_mss_lte, 476 msm_mux_nav_gpio, 477 msm_mux_pa_indicator_or, 478 msm_mux_pbs_in, 479 msm_mux_pbs_out, 480 msm_mux_pcie0_clk_req_n, 481 msm_mux_phase_flag, 482 msm_mux_pll, 483 msm_mux_prng_rosc, 484 msm_mux_pwm, 485 msm_mux_qdss_cti, 486 msm_mux_qup0_se0, 487 msm_mux_qup0_se1, 488 msm_mux_qup0_se1_01, 489 msm_mux_qup0_se1_23, 490 msm_mux_qup0_se2, 491 msm_mux_qup0_se3_01, 492 msm_mux_qup0_se3_23, 493 msm_mux_qup0_se4_01, 494 msm_mux_qup0_se4_23, 495 msm_mux_qup0_se5, 496 msm_mux_qup0_se6, 497 msm_mux_qup0_se7_01, 498 msm_mux_qup0_se7_23, 499 msm_mux_qup0_se8, 500 msm_mux_qup0_se9, 501 msm_mux_qup0_se9_01, 502 msm_mux_qup0_se9_23, 503 msm_mux_rgmii, 504 msm_mux_sd_write_protect, 505 msm_mux_sdc_cdc, 506 msm_mux_sdc_tb_trig, 507 msm_mux_ssbi_wtr, 508 msm_mux_swr0_rx, 509 msm_mux_swr0_tx, 510 msm_mux_tgu_ch_trigout, 511 msm_mux_tsc_async, 512 msm_mux_tsense_pwm, 513 msm_mux_uim1, 514 msm_mux_uim2, 515 msm_mux_unused_adsp, 516 msm_mux_unused_gsm1, 517 msm_mux_usb0_phy_ps, 518 msm_mux_vfr, 519 msm_mux_vsense_trigger_mirnat, 520 msm_mux_wlan, 521 msm_mux__, 522 }; 523 524 static const char *const gpio_groups[] = { 525 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 526 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", 527 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", 528 "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", 529 "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 530 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 531 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", 532 "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", 533 "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", 534 "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", 535 "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", 536 "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", 537 "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 538 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", 539 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", 540 "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", 541 "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", 542 "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", 543 "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", 544 "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", 545 "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", 546 "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", 547 "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", 548 "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", 549 "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", 550 "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", 551 "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", 552 "gpio162", "gpio163", "gpio164", "gpio165", 553 }; 554 555 static const char *const agera_pll_groups[] = { 556 "gpio22", "gpio23", 557 }; 558 559 static const char *const atest_bbrx_groups[] = { 560 "gpio58", "gpio59", 561 }; 562 563 static const char *const atest_char_groups[] = { 564 "gpio56", "gpio57", "gpio54", "gpio55", "gpio62", 565 }; 566 567 static const char *const atest_gpsadc_groups[] = { 568 "gpio60", "gpio96", 569 }; 570 571 static const char *const atest_tsens_groups[] = { 572 "gpio1", "gpio2", 573 }; 574 575 static const char *const atest_usb_groups[] = { 576 "gpio53", "gpio58", "gpio59", "gpio60", "gpio61", "gpio96", 577 "gpio98", "gpio99", "gpio100", "gpio101", 578 }; 579 580 static const char *const cam_mclk_groups[] = { 581 "gpio34", "gpio35", "gpio96", "gpio98", 582 }; 583 584 static const char *const cci_async_groups[] = { 585 "gpio39", 586 }; 587 588 static const char *const cci_i2c0_groups[] = { 589 "gpio36", "gpio37", 590 }; 591 592 static const char *const cci_i2c1_groups[] = { 593 "gpio41", "gpio42", 594 }; 595 596 static const char *const cci_timer_groups[] = { 597 "gpio38", "gpio40", "gpio43", "gpio47", 598 }; 599 600 static const char *const char_exec_groups[] = { 601 "gpio12", "gpio13", 602 }; 603 604 static const char *const cri_trng_groups[] = { 605 "gpio6", "gpio7", "gpio20", 606 }; 607 608 static const char *const dac_calib_groups[] = { 609 "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", 610 "gpio9", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", 611 "gpio19", "gpio63", "gpio64", "gpio66", "gpio68", "gpio69", 612 "gpio70", "gpio88", "gpio89", "gpio90", "gpio97", "gpio116", 613 "gpio117", "gpio118", 614 }; 615 616 static const char *const dbg_out_clk_groups[] = { 617 "gpio61", 618 }; 619 620 static const char *const ddr_bist_groups[] = { 621 "gpio1", "gpio2", "gpio3", "gpio4", 622 }; 623 624 static const char *const ddr_pxi_groups[] = { 625 "gpio98", "gpio99", "gpio100", "gpio101", 626 }; 627 628 static const char *const dmic_groups[] = { 629 "gpio96", "gpio97", "gpio98", "gpio99", 630 }; 631 632 static const char *const emac_dll_groups[] = { 633 "gpio58", "gpio59", "gpio60", "gpio61", 634 }; 635 636 static const char *const emac_mcg_groups[] = { 637 "gpio28", "gpio29", "gpio40", "gpio43", "gpio44", "gpio45", 638 "gpio46", "gpio47", 639 }; 640 641 static const char *const emac_phy_groups[] = { 642 "gpio120", "gpio136", 643 }; 644 645 static const char *const emac0_ptp_aux_groups[] = { 646 "gpio60", "gpio63", "gpio69", "gpio85", 647 }; 648 649 static const char *const emac0_ptp_pps_groups[] = { 650 "gpio60", "gpio63", "gpio69", "gpio85", 651 }; 652 653 static const char *const emac1_ptp_aux_groups[] = { 654 "gpio31", "gpio33", "gpio60", "gpio68", 655 }; 656 657 static const char *const emac1_ptp_pps_groups[] = { 658 "gpio31", "gpio33", "gpio60", "gpio68", 659 }; 660 661 static const char *const ext_mclk_groups[] = { 662 "gpio103", "gpio104", "gpio110", "gpio114", 663 }; 664 665 static const char *const gcc_gp_groups[] = { 666 "gpio45", "gpio53", "gpio61", "gpio88", "gpio89", "gpio110", 667 }; 668 669 static const char *const gsm0_tx_groups[] = { 670 "gpio75", 671 }; 672 673 static const char *const i2s0_groups[] = { 674 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 675 }; 676 677 static const char *const i2s1_groups[] = { 678 "gpio96", "gpio97", "gpio98", "gpio99", 679 }; 680 681 static const char *const i2s2_groups[] = { 682 "gpio100", "gpio101", "gpio102", "gpio103", 683 }; 684 685 static const char *const i2s3_groups[] = { 686 "gpio111", "gpio112", "gpio113", "gpio114", 687 }; 688 689 static const char *const jitter_bist_groups[] = { 690 "gpio96", "gpio99", 691 }; 692 693 static const char *const m_voc_groups[] = { 694 "gpio0", 695 }; 696 697 static const char *const mdp_vsync_e_groups[] = { 698 "gpio94", 699 }; 700 701 static const char *const mdp_vsync_out0_groups[] = { 702 "gpio86", 703 }; 704 705 static const char *const mdp_vsync_out1_groups[] = { 706 "gpio86", 707 }; 708 709 static const char *const mdp_vsync_p_groups[] = { 710 "gpio86", 711 }; 712 713 static const char *const mdp_vsync_s_groups[] = { 714 "gpio95", 715 }; 716 717 static const char *const mpm_pwr_groups[] = { 718 "gpio1", 719 }; 720 721 static const char *const mss_lte_groups[] = { 722 "gpio115", "gpio116", 723 }; 724 725 static const char *const nav_gpio_groups[] = { 726 "gpio53", "gpio58", "gpio63", "gpio71", "gpio91", "gpio92", 727 "gpio95", "gpio100", "gpio101", "gpio104", 728 }; 729 730 static const char *const pa_indicator_or_groups[] = { 731 "gpio61", 732 }; 733 734 static const char *const pbs_in_groups[] = { 735 "gpio48", "gpio49", "gpio50", "gpio51", "gpio53", "gpio54", 736 "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", 737 "gpio61", "gpio62", "gpio63", "gpio74", 738 }; 739 740 static const char *const pbs_out_groups[] = { 741 "gpio22", "gpio23", "gpio24", 742 }; 743 744 static const char *const pcie0_clk_req_n_groups[] = { 745 "gpio117", 746 }; 747 748 static const char *const phase_flag_groups[] = { 749 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 750 "gpio6", "gpio7", "gpio8", "gpio9", "gpio11", "gpio16", 751 "gpio17", "gpio28", "gpio29", "gpio30", "gpio31", "gpio48", 752 "gpio49", "gpio50", "gpio54", "gpio55", "gpio56", "gpio57", 753 "gpio62", "gpio63", "gpio64", "gpio69", "gpio70", "gpio71", 754 "gpio72", "gpio74", "gpio102", 755 }; 756 757 static const char *const pll_groups[] = { 758 "gpio14", "gpio22", "gpio43", "gpio44", "gpio74", "gpio76", 759 }; 760 761 static const char *const prng_rosc_groups[] = { 762 "gpio27", "gpio28", 763 }; 764 765 static const char *const pwm_groups[] = { 766 "gpio32", "gpio40", "gpio45", "gpio53", "gpio54", "gpio55", 767 "gpio56", "gpio57", "gpio58", "gpio61", "gpio62", "gpio68", 768 "gpio77", "gpio79", "gpio80", "gpio87", "gpio102" 769 }; 770 771 static const char *const qdss_cti_groups[] = { 772 "gpio28", "gpio29", "gpio30", "gpio31", "gpio94", "gpio95", 773 }; 774 775 static const char *const qup0_se0_groups[] = { 776 "gpio0", "gpio1", "gpio2", "gpio3", 777 }; 778 779 static const char *const qup0_se1_groups[] = { 780 "gpio28", "gpio29", 781 }; 782 783 static const char *const qup0_se1_01_groups[] = { 784 "gpio4", "gpio5", 785 }; 786 787 static const char *const qup0_se1_23_groups[] = { 788 "gpio4", "gpio5", 789 }; 790 791 static const char *const qup0_se2_groups[] = { 792 "gpio6", "gpio7", "gpio8", "gpio9", "gpio30", "gpio31", 793 }; 794 795 static const char *const qup0_se3_01_groups[] = { 796 "gpio10", "gpio11", 797 }; 798 799 static const char *const qup0_se3_23_groups[] = { 800 "gpio10", "gpio11", 801 }; 802 803 static const char *const qup0_se4_01_groups[] = { 804 "gpio12", "gpio13", 805 }; 806 807 static const char *const qup0_se4_23_groups[] = { 808 "gpio12", "gpio13", 809 }; 810 811 static const char *const qup0_se5_groups[] = { 812 "gpio14", "gpio15", "gpio16", "gpio17", 813 }; 814 815 static const char *const qup0_se6_groups[] = { 816 "gpio18", "gpio19", "gpio28", "gpio29", "gpio30", "gpio31", 817 }; 818 819 static const char *const qup0_se7_01_groups[] = { 820 "gpio20", "gpio21", 821 }; 822 823 static const char *const qup0_se7_23_groups[] = { 824 "gpio20", "gpio21", 825 }; 826 827 static const char *const qup0_se8_groups[] = { 828 "gpio22", "gpio23", "gpio24", "gpio25", 829 }; 830 831 static const char *const qup0_se9_groups[] = { 832 "gpio48", "gpio49", "gpio50", "gpio51", 833 }; 834 835 static const char *const qup0_se9_01_groups[] = { 836 "gpio26", "gpio27", 837 }; 838 839 static const char *const qup0_se9_23_groups[] = { 840 "gpio26", "gpio27", 841 }; 842 843 static const char *const rgmii_groups[] = { 844 "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", 845 "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", 846 "gpio133", "gpio134", "gpio137", "gpio138", "gpio139", "gpio140", 847 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", 848 "gpio147", "gpio148", "gpio149", "gpio150", 849 }; 850 851 static const char *const sd_write_protect_groups[] = { 852 "gpio109", 853 }; 854 855 static const char *const sdc_cdc_groups[] = { 856 "gpio98", "gpio99", "gpio100", "gpio101", 857 }; 858 859 static const char *const sdc_tb_trig_groups[] = { 860 "gpio32", "gpio33", 861 }; 862 863 static const char *const ssbi_wtr_groups[] = { 864 "gpio68", "gpio69", "gpio70", "gpio71", 865 }; 866 867 static const char *const swr0_rx_groups[] = { 868 "gpio107", "gpio108", "gpio109", 869 }; 870 871 static const char *const swr0_tx_groups[] = { 872 "gpio105", "gpio106", 873 }; 874 875 static const char *const tgu_ch_trigout_groups[] = { 876 "gpio14", "gpio15", "gpio16", "gpio17", 877 }; 878 879 static const char *const tsc_async_groups[] = { 880 "gpio45", "gpio46", 881 }; 882 883 static const char *const tsense_pwm_groups[] = { 884 "gpio21", 885 }; 886 887 static const char *const uim1_groups[] = { 888 "gpio81", "gpio82", "gpio83", "gpio84", 889 }; 890 891 static const char *const uim2_groups[] = { 892 "gpio77", "gpio78", "gpio79", "gpio80", 893 }; 894 895 static const char *const unused_adsp_groups[] = { 896 "gpio35", 897 }; 898 899 static const char *const unused_gsm1_groups[] = { 900 "gpio64", 901 }; 902 903 static const char *const usb0_phy_ps_groups[] = { 904 "gpio90", 905 }; 906 907 static const char *const vfr_groups[] = { 908 "gpio59", 909 }; 910 911 static const char *const vsense_trigger_mirnat_groups[] = { 912 "gpio58", 913 }; 914 915 static const char *const wlan_groups[] = { 916 "gpio14", "gpio15", 917 }; 918 919 static const struct pinfunction shikra_functions[] = { 920 MSM_GPIO_PIN_FUNCTION(gpio), 921 MSM_PIN_FUNCTION(agera_pll), 922 MSM_PIN_FUNCTION(atest_bbrx), 923 MSM_PIN_FUNCTION(atest_char), 924 MSM_PIN_FUNCTION(atest_gpsadc), 925 MSM_PIN_FUNCTION(atest_tsens), 926 MSM_PIN_FUNCTION(atest_usb), 927 MSM_PIN_FUNCTION(cam_mclk), 928 MSM_PIN_FUNCTION(cci_async), 929 MSM_PIN_FUNCTION(cci_i2c0), 930 MSM_PIN_FUNCTION(cci_i2c1), 931 MSM_PIN_FUNCTION(cci_timer), 932 MSM_PIN_FUNCTION(char_exec), 933 MSM_PIN_FUNCTION(cri_trng), 934 MSM_PIN_FUNCTION(dac_calib), 935 MSM_PIN_FUNCTION(dbg_out_clk), 936 MSM_PIN_FUNCTION(ddr_bist), 937 MSM_PIN_FUNCTION(ddr_pxi), 938 MSM_PIN_FUNCTION(dmic), 939 MSM_PIN_FUNCTION(emac_dll), 940 MSM_PIN_FUNCTION(emac_mcg), 941 MSM_PIN_FUNCTION(emac_phy), 942 MSM_PIN_FUNCTION(emac0_ptp_aux), 943 MSM_PIN_FUNCTION(emac0_ptp_pps), 944 MSM_PIN_FUNCTION(emac1_ptp_aux), 945 MSM_PIN_FUNCTION(emac1_ptp_pps), 946 MSM_PIN_FUNCTION(ext_mclk), 947 MSM_PIN_FUNCTION(gcc_gp), 948 MSM_PIN_FUNCTION(gsm0_tx), 949 MSM_PIN_FUNCTION(i2s0), 950 MSM_PIN_FUNCTION(i2s1), 951 MSM_PIN_FUNCTION(i2s2), 952 MSM_PIN_FUNCTION(i2s3), 953 MSM_PIN_FUNCTION(jitter_bist), 954 MSM_PIN_FUNCTION(m_voc), 955 MSM_PIN_FUNCTION(mdp_vsync_e), 956 MSM_PIN_FUNCTION(mdp_vsync_out0), 957 MSM_PIN_FUNCTION(mdp_vsync_out1), 958 MSM_PIN_FUNCTION(mdp_vsync_p), 959 MSM_PIN_FUNCTION(mdp_vsync_s), 960 MSM_PIN_FUNCTION(mpm_pwr), 961 MSM_PIN_FUNCTION(mss_lte), 962 MSM_PIN_FUNCTION(nav_gpio), 963 MSM_PIN_FUNCTION(pa_indicator_or), 964 MSM_PIN_FUNCTION(pbs_in), 965 MSM_PIN_FUNCTION(pbs_out), 966 MSM_PIN_FUNCTION(pcie0_clk_req_n), 967 MSM_PIN_FUNCTION(phase_flag), 968 MSM_PIN_FUNCTION(pll), 969 MSM_PIN_FUNCTION(prng_rosc), 970 MSM_PIN_FUNCTION(pwm), 971 MSM_PIN_FUNCTION(qdss_cti), 972 MSM_PIN_FUNCTION(qup0_se0), 973 MSM_PIN_FUNCTION(qup0_se1), 974 MSM_PIN_FUNCTION(qup0_se1_01), 975 MSM_PIN_FUNCTION(qup0_se1_23), 976 MSM_PIN_FUNCTION(qup0_se2), 977 MSM_PIN_FUNCTION(qup0_se3_01), 978 MSM_PIN_FUNCTION(qup0_se3_23), 979 MSM_PIN_FUNCTION(qup0_se4_01), 980 MSM_PIN_FUNCTION(qup0_se4_23), 981 MSM_PIN_FUNCTION(qup0_se5), 982 MSM_PIN_FUNCTION(qup0_se6), 983 MSM_PIN_FUNCTION(qup0_se7_01), 984 MSM_PIN_FUNCTION(qup0_se7_23), 985 MSM_PIN_FUNCTION(qup0_se8), 986 MSM_PIN_FUNCTION(qup0_se9), 987 MSM_PIN_FUNCTION(qup0_se9_01), 988 MSM_PIN_FUNCTION(qup0_se9_23), 989 MSM_PIN_FUNCTION(rgmii), 990 MSM_PIN_FUNCTION(sd_write_protect), 991 MSM_PIN_FUNCTION(sdc_cdc), 992 MSM_PIN_FUNCTION(sdc_tb_trig), 993 MSM_PIN_FUNCTION(ssbi_wtr), 994 MSM_PIN_FUNCTION(swr0_rx), 995 MSM_PIN_FUNCTION(swr0_tx), 996 MSM_PIN_FUNCTION(tgu_ch_trigout), 997 MSM_PIN_FUNCTION(tsc_async), 998 MSM_PIN_FUNCTION(tsense_pwm), 999 MSM_PIN_FUNCTION(uim1), 1000 MSM_PIN_FUNCTION(uim2), 1001 MSM_PIN_FUNCTION(unused_adsp), 1002 MSM_PIN_FUNCTION(unused_gsm1), 1003 MSM_PIN_FUNCTION(usb0_phy_ps), 1004 MSM_PIN_FUNCTION(vfr), 1005 MSM_PIN_FUNCTION(vsense_trigger_mirnat), 1006 MSM_PIN_FUNCTION(wlan), 1007 }; 1008 1009 static const struct msm_pingroup shikra_groups[] = { 1010 [0] = PINGROUP(0, qup0_se0, m_voc, _, phase_flag, _, _, _, _, _, _, _), 1011 [1] = PINGROUP(1, qup0_se0, mpm_pwr, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _), 1012 [2] = PINGROUP(2, qup0_se0, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _, _), 1013 [3] = PINGROUP(3, qup0_se0, ddr_bist, _, phase_flag, dac_calib, _, _, _, _, _, _), 1014 [4] = PINGROUP(4, qup0_se1_23, qup0_se1_01, ddr_bist, _, phase_flag, dac_calib, _, _, _, 1015 _, _), 1016 [5] = PINGROUP(5, qup0_se1_23, qup0_se1_01, _, phase_flag, dac_calib, _, _, _, _, _, _), 1017 [6] = PINGROUP(6, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _), 1018 [7] = PINGROUP(7, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _), 1019 [8] = PINGROUP(8, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _), 1020 [9] = PINGROUP(9, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _), 1021 [10] = PINGROUP(10, qup0_se3_01, qup0_se3_23, _, _, _, _, _, _, _, _, _), 1022 [11] = PINGROUP(11, qup0_se3_01, qup0_se3_23, _, phase_flag, _, _, _, _, _, _, _), 1023 [12] = PINGROUP(12, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _), 1024 [13] = PINGROUP(13, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _), 1025 [14] = PINGROUP(14, qup0_se5, pll, tgu_ch_trigout, dac_calib, wlan, _, _, _, _, _, _), 1026 [15] = PINGROUP(15, qup0_se5, tgu_ch_trigout, _, dac_calib, wlan, _, _, _, _, _, _), 1027 [16] = PINGROUP(16, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _), 1028 [17] = PINGROUP(17, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _), 1029 [18] = PINGROUP(18, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _), 1030 [19] = PINGROUP(19, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _), 1031 [20] = PINGROUP(20, qup0_se7_01, qup0_se7_23, cri_trng, _, _, _, _, _, _, _, _), 1032 [21] = PINGROUP(21, qup0_se7_01, qup0_se7_23, tsense_pwm, _, _, _, _, _, _, _, _), 1033 [22] = PINGROUP(22, qup0_se8, pll, agera_pll, pbs_out, _, _, _, _, _, _, _), 1034 [23] = PINGROUP(23, qup0_se8, agera_pll, pbs_out, _, _, _, _, _, _, _, _), 1035 [24] = PINGROUP(24, qup0_se8, pbs_out, _, _, _, _, _, _, _, _, _), 1036 [25] = PINGROUP(25, qup0_se8, _, _, _, _, _, _, _, _, _, _), 1037 [26] = PINGROUP(26, qup0_se9_23, qup0_se9_01, _, _, _, _, _, _, _, _, _), 1038 [27] = PINGROUP(27, qup0_se9_23, qup0_se9_01, prng_rosc, _, _, _, _, _, _, _, _), 1039 [28] = PINGROUP(28, qup0_se1, qup0_se6, emac_mcg, prng_rosc, _, phase_flag, qdss_cti, 1040 _, _, _, _), 1041 [29] = PINGROUP(29, qup0_se1, qup0_se6, emac_mcg, _, phase_flag, qdss_cti, _, _, _, _, _), 1042 [30] = PINGROUP(30, qup0_se2, qup0_se6, _, phase_flag, qdss_cti, _, _, _, _, _, _), 1043 [31] = PINGROUP(31, qup0_se2, qup0_se6, emac1_ptp_aux, emac1_ptp_pps, _, phase_flag, 1044 qdss_cti, _, _, _, _), 1045 [32] = PINGROUP(32, pwm, sdc_tb_trig, _, _, _, _, _, _, _, _, _), 1046 [33] = PINGROUP(33, emac1_ptp_aux, emac1_ptp_pps, sdc_tb_trig, _, _, _, _, _, _, _, _), 1047 [34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _, _, _, _, _), 1048 [35] = PINGROUP(35, cam_mclk, unused_adsp, _, _, _, _, _, _, _, _, _), 1049 [36] = PINGROUP(36, cci_i2c0, _, _, _, _, _, _, _, _, _, _), 1050 [37] = PINGROUP(37, cci_i2c0, _, _, _, _, _, _, _, _, _, _), 1051 [38] = PINGROUP(38, cci_timer, _, _, _, _, _, _, _, _, _, _), 1052 [39] = PINGROUP(39, cci_async, _, _, _, _, _, _, _, _, _, _), 1053 [40] = PINGROUP(40, cci_timer, emac_mcg, pwm, _, _, _, _, _, _, _, _), 1054 [41] = PINGROUP(41, cci_i2c1, _, _, _, _, _, _, _, _, _, _), 1055 [42] = PINGROUP(42, cci_i2c1, _, _, _, _, _, _, _, _, _, _), 1056 [43] = PINGROUP(43, cci_timer, emac_mcg, pll, _, _, _, _, _, _, _, _), 1057 [44] = PINGROUP(44, emac_mcg, pll, _, _, _, _, _, _, _, _, _), 1058 [45] = PINGROUP(45, tsc_async, emac_mcg, pwm, gcc_gp, _, _, _, _, _, _, _), 1059 [46] = PINGROUP(46, tsc_async, emac_mcg, _, _, _, _, _, _, _, _, _), 1060 [47] = PINGROUP(47, cci_timer, emac_mcg, _, _, _, _, _, _, _, _, _), 1061 [48] = PINGROUP(48, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), 1062 [49] = PINGROUP(49, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), 1063 [50] = PINGROUP(50, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), 1064 [51] = PINGROUP(51, _, qup0_se9, pbs_in, _, _, _, _, _, _, _, _), 1065 [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _, _, _), 1066 [53] = PINGROUP(53, _, nav_gpio, gcc_gp, pwm, _, pbs_in, atest_usb, _, _, _, _), 1067 [54] = PINGROUP(54, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), 1068 [55] = PINGROUP(55, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), 1069 [56] = PINGROUP(56, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), 1070 [57] = PINGROUP(57, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), 1071 [58] = PINGROUP(58, _, nav_gpio, pwm, _, pbs_in, atest_bbrx, atest_usb, 1072 vsense_trigger_mirnat, emac_dll, _, _), 1073 [59] = PINGROUP(59, _, vfr, _, pbs_in, atest_bbrx, atest_usb, emac_dll, _, _, _, _), 1074 [60] = PINGROUP(60, _, emac1_ptp_aux, emac1_ptp_pps, emac0_ptp_aux, emac0_ptp_pps, _, 1075 pbs_in, atest_gpsadc, atest_usb, emac_dll, _), 1076 [61] = PINGROUP(61, _, pwm, gcc_gp, pa_indicator_or, dbg_out_clk, pbs_in, atest_usb, 1077 emac_dll, _, _, _), 1078 [62] = PINGROUP(62, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), 1079 [63] = PINGROUP(63, _, nav_gpio, emac0_ptp_aux, emac0_ptp_pps, _, pbs_in, phase_flag, 1080 dac_calib, _, _, _), 1081 [64] = PINGROUP(64, _, unused_gsm1, dac_calib, _, _, _, _, _, _, _, _), 1082 [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _, _, _), 1083 [66] = PINGROUP(66, _, dac_calib, _, _, _, _, _, _, _, _, _), 1084 [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _, _, _), 1085 [68] = PINGROUP(68, _, ssbi_wtr, emac1_ptp_aux, emac1_ptp_pps, pwm, dac_calib, _, _, _, 1086 _, _), 1087 [69] = PINGROUP(69, _, ssbi_wtr, emac0_ptp_aux, emac0_ptp_pps, _, phase_flag, dac_calib, 1088 _, _, _, _), 1089 [70] = PINGROUP(70, _, ssbi_wtr, _, phase_flag, dac_calib, _, _, _, _, _, _), 1090 [71] = PINGROUP(71, _, ssbi_wtr, nav_gpio, _, phase_flag, _, _, _, _, _, _), 1091 [72] = PINGROUP(72, _, _, phase_flag, _, _, _, _, _, _, _, _), 1092 [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _, _), 1093 [74] = PINGROUP(74, pll, _, pbs_in, phase_flag, _, _, _, _, _, _, _), 1094 [75] = PINGROUP(75, gsm0_tx, _, _, _, _, _, _, _, _, _, _), 1095 [76] = PINGROUP(76, pll, _, _, _, _, _, _, _, _, _, _), 1096 [77] = PINGROUP(77, uim2, pwm, _, _, _, _, _, _, _, _, _), 1097 [78] = PINGROUP(78, uim2, _, _, _, _, _, _, _, _, _, _), 1098 [79] = PINGROUP(79, uim2, pwm, _, _, _, _, _, _, _, _, _), 1099 [80] = PINGROUP(80, uim2, pwm, _, _, _, _, _, _, _, _, _), 1100 [81] = PINGROUP(81, uim1, _, _, _, _, _, _, _, _, _, _), 1101 [82] = PINGROUP(82, uim1, _, _, _, _, _, _, _, _, _, _), 1102 [83] = PINGROUP(83, uim1, _, _, _, _, _, _, _, _, _, _), 1103 [84] = PINGROUP(84, uim1, _, _, _, _, _, _, _, _, _, _), 1104 [85] = PINGROUP(85, emac0_ptp_aux, emac0_ptp_pps, _, _, _, _, _, _, _, _, _), 1105 [86] = PINGROUP(86, mdp_vsync_p, mdp_vsync_out0, mdp_vsync_out1, _, _, _, _, _, _, _, _), 1106 [87] = PINGROUP(87, _, pwm, _, _, _, _, _, _, _, _, _), 1107 [88] = PINGROUP(88, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _), 1108 [89] = PINGROUP(89, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _), 1109 [90] = PINGROUP(90, usb0_phy_ps, _, dac_calib, _, _, _, _, _, _, _, _), 1110 [91] = PINGROUP(91, nav_gpio, _, _, _, _, _, _, _, _, _, _), 1111 [92] = PINGROUP(92, nav_gpio, _, _, _, _, _, _, _, _, _, _), 1112 [93] = PINGROUP(93, _, _, _, _, _, _, _, _, _, _, _), 1113 [94] = PINGROUP(94, mdp_vsync_e, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), 1114 [95] = PINGROUP(95, nav_gpio, mdp_vsync_s, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 1115 [96] = PINGROUP(96, dmic, cam_mclk, i2s1, jitter_bist, atest_gpsadc, atest_usb, _, _, _, 1116 _, _), 1117 [97] = PINGROUP(97, dmic, i2s1, dac_calib, _, _, _, _, _, _, _, _), 1118 [98] = PINGROUP(98, dmic, cam_mclk, i2s1, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _), 1119 [99] = PINGROUP(99, dmic, i2s1, jitter_bist, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), 1120 [100] = PINGROUP(100, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), 1121 [101] = PINGROUP(101, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), 1122 [102] = PINGROUP(102, i2s2, pwm, _, phase_flag, _, _, _, _, _, _, _), 1123 [103] = PINGROUP(103, ext_mclk, i2s2, _, _, _, _, _, _, _, _, _), 1124 [104] = PINGROUP(104, ext_mclk, nav_gpio, _, _, _, _, _, _, _, _, _), 1125 [105] = PINGROUP(105, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _), 1126 [106] = PINGROUP(106, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _), 1127 [107] = PINGROUP(107, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _), 1128 [108] = PINGROUP(108, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _), 1129 [109] = PINGROUP(109, swr0_rx, i2s0, sd_write_protect, _, _, _, _, _, _, _, _), 1130 [110] = PINGROUP(110, ext_mclk, i2s0, _, gcc_gp, _, _, _, _, _, _, _), 1131 [111] = PINGROUP(111, i2s3, _, _, _, _, _, _, _, _, _, _), 1132 [112] = PINGROUP(112, i2s3, _, _, _, _, _, _, _, _, _, _), 1133 [113] = PINGROUP(113, i2s3, _, _, _, _, _, _, _, _, _, _), 1134 [114] = PINGROUP(114, ext_mclk, i2s3, _, _, _, _, _, _, _, _, _), 1135 [115] = PINGROUP(115, mss_lte, _, _, _, _, _, _, _, _, _, _), 1136 [116] = PINGROUP(116, mss_lte, _, dac_calib, _, _, _, _, _, _, _, _), 1137 [117] = PINGROUP(117, pcie0_clk_req_n, _, dac_calib, _, _, _, _, _, _, _, _), 1138 [118] = PINGROUP(118, _, dac_calib, _, _, _, _, _, _, _, _, _), 1139 [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, _), 1140 [120] = PINGROUP(120, emac_phy, _, _, _, _, _, _, _, _, _, _), 1141 [121] = PINGROUP(121, rgmii, _, _, _, _, _, _, _, _, _, _), 1142 [122] = PINGROUP(122, rgmii, _, _, _, _, _, _, _, _, _, _), 1143 [123] = PINGROUP(123, rgmii, _, _, _, _, _, _, _, _, _, _), 1144 [124] = PINGROUP(124, rgmii, _, _, _, _, _, _, _, _, _, _), 1145 [125] = PINGROUP(125, rgmii, _, _, _, _, _, _, _, _, _, _), 1146 [126] = PINGROUP(126, rgmii, _, _, _, _, _, _, _, _, _, _), 1147 [127] = PINGROUP(127, rgmii, _, _, _, _, _, _, _, _, _, _), 1148 [128] = PINGROUP(128, rgmii, _, _, _, _, _, _, _, _, _, _), 1149 [129] = PINGROUP(129, rgmii, _, _, _, _, _, _, _, _, _, _), 1150 [130] = PINGROUP(130, rgmii, _, _, _, _, _, _, _, _, _, _), 1151 [131] = PINGROUP(131, rgmii, _, _, _, _, _, _, _, _, _, _), 1152 [132] = PINGROUP(132, rgmii, _, _, _, _, _, _, _, _, _, _), 1153 [133] = PINGROUP(133, rgmii, _, _, _, _, _, _, _, _, _, _), 1154 [134] = PINGROUP(134, rgmii, _, _, _, _, _, _, _, _, _, _), 1155 [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, _), 1156 [136] = PINGROUP(136, emac_phy, _, _, _, _, _, _, _, _, _, _), 1157 [137] = PINGROUP(137, rgmii, _, _, _, _, _, _, _, _, _, _), 1158 [138] = PINGROUP(138, rgmii, _, _, _, _, _, _, _, _, _, _), 1159 [139] = PINGROUP(139, rgmii, _, _, _, _, _, _, _, _, _, _), 1160 [140] = PINGROUP(140, rgmii, _, _, _, _, _, _, _, _, _, _), 1161 [141] = PINGROUP(141, rgmii, _, _, _, _, _, _, _, _, _, _), 1162 [142] = PINGROUP(142, rgmii, _, _, _, _, _, _, _, _, _, _), 1163 [143] = PINGROUP(143, rgmii, _, _, _, _, _, _, _, _, _, _), 1164 [144] = PINGROUP(144, rgmii, _, _, _, _, _, _, _, _, _, _), 1165 [145] = PINGROUP(145, rgmii, _, _, _, _, _, _, _, _, _, _), 1166 [146] = PINGROUP(146, rgmii, _, _, _, _, _, _, _, _, _, _), 1167 [147] = PINGROUP(147, rgmii, _, _, _, _, _, _, _, _, _, _), 1168 [148] = PINGROUP(148, rgmii, _, _, _, _, _, _, _, _, _, _), 1169 [149] = PINGROUP(149, rgmii, _, _, _, _, _, _, _, _, _, _), 1170 [150] = PINGROUP(150, rgmii, _, _, _, _, _, _, _, _, _, _), 1171 [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, _), 1172 [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, _), 1173 [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, _), 1174 [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, _), 1175 [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _, _, _), 1176 [156] = PINGROUP(156, _, _, _, _, _, _, _, _, _, _, _), 1177 [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _), 1178 [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _), 1179 [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _, _, _), 1180 [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _, _, _), 1181 [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _, _, _), 1182 [162] = PINGROUP(162, _, _, _, _, _, _, _, _, _, _, _), 1183 [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, _), 1184 [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, _), 1185 [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, _), 1186 [166] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xac004, 0, 0), 1187 [167] = SDC_QDSD_PINGROUP(sdc1_clk, 0xac000, 13, 6), 1188 [168] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xac000, 11, 3), 1189 [169] = SDC_QDSD_PINGROUP(sdc1_data, 0xac000, 9, 0), 1190 [170] = SDC_QDSD_PINGROUP(sdc2_clk, 0xaa000, 14, 6), 1191 [171] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xaa000, 11, 3), 1192 [172] = SDC_QDSD_PINGROUP(sdc2_data, 0xaa000, 9, 0), 1193 }; 1194 1195 static const struct msm_gpio_wakeirq_map shikra_mpm_map[] = { 1196 {1, 9 }, {2, 31 }, {5, 49 }, {6, 53 }, {9, 72 }, {10, 10 }, 1197 {12, 22 }, {14, 26 }, {17, 29 }, {18, 24 }, {20, 32 }, {22, 33 }, 1198 {25, 34 }, {27, 35 }, {28, 36 }, {29, 37 }, {30, 38 }, {31, 39 }, 1199 {32, 40 }, {33, 41 }, {38, 42 }, {40, 43 }, {43, 44 }, {44, 45 }, 1200 {45, 46 }, {46, 47 }, {47, 48 }, {48, 60 }, {50, 50 }, {51, 51 }, 1201 {52, 61 }, {53, 62 }, {57, 52 }, {58, 63 }, {60, 54 }, {63, 64 }, 1202 {73, 55 }, {74, 56 }, {75, 57 }, {77, 3 }, {80, 4 }, {84, 5 }, 1203 {85, 67 }, {86, 69 }, {88, 70 }, {89, 71 }, {90, 73 }, {91, 74 }, 1204 {92, 75 }, {93, 76 }, {94, 77 }, {95, 78 }, {97, 79 }, {99, 80 }, 1205 {100, 11 }, {101, 13 }, {102, 14 }, {103, 15 }, {106, 16 }, {108, 17 }, 1206 {112, 18 }, {116, 19 }, {117, 20 }, {119, 21 }, {120, 23 }, {136, 25 }, 1207 {159, 27 }, {161, 28 }, 1208 }; 1209 1210 static const struct msm_pinctrl_soc_data shikra_tlmm = { 1211 .pins = shikra_pins, 1212 .npins = ARRAY_SIZE(shikra_pins), 1213 .functions = shikra_functions, 1214 .nfunctions = ARRAY_SIZE(shikra_functions), 1215 .groups = shikra_groups, 1216 .ngroups = ARRAY_SIZE(shikra_groups), 1217 .ngpios = 166, 1218 .wakeirq_map = shikra_mpm_map, 1219 .nwakeirq_map = ARRAY_SIZE(shikra_mpm_map), 1220 }; 1221 1222 static int shikra_tlmm_probe(struct platform_device *pdev) 1223 { 1224 return msm_pinctrl_probe(pdev, &shikra_tlmm); 1225 } 1226 1227 static const struct of_device_id shikra_tlmm_of_match[] = { 1228 { .compatible = "qcom,shikra-tlmm", .data = &shikra_tlmm }, 1229 {}, 1230 }; 1231 MODULE_DEVICE_TABLE(of, shikra_tlmm_of_match); 1232 1233 static struct platform_driver shikra_tlmm_driver = { 1234 .driver = { 1235 .name = "shikra-tlmm", 1236 .of_match_table = shikra_tlmm_of_match, 1237 }, 1238 .probe = shikra_tlmm_probe, 1239 }; 1240 1241 static int __init shikra_tlmm_init(void) 1242 { 1243 return platform_driver_register(&shikra_tlmm_driver); 1244 } 1245 arch_initcall(shikra_tlmm_init); 1246 1247 static void __exit shikra_tlmm_exit(void) 1248 { 1249 platform_driver_unregister(&shikra_tlmm_driver); 1250 } 1251 module_exit(shikra_tlmm_exit); 1252 1253 MODULE_DESCRIPTION("QTI Shikra TLMM driver"); 1254 MODULE_LICENSE("GPL"); 1255