1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/platform_device.h> 9 #include "pinctrl-msm.h" 10 11 #define REG_BASE 0x100000 12 #define REG_SIZE 0x1000 13 14 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ 15 { \ 16 .grp = PINCTRL_PINGROUP("gpio"#id, gpio##id##_pins, \ 17 (unsigned int)ARRAY_SIZE(gpio##id##_pins)), \ 18 .ctl_reg = REG_BASE + REG_SIZE * id, \ 19 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 20 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 21 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 22 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 23 .mux_bit = 2, \ 24 .pull_bit = 0, \ 25 .drv_bit = 6, \ 26 .egpio_enable = 12, \ 27 .egpio_present = 11, \ 28 .oe_bit = 9, \ 29 .in_bit = 0, \ 30 .out_bit = 1, \ 31 .intr_enable_bit = 0, \ 32 .intr_status_bit = 0, \ 33 .intr_target_bit = 5, \ 34 .intr_target_kpss_val = 3, \ 35 .intr_raw_status_bit = 4, \ 36 .intr_polarity_bit = 1, \ 37 .intr_detection_bit = 2, \ 38 .intr_detection_width = 2, \ 39 .funcs = (int[]){ \ 40 msm_mux_gpio, /* gpio mode */ \ 41 msm_mux_##f1, \ 42 msm_mux_##f2, \ 43 msm_mux_##f3, \ 44 msm_mux_##f4, \ 45 msm_mux_##f5, \ 46 msm_mux_##f6, \ 47 msm_mux_##f7, \ 48 msm_mux_##f8, \ 49 msm_mux_##f9, \ 50 msm_mux_##f10 \ 51 }, \ 52 .nfuncs = 11, \ 53 } 54 55 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 56 { \ 57 .grp = PINCTRL_PINGROUP(#pg_name, pg_name##_pins, \ 58 (unsigned int)ARRAY_SIZE(pg_name##_pins)), \ 59 .ctl_reg = ctl, \ 60 .io_reg = 0, \ 61 .intr_cfg_reg = 0, \ 62 .intr_status_reg = 0, \ 63 .intr_target_reg = 0, \ 64 .mux_bit = -1, \ 65 .pull_bit = pull, \ 66 .drv_bit = drv, \ 67 .oe_bit = -1, \ 68 .in_bit = -1, \ 69 .out_bit = -1, \ 70 .intr_enable_bit = -1, \ 71 .intr_status_bit = -1, \ 72 .intr_target_bit = -1, \ 73 .intr_raw_status_bit = -1, \ 74 .intr_polarity_bit = -1, \ 75 .intr_detection_bit = -1, \ 76 .intr_detection_width = -1, \ 77 } 78 79 static const struct pinctrl_pin_desc sdx75_pins[] = { 80 PINCTRL_PIN(0, "GPIO_0"), 81 PINCTRL_PIN(1, "GPIO_1"), 82 PINCTRL_PIN(2, "GPIO_2"), 83 PINCTRL_PIN(3, "GPIO_3"), 84 PINCTRL_PIN(4, "GPIO_4"), 85 PINCTRL_PIN(5, "GPIO_5"), 86 PINCTRL_PIN(6, "GPIO_6"), 87 PINCTRL_PIN(7, "GPIO_7"), 88 PINCTRL_PIN(8, "GPIO_8"), 89 PINCTRL_PIN(9, "GPIO_9"), 90 PINCTRL_PIN(10, "GPIO_10"), 91 PINCTRL_PIN(11, "GPIO_11"), 92 PINCTRL_PIN(12, "GPIO_12"), 93 PINCTRL_PIN(13, "GPIO_13"), 94 PINCTRL_PIN(14, "GPIO_14"), 95 PINCTRL_PIN(15, "GPIO_15"), 96 PINCTRL_PIN(16, "GPIO_16"), 97 PINCTRL_PIN(17, "GPIO_17"), 98 PINCTRL_PIN(18, "GPIO_18"), 99 PINCTRL_PIN(19, "GPIO_19"), 100 PINCTRL_PIN(20, "GPIO_20"), 101 PINCTRL_PIN(21, "GPIO_21"), 102 PINCTRL_PIN(22, "GPIO_22"), 103 PINCTRL_PIN(23, "GPIO_23"), 104 PINCTRL_PIN(24, "GPIO_24"), 105 PINCTRL_PIN(25, "GPIO_25"), 106 PINCTRL_PIN(26, "GPIO_26"), 107 PINCTRL_PIN(27, "GPIO_27"), 108 PINCTRL_PIN(28, "GPIO_28"), 109 PINCTRL_PIN(29, "GPIO_29"), 110 PINCTRL_PIN(30, "GPIO_30"), 111 PINCTRL_PIN(31, "GPIO_31"), 112 PINCTRL_PIN(32, "GPIO_32"), 113 PINCTRL_PIN(33, "GPIO_33"), 114 PINCTRL_PIN(34, "GPIO_34"), 115 PINCTRL_PIN(35, "GPIO_35"), 116 PINCTRL_PIN(36, "GPIO_36"), 117 PINCTRL_PIN(37, "GPIO_37"), 118 PINCTRL_PIN(38, "GPIO_38"), 119 PINCTRL_PIN(39, "GPIO_39"), 120 PINCTRL_PIN(40, "GPIO_40"), 121 PINCTRL_PIN(41, "GPIO_41"), 122 PINCTRL_PIN(42, "GPIO_42"), 123 PINCTRL_PIN(43, "GPIO_43"), 124 PINCTRL_PIN(44, "GPIO_44"), 125 PINCTRL_PIN(45, "GPIO_45"), 126 PINCTRL_PIN(46, "GPIO_46"), 127 PINCTRL_PIN(47, "GPIO_47"), 128 PINCTRL_PIN(48, "GPIO_48"), 129 PINCTRL_PIN(49, "GPIO_49"), 130 PINCTRL_PIN(50, "GPIO_50"), 131 PINCTRL_PIN(51, "GPIO_51"), 132 PINCTRL_PIN(52, "GPIO_52"), 133 PINCTRL_PIN(53, "GPIO_53"), 134 PINCTRL_PIN(54, "GPIO_54"), 135 PINCTRL_PIN(55, "GPIO_55"), 136 PINCTRL_PIN(56, "GPIO_56"), 137 PINCTRL_PIN(57, "GPIO_57"), 138 PINCTRL_PIN(58, "GPIO_58"), 139 PINCTRL_PIN(59, "GPIO_59"), 140 PINCTRL_PIN(60, "GPIO_60"), 141 PINCTRL_PIN(61, "GPIO_61"), 142 PINCTRL_PIN(62, "GPIO_62"), 143 PINCTRL_PIN(63, "GPIO_63"), 144 PINCTRL_PIN(64, "GPIO_64"), 145 PINCTRL_PIN(65, "GPIO_65"), 146 PINCTRL_PIN(66, "GPIO_66"), 147 PINCTRL_PIN(67, "GPIO_67"), 148 PINCTRL_PIN(68, "GPIO_68"), 149 PINCTRL_PIN(69, "GPIO_69"), 150 PINCTRL_PIN(70, "GPIO_70"), 151 PINCTRL_PIN(71, "GPIO_71"), 152 PINCTRL_PIN(72, "GPIO_72"), 153 PINCTRL_PIN(73, "GPIO_73"), 154 PINCTRL_PIN(74, "GPIO_74"), 155 PINCTRL_PIN(75, "GPIO_75"), 156 PINCTRL_PIN(76, "GPIO_76"), 157 PINCTRL_PIN(77, "GPIO_77"), 158 PINCTRL_PIN(78, "GPIO_78"), 159 PINCTRL_PIN(79, "GPIO_79"), 160 PINCTRL_PIN(80, "GPIO_80"), 161 PINCTRL_PIN(81, "GPIO_81"), 162 PINCTRL_PIN(82, "GPIO_82"), 163 PINCTRL_PIN(83, "GPIO_83"), 164 PINCTRL_PIN(84, "GPIO_84"), 165 PINCTRL_PIN(85, "GPIO_85"), 166 PINCTRL_PIN(86, "GPIO_86"), 167 PINCTRL_PIN(87, "GPIO_87"), 168 PINCTRL_PIN(88, "GPIO_88"), 169 PINCTRL_PIN(89, "GPIO_89"), 170 PINCTRL_PIN(90, "GPIO_90"), 171 PINCTRL_PIN(91, "GPIO_91"), 172 PINCTRL_PIN(92, "GPIO_92"), 173 PINCTRL_PIN(93, "GPIO_93"), 174 PINCTRL_PIN(94, "GPIO_94"), 175 PINCTRL_PIN(95, "GPIO_95"), 176 PINCTRL_PIN(96, "GPIO_96"), 177 PINCTRL_PIN(97, "GPIO_97"), 178 PINCTRL_PIN(98, "GPIO_98"), 179 PINCTRL_PIN(99, "GPIO_99"), 180 PINCTRL_PIN(100, "GPIO_100"), 181 PINCTRL_PIN(101, "GPIO_101"), 182 PINCTRL_PIN(102, "GPIO_102"), 183 PINCTRL_PIN(103, "GPIO_103"), 184 PINCTRL_PIN(104, "GPIO_104"), 185 PINCTRL_PIN(105, "GPIO_105"), 186 PINCTRL_PIN(106, "GPIO_106"), 187 PINCTRL_PIN(107, "GPIO_107"), 188 PINCTRL_PIN(108, "GPIO_108"), 189 PINCTRL_PIN(109, "GPIO_109"), 190 PINCTRL_PIN(110, "GPIO_110"), 191 PINCTRL_PIN(111, "GPIO_111"), 192 PINCTRL_PIN(112, "GPIO_112"), 193 PINCTRL_PIN(113, "GPIO_113"), 194 PINCTRL_PIN(114, "GPIO_114"), 195 PINCTRL_PIN(115, "GPIO_115"), 196 PINCTRL_PIN(116, "GPIO_116"), 197 PINCTRL_PIN(117, "GPIO_117"), 198 PINCTRL_PIN(118, "GPIO_118"), 199 PINCTRL_PIN(119, "GPIO_119"), 200 PINCTRL_PIN(120, "GPIO_120"), 201 PINCTRL_PIN(121, "GPIO_121"), 202 PINCTRL_PIN(122, "GPIO_122"), 203 PINCTRL_PIN(123, "GPIO_123"), 204 PINCTRL_PIN(124, "GPIO_124"), 205 PINCTRL_PIN(125, "GPIO_125"), 206 PINCTRL_PIN(126, "GPIO_126"), 207 PINCTRL_PIN(127, "GPIO_127"), 208 PINCTRL_PIN(128, "GPIO_128"), 209 PINCTRL_PIN(129, "GPIO_129"), 210 PINCTRL_PIN(130, "GPIO_130"), 211 PINCTRL_PIN(131, "GPIO_131"), 212 PINCTRL_PIN(132, "GPIO_132"), 213 PINCTRL_PIN(133, "SDC1_RCLK"), 214 PINCTRL_PIN(134, "SDC1_CLK"), 215 PINCTRL_PIN(135, "SDC1_CMD"), 216 PINCTRL_PIN(136, "SDC1_DATA"), 217 PINCTRL_PIN(137, "SDC2_CLK"), 218 PINCTRL_PIN(138, "SDC2_CMD"), 219 PINCTRL_PIN(139, "SDC2_DATA"), 220 }; 221 222 #define DECLARE_MSM_GPIO_PINS(pin) \ 223 static const unsigned int gpio##pin##_pins[] = {pin} 224 DECLARE_MSM_GPIO_PINS(0); 225 DECLARE_MSM_GPIO_PINS(1); 226 DECLARE_MSM_GPIO_PINS(2); 227 DECLARE_MSM_GPIO_PINS(3); 228 DECLARE_MSM_GPIO_PINS(4); 229 DECLARE_MSM_GPIO_PINS(5); 230 DECLARE_MSM_GPIO_PINS(6); 231 DECLARE_MSM_GPIO_PINS(7); 232 DECLARE_MSM_GPIO_PINS(8); 233 DECLARE_MSM_GPIO_PINS(9); 234 DECLARE_MSM_GPIO_PINS(10); 235 DECLARE_MSM_GPIO_PINS(11); 236 DECLARE_MSM_GPIO_PINS(12); 237 DECLARE_MSM_GPIO_PINS(13); 238 DECLARE_MSM_GPIO_PINS(14); 239 DECLARE_MSM_GPIO_PINS(15); 240 DECLARE_MSM_GPIO_PINS(16); 241 DECLARE_MSM_GPIO_PINS(17); 242 DECLARE_MSM_GPIO_PINS(18); 243 DECLARE_MSM_GPIO_PINS(19); 244 DECLARE_MSM_GPIO_PINS(20); 245 DECLARE_MSM_GPIO_PINS(21); 246 DECLARE_MSM_GPIO_PINS(22); 247 DECLARE_MSM_GPIO_PINS(23); 248 DECLARE_MSM_GPIO_PINS(24); 249 DECLARE_MSM_GPIO_PINS(25); 250 DECLARE_MSM_GPIO_PINS(26); 251 DECLARE_MSM_GPIO_PINS(27); 252 DECLARE_MSM_GPIO_PINS(28); 253 DECLARE_MSM_GPIO_PINS(29); 254 DECLARE_MSM_GPIO_PINS(30); 255 DECLARE_MSM_GPIO_PINS(31); 256 DECLARE_MSM_GPIO_PINS(32); 257 DECLARE_MSM_GPIO_PINS(33); 258 DECLARE_MSM_GPIO_PINS(34); 259 DECLARE_MSM_GPIO_PINS(35); 260 DECLARE_MSM_GPIO_PINS(36); 261 DECLARE_MSM_GPIO_PINS(37); 262 DECLARE_MSM_GPIO_PINS(38); 263 DECLARE_MSM_GPIO_PINS(39); 264 DECLARE_MSM_GPIO_PINS(40); 265 DECLARE_MSM_GPIO_PINS(41); 266 DECLARE_MSM_GPIO_PINS(42); 267 DECLARE_MSM_GPIO_PINS(43); 268 DECLARE_MSM_GPIO_PINS(44); 269 DECLARE_MSM_GPIO_PINS(45); 270 DECLARE_MSM_GPIO_PINS(46); 271 DECLARE_MSM_GPIO_PINS(47); 272 DECLARE_MSM_GPIO_PINS(48); 273 DECLARE_MSM_GPIO_PINS(49); 274 DECLARE_MSM_GPIO_PINS(50); 275 DECLARE_MSM_GPIO_PINS(51); 276 DECLARE_MSM_GPIO_PINS(52); 277 DECLARE_MSM_GPIO_PINS(53); 278 DECLARE_MSM_GPIO_PINS(54); 279 DECLARE_MSM_GPIO_PINS(55); 280 DECLARE_MSM_GPIO_PINS(56); 281 DECLARE_MSM_GPIO_PINS(57); 282 DECLARE_MSM_GPIO_PINS(58); 283 DECLARE_MSM_GPIO_PINS(59); 284 DECLARE_MSM_GPIO_PINS(60); 285 DECLARE_MSM_GPIO_PINS(61); 286 DECLARE_MSM_GPIO_PINS(62); 287 DECLARE_MSM_GPIO_PINS(63); 288 DECLARE_MSM_GPIO_PINS(64); 289 DECLARE_MSM_GPIO_PINS(65); 290 DECLARE_MSM_GPIO_PINS(66); 291 DECLARE_MSM_GPIO_PINS(67); 292 DECLARE_MSM_GPIO_PINS(68); 293 DECLARE_MSM_GPIO_PINS(69); 294 DECLARE_MSM_GPIO_PINS(70); 295 DECLARE_MSM_GPIO_PINS(71); 296 DECLARE_MSM_GPIO_PINS(72); 297 DECLARE_MSM_GPIO_PINS(73); 298 DECLARE_MSM_GPIO_PINS(74); 299 DECLARE_MSM_GPIO_PINS(75); 300 DECLARE_MSM_GPIO_PINS(76); 301 DECLARE_MSM_GPIO_PINS(77); 302 DECLARE_MSM_GPIO_PINS(78); 303 DECLARE_MSM_GPIO_PINS(79); 304 DECLARE_MSM_GPIO_PINS(80); 305 DECLARE_MSM_GPIO_PINS(81); 306 DECLARE_MSM_GPIO_PINS(82); 307 DECLARE_MSM_GPIO_PINS(83); 308 DECLARE_MSM_GPIO_PINS(84); 309 DECLARE_MSM_GPIO_PINS(85); 310 DECLARE_MSM_GPIO_PINS(86); 311 DECLARE_MSM_GPIO_PINS(87); 312 DECLARE_MSM_GPIO_PINS(88); 313 DECLARE_MSM_GPIO_PINS(89); 314 DECLARE_MSM_GPIO_PINS(90); 315 DECLARE_MSM_GPIO_PINS(91); 316 DECLARE_MSM_GPIO_PINS(92); 317 DECLARE_MSM_GPIO_PINS(93); 318 DECLARE_MSM_GPIO_PINS(94); 319 DECLARE_MSM_GPIO_PINS(95); 320 DECLARE_MSM_GPIO_PINS(96); 321 DECLARE_MSM_GPIO_PINS(97); 322 DECLARE_MSM_GPIO_PINS(98); 323 DECLARE_MSM_GPIO_PINS(99); 324 DECLARE_MSM_GPIO_PINS(100); 325 DECLARE_MSM_GPIO_PINS(101); 326 DECLARE_MSM_GPIO_PINS(102); 327 DECLARE_MSM_GPIO_PINS(103); 328 DECLARE_MSM_GPIO_PINS(104); 329 DECLARE_MSM_GPIO_PINS(105); 330 DECLARE_MSM_GPIO_PINS(106); 331 DECLARE_MSM_GPIO_PINS(107); 332 DECLARE_MSM_GPIO_PINS(108); 333 DECLARE_MSM_GPIO_PINS(109); 334 DECLARE_MSM_GPIO_PINS(110); 335 DECLARE_MSM_GPIO_PINS(111); 336 DECLARE_MSM_GPIO_PINS(112); 337 DECLARE_MSM_GPIO_PINS(113); 338 DECLARE_MSM_GPIO_PINS(114); 339 DECLARE_MSM_GPIO_PINS(115); 340 DECLARE_MSM_GPIO_PINS(116); 341 DECLARE_MSM_GPIO_PINS(117); 342 DECLARE_MSM_GPIO_PINS(118); 343 DECLARE_MSM_GPIO_PINS(119); 344 DECLARE_MSM_GPIO_PINS(120); 345 DECLARE_MSM_GPIO_PINS(121); 346 DECLARE_MSM_GPIO_PINS(122); 347 DECLARE_MSM_GPIO_PINS(123); 348 DECLARE_MSM_GPIO_PINS(124); 349 DECLARE_MSM_GPIO_PINS(125); 350 DECLARE_MSM_GPIO_PINS(126); 351 DECLARE_MSM_GPIO_PINS(127); 352 DECLARE_MSM_GPIO_PINS(128); 353 DECLARE_MSM_GPIO_PINS(129); 354 DECLARE_MSM_GPIO_PINS(130); 355 DECLARE_MSM_GPIO_PINS(131); 356 DECLARE_MSM_GPIO_PINS(132); 357 358 static const unsigned int sdc1_rclk_pins[] = {133}; 359 static const unsigned int sdc1_clk_pins[] = {134}; 360 static const unsigned int sdc1_cmd_pins[] = {135}; 361 static const unsigned int sdc1_data_pins[] = {136}; 362 static const unsigned int sdc2_clk_pins[] = {137}; 363 static const unsigned int sdc2_cmd_pins[] = {138}; 364 static const unsigned int sdc2_data_pins[] = {139}; 365 366 enum sdx75_functions { 367 msm_mux_adsp_ext, 368 msm_mux_atest_char, 369 msm_mux_audio_ref_clk, 370 msm_mux_bimc_dte, 371 msm_mux_char_exec, 372 msm_mux_coex_uart2, 373 msm_mux_coex_uart, 374 msm_mux_cri_trng, 375 msm_mux_cri_trng0, 376 msm_mux_cri_trng1, 377 msm_mux_dbg_out_clk, 378 msm_mux_ddr_bist, 379 msm_mux_ddr_pxi0, 380 msm_mux_ebi0_wrcdc, 381 msm_mux_ebi2_a, 382 msm_mux_ebi2_lcd, 383 msm_mux_ebi2_lcd_te, 384 msm_mux_emac0_mcg, 385 msm_mux_emac0_ptp, 386 msm_mux_emac1_mcg, 387 msm_mux_emac1_ptp, 388 msm_mux_emac_cdc, 389 msm_mux_emac_pps_in, 390 msm_mux_eth0_mdc, 391 msm_mux_eth0_mdio, 392 msm_mux_eth1_mdc, 393 msm_mux_eth1_mdio, 394 msm_mux_ext_dbg, 395 msm_mux_gcc_125_clk, 396 msm_mux_gcc_gp1_clk, 397 msm_mux_gcc_gp2_clk, 398 msm_mux_gcc_gp3_clk, 399 msm_mux_gcc_plltest, 400 msm_mux_gpio, 401 msm_mux_i2s_mclk, 402 msm_mux_jitter_bist, 403 msm_mux_ldo_en, 404 msm_mux_ldo_update, 405 msm_mux_m_voc, 406 msm_mux_mgpi_clk, 407 msm_mux_native_char, 408 msm_mux_native_tsens, 409 msm_mux_native_tsense, 410 msm_mux_nav_dr_sync, 411 msm_mux_nav_gpio, 412 msm_mux_pa_indicator, 413 msm_mux_pci_e, 414 msm_mux_pcie0_clkreq_n, 415 msm_mux_pcie1_clkreq_n, 416 msm_mux_pcie2_clkreq_n, 417 msm_mux_pll_bist_sync, 418 msm_mux_pll_clk_aux, 419 msm_mux_pll_ref_clk, 420 msm_mux_pri_mi2s, 421 msm_mux_prng_rosc, 422 msm_mux_qdss_cti, 423 msm_mux_qdss_gpio, 424 msm_mux_qlink0_b_en, 425 msm_mux_qlink0_b_req, 426 msm_mux_qlink0_l_en, 427 msm_mux_qlink0_l_req, 428 msm_mux_qlink0_wmss, 429 msm_mux_qlink1_l_en, 430 msm_mux_qlink1_l_req, 431 msm_mux_qlink1_wmss, 432 msm_mux_qup_se0, 433 msm_mux_qup_se1_l2_mira, 434 msm_mux_qup_se1_l2_mirb, 435 msm_mux_qup_se1_l3_mira, 436 msm_mux_qup_se1_l3_mirb, 437 msm_mux_qup_se2, 438 msm_mux_qup_se3, 439 msm_mux_qup_se4, 440 msm_mux_qup_se5, 441 msm_mux_qup_se6, 442 msm_mux_qup_se7, 443 msm_mux_qup_se8, 444 msm_mux_rgmii_rx_ctl, 445 msm_mux_rgmii_rxc, 446 msm_mux_rgmii_rxd, 447 msm_mux_rgmii_tx_ctl, 448 msm_mux_rgmii_txc, 449 msm_mux_rgmii_txd, 450 msm_mux_sd_card, 451 msm_mux_sdc1_tb, 452 msm_mux_sdc2_tb_trig, 453 msm_mux_sec_mi2s, 454 msm_mux_sgmii_phy_intr0_n, 455 msm_mux_sgmii_phy_intr1_n, 456 msm_mux_spmi_coex, 457 msm_mux_spmi_vgi, 458 msm_mux_tgu_ch0_trigout, 459 msm_mux_tmess_prng0, 460 msm_mux_tmess_prng1, 461 msm_mux_tmess_prng2, 462 msm_mux_tmess_prng3, 463 msm_mux_tri_mi2s, 464 msm_mux_uim1_clk, 465 msm_mux_uim1_data, 466 msm_mux_uim1_present, 467 msm_mux_uim1_reset, 468 msm_mux_uim2_clk, 469 msm_mux_uim2_data, 470 msm_mux_uim2_present, 471 msm_mux_uim2_reset, 472 msm_mux_usb2phy_ac_en, 473 msm_mux_vsense_trigger_mirnat, 474 msm_mux__, 475 }; 476 477 static const char *const gpio_groups[] = { 478 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", 479 "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", 480 "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", 481 "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", 482 "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", 483 "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", 484 "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", 485 "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", 486 "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", 487 "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", 488 "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", 489 "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", 490 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", 491 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", 492 "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 493 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", 494 "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", 495 "gpio119", "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", 496 "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", 497 }; 498 static const char *const adsp_ext_groups[] = { 499 "gpio59", "gpio68", 500 }; 501 static const char *const atest_char_groups[] = { 502 "gpio24", "gpio25", "gpio26", "gpio41", "gpio63", 503 }; 504 static const char *const audio_ref_clk_groups[] = { 505 "gpio126", 506 }; 507 static const char *const bimc_dte_groups[] = { 508 "gpio14", "gpio15", "gpio61", "gpio59", 509 }; 510 static const char *const char_exec_groups[] = { 511 "gpio6", "gpio7", 512 }; 513 static const char *const coex_uart2_groups[] = { 514 "gpio48", "gpio49", "gpio90", "gpio91", 515 }; 516 static const char *const coex_uart_groups[] = { 517 "gpio46", "gpio47", 518 }; 519 static const char *const cri_trng_groups[] = { 520 "gpio36", 521 }; 522 static const char *const cri_trng0_groups[] = { 523 "gpio31", 524 }; 525 static const char *const cri_trng1_groups[] = { 526 "gpio32", 527 }; 528 static const char *const dbg_out_clk_groups[] = { 529 "gpio26", 530 }; 531 static const char *const ddr_bist_groups[] = { 532 "gpio46", "gpio47", "gpio48", "gpio49", 533 }; 534 static const char *const ddr_pxi0_groups[] = { 535 "gpio45", "gpio46", 536 }; 537 static const char *const ebi0_wrcdc_groups[] = { 538 "gpio0", "gpio2", 539 }; 540 static const char *const ebi2_a_groups[] = { 541 "gpio100", 542 }; 543 static const char *const ebi2_lcd_groups[] = { 544 "gpio99", "gpio101", 545 }; 546 static const char *const ebi2_lcd_te_groups[] = { 547 "gpio98", 548 }; 549 static const char *const emac0_mcg_groups[] = { 550 "gpio83", "gpio84", "gpio85", "gpio89", 551 }; 552 static const char *const emac0_ptp_groups[] = { 553 "gpio35", "gpio83", "gpio84", "gpio85", "gpio89", "gpio119", "gpio123", 554 }; 555 static const char *const emac1_mcg_groups[] = { 556 "gpio90", "gpio92", "gpio93", "gpio122", 557 }; 558 static const char *const emac1_ptp_groups[] = { 559 "gpio112", "gpio113", "gpio114", "gpio115", 560 }; 561 static const char *const emac_cdc_groups[] = { 562 "gpio38", "gpio39", 563 }; 564 static const char *const emac_pps_in_groups[] = { 565 "gpio127", 566 }; 567 static const char *const eth0_mdc_groups[] = { 568 "gpio94", 569 }; 570 static const char *const eth0_mdio_groups[] = { 571 "gpio95", 572 }; 573 static const char *const eth1_mdc_groups[] = { 574 "gpio106", 575 }; 576 static const char *const eth1_mdio_groups[] = { 577 "gpio107", 578 }; 579 static const char *const ext_dbg_groups[] = { 580 "gpio12", "gpio13", "gpio14", "gpio15", 581 }; 582 static const char *const gcc_125_clk_groups[] = { 583 "gpio25", 584 }; 585 static const char *const gcc_gp1_clk_groups[] = { 586 "gpio39", 587 }; 588 static const char *const gcc_gp2_clk_groups[] = { 589 "gpio40", 590 }; 591 static const char *const gcc_gp3_clk_groups[] = { 592 "gpio41", 593 }; 594 static const char *const gcc_plltest_groups[] = { 595 "gpio81", "gpio82", 596 }; 597 static const char *const i2s_mclk_groups[] = { 598 "gpio74", 599 }; 600 static const char *const jitter_bist_groups[] = { 601 "gpio41", 602 }; 603 static const char *const ldo_en_groups[] = { 604 "gpio8", 605 }; 606 static const char *const ldo_update_groups[] = { 607 "gpio62", 608 }; 609 static const char *const m_voc_groups[] = { 610 "gpio62", "gpio63", "gpio64", "gpio65", "gpio71", 611 }; 612 static const char *const mgpi_clk_groups[] = { 613 "gpio39", "gpio40", 614 }; 615 static const char *const native_char_groups[] = { 616 "gpio29", "gpio33", "gpio57", "gpio66", "gpio67", 617 }; 618 static const char *const native_tsens_groups[] = { 619 "gpio38", 620 }; 621 static const char *const native_tsense_groups[] = { 622 "gpio64", "gpio76", 623 }; 624 static const char *const nav_dr_sync_groups[] = { 625 "gpio36", 626 }; 627 static const char *const nav_gpio_groups[] = { 628 "gpio35", "gpio36", "gpio104", 629 }; 630 static const char *const pa_indicator_groups[] = { 631 "gpio58", 632 }; 633 static const char *const pci_e_groups[] = { 634 "gpio42", 635 }; 636 static const char *const pcie0_clkreq_n_groups[] = { 637 "gpio43", 638 }; 639 static const char *const pcie1_clkreq_n_groups[] = { 640 "gpio124", 641 }; 642 static const char *const pcie2_clkreq_n_groups[] = { 643 "gpio121", 644 }; 645 static const char *const pll_bist_sync_groups[] = { 646 "gpio38", 647 }; 648 static const char *const pll_clk_aux_groups[] = { 649 "gpio40", 650 }; 651 static const char *const pll_ref_clk_groups[] = { 652 "gpio37", 653 }; 654 static const char *const pri_mi2s_groups[] = { 655 "gpio16", "gpio17", "gpio18", "gpio19", 656 }; 657 static const char *const prng_rosc_groups[] = { 658 "gpio27", "gpio36", "gpio37", "gpio38", 659 }; 660 static const char *const qdss_cti_groups[] = { 661 "gpio16", "gpio17", "gpio52", "gpio53", "gpio56", 662 "gpio57", "gpio59", "gpio60", "gpio78", "gpio79", 663 }; 664 static const char *const qdss_gpio_groups[] = { 665 "gpio82", "gpio83", "gpio84", "gpio85", "gpio94", 666 "gpio95", "gpio96", "gpio97", "gpio110", "gpio111", 667 "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 668 "gpio117", "gpio118", "gpio119", 669 }; 670 static const char *const qlink0_b_en_groups[] = { 671 "gpio40", 672 }; 673 static const char *const qlink0_b_req_groups[] = { 674 "gpio41", 675 }; 676 static const char *const qlink0_l_en_groups[] = { 677 "gpio37", 678 }; 679 static const char *const qlink0_l_req_groups[] = { 680 "gpio38", 681 }; 682 static const char *const qlink0_wmss_groups[] = { 683 "gpio39", 684 }; 685 static const char *const qlink1_l_en_groups[] = { 686 "gpio26", 687 }; 688 static const char *const qlink1_l_req_groups[] = { 689 "gpio27", 690 }; 691 static const char *const qlink1_wmss_groups[] = { 692 "gpio28", 693 }; 694 static const char *const qup_se0_groups[] = { 695 "gpio8", "gpio9", "gpio10", "gpio11", 696 }; 697 static const char *const qup_se1_l2_mira_groups[] = { 698 "gpio12", 699 }; 700 static const char *const qup_se1_l2_mirb_groups[] = { 701 "gpio16", 702 }; 703 static const char *const qup_se1_l3_mira_groups[] = { 704 "gpio13", 705 }; 706 static const char *const qup_se1_l3_mirb_groups[] = { 707 "gpio17", 708 }; 709 static const char *const qup_se2_groups[] = { 710 "gpio14", "gpio15", "gpio16", "gpio17", 711 }; 712 static const char *const qup_se3_groups[] = { 713 "gpio52", "gpio53", "gpio54", "gpio55", 714 }; 715 static const char *const qup_se4_groups[] = { 716 "gpio64", "gpio65", 717 }; 718 static const char *const qup_se5_groups[] = { 719 "gpio110", "gpio111", 720 }; 721 static const char *const qup_se6_groups[] = { 722 "gpio112", "gpio113", "gpio114", "gpio115", 723 }; 724 static const char *const qup_se7_groups[] = { 725 "gpio116", "gpio117", "gpio118", "gpio119", 726 }; 727 static const char *const qup_se8_groups[] = { 728 "gpio124", "gpio125", 729 }; 730 static const char *const rgmii_rx_ctl_groups[] = { 731 "gpio93", 732 }; 733 static const char *const rgmii_rxc_groups[] = { 734 "gpio88", 735 }; 736 static const char *const rgmii_rxd_groups[] = { 737 "gpio89", "gpio90", "gpio91", "gpio92", 738 }; 739 static const char *const rgmii_tx_ctl_groups[] = { 740 "gpio87", 741 }; 742 static const char *const rgmii_txc_groups[] = { 743 "gpio82", 744 }; 745 static const char *const rgmii_txd_groups[] = { 746 "gpio83", "gpio84", "gpio85", "gpio86", 747 }; 748 static const char *const sd_card_groups[] = { 749 "gpio105", 750 }; 751 static const char *const sdc1_tb_groups[] = { 752 "gpio84", "gpio130", 753 }; 754 static const char *const sdc2_tb_trig_groups[] = { 755 "gpio129", 756 }; 757 static const char *const sec_mi2s_groups[] = { 758 "gpio20", "gpio21", "gpio22", "gpio23", 759 }; 760 static const char *const sgmii_phy_intr0_n_groups[] = { 761 "gpio97", 762 }; 763 static const char *const sgmii_phy_intr1_n_groups[] = { 764 "gpio109", 765 }; 766 static const char *const spmi_coex_groups[] = { 767 "gpio48", "gpio49", 768 }; 769 static const char *const spmi_vgi_groups[] = { 770 "gpio50", "gpio51", 771 }; 772 static const char *const tgu_ch0_trigout_groups[] = { 773 "gpio55", 774 }; 775 static const char *const tmess_prng0_groups[] = { 776 "gpio28", 777 }; 778 static const char *const tmess_prng1_groups[] = { 779 "gpio29", 780 }; 781 static const char *const tmess_prng2_groups[] = { 782 "gpio30", 783 }; 784 static const char *const tmess_prng3_groups[] = { 785 "gpio31", 786 }; 787 static const char *const tri_mi2s_groups[] = { 788 "gpio98", "gpio99", "gpio100", "gpio101", 789 }; 790 static const char *const uim1_clk_groups[] = { 791 "gpio7", 792 }; 793 static const char *const uim1_data_groups[] = { 794 "gpio4", 795 }; 796 static const char *const uim1_present_groups[] = { 797 "gpio5", 798 }; 799 static const char *const uim1_reset_groups[] = { 800 "gpio6", 801 }; 802 static const char *const uim2_clk_groups[] = { 803 "gpio3", 804 }; 805 static const char *const uim2_data_groups[] = { 806 "gpio0", 807 }; 808 static const char *const uim2_present_groups[] = { 809 "gpio1", 810 }; 811 static const char *const uim2_reset_groups[] = { 812 "gpio2", 813 }; 814 static const char *const usb2phy_ac_en_groups[] = { 815 "gpio80", 816 }; 817 static const char *const vsense_trigger_mirnat_groups[] = { 818 "gpio37", 819 }; 820 821 static const struct pinfunction sdx75_functions[] = { 822 MSM_PIN_FUNCTION(adsp_ext), 823 MSM_PIN_FUNCTION(atest_char), 824 MSM_PIN_FUNCTION(audio_ref_clk), 825 MSM_PIN_FUNCTION(bimc_dte), 826 MSM_PIN_FUNCTION(char_exec), 827 MSM_PIN_FUNCTION(coex_uart2), 828 MSM_PIN_FUNCTION(coex_uart), 829 MSM_PIN_FUNCTION(cri_trng), 830 MSM_PIN_FUNCTION(cri_trng0), 831 MSM_PIN_FUNCTION(cri_trng1), 832 MSM_PIN_FUNCTION(dbg_out_clk), 833 MSM_PIN_FUNCTION(ddr_bist), 834 MSM_PIN_FUNCTION(ddr_pxi0), 835 MSM_PIN_FUNCTION(ebi0_wrcdc), 836 MSM_PIN_FUNCTION(ebi2_a), 837 MSM_PIN_FUNCTION(ebi2_lcd), 838 MSM_PIN_FUNCTION(ebi2_lcd_te), 839 MSM_PIN_FUNCTION(emac0_mcg), 840 MSM_PIN_FUNCTION(emac0_ptp), 841 MSM_PIN_FUNCTION(emac1_mcg), 842 MSM_PIN_FUNCTION(emac1_ptp), 843 MSM_PIN_FUNCTION(emac_cdc), 844 MSM_PIN_FUNCTION(emac_pps_in), 845 MSM_PIN_FUNCTION(eth0_mdc), 846 MSM_PIN_FUNCTION(eth0_mdio), 847 MSM_PIN_FUNCTION(eth1_mdc), 848 MSM_PIN_FUNCTION(eth1_mdio), 849 MSM_PIN_FUNCTION(ext_dbg), 850 MSM_PIN_FUNCTION(gcc_125_clk), 851 MSM_PIN_FUNCTION(gcc_gp1_clk), 852 MSM_PIN_FUNCTION(gcc_gp2_clk), 853 MSM_PIN_FUNCTION(gcc_gp3_clk), 854 MSM_PIN_FUNCTION(gcc_plltest), 855 MSM_PIN_FUNCTION(gpio), 856 MSM_PIN_FUNCTION(i2s_mclk), 857 MSM_PIN_FUNCTION(jitter_bist), 858 MSM_PIN_FUNCTION(ldo_en), 859 MSM_PIN_FUNCTION(ldo_update), 860 MSM_PIN_FUNCTION(m_voc), 861 MSM_PIN_FUNCTION(mgpi_clk), 862 MSM_PIN_FUNCTION(native_char), 863 MSM_PIN_FUNCTION(native_tsens), 864 MSM_PIN_FUNCTION(native_tsense), 865 MSM_PIN_FUNCTION(nav_dr_sync), 866 MSM_PIN_FUNCTION(nav_gpio), 867 MSM_PIN_FUNCTION(pa_indicator), 868 MSM_PIN_FUNCTION(pci_e), 869 MSM_PIN_FUNCTION(pcie0_clkreq_n), 870 MSM_PIN_FUNCTION(pcie1_clkreq_n), 871 MSM_PIN_FUNCTION(pcie2_clkreq_n), 872 MSM_PIN_FUNCTION(pll_bist_sync), 873 MSM_PIN_FUNCTION(pll_clk_aux), 874 MSM_PIN_FUNCTION(pll_ref_clk), 875 MSM_PIN_FUNCTION(pri_mi2s), 876 MSM_PIN_FUNCTION(prng_rosc), 877 MSM_PIN_FUNCTION(qdss_cti), 878 MSM_PIN_FUNCTION(qdss_gpio), 879 MSM_PIN_FUNCTION(qlink0_b_en), 880 MSM_PIN_FUNCTION(qlink0_b_req), 881 MSM_PIN_FUNCTION(qlink0_l_en), 882 MSM_PIN_FUNCTION(qlink0_l_req), 883 MSM_PIN_FUNCTION(qlink1_l_en), 884 MSM_PIN_FUNCTION(qlink1_l_req), 885 MSM_PIN_FUNCTION(qlink0_wmss), 886 MSM_PIN_FUNCTION(qlink1_wmss), 887 MSM_PIN_FUNCTION(qup_se0), 888 MSM_PIN_FUNCTION(qup_se1_l2_mira), 889 MSM_PIN_FUNCTION(qup_se1_l2_mirb), 890 MSM_PIN_FUNCTION(qup_se1_l3_mira), 891 MSM_PIN_FUNCTION(qup_se1_l3_mirb), 892 MSM_PIN_FUNCTION(qup_se2), 893 MSM_PIN_FUNCTION(qup_se3), 894 MSM_PIN_FUNCTION(qup_se4), 895 MSM_PIN_FUNCTION(qup_se5), 896 MSM_PIN_FUNCTION(qup_se6), 897 MSM_PIN_FUNCTION(qup_se7), 898 MSM_PIN_FUNCTION(qup_se8), 899 MSM_PIN_FUNCTION(rgmii_rx_ctl), 900 MSM_PIN_FUNCTION(rgmii_rxc), 901 MSM_PIN_FUNCTION(rgmii_rxd), 902 MSM_PIN_FUNCTION(rgmii_tx_ctl), 903 MSM_PIN_FUNCTION(rgmii_txc), 904 MSM_PIN_FUNCTION(rgmii_txd), 905 MSM_PIN_FUNCTION(sd_card), 906 MSM_PIN_FUNCTION(sdc1_tb), 907 MSM_PIN_FUNCTION(sdc2_tb_trig), 908 MSM_PIN_FUNCTION(sec_mi2s), 909 MSM_PIN_FUNCTION(sgmii_phy_intr0_n), 910 MSM_PIN_FUNCTION(sgmii_phy_intr1_n), 911 MSM_PIN_FUNCTION(spmi_coex), 912 MSM_PIN_FUNCTION(spmi_vgi), 913 MSM_PIN_FUNCTION(tgu_ch0_trigout), 914 MSM_PIN_FUNCTION(tmess_prng0), 915 MSM_PIN_FUNCTION(tmess_prng1), 916 MSM_PIN_FUNCTION(tmess_prng2), 917 MSM_PIN_FUNCTION(tmess_prng3), 918 MSM_PIN_FUNCTION(tri_mi2s), 919 MSM_PIN_FUNCTION(uim1_clk), 920 MSM_PIN_FUNCTION(uim1_data), 921 MSM_PIN_FUNCTION(uim1_present), 922 MSM_PIN_FUNCTION(uim1_reset), 923 MSM_PIN_FUNCTION(uim2_clk), 924 MSM_PIN_FUNCTION(uim2_data), 925 MSM_PIN_FUNCTION(uim2_present), 926 MSM_PIN_FUNCTION(uim2_reset), 927 MSM_PIN_FUNCTION(usb2phy_ac_en), 928 MSM_PIN_FUNCTION(vsense_trigger_mirnat), 929 }; 930 931 static const struct msm_pingroup sdx75_groups[] = { 932 [0] = PINGROUP(0, uim2_data, ebi0_wrcdc, _, _, _, _, _, _, _, _), 933 [1] = PINGROUP(1, uim2_present, _, _, _, _, _, _, _, _, _), 934 [2] = PINGROUP(2, uim2_reset, ebi0_wrcdc, _, _, _, _, _, _, _, _), 935 [3] = PINGROUP(3, uim2_clk, _, _, _, _, _, _, _, _, _), 936 [4] = PINGROUP(4, uim1_data, _, _, _, _, _, _, _, _, _), 937 [5] = PINGROUP(5, uim1_present, _, _, _, _, _, _, _, _, _), 938 [6] = PINGROUP(6, uim1_reset, char_exec, _, _, _, _, _, _, _, _), 939 [7] = PINGROUP(7, uim1_clk, char_exec, _, _, _, _, _, _, _, _), 940 [8] = PINGROUP(8, qup_se0, ldo_en, _, _, _, _, _, _, _, _), 941 [9] = PINGROUP(9, qup_se0, _, _, _, _, _, _, _, _, _), 942 [10] = PINGROUP(10, qup_se0, _, _, _, _, _, _, _, _, _), 943 [11] = PINGROUP(11, qup_se0, _, _, _, _, _, _, _, _, _), 944 [12] = PINGROUP(12, qup_se1_l2_mira, ext_dbg, _, _, _, _, _, _, _, _), 945 [13] = PINGROUP(13, qup_se1_l3_mira, ext_dbg, _, _, _, _, _, _, _, _), 946 [14] = PINGROUP(14, qup_se2, ext_dbg, bimc_dte, _, _, _, _, _, _, _), 947 [15] = PINGROUP(15, qup_se2, ext_dbg, bimc_dte, _, _, _, _, _, _, _), 948 [16] = PINGROUP(16, pri_mi2s, qup_se2, qup_se1_l2_mirb, qdss_cti, qdss_cti, _, _, _, _, _), 949 [17] = PINGROUP(17, pri_mi2s, qup_se2, qup_se1_l3_mirb, qdss_cti, qdss_cti, _, _, _, _, _), 950 [18] = PINGROUP(18, pri_mi2s, _, _, _, _, _, _, _, _, _), 951 [19] = PINGROUP(19, pri_mi2s, _, _, _, _, _, _, _, _, _), 952 [20] = PINGROUP(20, sec_mi2s, _, _, _, _, _, _, _, _, _), 953 [21] = PINGROUP(21, sec_mi2s, _, _, _, _, _, _, _, _, _), 954 [22] = PINGROUP(22, sec_mi2s, _, _, _, _, _, _, _, _, _), 955 [23] = PINGROUP(23, sec_mi2s, _, _, _, _, _, _, _, _, _), 956 [24] = PINGROUP(24, _, atest_char, _, _, _, _, _, _, _, _), 957 [25] = PINGROUP(25, gcc_125_clk, _, atest_char, _, _, _, _, _, _, _), 958 [26] = PINGROUP(26, _, _, qlink1_l_en, dbg_out_clk, atest_char, _, _, _, _, _), 959 [27] = PINGROUP(27, _, _, qlink1_l_req, prng_rosc, _, _, _, _, _, _), 960 [28] = PINGROUP(28, _, qlink1_wmss, tmess_prng0, _, _, _, _, _, _, _), 961 [29] = PINGROUP(29, _, _, _, native_char, tmess_prng1, _, _, _, _, _), 962 [30] = PINGROUP(30, _, _, _, tmess_prng2, _, _, _, _, _, _), 963 [31] = PINGROUP(31, _, _, cri_trng0, _, tmess_prng3, _, _, _, _, _), 964 [32] = PINGROUP(32, _, _, cri_trng1, _, _, _, _, _, _, _), 965 [33] = PINGROUP(33, _, _, native_char, _, _, _, _, _, _, _), 966 [34] = PINGROUP(34, _, _, _, _, _, _, _, _, _, _), 967 [35] = PINGROUP(35, nav_gpio, emac0_ptp, emac0_ptp, _, _, _, _, _, _, _), 968 [36] = PINGROUP(36, nav_gpio, nav_dr_sync, nav_gpio, cri_trng, prng_rosc, _, _, _, _, _), 969 [37] = PINGROUP(37, qlink0_l_en, _, pll_ref_clk, prng_rosc, vsense_trigger_mirnat, _, _, _, _, _), 970 [38] = PINGROUP(38, qlink0_l_req, _, pll_bist_sync, prng_rosc, _, emac_cdc, _, native_tsens, _, _), 971 [39] = PINGROUP(39, qlink0_wmss, _, mgpi_clk, gcc_gp1_clk, _, emac_cdc, _, _, _, _), 972 [40] = PINGROUP(40, qlink0_b_en, _, mgpi_clk, pll_clk_aux, gcc_gp2_clk, _, _, _, _, _), 973 [41] = PINGROUP(41, qlink0_b_req, _, jitter_bist, gcc_gp3_clk, _, _, atest_char, _, _, _), 974 [42] = PINGROUP(42, pci_e, _, _, _, _, _, _, _, _, _), 975 [43] = PINGROUP(43, pcie0_clkreq_n, _, _, _, _, _, _, _, _, _), 976 [44] = PINGROUP(44, _, _, _, _, _, _, _, _, _, _), 977 [45] = PINGROUP(45, ddr_pxi0, _, _, _, _, _, _, _, _, _), 978 [46] = PINGROUP(46, coex_uart, ddr_bist, ddr_pxi0, _, _, _, _, _, _, _), 979 [47] = PINGROUP(47, coex_uart, ddr_bist, _, _, _, _, _, _, _, _), 980 [48] = PINGROUP(48, coex_uart2, spmi_coex, ddr_bist, _, _, _, _, _, _, _), 981 [49] = PINGROUP(49, coex_uart2, spmi_coex, ddr_bist, _, _, _, _, _, _, _), 982 [50] = PINGROUP(50, spmi_vgi, _, _, _, _, _, _, _, _, _), 983 [51] = PINGROUP(51, spmi_vgi, _, _, _, _, _, _, _, _, _), 984 [52] = PINGROUP(52, qup_se3, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 985 [53] = PINGROUP(53, qup_se3, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 986 [54] = PINGROUP(54, qup_se3, _, _, _, _, _, _, _, _, _), 987 [55] = PINGROUP(55, qup_se3, tgu_ch0_trigout, _, _, _, _, _, _, _, _), 988 [56] = PINGROUP(56, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), 989 [57] = PINGROUP(57, qdss_cti, qdss_cti, _, native_char, _, _, _, _, _, _), 990 [58] = PINGROUP(58, _, pa_indicator, _, _, _, _, _, _, _, _), 991 [59] = PINGROUP(59, adsp_ext, qdss_cti, _, bimc_dte, _, _, _, _, _, _), 992 [60] = PINGROUP(60, qdss_cti, _, _, _, _, _, _, _, _, _), 993 [61] = PINGROUP(61, _, bimc_dte, _, _, _, _, _, _, _, _), 994 [62] = PINGROUP(62, m_voc, ldo_update, _, _, _, _, _, _, _, _), 995 [63] = PINGROUP(63, m_voc, _, atest_char, _, _, _, _, _, _, _), 996 [64] = PINGROUP(64, qup_se4, m_voc, _, native_tsense, _, _, _, _, _, _), 997 [65] = PINGROUP(65, qup_se4, m_voc, _, _, _, _, _, _, _, _), 998 [66] = PINGROUP(66, _, native_char, _, _, _, _, _, _, _, _), 999 [67] = PINGROUP(67, _, native_char, _, _, _, _, _, _, _, _), 1000 [68] = PINGROUP(68, adsp_ext, _, _, _, _, _, _, _, _, _), 1001 [69] = PINGROUP(69, _, _, _, _, _, _, _, _, _, _), 1002 [70] = PINGROUP(70, _, _, _, _, _, _, _, _, _, _), 1003 [71] = PINGROUP(71, m_voc, _, _, _, _, _, _, _, _, _), 1004 [72] = PINGROUP(72, _, _, _, _, _, _, _, _, _, _), 1005 [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _), 1006 [74] = PINGROUP(74, i2s_mclk, _, _, _, _, _, _, _, _, _), 1007 [75] = PINGROUP(75, _, _, _, _, _, _, _, _, _, _), 1008 [76] = PINGROUP(76, native_tsense, _, _, _, _, _, _, _, _, _), 1009 [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _, _), 1010 [78] = PINGROUP(78, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), 1011 [79] = PINGROUP(79, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), 1012 [80] = PINGROUP(80, usb2phy_ac_en, _, _, _, _, _, _, _, _, _), 1013 [81] = PINGROUP(81, gcc_plltest, _, _, _, _, _, _, _, _, _), 1014 [82] = PINGROUP(82, rgmii_txc, gcc_plltest, qdss_gpio, _, _, _, _, _, _, _), 1015 [83] = PINGROUP(83, rgmii_txd, emac0_ptp, emac0_ptp, emac0_mcg, qdss_gpio, _, _, _, _, _), 1016 [84] = PINGROUP(84, rgmii_txd, emac0_ptp, emac0_mcg, qdss_gpio, _, sdc1_tb, _, _, _, _), 1017 [85] = PINGROUP(85, rgmii_txd, emac0_ptp, emac0_mcg, qdss_gpio, _, _, _, _, _, _), 1018 [86] = PINGROUP(86, rgmii_txd, _, _, _, _, _, _, _, _, _), 1019 [87] = PINGROUP(87, rgmii_tx_ctl, _, _, _, _, _, _, _, _, _), 1020 [88] = PINGROUP(88, rgmii_rxc, _, _, _, _, _, _, _, _, _), 1021 [89] = PINGROUP(89, rgmii_rxd, emac0_ptp, emac0_ptp, emac0_mcg, _, _, _, _, _, _), 1022 [90] = PINGROUP(90, rgmii_rxd, coex_uart2, emac1_mcg, _, _, _, _, _, _, _), 1023 [91] = PINGROUP(91, rgmii_rxd, coex_uart2, _, _, _, _, _, _, _, _), 1024 [92] = PINGROUP(92, rgmii_rxd, emac1_mcg, _, _, _, _, _, _, _, _), 1025 [93] = PINGROUP(93, rgmii_rx_ctl, emac1_mcg, _, _, _, _, _, _, _, _), 1026 [94] = PINGROUP(94, eth0_mdc, qdss_gpio, _, _, _, _, _, _, _, _), 1027 [95] = PINGROUP(95, eth0_mdio, qdss_gpio, _, _, _, _, _, _, _, _), 1028 [96] = PINGROUP(96, qdss_gpio, _, _, _, _, _, _, _, _, _), 1029 [97] = PINGROUP(97, sgmii_phy_intr0_n, _, qdss_gpio, _, _, _, _, _, _, _), 1030 [98] = PINGROUP(98, tri_mi2s, ebi2_lcd_te, _, _, _, _, _, _, _, _), 1031 [99] = PINGROUP(99, tri_mi2s, ebi2_lcd, _, _, _, _, _, _, _, _), 1032 [100] = PINGROUP(100, tri_mi2s, ebi2_a, _, _, _, _, _, _, _, _), 1033 [101] = PINGROUP(101, tri_mi2s, ebi2_lcd, _, _, _, _, _, _, _, _), 1034 [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _), 1035 [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _), 1036 [104] = PINGROUP(104, nav_gpio, _, _, _, _, _, _, _, _, _), 1037 [105] = PINGROUP(105, sd_card, _, _, _, _, _, _, _, _, _), 1038 [106] = PINGROUP(106, eth1_mdc, _, _, _, _, _, _, _, _, _), 1039 [107] = PINGROUP(107, eth1_mdio, _, _, _, _, _, _, _, _, _), 1040 [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _, _), 1041 [109] = PINGROUP(109, sgmii_phy_intr1_n, _, _, _, _, _, _, _, _, _), 1042 [110] = PINGROUP(110, qup_se5, qdss_gpio, _, _, _, _, _, _, _, _), 1043 [111] = PINGROUP(111, qup_se5, qdss_gpio, _, _, _, _, _, _, _, _), 1044 [112] = PINGROUP(112, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _), 1045 [113] = PINGROUP(113, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _), 1046 [114] = PINGROUP(114, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _), 1047 [115] = PINGROUP(115, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _), 1048 [116] = PINGROUP(116, qup_se7, qdss_gpio, _, _, _, _, _, _, _, _), 1049 [117] = PINGROUP(117, qup_se7, qdss_gpio, _, _, _, _, _, _, _, _), 1050 [118] = PINGROUP(118, qup_se7, qdss_gpio, _, _, _, _, _, _, _, _), 1051 [119] = PINGROUP(119, qup_se7, emac0_ptp, qdss_gpio, _, _, _, _, _, _, _), 1052 [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _, _), 1053 [121] = PINGROUP(121, pcie2_clkreq_n, _, _, _, _, _, _, _, _, _), 1054 [122] = PINGROUP(122, emac1_mcg, _, _, _, _, _, _, _, _, _), 1055 [123] = PINGROUP(123, emac0_ptp, emac0_ptp, emac0_ptp, emac0_ptp, _, _, _, _, _, _), 1056 [124] = PINGROUP(124, pcie1_clkreq_n, qup_se8, _, _, _, _, _, _, _, _), 1057 [125] = PINGROUP(125, qup_se8, _, _, _, _, _, _, _, _, _), 1058 [126] = PINGROUP(126, audio_ref_clk, _, _, _, _, _, _, _, _, _), 1059 [127] = PINGROUP(127, emac_pps_in, _, _, _, _, _, _, _, _, _), 1060 [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _, _), 1061 [129] = PINGROUP(129, sdc2_tb_trig, _, _, _, _, _, _, _, _, _), 1062 [130] = PINGROUP(130, sdc1_tb, _, _, _, _, _, _, _, _, _), 1063 [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _, _), 1064 [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _, _), 1065 [133] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x19a000, 16, 0), 1066 [134] = SDC_QDSD_PINGROUP(sdc1_clk, 0x19a000, 14, 6), 1067 [135] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x19a000, 11, 3), 1068 [136] = SDC_QDSD_PINGROUP(sdc1_data, 0x19a000, 9, 0), 1069 [137] = SDC_QDSD_PINGROUP(sdc2_clk, 0x19b000, 14, 6), 1070 [138] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x19b000, 11, 3), 1071 [139] = SDC_QDSD_PINGROUP(sdc2_data, 0x19b000, 9, 0), 1072 }; 1073 1074 static const struct msm_gpio_wakeirq_map sdx75_pdc_map[] = { 1075 { 1, 57 }, { 2, 91 }, {5, 52 }, { 6, 109 }, { 9, 129 }, { 11, 62 }, 1076 { 13, 84 }, { 15, 87 }, { 17, 88 }, { 18, 89 }, { 19, 90 }, { 20, 92 }, 1077 { 21, 93 }, { 22, 94 }, { 23, 95 }, { 25, 96 }, { 27, 97 }, { 35, 58 }, 1078 { 36, 53 }, { 38, 98 }, { 39, 99 }, { 40, 100 }, { 41, 101 }, { 42, 54 }, 1079 { 43, 56 }, { 44, 71 }, { 46, 60 }, { 47, 61 }, { 49, 47 }, { 50, 126 }, 1080 { 51, 55 }, { 52, 102 }, { 53, 141 }, { 54, 104 }, { 55, 105 }, { 56, 106 }, 1081 { 57, 107 }, { 59, 108 }, { 60, 110 }, { 62, 111 }, { 63, 112 }, { 64, 113 }, 1082 { 65, 114 }, { 67, 115 }, { 68, 116 }, { 69, 117 }, { 70, 118 }, { 71, 119 }, 1083 { 72, 120 }, { 75, 121 }, { 76, 122 }, { 78, 123 }, { 79, 124 }, { 80, 125 }, 1084 { 81, 50 }, { 85, 127 }, { 87, 128 }, { 91, 130 }, { 92, 131 }, { 93, 132 }, 1085 { 94, 133 }, { 95, 134 }, { 97, 135 }, { 98, 136 }, { 101, 64 }, { 103, 51 }, 1086 { 105, 65 }, { 106, 66 }, { 107, 67 }, { 108, 68 }, { 109, 69 }, { 111, 70 }, 1087 { 113, 59 }, { 115, 72 }, { 116, 73 }, { 117, 74 }, { 118, 75 }, { 119, 76 }, 1088 { 120, 77 }, { 121, 78 }, { 123, 79 }, { 124, 80 }, { 125, 63 }, { 127, 81 }, 1089 { 128, 82 }, { 129, 83 }, { 130, 85 }, { 132, 86 }, 1090 }; 1091 1092 static const struct msm_pinctrl_soc_data sdx75_pinctrl = { 1093 .pins = sdx75_pins, 1094 .npins = ARRAY_SIZE(sdx75_pins), 1095 .functions = sdx75_functions, 1096 .nfunctions = ARRAY_SIZE(sdx75_functions), 1097 .groups = sdx75_groups, 1098 .ngroups = ARRAY_SIZE(sdx75_groups), 1099 .ngpios = 133, 1100 .wakeirq_map = sdx75_pdc_map, 1101 .nwakeirq_map = ARRAY_SIZE(sdx75_pdc_map), 1102 }; 1103 1104 static const struct of_device_id sdx75_pinctrl_of_match[] = { 1105 { .compatible = "qcom,sdx75-tlmm", .data = &sdx75_pinctrl }, 1106 { } 1107 }; 1108 MODULE_DEVICE_TABLE(of, sdx75_pinctrl_of_match); 1109 1110 static int sdx75_pinctrl_probe(struct platform_device *pdev) 1111 { 1112 const struct msm_pinctrl_soc_data *pinctrl_data; 1113 1114 pinctrl_data = of_device_get_match_data(&pdev->dev); 1115 if (!pinctrl_data) 1116 return -EINVAL; 1117 1118 return msm_pinctrl_probe(pdev, pinctrl_data); 1119 } 1120 1121 static struct platform_driver sdx75_pinctrl_driver = { 1122 .driver = { 1123 .name = "sdx75-tlmm", 1124 .of_match_table = sdx75_pinctrl_of_match, 1125 }, 1126 .probe = sdx75_pinctrl_probe, 1127 .remove_new = msm_pinctrl_remove, 1128 }; 1129 1130 static int __init sdx75_pinctrl_init(void) 1131 { 1132 return platform_driver_register(&sdx75_pinctrl_driver); 1133 } 1134 arch_initcall(sdx75_pinctrl_init); 1135 1136 static void __exit sdx75_pinctrl_exit(void) 1137 { 1138 platform_driver_unregister(&sdx75_pinctrl_driver); 1139 } 1140 module_exit(sdx75_pinctrl_exit); 1141 1142 MODULE_DESCRIPTION("QTI sdx75 pinctrl driver"); 1143 MODULE_LICENSE("GPL"); 1144