1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/platform_device.h> 9 10 #include "pinctrl-msm.h" 11 12 #define REG_SIZE 0x1000 13 14 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 15 { \ 16 .grp = PINCTRL_PINGROUP("gpio" #id, \ 17 gpio##id##_pins, \ 18 ARRAY_SIZE(gpio##id##_pins)), \ 19 .funcs = (int[]){ \ 20 msm_mux_gpio, /* gpio mode */ \ 21 msm_mux_##f1, \ 22 msm_mux_##f2, \ 23 msm_mux_##f3, \ 24 msm_mux_##f4, \ 25 msm_mux_##f5, \ 26 msm_mux_##f6, \ 27 msm_mux_##f7, \ 28 msm_mux_##f8, \ 29 msm_mux_##f9 \ 30 }, \ 31 .nfuncs = 10, \ 32 .ctl_reg = REG_SIZE * id, \ 33 .io_reg = 0x4 + REG_SIZE * id, \ 34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 35 .intr_status_reg = 0xc + REG_SIZE * id, \ 36 .mux_bit = 2, \ 37 .pull_bit = 0, \ 38 .drv_bit = 6, \ 39 .oe_bit = 9, \ 40 .in_bit = 0, \ 41 .out_bit = 1, \ 42 .intr_enable_bit = 0, \ 43 .intr_status_bit = 0, \ 44 .intr_target_bit = 5, \ 45 .intr_target_kpss_val = 3, \ 46 .intr_raw_status_bit = 4, \ 47 .intr_polarity_bit = 1, \ 48 .intr_detection_bit = 2, \ 49 .intr_detection_width = 2, \ 50 } 51 52 #define SDC_PINGROUP(pg_name, ctl, pull, drv) \ 53 { \ 54 .grp = PINCTRL_PINGROUP(#pg_name, \ 55 pg_name##_pins, \ 56 ARRAY_SIZE(pg_name##_pins)), \ 57 .ctl_reg = ctl, \ 58 .io_reg = 0, \ 59 .intr_cfg_reg = 0, \ 60 .intr_status_reg = 0, \ 61 .mux_bit = -1, \ 62 .pull_bit = pull, \ 63 .drv_bit = drv, \ 64 .oe_bit = -1, \ 65 .in_bit = -1, \ 66 .out_bit = -1, \ 67 .intr_enable_bit = -1, \ 68 .intr_status_bit = -1, \ 69 .intr_target_bit = -1, \ 70 .intr_raw_status_bit = -1, \ 71 .intr_polarity_bit = -1, \ 72 .intr_detection_bit = -1, \ 73 .intr_detection_width = -1, \ 74 } 75 76 static const struct pinctrl_pin_desc sdx55_pins[] = { 77 PINCTRL_PIN(0, "GPIO_0"), 78 PINCTRL_PIN(1, "GPIO_1"), 79 PINCTRL_PIN(2, "GPIO_2"), 80 PINCTRL_PIN(3, "GPIO_3"), 81 PINCTRL_PIN(4, "GPIO_4"), 82 PINCTRL_PIN(5, "GPIO_5"), 83 PINCTRL_PIN(6, "GPIO_6"), 84 PINCTRL_PIN(7, "GPIO_7"), 85 PINCTRL_PIN(8, "GPIO_8"), 86 PINCTRL_PIN(9, "GPIO_9"), 87 PINCTRL_PIN(10, "GPIO_10"), 88 PINCTRL_PIN(11, "GPIO_11"), 89 PINCTRL_PIN(12, "GPIO_12"), 90 PINCTRL_PIN(13, "GPIO_13"), 91 PINCTRL_PIN(14, "GPIO_14"), 92 PINCTRL_PIN(15, "GPIO_15"), 93 PINCTRL_PIN(16, "GPIO_16"), 94 PINCTRL_PIN(17, "GPIO_17"), 95 PINCTRL_PIN(18, "GPIO_18"), 96 PINCTRL_PIN(19, "GPIO_19"), 97 PINCTRL_PIN(20, "GPIO_20"), 98 PINCTRL_PIN(21, "GPIO_21"), 99 PINCTRL_PIN(22, "GPIO_22"), 100 PINCTRL_PIN(23, "GPIO_23"), 101 PINCTRL_PIN(24, "GPIO_24"), 102 PINCTRL_PIN(25, "GPIO_25"), 103 PINCTRL_PIN(26, "GPIO_26"), 104 PINCTRL_PIN(27, "GPIO_27"), 105 PINCTRL_PIN(28, "GPIO_28"), 106 PINCTRL_PIN(29, "GPIO_29"), 107 PINCTRL_PIN(30, "GPIO_30"), 108 PINCTRL_PIN(31, "GPIO_31"), 109 PINCTRL_PIN(32, "GPIO_32"), 110 PINCTRL_PIN(33, "GPIO_33"), 111 PINCTRL_PIN(34, "GPIO_34"), 112 PINCTRL_PIN(35, "GPIO_35"), 113 PINCTRL_PIN(36, "GPIO_36"), 114 PINCTRL_PIN(37, "GPIO_37"), 115 PINCTRL_PIN(38, "GPIO_38"), 116 PINCTRL_PIN(39, "GPIO_39"), 117 PINCTRL_PIN(40, "GPIO_40"), 118 PINCTRL_PIN(41, "GPIO_41"), 119 PINCTRL_PIN(42, "GPIO_42"), 120 PINCTRL_PIN(43, "GPIO_43"), 121 PINCTRL_PIN(44, "GPIO_44"), 122 PINCTRL_PIN(45, "GPIO_45"), 123 PINCTRL_PIN(46, "GPIO_46"), 124 PINCTRL_PIN(47, "GPIO_47"), 125 PINCTRL_PIN(48, "GPIO_48"), 126 PINCTRL_PIN(49, "GPIO_49"), 127 PINCTRL_PIN(50, "GPIO_50"), 128 PINCTRL_PIN(51, "GPIO_51"), 129 PINCTRL_PIN(52, "GPIO_52"), 130 PINCTRL_PIN(53, "GPIO_53"), 131 PINCTRL_PIN(54, "GPIO_54"), 132 PINCTRL_PIN(55, "GPIO_55"), 133 PINCTRL_PIN(56, "GPIO_56"), 134 PINCTRL_PIN(57, "GPIO_57"), 135 PINCTRL_PIN(58, "GPIO_58"), 136 PINCTRL_PIN(59, "GPIO_59"), 137 PINCTRL_PIN(60, "GPIO_60"), 138 PINCTRL_PIN(61, "GPIO_61"), 139 PINCTRL_PIN(62, "GPIO_62"), 140 PINCTRL_PIN(63, "GPIO_63"), 141 PINCTRL_PIN(64, "GPIO_64"), 142 PINCTRL_PIN(65, "GPIO_65"), 143 PINCTRL_PIN(66, "GPIO_66"), 144 PINCTRL_PIN(67, "GPIO_67"), 145 PINCTRL_PIN(68, "GPIO_68"), 146 PINCTRL_PIN(69, "GPIO_69"), 147 PINCTRL_PIN(70, "GPIO_70"), 148 PINCTRL_PIN(71, "GPIO_71"), 149 PINCTRL_PIN(72, "GPIO_72"), 150 PINCTRL_PIN(73, "GPIO_73"), 151 PINCTRL_PIN(74, "GPIO_74"), 152 PINCTRL_PIN(75, "GPIO_75"), 153 PINCTRL_PIN(76, "GPIO_76"), 154 PINCTRL_PIN(77, "GPIO_77"), 155 PINCTRL_PIN(78, "GPIO_78"), 156 PINCTRL_PIN(79, "GPIO_79"), 157 PINCTRL_PIN(80, "GPIO_80"), 158 PINCTRL_PIN(81, "GPIO_81"), 159 PINCTRL_PIN(82, "GPIO_82"), 160 PINCTRL_PIN(83, "GPIO_83"), 161 PINCTRL_PIN(84, "GPIO_84"), 162 PINCTRL_PIN(85, "GPIO_85"), 163 PINCTRL_PIN(86, "GPIO_86"), 164 PINCTRL_PIN(87, "GPIO_87"), 165 PINCTRL_PIN(88, "GPIO_88"), 166 PINCTRL_PIN(89, "GPIO_89"), 167 PINCTRL_PIN(90, "GPIO_90"), 168 PINCTRL_PIN(91, "GPIO_91"), 169 PINCTRL_PIN(92, "GPIO_92"), 170 PINCTRL_PIN(93, "GPIO_93"), 171 PINCTRL_PIN(94, "GPIO_94"), 172 PINCTRL_PIN(95, "GPIO_95"), 173 PINCTRL_PIN(96, "GPIO_96"), 174 PINCTRL_PIN(97, "GPIO_97"), 175 PINCTRL_PIN(98, "GPIO_98"), 176 PINCTRL_PIN(99, "GPIO_99"), 177 PINCTRL_PIN(100, "GPIO_100"), 178 PINCTRL_PIN(101, "GPIO_101"), 179 PINCTRL_PIN(102, "GPIO_102"), 180 PINCTRL_PIN(103, "GPIO_103"), 181 PINCTRL_PIN(104, "GPIO_104"), 182 PINCTRL_PIN(105, "GPIO_105"), 183 PINCTRL_PIN(106, "GPIO_106"), 184 PINCTRL_PIN(107, "GPIO_107"), 185 PINCTRL_PIN(108, "SDC1_RCLK"), 186 PINCTRL_PIN(109, "SDC1_CLK"), 187 PINCTRL_PIN(110, "SDC1_CMD"), 188 PINCTRL_PIN(111, "SDC1_DATA"), 189 }; 190 191 #define DECLARE_MSM_GPIO_PINS(pin) \ 192 static const unsigned int gpio##pin##_pins[] = { pin } 193 DECLARE_MSM_GPIO_PINS(0); 194 DECLARE_MSM_GPIO_PINS(1); 195 DECLARE_MSM_GPIO_PINS(2); 196 DECLARE_MSM_GPIO_PINS(3); 197 DECLARE_MSM_GPIO_PINS(4); 198 DECLARE_MSM_GPIO_PINS(5); 199 DECLARE_MSM_GPIO_PINS(6); 200 DECLARE_MSM_GPIO_PINS(7); 201 DECLARE_MSM_GPIO_PINS(8); 202 DECLARE_MSM_GPIO_PINS(9); 203 DECLARE_MSM_GPIO_PINS(10); 204 DECLARE_MSM_GPIO_PINS(11); 205 DECLARE_MSM_GPIO_PINS(12); 206 DECLARE_MSM_GPIO_PINS(13); 207 DECLARE_MSM_GPIO_PINS(14); 208 DECLARE_MSM_GPIO_PINS(15); 209 DECLARE_MSM_GPIO_PINS(16); 210 DECLARE_MSM_GPIO_PINS(17); 211 DECLARE_MSM_GPIO_PINS(18); 212 DECLARE_MSM_GPIO_PINS(19); 213 DECLARE_MSM_GPIO_PINS(20); 214 DECLARE_MSM_GPIO_PINS(21); 215 DECLARE_MSM_GPIO_PINS(22); 216 DECLARE_MSM_GPIO_PINS(23); 217 DECLARE_MSM_GPIO_PINS(24); 218 DECLARE_MSM_GPIO_PINS(25); 219 DECLARE_MSM_GPIO_PINS(26); 220 DECLARE_MSM_GPIO_PINS(27); 221 DECLARE_MSM_GPIO_PINS(28); 222 DECLARE_MSM_GPIO_PINS(29); 223 DECLARE_MSM_GPIO_PINS(30); 224 DECLARE_MSM_GPIO_PINS(31); 225 DECLARE_MSM_GPIO_PINS(32); 226 DECLARE_MSM_GPIO_PINS(33); 227 DECLARE_MSM_GPIO_PINS(34); 228 DECLARE_MSM_GPIO_PINS(35); 229 DECLARE_MSM_GPIO_PINS(36); 230 DECLARE_MSM_GPIO_PINS(37); 231 DECLARE_MSM_GPIO_PINS(38); 232 DECLARE_MSM_GPIO_PINS(39); 233 DECLARE_MSM_GPIO_PINS(40); 234 DECLARE_MSM_GPIO_PINS(41); 235 DECLARE_MSM_GPIO_PINS(42); 236 DECLARE_MSM_GPIO_PINS(43); 237 DECLARE_MSM_GPIO_PINS(44); 238 DECLARE_MSM_GPIO_PINS(45); 239 DECLARE_MSM_GPIO_PINS(46); 240 DECLARE_MSM_GPIO_PINS(47); 241 DECLARE_MSM_GPIO_PINS(48); 242 DECLARE_MSM_GPIO_PINS(49); 243 DECLARE_MSM_GPIO_PINS(50); 244 DECLARE_MSM_GPIO_PINS(51); 245 DECLARE_MSM_GPIO_PINS(52); 246 DECLARE_MSM_GPIO_PINS(53); 247 DECLARE_MSM_GPIO_PINS(54); 248 DECLARE_MSM_GPIO_PINS(55); 249 DECLARE_MSM_GPIO_PINS(56); 250 DECLARE_MSM_GPIO_PINS(57); 251 DECLARE_MSM_GPIO_PINS(58); 252 DECLARE_MSM_GPIO_PINS(59); 253 DECLARE_MSM_GPIO_PINS(60); 254 DECLARE_MSM_GPIO_PINS(61); 255 DECLARE_MSM_GPIO_PINS(62); 256 DECLARE_MSM_GPIO_PINS(63); 257 DECLARE_MSM_GPIO_PINS(64); 258 DECLARE_MSM_GPIO_PINS(65); 259 DECLARE_MSM_GPIO_PINS(66); 260 DECLARE_MSM_GPIO_PINS(67); 261 DECLARE_MSM_GPIO_PINS(68); 262 DECLARE_MSM_GPIO_PINS(69); 263 DECLARE_MSM_GPIO_PINS(70); 264 DECLARE_MSM_GPIO_PINS(71); 265 DECLARE_MSM_GPIO_PINS(72); 266 DECLARE_MSM_GPIO_PINS(73); 267 DECLARE_MSM_GPIO_PINS(74); 268 DECLARE_MSM_GPIO_PINS(75); 269 DECLARE_MSM_GPIO_PINS(76); 270 DECLARE_MSM_GPIO_PINS(77); 271 DECLARE_MSM_GPIO_PINS(78); 272 DECLARE_MSM_GPIO_PINS(79); 273 DECLARE_MSM_GPIO_PINS(80); 274 DECLARE_MSM_GPIO_PINS(81); 275 DECLARE_MSM_GPIO_PINS(82); 276 DECLARE_MSM_GPIO_PINS(83); 277 DECLARE_MSM_GPIO_PINS(84); 278 DECLARE_MSM_GPIO_PINS(85); 279 DECLARE_MSM_GPIO_PINS(86); 280 DECLARE_MSM_GPIO_PINS(87); 281 DECLARE_MSM_GPIO_PINS(88); 282 DECLARE_MSM_GPIO_PINS(89); 283 DECLARE_MSM_GPIO_PINS(90); 284 DECLARE_MSM_GPIO_PINS(91); 285 DECLARE_MSM_GPIO_PINS(92); 286 DECLARE_MSM_GPIO_PINS(93); 287 DECLARE_MSM_GPIO_PINS(94); 288 DECLARE_MSM_GPIO_PINS(95); 289 DECLARE_MSM_GPIO_PINS(96); 290 DECLARE_MSM_GPIO_PINS(97); 291 DECLARE_MSM_GPIO_PINS(98); 292 DECLARE_MSM_GPIO_PINS(99); 293 DECLARE_MSM_GPIO_PINS(100); 294 DECLARE_MSM_GPIO_PINS(101); 295 DECLARE_MSM_GPIO_PINS(102); 296 DECLARE_MSM_GPIO_PINS(103); 297 DECLARE_MSM_GPIO_PINS(104); 298 DECLARE_MSM_GPIO_PINS(105); 299 DECLARE_MSM_GPIO_PINS(106); 300 DECLARE_MSM_GPIO_PINS(107); 301 302 static const unsigned int sdc1_rclk_pins[] = { 108 }; 303 static const unsigned int sdc1_clk_pins[] = { 109 }; 304 static const unsigned int sdc1_cmd_pins[] = { 110 }; 305 static const unsigned int sdc1_data_pins[] = { 111 }; 306 307 enum sdx55_functions { 308 msm_mux_adsp_ext, 309 msm_mux_atest, 310 msm_mux_audio_ref, 311 msm_mux_bimc_dte0, 312 msm_mux_bimc_dte1, 313 msm_mux_blsp_i2c1, 314 msm_mux_blsp_i2c2, 315 msm_mux_blsp_i2c3, 316 msm_mux_blsp_i2c4, 317 msm_mux_blsp_spi1, 318 msm_mux_blsp_spi2, 319 msm_mux_blsp_spi3, 320 msm_mux_blsp_spi4, 321 msm_mux_blsp_uart1, 322 msm_mux_blsp_uart2, 323 msm_mux_blsp_uart3, 324 msm_mux_blsp_uart4, 325 msm_mux_char_exec, 326 msm_mux_coex_uart, 327 msm_mux_coex_uart2, 328 msm_mux_cri_trng, 329 msm_mux_cri_trng0, 330 msm_mux_cri_trng1, 331 msm_mux_dbg_out, 332 msm_mux_ddr_bist, 333 msm_mux_ddr_pxi0, 334 msm_mux_ebi0_wrcdc, 335 msm_mux_ebi2_a, 336 msm_mux_ebi2_lcd, 337 msm_mux_emac_gcc0, 338 msm_mux_emac_gcc1, 339 msm_mux_emac_pps0, 340 msm_mux_emac_pps1, 341 msm_mux_ext_dbg, 342 msm_mux_gcc_gp1, 343 msm_mux_gcc_gp2, 344 msm_mux_gcc_gp3, 345 msm_mux_gcc_plltest, 346 msm_mux_gpio, 347 msm_mux_i2s_mclk, 348 msm_mux_jitter_bist, 349 msm_mux_ldo_en, 350 msm_mux_ldo_update, 351 msm_mux_mgpi_clk, 352 msm_mux_m_voc, 353 msm_mux_native_char, 354 msm_mux_native_char0, 355 msm_mux_native_char1, 356 msm_mux_native_char2, 357 msm_mux_native_char3, 358 msm_mux_native_tsens, 359 msm_mux_native_tsense, 360 msm_mux_nav_gpio, 361 msm_mux_pa_indicator, 362 msm_mux_pcie_clkreq, 363 msm_mux_pci_e, 364 msm_mux_pll_bist, 365 msm_mux_pll_ref, 366 msm_mux_pll_test, 367 msm_mux_pri_mi2s, 368 msm_mux_prng_rosc, 369 msm_mux_qdss_cti, 370 msm_mux_qdss_gpio, 371 msm_mux_qdss_stm, 372 msm_mux_qlink0_en, 373 msm_mux_qlink0_req, 374 msm_mux_qlink0_wmss, 375 msm_mux_qlink1_en, 376 msm_mux_qlink1_req, 377 msm_mux_qlink1_wmss, 378 msm_mux_spmi_coex, 379 msm_mux_sec_mi2s, 380 msm_mux_spmi_vgi, 381 msm_mux_tgu_ch0, 382 msm_mux_uim1_clk, 383 msm_mux_uim1_data, 384 msm_mux_uim1_present, 385 msm_mux_uim1_reset, 386 msm_mux_uim2_clk, 387 msm_mux_uim2_data, 388 msm_mux_uim2_present, 389 msm_mux_uim2_reset, 390 msm_mux_usb2phy_ac, 391 msm_mux_vsense_trigger, 392 msm_mux__, 393 }; 394 395 static const char * const gpio_groups[] = { 396 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 397 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 398 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 399 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 400 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 401 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 402 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 403 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 404 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 405 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 406 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 407 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 408 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 409 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 410 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 411 "gpio105", "gpio106", "gpio107", 412 }; 413 414 static const char * const qdss_stm_groups[] = { 415 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13", 416 "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", 417 "gpio23", "gpio44", "gpio45", "gpio52", "gpio53", "gpio56", "gpio57", "gpio61", "gpio62", 418 "gpio63", "gpio64", "gpio65", "gpio66", 419 }; 420 421 static const char * const ddr_pxi0_groups[] = { 422 "gpio45", "gpio46", 423 }; 424 425 static const char * const m_voc_groups[] = { 426 "gpio46", "gpio48", "gpio49", "gpio59", "gpio60", 427 }; 428 429 static const char * const ddr_bist_groups[] = { 430 "gpio46", "gpio47", "gpio48", "gpio49", 431 }; 432 433 static const char * const blsp_spi1_groups[] = { 434 "gpio52", "gpio62", "gpio71", "gpio80", "gpio81", "gpio82", "gpio83", 435 }; 436 437 static const char * const pci_e_groups[] = { 438 "gpio53", 439 }; 440 441 static const char * const tgu_ch0_groups[] = { 442 "gpio55", 443 }; 444 445 static const char * const pcie_clkreq_groups[] = { 446 "gpio56", 447 }; 448 449 static const char * const mgpi_clk_groups[] = { 450 "gpio61", "gpio71", 451 }; 452 453 static const char * const i2s_mclk_groups[] = { 454 "gpio62", 455 }; 456 457 static const char * const audio_ref_groups[] = { 458 "gpio62", 459 }; 460 461 static const char * const ldo_update_groups[] = { 462 "gpio62", 463 }; 464 465 static const char * const atest_groups[] = { 466 "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", 467 }; 468 469 static const char * const uim1_data_groups[] = { 470 "gpio67", 471 }; 472 473 static const char * const uim1_present_groups[] = { 474 "gpio68", 475 }; 476 477 static const char * const uim1_reset_groups[] = { 478 "gpio69", 479 }; 480 481 static const char * const uim1_clk_groups[] = { 482 "gpio70", 483 }; 484 485 static const char * const qlink1_en_groups[] = { 486 "gpio72", 487 }; 488 489 static const char * const qlink1_req_groups[] = { 490 "gpio73", 491 }; 492 493 static const char * const qlink1_wmss_groups[] = { 494 "gpio74", 495 }; 496 497 static const char * const coex_uart2_groups[] = { 498 "gpio75", "gpio76", 499 }; 500 501 static const char * const spmi_vgi_groups[] = { 502 "gpio78", "gpio79", 503 }; 504 505 static const char * const gcc_plltest_groups[] = { 506 "gpio81", "gpio82", 507 }; 508 509 static const char * const usb2phy_ac_groups[] = { 510 "gpio93", 511 }; 512 513 static const char * const emac_pps1_groups[] = { 514 "gpio95", 515 }; 516 517 static const char * const emac_pps0_groups[] = { 518 "gpio106", 519 }; 520 521 static const char * const uim2_data_groups[] = { 522 "gpio0", 523 }; 524 525 static const char * const ebi0_wrcdc_groups[] = { 526 "gpio0", "gpio2", 527 }; 528 529 static const char * const uim2_present_groups[] = { 530 "gpio1", 531 }; 532 533 static const char * const blsp_uart1_groups[] = { 534 "gpio0", "gpio1", "gpio2", "gpio3", "gpio20", "gpio21", "gpio22", 535 "gpio23", 536 }; 537 538 static const char * const uim2_reset_groups[] = { 539 "gpio2", 540 }; 541 542 static const char * const blsp_i2c1_groups[] = { 543 "gpio2", "gpio3", "gpio82", "gpio83", 544 }; 545 546 static const char * const uim2_clk_groups[] = { 547 "gpio3", 548 }; 549 550 static const char * const blsp_spi2_groups[] = { 551 "gpio4", "gpio5", "gpio6", "gpio7", "gpio52", "gpio62", "gpio71", 552 }; 553 554 static const char * const blsp_uart2_groups[] = { 555 "gpio4", "gpio5", "gpio6", "gpio7", "gpio63", "gpio64", "gpio65", 556 "gpio66", 557 }; 558 559 static const char * const blsp_i2c2_groups[] = { 560 "gpio6", "gpio7", "gpio65", "gpio66", 561 }; 562 563 static const char * const char_exec_groups[] = { 564 "gpio6", "gpio7", 565 }; 566 567 static const char * const pri_mi2s_groups[] = { 568 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 569 "gpio15", 570 }; 571 572 static const char * const blsp_spi3_groups[] = { 573 "gpio8", "gpio9", "gpio10", "gpio11", "gpio52", "gpio62", "gpio71", 574 }; 575 576 static const char * const blsp_uart3_groups[] = { 577 "gpio8", "gpio9", "gpio10", "gpio11", 578 }; 579 580 static const char * const ext_dbg_groups[] = { 581 "gpio8", "gpio9", "gpio10", "gpio11", 582 }; 583 584 static const char * const ldo_en_groups[] = { 585 "gpio8", 586 }; 587 588 static const char * const blsp_i2c3_groups[] = { 589 "gpio10", "gpio11", 590 }; 591 592 static const char * const gcc_gp3_groups[] = { 593 "gpio11", 594 }; 595 596 static const char * const emac_gcc1_groups[] = { 597 "gpio14", 598 }; 599 600 static const char * const bimc_dte0_groups[] = { 601 "gpio14", "gpio59", 602 }; 603 604 static const char * const native_tsens_groups[] = { 605 "gpio14", 606 }; 607 608 static const char * const vsense_trigger_groups[] = { 609 "gpio14", 610 }; 611 612 static const char * const emac_gcc0_groups[] = { 613 "gpio15", 614 }; 615 616 static const char * const bimc_dte1_groups[] = { 617 "gpio15", "gpio61", 618 }; 619 620 static const char * const sec_mi2s_groups[] = { 621 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", 622 "gpio23", 623 }; 624 625 static const char * const blsp_spi4_groups[] = { 626 "gpio16", "gpio17", "gpio18", "gpio19", "gpio52", "gpio62", "gpio71", 627 }; 628 629 static const char * const blsp_uart4_groups[] = { 630 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", 631 "gpio23", 632 }; 633 634 static const char * const qdss_cti_groups[] = { 635 "gpio16", "gpio16", "gpio17", "gpio17", "gpio22", "gpio22", "gpio23", 636 "gpio23", "gpio54", "gpio54", "gpio55", "gpio55", "gpio59", "gpio60", 637 "gpio94", "gpio94", "gpio95", "gpio95", 638 }; 639 640 static const char * const blsp_i2c4_groups[] = { 641 "gpio18", "gpio19", "gpio78", "gpio79", 642 }; 643 644 static const char * const gcc_gp1_groups[] = { 645 "gpio18", 646 }; 647 648 static const char * const jitter_bist_groups[] = { 649 "gpio19", 650 }; 651 652 static const char * const gcc_gp2_groups[] = { 653 "gpio19", 654 }; 655 656 static const char * const ebi2_a_groups[] = { 657 "gpio20", 658 }; 659 660 static const char * const ebi2_lcd_groups[] = { 661 "gpio21", "gpio22", "gpio23", 662 }; 663 664 static const char * const pll_bist_groups[] = { 665 "gpio22", 666 }; 667 668 static const char * const adsp_ext_groups[] = { 669 "gpio24", "gpio25", 670 }; 671 672 static const char * const native_char_groups[] = { 673 "gpio26", 674 }; 675 676 static const char * const qlink0_wmss_groups[] = { 677 "gpio28", 678 }; 679 680 static const char * const native_char3_groups[] = { 681 "gpio28", 682 }; 683 684 static const char * const native_char2_groups[] = { 685 "gpio29", 686 }; 687 688 static const char * const native_tsense_groups[] = { 689 "gpio29", 690 }; 691 692 static const char * const nav_gpio_groups[] = { 693 "gpio31", "gpio32", "gpio76", 694 }; 695 696 static const char * const pll_ref_groups[] = { 697 "gpio32", 698 }; 699 700 static const char * const pa_indicator_groups[] = { 701 "gpio33", 702 }; 703 704 static const char * const native_char0_groups[] = { 705 "gpio33", 706 }; 707 708 static const char * const qlink0_en_groups[] = { 709 "gpio34", 710 }; 711 712 static const char * const qlink0_req_groups[] = { 713 "gpio35", 714 }; 715 716 static const char * const pll_test_groups[] = { 717 "gpio35", 718 }; 719 720 static const char * const cri_trng_groups[] = { 721 "gpio36", 722 }; 723 724 static const char * const dbg_out_groups[] = { 725 "gpio36", 726 }; 727 728 static const char * const prng_rosc_groups[] = { 729 "gpio38", 730 }; 731 732 static const char * const cri_trng0_groups[] = { 733 "gpio40", 734 }; 735 736 static const char * const cri_trng1_groups[] = { 737 "gpio41", 738 }; 739 740 static const char * const qdss_gpio_groups[] = { 741 "gpio4", "gpio5", "gpio6", "gpio7", 742 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", 743 "gpio42", "gpio61", "gpio63", "gpio64", "gpio65", "gpio66", 744 }; 745 746 static const char * const native_char1_groups[] = { 747 "gpio42", 748 }; 749 750 static const char * const coex_uart_groups[] = { 751 "gpio44", "gpio45", 752 }; 753 754 static const char * const spmi_coex_groups[] = { 755 "gpio44", "gpio45", 756 }; 757 758 static const struct pinfunction sdx55_functions[] = { 759 MSM_PIN_FUNCTION(adsp_ext), 760 MSM_PIN_FUNCTION(atest), 761 MSM_PIN_FUNCTION(audio_ref), 762 MSM_PIN_FUNCTION(bimc_dte0), 763 MSM_PIN_FUNCTION(bimc_dte1), 764 MSM_PIN_FUNCTION(blsp_i2c1), 765 MSM_PIN_FUNCTION(blsp_i2c2), 766 MSM_PIN_FUNCTION(blsp_i2c3), 767 MSM_PIN_FUNCTION(blsp_i2c4), 768 MSM_PIN_FUNCTION(blsp_spi1), 769 MSM_PIN_FUNCTION(blsp_spi2), 770 MSM_PIN_FUNCTION(blsp_spi3), 771 MSM_PIN_FUNCTION(blsp_spi4), 772 MSM_PIN_FUNCTION(blsp_uart1), 773 MSM_PIN_FUNCTION(blsp_uart2), 774 MSM_PIN_FUNCTION(blsp_uart3), 775 MSM_PIN_FUNCTION(blsp_uart4), 776 MSM_PIN_FUNCTION(char_exec), 777 MSM_PIN_FUNCTION(coex_uart), 778 MSM_PIN_FUNCTION(coex_uart2), 779 MSM_PIN_FUNCTION(cri_trng), 780 MSM_PIN_FUNCTION(cri_trng0), 781 MSM_PIN_FUNCTION(cri_trng1), 782 MSM_PIN_FUNCTION(dbg_out), 783 MSM_PIN_FUNCTION(ddr_bist), 784 MSM_PIN_FUNCTION(ddr_pxi0), 785 MSM_PIN_FUNCTION(ebi0_wrcdc), 786 MSM_PIN_FUNCTION(ebi2_a), 787 MSM_PIN_FUNCTION(ebi2_lcd), 788 MSM_PIN_FUNCTION(emac_gcc0), 789 MSM_PIN_FUNCTION(emac_gcc1), 790 MSM_PIN_FUNCTION(emac_pps0), 791 MSM_PIN_FUNCTION(emac_pps1), 792 MSM_PIN_FUNCTION(ext_dbg), 793 MSM_PIN_FUNCTION(gcc_gp1), 794 MSM_PIN_FUNCTION(gcc_gp2), 795 MSM_PIN_FUNCTION(gcc_gp3), 796 MSM_PIN_FUNCTION(gcc_plltest), 797 MSM_GPIO_PIN_FUNCTION(gpio), 798 MSM_PIN_FUNCTION(i2s_mclk), 799 MSM_PIN_FUNCTION(jitter_bist), 800 MSM_PIN_FUNCTION(ldo_en), 801 MSM_PIN_FUNCTION(ldo_update), 802 MSM_PIN_FUNCTION(mgpi_clk), 803 MSM_PIN_FUNCTION(m_voc), 804 MSM_PIN_FUNCTION(native_char), 805 MSM_PIN_FUNCTION(native_char0), 806 MSM_PIN_FUNCTION(native_char1), 807 MSM_PIN_FUNCTION(native_char2), 808 MSM_PIN_FUNCTION(native_char3), 809 MSM_PIN_FUNCTION(native_tsens), 810 MSM_PIN_FUNCTION(native_tsense), 811 MSM_PIN_FUNCTION(nav_gpio), 812 MSM_PIN_FUNCTION(pa_indicator), 813 MSM_PIN_FUNCTION(pcie_clkreq), 814 MSM_PIN_FUNCTION(pci_e), 815 MSM_PIN_FUNCTION(pll_bist), 816 MSM_PIN_FUNCTION(pll_ref), 817 MSM_PIN_FUNCTION(pll_test), 818 MSM_PIN_FUNCTION(pri_mi2s), 819 MSM_PIN_FUNCTION(prng_rosc), 820 MSM_PIN_FUNCTION(qdss_cti), 821 MSM_PIN_FUNCTION(qdss_gpio), 822 MSM_PIN_FUNCTION(qdss_stm), 823 MSM_PIN_FUNCTION(qlink0_en), 824 MSM_PIN_FUNCTION(qlink0_req), 825 MSM_PIN_FUNCTION(qlink0_wmss), 826 MSM_PIN_FUNCTION(qlink1_en), 827 MSM_PIN_FUNCTION(qlink1_req), 828 MSM_PIN_FUNCTION(qlink1_wmss), 829 MSM_PIN_FUNCTION(spmi_coex), 830 MSM_PIN_FUNCTION(sec_mi2s), 831 MSM_PIN_FUNCTION(spmi_vgi), 832 MSM_PIN_FUNCTION(tgu_ch0), 833 MSM_PIN_FUNCTION(uim1_clk), 834 MSM_PIN_FUNCTION(uim1_data), 835 MSM_PIN_FUNCTION(uim1_present), 836 MSM_PIN_FUNCTION(uim1_reset), 837 MSM_PIN_FUNCTION(uim2_clk), 838 MSM_PIN_FUNCTION(uim2_data), 839 MSM_PIN_FUNCTION(uim2_present), 840 MSM_PIN_FUNCTION(uim2_reset), 841 MSM_PIN_FUNCTION(usb2phy_ac), 842 MSM_PIN_FUNCTION(vsense_trigger), 843 }; 844 845 /* Every pin is maintained as a single group, and missing or non-existing pin 846 * would be maintained as dummy group to synchronize pin group index with 847 * pin descriptor registered with pinctrl core. 848 * Clients would not be able to request these dummy pin groups. 849 */ 850 static const struct msm_pingroup sdx55_groups[] = { 851 [0] = PINGROUP(0, uim2_data, blsp_uart1, qdss_stm, ebi0_wrcdc, _, _, _, _, _), 852 [1] = PINGROUP(1, uim2_present, blsp_uart1, qdss_stm, _, _, _, _, _, _), 853 [2] = PINGROUP(2, uim2_reset, blsp_uart1, blsp_i2c1, qdss_stm, ebi0_wrcdc, _, _, _, _), 854 [3] = PINGROUP(3, uim2_clk, blsp_uart1, blsp_i2c1, qdss_stm, _, _, _, _, _), 855 [4] = PINGROUP(4, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _), 856 [5] = PINGROUP(5, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _), 857 [6] = PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _), 858 [7] = PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _), 859 [8] = PINGROUP(8, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, ldo_en, _, _, _, _), 860 [9] = PINGROUP(9, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, _, _, _, _, _), 861 [10] = PINGROUP(10, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, _, _, _, _), 862 [11] = PINGROUP(11, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, gcc_gp3, _, _, _), 863 [12] = PINGROUP(12, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _), 864 [13] = PINGROUP(13, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _), 865 [14] = PINGROUP(14, pri_mi2s, emac_gcc1, _, _, qdss_stm, qdss_gpio, bimc_dte0, native_tsens, vsense_trigger), 866 [15] = PINGROUP(15, pri_mi2s, emac_gcc0, _, _, qdss_stm, qdss_gpio, bimc_dte1, _, _), 867 [16] = PINGROUP(16, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, _, qdss_stm, qdss_gpio), 868 [17] = PINGROUP(17, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, qdss_stm, qdss_gpio, _), 869 [18] = PINGROUP(18, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, gcc_gp1, qdss_stm, qdss_gpio, _, _), 870 [19] = PINGROUP(19, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, jitter_bist, gcc_gp2, _, qdss_stm, qdss_gpio), 871 [20] = PINGROUP(20, sec_mi2s, ebi2_a, blsp_uart1, blsp_uart4, qdss_stm, _, _, _, _), 872 [21] = PINGROUP(21, sec_mi2s, ebi2_lcd, blsp_uart1, blsp_uart4, _, qdss_stm, _, _, _), 873 [22] = PINGROUP(22, sec_mi2s, ebi2_lcd, blsp_uart1, qdss_cti, qdss_cti, blsp_uart4, pll_bist, _, qdss_stm), 874 [23] = PINGROUP(23, sec_mi2s, ebi2_lcd, qdss_cti, qdss_cti, blsp_uart1, blsp_uart4, qdss_stm, _, _), 875 [24] = PINGROUP(24, adsp_ext, _, _, _, _, _, _, _, _), 876 [25] = PINGROUP(25, adsp_ext, _, _, _, _, _, _, _, _), 877 [26] = PINGROUP(26, _, _, _, native_char, _, _, _, _, _), 878 [27] = PINGROUP(27, _, _, _, _, _, _, _, _, _), 879 [28] = PINGROUP(28, qlink0_wmss, _, native_char3, _, _, _, _, _, _), 880 [29] = PINGROUP(29, _, _, _, native_char2, native_tsense, _, _, _, _), 881 [30] = PINGROUP(30, _, _, _, _, _, _, _, _, _), 882 [31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _), 883 [32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _), 884 [33] = PINGROUP(33, _, pa_indicator, native_char0, _, _, _, _, _, _), 885 [34] = PINGROUP(34, qlink0_en, _, _, _, _, _, _, _, _), 886 [35] = PINGROUP(35, qlink0_req, pll_test, _, _, _, _, _, _, _), 887 [36] = PINGROUP(36, _, _, cri_trng, dbg_out, _, _, _, _, _), 888 [37] = PINGROUP(37, _, _, _, _, _, _, _, _, _), 889 [38] = PINGROUP(38, _, _, prng_rosc, _, _, _, _, _, _), 890 [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _), 891 [40] = PINGROUP(40, _, _, cri_trng0, _, _, _, _, _, _), 892 [41] = PINGROUP(41, _, _, cri_trng1, _, _, _, _, _, _), 893 [42] = PINGROUP(42, _, qdss_gpio, native_char1, _, _, _, _, _, _), 894 [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _), 895 [44] = PINGROUP(44, coex_uart, spmi_coex, _, qdss_stm, _, _, _, _, _), 896 [45] = PINGROUP(45, coex_uart, spmi_coex, qdss_stm, ddr_pxi0, _, _, _, _, _), 897 [46] = PINGROUP(46, m_voc, ddr_bist, ddr_pxi0, _, _, _, _, _, _), 898 [47] = PINGROUP(47, ddr_bist, _, _, _, _, _, _, _, _), 899 [48] = PINGROUP(48, m_voc, ddr_bist, _, _, _, _, _, _, _), 900 [49] = PINGROUP(49, m_voc, ddr_bist, _, _, _, _, _, _, _), 901 [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), 902 [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), 903 [52] = PINGROUP(52, blsp_spi2, blsp_spi1, blsp_spi3, blsp_spi4, _, _, qdss_stm, _, _), 904 [53] = PINGROUP(53, pci_e, _, _, qdss_stm, _, _, _, _, _), 905 [54] = PINGROUP(54, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 906 [55] = PINGROUP(55, qdss_cti, qdss_cti, tgu_ch0, _, _, _, _, _, _), 907 [56] = PINGROUP(56, pcie_clkreq, _, qdss_stm, _, _, _, _, _, _), 908 [57] = PINGROUP(57, _, qdss_stm, _, _, _, _, _, _, _), 909 [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), 910 [59] = PINGROUP(59, qdss_cti, m_voc, bimc_dte0, _, _, _, _, _, _), 911 [60] = PINGROUP(60, qdss_cti, _, m_voc, _, _, _, _, _, _), 912 [61] = PINGROUP(61, mgpi_clk, qdss_stm, qdss_gpio, bimc_dte1, _, _, _, _, _), 913 [62] = PINGROUP(62, i2s_mclk, audio_ref, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, ldo_update, qdss_stm, _), 914 [63] = PINGROUP(63, blsp_uart2, _, qdss_stm, qdss_gpio, atest, _, _, _, _), 915 [64] = PINGROUP(64, blsp_uart2, qdss_stm, qdss_gpio, atest, _, _, _, _, _), 916 [65] = PINGROUP(65, blsp_uart2, blsp_i2c2, _, qdss_stm, qdss_gpio, atest, _, _, _), 917 [66] = PINGROUP(66, blsp_uart2, blsp_i2c2, qdss_stm, qdss_gpio, atest, _, _, _, _), 918 [67] = PINGROUP(67, uim1_data, atest, _, _, _, _, _, _, _), 919 [68] = PINGROUP(68, uim1_present, _, _, _, _, _, _, _, _), 920 [69] = PINGROUP(69, uim1_reset, _, _, _, _, _, _, _, _), 921 [70] = PINGROUP(70, uim1_clk, _, _, _, _, _, _, _, _), 922 [71] = PINGROUP(71, mgpi_clk, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, _, _, _, _), 923 [72] = PINGROUP(72, qlink1_en, _, _, _, _, _, _, _, _), 924 [73] = PINGROUP(73, qlink1_req, _, _, _, _, _, _, _, _), 925 [74] = PINGROUP(74, qlink1_wmss, _, _, _, _, _, _, _, _), 926 [75] = PINGROUP(75, coex_uart2, _, _, _, _, _, _, _, _), 927 [76] = PINGROUP(76, coex_uart2, nav_gpio, _, _, _, _, _, _, _), 928 [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _), 929 [78] = PINGROUP(78, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _), 930 [79] = PINGROUP(79, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _), 931 [80] = PINGROUP(80, _, blsp_spi1, _, _, _, _, _, _, _), 932 [81] = PINGROUP(81, _, blsp_spi1, _, gcc_plltest, _, _, _, _, _), 933 [82] = PINGROUP(82, _, blsp_spi1, _, blsp_i2c1, gcc_plltest, _, _, _, _), 934 [83] = PINGROUP(83, _, blsp_spi1, _, blsp_i2c1, _, _, _, _, _), 935 [84] = PINGROUP(84, _, _, _, _, _, _, _, _, _), 936 [85] = PINGROUP(85, _, _, _, _, _, _, _, _, _), 937 [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _), 938 [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _), 939 [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _), 940 [89] = PINGROUP(89, _, _, _, _, _, _, _, _, _), 941 [90] = PINGROUP(90, _, _, _, _, _, _, _, _, _), 942 [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _), 943 [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), 944 [93] = PINGROUP(93, _, _, usb2phy_ac, _, _, _, _, _, _), 945 [94] = PINGROUP(94, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 946 [95] = PINGROUP(95, qdss_cti, qdss_cti, emac_pps1, _, _, _, _, _, _), 947 [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _), 948 [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _), 949 [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _), 950 [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), 951 [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _), 952 [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _), 953 [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _), 954 [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _), 955 [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), 956 [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), 957 [106] = PINGROUP(106, emac_pps0, _, _, _, _, _, _, _, _), 958 [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), 959 [109] = SDC_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), 960 [110] = SDC_PINGROUP(sdc1_clk, 0x9a000, 13, 6), 961 [111] = SDC_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), 962 [112] = SDC_PINGROUP(sdc1_data, 0x9a000, 9, 0), 963 }; 964 965 static const struct msm_pinctrl_soc_data sdx55_pinctrl = { 966 .pins = sdx55_pins, 967 .npins = ARRAY_SIZE(sdx55_pins), 968 .functions = sdx55_functions, 969 .nfunctions = ARRAY_SIZE(sdx55_functions), 970 .groups = sdx55_groups, 971 .ngroups = ARRAY_SIZE(sdx55_groups), 972 .ngpios = 108, 973 }; 974 975 static int sdx55_pinctrl_probe(struct platform_device *pdev) 976 { 977 return msm_pinctrl_probe(pdev, &sdx55_pinctrl); 978 } 979 980 static const struct of_device_id sdx55_pinctrl_of_match[] = { 981 { .compatible = "qcom,sdx55-pinctrl", }, 982 { }, 983 }; 984 985 static struct platform_driver sdx55_pinctrl_driver = { 986 .driver = { 987 .name = "sdx55-pinctrl", 988 .of_match_table = sdx55_pinctrl_of_match, 989 }, 990 .probe = sdx55_pinctrl_probe, 991 }; 992 993 static int __init sdx55_pinctrl_init(void) 994 { 995 return platform_driver_register(&sdx55_pinctrl_driver); 996 } 997 arch_initcall(sdx55_pinctrl_init); 998 999 static void __exit sdx55_pinctrl_exit(void) 1000 { 1001 platform_driver_unregister(&sdx55_pinctrl_driver); 1002 } 1003 module_exit(sdx55_pinctrl_exit); 1004 1005 MODULE_DESCRIPTION("QTI sdx55 pinctrl driver"); 1006 MODULE_LICENSE("GPL v2"); 1007 MODULE_DEVICE_TABLE(of, sdx55_pinctrl_of_match); 1008