1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * This driver is solely based on the limited information in downstream code. 4 * Any verification with schematics would be greatly appreciated. 5 * 6 * Copyright (c) 2023, Richard Acayan. All rights reserved. 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/pinctrl/pinctrl.h> 14 15 #include "pinctrl-lpass-lpi.h" 16 17 enum lpass_lpi_functions { 18 LPI_MUX_comp_rx, 19 LPI_MUX_dmic1_clk, 20 LPI_MUX_dmic1_data, 21 LPI_MUX_dmic2_clk, 22 LPI_MUX_dmic2_data, 23 LPI_MUX_mclk0, 24 LPI_MUX_pdm_tx, 25 LPI_MUX_pdm_clk, 26 LPI_MUX_pdm_rx, 27 LPI_MUX_pdm_sync, 28 29 LPI_MUX_gpio, 30 LPI_MUX__, 31 }; 32 33 static const struct pinctrl_pin_desc sdm660_lpi_pinctrl_pins[] = { 34 PINCTRL_PIN(0, "gpio0"), 35 PINCTRL_PIN(1, "gpio1"), 36 PINCTRL_PIN(2, "gpio2"), 37 PINCTRL_PIN(3, "gpio3"), 38 PINCTRL_PIN(4, "gpio4"), 39 PINCTRL_PIN(5, "gpio5"), 40 PINCTRL_PIN(6, "gpio6"), 41 PINCTRL_PIN(7, "gpio7"), 42 PINCTRL_PIN(8, "gpio8"), 43 PINCTRL_PIN(9, "gpio9"), 44 PINCTRL_PIN(10, "gpio10"), 45 PINCTRL_PIN(11, "gpio11"), 46 PINCTRL_PIN(12, "gpio12"), 47 PINCTRL_PIN(13, "gpio13"), 48 PINCTRL_PIN(14, "gpio14"), 49 PINCTRL_PIN(15, "gpio15"), 50 PINCTRL_PIN(16, "gpio16"), 51 PINCTRL_PIN(17, "gpio17"), 52 PINCTRL_PIN(18, "gpio18"), 53 PINCTRL_PIN(19, "gpio19"), 54 PINCTRL_PIN(20, "gpio20"), 55 PINCTRL_PIN(21, "gpio21"), 56 PINCTRL_PIN(22, "gpio22"), 57 PINCTRL_PIN(23, "gpio23"), 58 PINCTRL_PIN(24, "gpio24"), 59 PINCTRL_PIN(25, "gpio25"), 60 PINCTRL_PIN(26, "gpio26"), 61 PINCTRL_PIN(27, "gpio27"), 62 PINCTRL_PIN(28, "gpio28"), 63 PINCTRL_PIN(29, "gpio29"), 64 PINCTRL_PIN(30, "gpio30"), 65 PINCTRL_PIN(31, "gpio31"), 66 }; 67 68 static const char * const comp_rx_groups[] = { "gpio22", "gpio24" }; 69 static const char * const dmic1_clk_groups[] = { "gpio26" }; 70 static const char * const dmic1_data_groups[] = { "gpio27" }; 71 static const char * const dmic2_clk_groups[] = { "gpio28" }; 72 static const char * const dmic2_data_groups[] = { "gpio29" }; 73 static const char * const mclk0_groups[] = { "gpio18" }; 74 static const char * const pdm_tx_groups[] = { "gpio20" }; 75 static const char * const pdm_clk_groups[] = { "gpio18" }; 76 static const char * const pdm_rx_groups[] = { "gpio21", "gpio23", "gpio25" }; 77 static const char * const pdm_sync_groups[] = { "gpio19" }; 78 79 const struct lpi_pingroup sdm660_lpi_pinctrl_groups[] = { 80 LPI_PINGROUP_OFFSET(0, LPI_NO_SLEW, _, _, _, _, 0x0000), 81 LPI_PINGROUP_OFFSET(1, LPI_NO_SLEW, _, _, _, _, 0x1000), 82 LPI_PINGROUP_OFFSET(2, LPI_NO_SLEW, _, _, _, _, 0x2000), 83 LPI_PINGROUP_OFFSET(3, LPI_NO_SLEW, _, _, _, _, 0x2010), 84 LPI_PINGROUP_OFFSET(4, LPI_NO_SLEW, _, _, _, _, 0x3000), 85 LPI_PINGROUP_OFFSET(5, LPI_NO_SLEW, _, _, _, _, 0x3010), 86 LPI_PINGROUP_OFFSET(6, LPI_NO_SLEW, _, _, _, _, 0x4000), 87 LPI_PINGROUP_OFFSET(7, LPI_NO_SLEW, _, _, _, _, 0x4010), 88 LPI_PINGROUP_OFFSET(8, LPI_NO_SLEW, _, _, _, _, 0x5000), 89 LPI_PINGROUP_OFFSET(9, LPI_NO_SLEW, _, _, _, _, 0x5010), 90 LPI_PINGROUP_OFFSET(10, LPI_NO_SLEW, _, _, _, _, 0x5020), 91 LPI_PINGROUP_OFFSET(11, LPI_NO_SLEW, _, _, _, _, 0x5030), 92 LPI_PINGROUP_OFFSET(12, LPI_NO_SLEW, _, _, _, _, 0x6000), 93 LPI_PINGROUP_OFFSET(13, LPI_NO_SLEW, _, _, _, _, 0x6010), 94 LPI_PINGROUP_OFFSET(14, LPI_NO_SLEW, _, _, _, _, 0x7000), 95 LPI_PINGROUP_OFFSET(15, LPI_NO_SLEW, _, _, _, _, 0x7010), 96 LPI_PINGROUP_OFFSET(16, LPI_NO_SLEW, _, _, _, _, 0x5040), 97 LPI_PINGROUP_OFFSET(17, LPI_NO_SLEW, _, _, _, _, 0x5050), 98 99 LPI_PINGROUP_OFFSET(18, LPI_NO_SLEW, pdm_clk, mclk0, _, _, 0x8000), 100 LPI_PINGROUP_OFFSET(19, LPI_NO_SLEW, pdm_sync, _, _, _, 0x8010), 101 LPI_PINGROUP_OFFSET(20, LPI_NO_SLEW, pdm_tx, _, _, _, 0x8020), 102 LPI_PINGROUP_OFFSET(21, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8030), 103 LPI_PINGROUP_OFFSET(22, LPI_NO_SLEW, comp_rx, _, _, _, 0x8040), 104 LPI_PINGROUP_OFFSET(23, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8050), 105 LPI_PINGROUP_OFFSET(24, LPI_NO_SLEW, comp_rx, _, _, _, 0x8060), 106 LPI_PINGROUP_OFFSET(25, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8070), 107 LPI_PINGROUP_OFFSET(26, LPI_NO_SLEW, dmic1_clk, _, _, _, 0x9000), 108 LPI_PINGROUP_OFFSET(27, LPI_NO_SLEW, dmic1_data, _, _, _, 0x9010), 109 LPI_PINGROUP_OFFSET(28, LPI_NO_SLEW, dmic2_clk, _, _, _, 0xa000), 110 LPI_PINGROUP_OFFSET(29, LPI_NO_SLEW, dmic2_data, _, _, _, 0xa010), 111 112 LPI_PINGROUP_OFFSET(30, LPI_NO_SLEW, _, _, _, _, 0xb000), 113 LPI_PINGROUP_OFFSET(31, LPI_NO_SLEW, _, _, _, _, 0xb010), 114 }; 115 116 const struct lpi_function sdm660_lpi_pinctrl_functions[] = { 117 LPI_FUNCTION(comp_rx), 118 LPI_FUNCTION(dmic1_clk), 119 LPI_FUNCTION(dmic1_data), 120 LPI_FUNCTION(dmic2_clk), 121 LPI_FUNCTION(dmic2_data), 122 LPI_FUNCTION(mclk0), 123 LPI_FUNCTION(pdm_tx), 124 LPI_FUNCTION(pdm_clk), 125 LPI_FUNCTION(pdm_rx), 126 LPI_FUNCTION(pdm_sync), 127 }; 128 129 static const struct lpi_pinctrl_variant_data sdm660_lpi_pinctrl_data = { 130 .pins = sdm660_lpi_pinctrl_pins, 131 .npins = ARRAY_SIZE(sdm660_lpi_pinctrl_pins), 132 .groups = sdm660_lpi_pinctrl_groups, 133 .ngroups = ARRAY_SIZE(sdm660_lpi_pinctrl_groups), 134 .functions = sdm660_lpi_pinctrl_functions, 135 .nfunctions = ARRAY_SIZE(sdm660_lpi_pinctrl_functions), 136 .flags = LPI_FLAG_SLEW_RATE_SAME_REG | LPI_FLAG_USE_PREDEFINED_PIN_OFFSET 137 }; 138 139 static const struct of_device_id sdm660_lpi_pinctrl_of_match[] = { 140 { 141 .compatible = "qcom,sdm660-lpass-lpi-pinctrl", 142 .data = &sdm660_lpi_pinctrl_data, 143 }, 144 { } 145 }; 146 MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match); 147 148 static struct platform_driver sdm660_lpi_pinctrl_driver = { 149 .driver = { 150 .name = "qcom-sdm660-lpass-lpi-pinctrl", 151 .of_match_table = sdm660_lpi_pinctrl_of_match, 152 }, 153 .probe = lpi_pinctrl_probe, 154 .remove = lpi_pinctrl_remove, 155 }; 156 module_platform_driver(sdm660_lpi_pinctrl_driver); 157 158 MODULE_AUTHOR("Richard Acayan <mailingradian@gmail.com>"); 159 MODULE_DESCRIPTION("QTI SDM660 LPI GPIO pin control driver"); 160 MODULE_LICENSE("GPL"); 161