1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/platform_device.h> 9 10 #include "pinctrl-msm.h" 11 12 #define REG_SIZE 0x1000 13 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11)\ 14 { \ 15 .grp = PINCTRL_PINGROUP("gpio" #id, \ 16 gpio##id##_pins, \ 17 ARRAY_SIZE(gpio##id##_pins)), \ 18 .funcs = (int[]){ \ 19 msm_mux_gpio, /* gpio mode */ \ 20 msm_mux_##f1, \ 21 msm_mux_##f2, \ 22 msm_mux_##f3, \ 23 msm_mux_##f4, \ 24 msm_mux_##f5, \ 25 msm_mux_##f6, \ 26 msm_mux_##f7, \ 27 msm_mux_##f8, \ 28 msm_mux_##f9, \ 29 msm_mux_##f10, \ 30 msm_mux_##f11 /* egpio mode */ \ 31 }, \ 32 .nfuncs = 12, \ 33 .ctl_reg = REG_SIZE * id, \ 34 .io_reg = 0x4 + REG_SIZE * id, \ 35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 36 .intr_status_reg = 0xc + REG_SIZE * id, \ 37 .mux_bit = 2, \ 38 .pull_bit = 0, \ 39 .drv_bit = 6, \ 40 .egpio_enable = 12, \ 41 .egpio_present = 11, \ 42 .oe_bit = 9, \ 43 .in_bit = 0, \ 44 .out_bit = 1, \ 45 .intr_enable_bit = 0, \ 46 .intr_status_bit = 0, \ 47 .intr_target_bit = 5, \ 48 .intr_target_kpss_val = 3, \ 49 .intr_raw_status_bit = 4, \ 50 .intr_polarity_bit = 1, \ 51 .intr_detection_bit = 2, \ 52 .intr_detection_width = 2, \ 53 } 54 55 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 56 { \ 57 .grp = PINCTRL_PINGROUP(#pg_name, \ 58 pg_name##_pins, \ 59 ARRAY_SIZE(pg_name##_pins)), \ 60 .ctl_reg = ctl, \ 61 .io_reg = 0, \ 62 .intr_cfg_reg = 0, \ 63 .intr_status_reg = 0, \ 64 .mux_bit = -1, \ 65 .pull_bit = pull, \ 66 .drv_bit = drv, \ 67 .oe_bit = -1, \ 68 .in_bit = -1, \ 69 .out_bit = -1, \ 70 .intr_enable_bit = -1, \ 71 .intr_status_bit = -1, \ 72 .intr_target_bit = -1, \ 73 .intr_raw_status_bit = -1, \ 74 .intr_polarity_bit = -1, \ 75 .intr_detection_bit = -1, \ 76 .intr_detection_width = -1, \ 77 } 78 79 #define UFS_RESET(pg_name, offset) \ 80 { \ 81 .grp = PINCTRL_PINGROUP(#pg_name, \ 82 pg_name##_pins, \ 83 ARRAY_SIZE(pg_name##_pins)), \ 84 .ctl_reg = offset, \ 85 .io_reg = offset + 0x4, \ 86 .intr_cfg_reg = 0, \ 87 .intr_status_reg = 0, \ 88 .mux_bit = -1, \ 89 .pull_bit = 3, \ 90 .drv_bit = 0, \ 91 .oe_bit = -1, \ 92 .in_bit = -1, \ 93 .out_bit = 0, \ 94 .intr_enable_bit = -1, \ 95 .intr_status_bit = -1, \ 96 .intr_target_bit = -1, \ 97 .intr_raw_status_bit = -1, \ 98 .intr_polarity_bit = -1, \ 99 .intr_detection_bit = -1, \ 100 .intr_detection_width = -1, \ 101 } 102 103 #define QUP_I3C_6_MODE_OFFSET 0xaf000 104 #define QUP_I3C_7_MODE_OFFSET 0xb0000 105 #define QUP_I3C_13_MODE_OFFSET 0xb1000 106 #define QUP_I3C_14_MODE_OFFSET 0xb2000 107 108 static const struct pinctrl_pin_desc qcs8300_pins[] = { 109 PINCTRL_PIN(0, "GPIO_0"), 110 PINCTRL_PIN(1, "GPIO_1"), 111 PINCTRL_PIN(2, "GPIO_2"), 112 PINCTRL_PIN(3, "GPIO_3"), 113 PINCTRL_PIN(4, "GPIO_4"), 114 PINCTRL_PIN(5, "GPIO_5"), 115 PINCTRL_PIN(6, "GPIO_6"), 116 PINCTRL_PIN(7, "GPIO_7"), 117 PINCTRL_PIN(8, "GPIO_8"), 118 PINCTRL_PIN(9, "GPIO_9"), 119 PINCTRL_PIN(10, "GPIO_10"), 120 PINCTRL_PIN(11, "GPIO_11"), 121 PINCTRL_PIN(12, "GPIO_12"), 122 PINCTRL_PIN(13, "GPIO_13"), 123 PINCTRL_PIN(14, "GPIO_14"), 124 PINCTRL_PIN(15, "GPIO_15"), 125 PINCTRL_PIN(16, "GPIO_16"), 126 PINCTRL_PIN(17, "GPIO_17"), 127 PINCTRL_PIN(18, "GPIO_18"), 128 PINCTRL_PIN(19, "GPIO_19"), 129 PINCTRL_PIN(20, "GPIO_20"), 130 PINCTRL_PIN(21, "GPIO_21"), 131 PINCTRL_PIN(22, "GPIO_22"), 132 PINCTRL_PIN(23, "GPIO_23"), 133 PINCTRL_PIN(24, "GPIO_24"), 134 PINCTRL_PIN(25, "GPIO_25"), 135 PINCTRL_PIN(26, "GPIO_26"), 136 PINCTRL_PIN(27, "GPIO_27"), 137 PINCTRL_PIN(28, "GPIO_28"), 138 PINCTRL_PIN(29, "GPIO_29"), 139 PINCTRL_PIN(30, "GPIO_30"), 140 PINCTRL_PIN(31, "GPIO_31"), 141 PINCTRL_PIN(32, "GPIO_32"), 142 PINCTRL_PIN(33, "GPIO_33"), 143 PINCTRL_PIN(34, "GPIO_34"), 144 PINCTRL_PIN(35, "GPIO_35"), 145 PINCTRL_PIN(36, "GPIO_36"), 146 PINCTRL_PIN(37, "GPIO_37"), 147 PINCTRL_PIN(38, "GPIO_38"), 148 PINCTRL_PIN(39, "GPIO_39"), 149 PINCTRL_PIN(40, "GPIO_40"), 150 PINCTRL_PIN(41, "GPIO_41"), 151 PINCTRL_PIN(42, "GPIO_42"), 152 PINCTRL_PIN(43, "GPIO_43"), 153 PINCTRL_PIN(44, "GPIO_44"), 154 PINCTRL_PIN(45, "GPIO_45"), 155 PINCTRL_PIN(46, "GPIO_46"), 156 PINCTRL_PIN(47, "GPIO_47"), 157 PINCTRL_PIN(48, "GPIO_48"), 158 PINCTRL_PIN(49, "GPIO_49"), 159 PINCTRL_PIN(50, "GPIO_50"), 160 PINCTRL_PIN(51, "GPIO_51"), 161 PINCTRL_PIN(52, "GPIO_52"), 162 PINCTRL_PIN(53, "GPIO_53"), 163 PINCTRL_PIN(54, "GPIO_54"), 164 PINCTRL_PIN(55, "GPIO_55"), 165 PINCTRL_PIN(56, "GPIO_56"), 166 PINCTRL_PIN(57, "GPIO_57"), 167 PINCTRL_PIN(58, "GPIO_58"), 168 PINCTRL_PIN(59, "GPIO_59"), 169 PINCTRL_PIN(60, "GPIO_60"), 170 PINCTRL_PIN(61, "GPIO_61"), 171 PINCTRL_PIN(62, "GPIO_62"), 172 PINCTRL_PIN(63, "GPIO_63"), 173 PINCTRL_PIN(64, "GPIO_64"), 174 PINCTRL_PIN(65, "GPIO_65"), 175 PINCTRL_PIN(66, "GPIO_66"), 176 PINCTRL_PIN(67, "GPIO_67"), 177 PINCTRL_PIN(68, "GPIO_68"), 178 PINCTRL_PIN(69, "GPIO_69"), 179 PINCTRL_PIN(70, "GPIO_70"), 180 PINCTRL_PIN(71, "GPIO_71"), 181 PINCTRL_PIN(72, "GPIO_72"), 182 PINCTRL_PIN(73, "GPIO_73"), 183 PINCTRL_PIN(74, "GPIO_74"), 184 PINCTRL_PIN(75, "GPIO_75"), 185 PINCTRL_PIN(76, "GPIO_76"), 186 PINCTRL_PIN(77, "GPIO_77"), 187 PINCTRL_PIN(78, "GPIO_78"), 188 PINCTRL_PIN(79, "GPIO_79"), 189 PINCTRL_PIN(80, "GPIO_80"), 190 PINCTRL_PIN(81, "GPIO_81"), 191 PINCTRL_PIN(82, "GPIO_82"), 192 PINCTRL_PIN(83, "GPIO_83"), 193 PINCTRL_PIN(84, "GPIO_84"), 194 PINCTRL_PIN(85, "GPIO_85"), 195 PINCTRL_PIN(86, "GPIO_86"), 196 PINCTRL_PIN(87, "GPIO_87"), 197 PINCTRL_PIN(88, "GPIO_88"), 198 PINCTRL_PIN(89, "GPIO_89"), 199 PINCTRL_PIN(90, "GPIO_90"), 200 PINCTRL_PIN(91, "GPIO_91"), 201 PINCTRL_PIN(92, "GPIO_92"), 202 PINCTRL_PIN(93, "GPIO_93"), 203 PINCTRL_PIN(94, "GPIO_94"), 204 PINCTRL_PIN(95, "GPIO_95"), 205 PINCTRL_PIN(96, "GPIO_96"), 206 PINCTRL_PIN(97, "GPIO_97"), 207 PINCTRL_PIN(98, "GPIO_98"), 208 PINCTRL_PIN(99, "GPIO_99"), 209 PINCTRL_PIN(100, "GPIO_100"), 210 PINCTRL_PIN(101, "GPIO_101"), 211 PINCTRL_PIN(102, "GPIO_102"), 212 PINCTRL_PIN(103, "GPIO_103"), 213 PINCTRL_PIN(104, "GPIO_104"), 214 PINCTRL_PIN(105, "GPIO_105"), 215 PINCTRL_PIN(106, "GPIO_106"), 216 PINCTRL_PIN(107, "GPIO_107"), 217 PINCTRL_PIN(108, "GPIO_108"), 218 PINCTRL_PIN(109, "GPIO_109"), 219 PINCTRL_PIN(110, "GPIO_110"), 220 PINCTRL_PIN(111, "GPIO_111"), 221 PINCTRL_PIN(112, "GPIO_112"), 222 PINCTRL_PIN(113, "GPIO_113"), 223 PINCTRL_PIN(114, "GPIO_114"), 224 PINCTRL_PIN(115, "GPIO_115"), 225 PINCTRL_PIN(116, "GPIO_116"), 226 PINCTRL_PIN(117, "GPIO_117"), 227 PINCTRL_PIN(118, "GPIO_118"), 228 PINCTRL_PIN(119, "GPIO_119"), 229 PINCTRL_PIN(120, "GPIO_120"), 230 PINCTRL_PIN(121, "GPIO_121"), 231 PINCTRL_PIN(122, "GPIO_122"), 232 PINCTRL_PIN(123, "GPIO_123"), 233 PINCTRL_PIN(124, "GPIO_124"), 234 PINCTRL_PIN(125, "GPIO_125"), 235 PINCTRL_PIN(126, "GPIO_126"), 236 PINCTRL_PIN(127, "GPIO_127"), 237 PINCTRL_PIN(128, "GPIO_128"), 238 PINCTRL_PIN(129, "GPIO_129"), 239 PINCTRL_PIN(130, "GPIO_130"), 240 PINCTRL_PIN(131, "GPIO_131"), 241 PINCTRL_PIN(132, "GPIO_132"), 242 PINCTRL_PIN(133, "UFS_RESET"), 243 PINCTRL_PIN(134, "SDC1_RCLK"), 244 PINCTRL_PIN(135, "SDC1_CLK"), 245 PINCTRL_PIN(136, "SDC1_CMD"), 246 PINCTRL_PIN(137, "SDC1_DATA"), 247 }; 248 249 #define DECLARE_MSM_GPIO_PINS(pin) \ 250 static const unsigned int gpio##pin##_pins[] = { pin } 251 DECLARE_MSM_GPIO_PINS(0); 252 DECLARE_MSM_GPIO_PINS(1); 253 DECLARE_MSM_GPIO_PINS(2); 254 DECLARE_MSM_GPIO_PINS(3); 255 DECLARE_MSM_GPIO_PINS(4); 256 DECLARE_MSM_GPIO_PINS(5); 257 DECLARE_MSM_GPIO_PINS(6); 258 DECLARE_MSM_GPIO_PINS(7); 259 DECLARE_MSM_GPIO_PINS(8); 260 DECLARE_MSM_GPIO_PINS(9); 261 DECLARE_MSM_GPIO_PINS(10); 262 DECLARE_MSM_GPIO_PINS(11); 263 DECLARE_MSM_GPIO_PINS(12); 264 DECLARE_MSM_GPIO_PINS(13); 265 DECLARE_MSM_GPIO_PINS(14); 266 DECLARE_MSM_GPIO_PINS(15); 267 DECLARE_MSM_GPIO_PINS(16); 268 DECLARE_MSM_GPIO_PINS(17); 269 DECLARE_MSM_GPIO_PINS(18); 270 DECLARE_MSM_GPIO_PINS(19); 271 DECLARE_MSM_GPIO_PINS(20); 272 DECLARE_MSM_GPIO_PINS(21); 273 DECLARE_MSM_GPIO_PINS(22); 274 DECLARE_MSM_GPIO_PINS(23); 275 DECLARE_MSM_GPIO_PINS(24); 276 DECLARE_MSM_GPIO_PINS(25); 277 DECLARE_MSM_GPIO_PINS(26); 278 DECLARE_MSM_GPIO_PINS(27); 279 DECLARE_MSM_GPIO_PINS(28); 280 DECLARE_MSM_GPIO_PINS(29); 281 DECLARE_MSM_GPIO_PINS(30); 282 DECLARE_MSM_GPIO_PINS(31); 283 DECLARE_MSM_GPIO_PINS(32); 284 DECLARE_MSM_GPIO_PINS(33); 285 DECLARE_MSM_GPIO_PINS(34); 286 DECLARE_MSM_GPIO_PINS(35); 287 DECLARE_MSM_GPIO_PINS(36); 288 DECLARE_MSM_GPIO_PINS(37); 289 DECLARE_MSM_GPIO_PINS(38); 290 DECLARE_MSM_GPIO_PINS(39); 291 DECLARE_MSM_GPIO_PINS(40); 292 DECLARE_MSM_GPIO_PINS(41); 293 DECLARE_MSM_GPIO_PINS(42); 294 DECLARE_MSM_GPIO_PINS(43); 295 DECLARE_MSM_GPIO_PINS(44); 296 DECLARE_MSM_GPIO_PINS(45); 297 DECLARE_MSM_GPIO_PINS(46); 298 DECLARE_MSM_GPIO_PINS(47); 299 DECLARE_MSM_GPIO_PINS(48); 300 DECLARE_MSM_GPIO_PINS(49); 301 DECLARE_MSM_GPIO_PINS(50); 302 DECLARE_MSM_GPIO_PINS(51); 303 DECLARE_MSM_GPIO_PINS(52); 304 DECLARE_MSM_GPIO_PINS(53); 305 DECLARE_MSM_GPIO_PINS(54); 306 DECLARE_MSM_GPIO_PINS(55); 307 DECLARE_MSM_GPIO_PINS(56); 308 DECLARE_MSM_GPIO_PINS(57); 309 DECLARE_MSM_GPIO_PINS(58); 310 DECLARE_MSM_GPIO_PINS(59); 311 DECLARE_MSM_GPIO_PINS(60); 312 DECLARE_MSM_GPIO_PINS(61); 313 DECLARE_MSM_GPIO_PINS(62); 314 DECLARE_MSM_GPIO_PINS(63); 315 DECLARE_MSM_GPIO_PINS(64); 316 DECLARE_MSM_GPIO_PINS(65); 317 DECLARE_MSM_GPIO_PINS(66); 318 DECLARE_MSM_GPIO_PINS(67); 319 DECLARE_MSM_GPIO_PINS(68); 320 DECLARE_MSM_GPIO_PINS(69); 321 DECLARE_MSM_GPIO_PINS(70); 322 DECLARE_MSM_GPIO_PINS(71); 323 DECLARE_MSM_GPIO_PINS(72); 324 DECLARE_MSM_GPIO_PINS(73); 325 DECLARE_MSM_GPIO_PINS(74); 326 DECLARE_MSM_GPIO_PINS(75); 327 DECLARE_MSM_GPIO_PINS(76); 328 DECLARE_MSM_GPIO_PINS(77); 329 DECLARE_MSM_GPIO_PINS(78); 330 DECLARE_MSM_GPIO_PINS(79); 331 DECLARE_MSM_GPIO_PINS(80); 332 DECLARE_MSM_GPIO_PINS(81); 333 DECLARE_MSM_GPIO_PINS(82); 334 DECLARE_MSM_GPIO_PINS(83); 335 DECLARE_MSM_GPIO_PINS(84); 336 DECLARE_MSM_GPIO_PINS(85); 337 DECLARE_MSM_GPIO_PINS(86); 338 DECLARE_MSM_GPIO_PINS(87); 339 DECLARE_MSM_GPIO_PINS(88); 340 DECLARE_MSM_GPIO_PINS(89); 341 DECLARE_MSM_GPIO_PINS(90); 342 DECLARE_MSM_GPIO_PINS(91); 343 DECLARE_MSM_GPIO_PINS(92); 344 DECLARE_MSM_GPIO_PINS(93); 345 DECLARE_MSM_GPIO_PINS(94); 346 DECLARE_MSM_GPIO_PINS(95); 347 DECLARE_MSM_GPIO_PINS(96); 348 DECLARE_MSM_GPIO_PINS(97); 349 DECLARE_MSM_GPIO_PINS(98); 350 DECLARE_MSM_GPIO_PINS(99); 351 DECLARE_MSM_GPIO_PINS(100); 352 DECLARE_MSM_GPIO_PINS(101); 353 DECLARE_MSM_GPIO_PINS(102); 354 DECLARE_MSM_GPIO_PINS(103); 355 DECLARE_MSM_GPIO_PINS(104); 356 DECLARE_MSM_GPIO_PINS(105); 357 DECLARE_MSM_GPIO_PINS(106); 358 DECLARE_MSM_GPIO_PINS(107); 359 DECLARE_MSM_GPIO_PINS(108); 360 DECLARE_MSM_GPIO_PINS(109); 361 DECLARE_MSM_GPIO_PINS(110); 362 DECLARE_MSM_GPIO_PINS(111); 363 DECLARE_MSM_GPIO_PINS(112); 364 DECLARE_MSM_GPIO_PINS(113); 365 DECLARE_MSM_GPIO_PINS(114); 366 DECLARE_MSM_GPIO_PINS(115); 367 DECLARE_MSM_GPIO_PINS(116); 368 DECLARE_MSM_GPIO_PINS(117); 369 DECLARE_MSM_GPIO_PINS(118); 370 DECLARE_MSM_GPIO_PINS(119); 371 DECLARE_MSM_GPIO_PINS(120); 372 DECLARE_MSM_GPIO_PINS(121); 373 DECLARE_MSM_GPIO_PINS(122); 374 DECLARE_MSM_GPIO_PINS(123); 375 DECLARE_MSM_GPIO_PINS(124); 376 DECLARE_MSM_GPIO_PINS(125); 377 DECLARE_MSM_GPIO_PINS(126); 378 DECLARE_MSM_GPIO_PINS(127); 379 DECLARE_MSM_GPIO_PINS(128); 380 DECLARE_MSM_GPIO_PINS(129); 381 DECLARE_MSM_GPIO_PINS(130); 382 DECLARE_MSM_GPIO_PINS(131); 383 DECLARE_MSM_GPIO_PINS(132); 384 385 static const unsigned int ufs_reset_pins[] = { 133 }; 386 static const unsigned int sdc1_rclk_pins[] = { 134 }; 387 static const unsigned int sdc1_clk_pins[] = { 135 }; 388 static const unsigned int sdc1_cmd_pins[] = { 136 }; 389 static const unsigned int sdc1_data_pins[] = { 137 }; 390 391 enum qcs8300_functions { 392 msm_mux_gpio, 393 msm_mux_aoss_cti, 394 msm_mux_atest_char, 395 msm_mux_atest_usb2, 396 msm_mux_audio_ref, 397 msm_mux_cam_mclk, 398 msm_mux_cci_async, 399 msm_mux_cci_i2c_scl, 400 msm_mux_cci_i2c_sda, 401 msm_mux_cci_timer, 402 msm_mux_cri_trng, 403 msm_mux_dbg_out, 404 msm_mux_ddr_bist, 405 msm_mux_ddr_pxi0, 406 msm_mux_ddr_pxi1, 407 msm_mux_ddr_pxi2, 408 msm_mux_ddr_pxi3, 409 msm_mux_edp0_hot, 410 msm_mux_edp0_lcd, 411 msm_mux_edp1_lcd, 412 msm_mux_egpio, 413 msm_mux_emac0_mcg0, 414 msm_mux_emac0_mcg1, 415 msm_mux_emac0_mcg2, 416 msm_mux_emac0_mcg3, 417 msm_mux_emac0_mdc, 418 msm_mux_emac0_mdio, 419 msm_mux_emac0_ptp_aux, 420 msm_mux_emac0_ptp_pps, 421 msm_mux_gcc_gp1, 422 msm_mux_gcc_gp2, 423 msm_mux_gcc_gp3, 424 msm_mux_gcc_gp4, 425 msm_mux_gcc_gp5, 426 msm_mux_hs0_mi2s, 427 msm_mux_hs1_mi2s, 428 msm_mux_hs2_mi2s, 429 msm_mux_ibi_i3c, 430 msm_mux_jitter_bist, 431 msm_mux_mdp0_vsync0, 432 msm_mux_mdp0_vsync1, 433 msm_mux_mdp0_vsync3, 434 msm_mux_mdp0_vsync6, 435 msm_mux_mdp0_vsync7, 436 msm_mux_mdp_vsync, 437 msm_mux_mi2s1_data0, 438 msm_mux_mi2s1_data1, 439 msm_mux_mi2s1_sck, 440 msm_mux_mi2s1_ws, 441 msm_mux_mi2s2_data0, 442 msm_mux_mi2s2_data1, 443 msm_mux_mi2s2_sck, 444 msm_mux_mi2s2_ws, 445 msm_mux_mi2s_mclk0, 446 msm_mux_mi2s_mclk1, 447 msm_mux_pcie0_clkreq, 448 msm_mux_pcie1_clkreq, 449 msm_mux_phase_flag, 450 msm_mux_pll_bist, 451 msm_mux_pll_clk, 452 msm_mux_prng_rosc0, 453 msm_mux_prng_rosc1, 454 msm_mux_prng_rosc2, 455 msm_mux_prng_rosc3, 456 msm_mux_qdss_cti, 457 msm_mux_qdss_gpio, 458 msm_mux_qup0_se0, 459 msm_mux_qup0_se1, 460 msm_mux_qup0_se2, 461 msm_mux_qup0_se3, 462 msm_mux_qup0_se4, 463 msm_mux_qup0_se5, 464 msm_mux_qup0_se6, 465 msm_mux_qup0_se7, 466 msm_mux_qup1_se0, 467 msm_mux_qup1_se1, 468 msm_mux_qup1_se2, 469 msm_mux_qup1_se3, 470 msm_mux_qup1_se4, 471 msm_mux_qup1_se5, 472 msm_mux_qup1_se6, 473 msm_mux_qup1_se7, 474 msm_mux_qup2_se0, 475 msm_mux_sailss_emac0, 476 msm_mux_sailss_ospi, 477 msm_mux_sgmii_phy, 478 msm_mux_tb_trig, 479 msm_mux_tgu_ch0, 480 msm_mux_tgu_ch1, 481 msm_mux_tgu_ch2, 482 msm_mux_tgu_ch3, 483 msm_mux_tsense_pwm1, 484 msm_mux_tsense_pwm2, 485 msm_mux_tsense_pwm3, 486 msm_mux_tsense_pwm4, 487 msm_mux_usb2phy_ac, 488 msm_mux_vsense_trigger, 489 msm_mux__, 490 }; 491 492 static const char * const gpio_groups[] = { 493 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 494 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 495 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 496 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 497 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 498 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 499 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 500 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 501 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 502 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 503 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 504 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 505 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 506 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 507 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 508 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 509 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 510 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", 511 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", 512 "gpio129", "gpio130", "gpio131", "gpio132", 513 }; 514 515 static const char *const aoss_cti_groups[] = { 516 "gpio37", "gpio38", "gpio39", "gpio40", 517 }; 518 519 static const char * const atest_char_groups[] = { 520 "gpio66", "gpio70", "gpio71", "gpio72", "gpio93", 521 }; 522 523 static const char * const atest_usb2_groups[] = { 524 "gpio63", "gpio83", "gpio92", "gpio74", "gpio84", "gpio87", "gpio67", 525 "gpio75", "gpio85", "gpio65", "gpio68", "gpio80", "gpio64", "gpio69", 526 "gpio81", 527 }; 528 529 static const char * const audio_ref_groups[] = { 530 "gpio105", 531 }; 532 533 static const char * const cam_mclk_groups[] = { 534 "gpio67", "gpio68", "gpio69", 535 }; 536 537 static const char * const cci_async_groups[] = { 538 "gpio63", "gpio64", "gpio65", "gpio29", "gpio30", "gpio31", 539 }; 540 541 static const char * const cci_i2c_scl_groups[] = { 542 "gpio58", "gpio30", "gpio60", "gpio32", "gpio62", "gpio55", 543 }; 544 545 static const char * const cci_i2c_sda_groups[] = { 546 "gpio57", "gpio29", "gpio59", "gpio31", "gpio61", "gpio54", 547 }; 548 549 static const char *const cci_timer_groups[] = { 550 "gpio63", "gpio64", "gpio65", "gpio49", "gpio50", "gpio19", 551 "gpio20", "gpio21", "gpio22", "gpio23", 552 }; 553 554 static const char *const cri_trng_groups[] = { 555 "gpio92", "gpio90", "gpio91", 556 }; 557 558 static const char *const dbg_out_groups[] = { 559 "gpio75", 560 }; 561 562 static const char * const ddr_bist_groups[] = { 563 "gpio53", "gpio54", "gpio55", "gpio56", 564 }; 565 566 static const char *const ddr_pxi0_groups[] = { 567 "gpio68", "gpio69", 568 }; 569 570 static const char *const ddr_pxi1_groups[] = { 571 "gpio49", "gpio50", 572 }; 573 574 static const char *const ddr_pxi2_groups[] = { 575 "gpio52", "gpio83", 576 }; 577 578 static const char *const ddr_pxi3_groups[] = { 579 "gpio80", "gpio81", 580 }; 581 582 static const char *const edp0_hot_groups[] = { 583 "gpio94", 584 }; 585 586 static const char *const edp0_lcd_groups[] = { 587 "gpio48", 588 }; 589 590 static const char *const edp1_lcd_groups[] = { 591 "gpio49", 592 }; 593 594 static const char *const egpio_groups[] = { 595 "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", 596 "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", 597 "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", 598 "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", 599 }; 600 601 static const char *const emac0_mcg0_groups[] = { 602 "gpio10", 603 }; 604 605 static const char *const emac0_mcg1_groups[] = { 606 "gpio11", 607 }; 608 609 static const char *const emac0_mcg2_groups[] = { 610 "gpio24", 611 }; 612 613 static const char *const emac0_mcg3_groups[] = { 614 "gpio79", 615 }; 616 617 static const char *const emac0_mdc_groups[] = { 618 "gpio5", 619 }; 620 621 static const char *const emac0_mdio_groups[] = { 622 "gpio6", 623 }; 624 625 static const char * const emac0_ptp_aux_groups[] = { 626 "gpio24", "gpio31", "gpio32", "gpio79", 627 }; 628 629 static const char * const emac0_ptp_pps_groups[] = { 630 "gpio24", "gpio29", "gpio30", "gpio79", 631 }; 632 633 static const char *const gcc_gp1_groups[] = { 634 "gpio35", "gpio84", 635 }; 636 637 static const char *const gcc_gp2_groups[] = { 638 "gpio36", "gpio81", 639 }; 640 641 static const char *const gcc_gp3_groups[] = { 642 "gpio69", "gpio82", 643 }; 644 645 static const char *const gcc_gp4_groups[] = { 646 "gpio68", "gpio83", 647 }; 648 649 static const char *const gcc_gp5_groups[] = { 650 "gpio76", "gpio77", 651 }; 652 653 static const char * const hs0_mi2s_groups[] = { 654 "gpio106", "gpio107", "gpio108", "gpio109", 655 }; 656 657 static const char * const hs1_mi2s_groups[] = { 658 "gpio45", "gpio46", "gpio47", "gpio48", 659 }; 660 661 static const char * const hs2_mi2s_groups[] = { 662 "gpio49", "gpio50", "gpio51", "gpio52", 663 }; 664 665 static const char * const ibi_i3c_groups[] = { 666 "gpio17", "gpio18", "gpio19", "gpio20", "gpio37", "gpio38", 667 "gpio39", "gpio40", 668 }; 669 670 static const char *const jitter_bist_groups[] = { 671 "gpio97", 672 }; 673 674 static const char *const mdp0_vsync0_groups[] = { 675 "gpio89", 676 }; 677 678 static const char *const mdp0_vsync1_groups[] = { 679 "gpio90", 680 }; 681 682 static const char *const mdp0_vsync3_groups[] = { 683 "gpio91", 684 }; 685 686 static const char *const mdp0_vsync6_groups[] = { 687 "gpio80", 688 }; 689 690 static const char *const mdp0_vsync7_groups[] = { 691 "gpio81", 692 }; 693 694 static const char *const mdp_vsync_groups[] = { 695 "gpio42", "gpio52", "gpio32", 696 }; 697 698 static const char *const mi2s1_data0_groups[] = { 699 "gpio100", 700 }; 701 702 static const char *const mi2s1_data1_groups[] = { 703 "gpio101", 704 }; 705 706 static const char *const mi2s1_sck_groups[] = { 707 "gpio98", 708 }; 709 710 static const char *const mi2s1_ws_groups[] = { 711 "gpio99", 712 }; 713 714 static const char *const mi2s2_data0_groups[] = { 715 "gpio104", 716 }; 717 718 static const char *const mi2s2_data1_groups[] = { 719 "gpio105", 720 }; 721 722 static const char *const mi2s2_sck_groups[] = { 723 "gpio102", 724 }; 725 726 static const char *const mi2s2_ws_groups[] = { 727 "gpio103", 728 }; 729 730 static const char *const mi2s_mclk0_groups[] = { 731 "gpio97", 732 }; 733 734 static const char *const mi2s_mclk1_groups[] = { 735 "gpio109", 736 }; 737 738 static const char *const pcie0_clkreq_groups[] = { 739 "gpio1", 740 }; 741 742 static const char *const pcie1_clkreq_groups[] = { 743 "gpio22", 744 }; 745 746 static const char *const phase_flag_groups[] = { 747 "gpio66", "gpio56", "gpio118", "gpio117", "gpio116", 748 "gpio3", "gpio114", "gpio113", "gpio112", "gpio111", 749 "gpio110", "gpio28", "gpio55", "gpio108", "gpio107", 750 "gpio106", "gpio105", "gpio104", "gpio103", "gpio102", 751 "gpio101", "gpio100", "gpio99", "gpio125", "gpio98", 752 "gpio54", "gpio25", "gpio26", "gpio122", "gpio121", 753 "gpio120", "gpio9", 754 }; 755 756 static const char *const pll_bist_groups[] = { 757 "gpio107", 758 }; 759 760 static const char *const pll_clk_groups[] = { 761 "gpio74", 762 }; 763 764 static const char *const prng_rosc0_groups[] = { 765 "gpio57", 766 }; 767 768 static const char *const prng_rosc1_groups[] = { 769 "gpio58", 770 }; 771 772 static const char *const prng_rosc2_groups[] = { 773 "gpio59", 774 }; 775 776 static const char *const prng_rosc3_groups[] = { 777 "gpio60", 778 }; 779 780 static const char *const qdss_cti_groups[] = { 781 "gpio4", "gpio5", "gpio23", "gpio24", "gpio49", "gpio50", 782 "gpio51", "gpio52", 783 }; 784 785 static const char *const qdss_gpio_groups[] = { 786 "gpio57", "gpio58", "gpio97", "gpio106", 787 "gpio59", "gpio107", "gpio60", "gpio108", 788 "gpio36", "gpio100", "gpio61", "gpio101", 789 "gpio62", "gpio102", "gpio33", "gpio103", 790 "gpio34", "gpio104", "gpio75", "gpio105", 791 "gpio72", "gpio109", "gpio71", "gpio110", 792 "gpio70", "gpio111", "gpio63", "gpio112", 793 "gpio64", "gpio113", "gpio65", "gpio114", 794 "gpio73", "gpio98", "gpio74", "gpio99", 795 }; 796 797 static const char *const qup0_se0_groups[] = { 798 "gpio17", "gpio18", "gpio19", "gpio20", 799 }; 800 801 static const char *const qup0_se1_groups[] = { 802 "gpio19", "gpio20", "gpio17", "gpio18", 803 }; 804 805 static const char *const qup0_se2_groups[] = { 806 "gpio33", "gpio34", "gpio35", "gpio36", 807 }; 808 809 static const char *const qup0_se3_groups[] = { 810 "gpio25", "gpio26", "gpio27", "gpio28", 811 }; 812 813 static const char *const qup0_se4_groups[] = { 814 "gpio29", "gpio30", "gpio31", "gpio32", 815 }; 816 817 static const char *const qup0_se5_groups[] = { 818 "gpio21", "gpio22", "gpio23", "gpio24", 819 }; 820 821 static const char *const qup0_se6_groups[] = { 822 "gpio80", "gpio81", "gpio82", "gpio83", 823 }; 824 825 static const char *const qup0_se7_groups[] = { 826 "gpio43", "gpio44", "gpio43", "gpio44", 827 }; 828 829 static const char *const qup1_se0_groups[] = { 830 "gpio37", "gpio38", "gpio39", "gpio40", 831 }; 832 833 static const char *const qup1_se1_groups[] = { 834 "gpio39", "gpio40", "gpio37", "gpio38", 835 }; 836 837 static const char *const qup1_se2_groups[] = { 838 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", 839 }; 840 841 static const char *const qup1_se3_groups[] = { 842 "gpio41", "gpio42", "gpio41", "gpio42", 843 }; 844 845 static const char *const qup1_se4_groups[] = { 846 "gpio45", "gpio46", "gpio47", "gpio48", 847 }; 848 849 static const char *const qup1_se5_groups[] = { 850 "gpio49", "gpio50", "gpio51", "gpio52", 851 }; 852 853 static const char *const qup1_se6_groups[] = { 854 "gpio89", "gpio90", "gpio91", "gpio92", 855 }; 856 857 static const char *const qup1_se7_groups[] = { 858 "gpio91", "gpio92", "gpio89", "gpio90", 859 }; 860 861 static const char *const qup2_se0_groups[] = { 862 "gpio10", "gpio11", "gpio12", "gpio13", 863 "gpio14", "gpio15", "gpio16", 864 }; 865 866 static const char *const sailss_emac0_groups[] = { 867 "gpio15", "gpio16", 868 }; 869 870 static const char *const sailss_ospi_groups[] = { 871 "gpio15", "gpio16", 872 }; 873 874 static const char *const sgmii_phy_groups[] = { 875 "gpio4", 876 }; 877 878 static const char *const tb_trig_groups[] = { 879 "gpio14", 880 }; 881 882 static const char *const tgu_ch0_groups[] = { 883 "gpio43", 884 }; 885 886 static const char *const tgu_ch1_groups[] = { 887 "gpio44", 888 }; 889 890 static const char *const tgu_ch2_groups[] = { 891 "gpio29", 892 }; 893 894 static const char *const tgu_ch3_groups[] = { 895 "gpio30", 896 }; 897 898 static const char *const tsense_pwm1_groups[] = { 899 "gpio79", 900 }; 901 902 static const char *const tsense_pwm2_groups[] = { 903 "gpio78", 904 }; 905 906 static const char *const tsense_pwm3_groups[] = { 907 "gpio77", 908 }; 909 910 static const char *const tsense_pwm4_groups[] = { 911 "gpio76", 912 }; 913 914 static const char *const usb2phy_ac_groups[] = { 915 "gpio7", "gpio8", 916 }; 917 918 static const char *const vsense_trigger_groups[] = { 919 "gpio67", 920 }; 921 922 static const struct pinfunction qcs8300_functions[] = { 923 MSM_GPIO_PIN_FUNCTION(gpio), 924 MSM_PIN_FUNCTION(aoss_cti), 925 MSM_PIN_FUNCTION(atest_char), 926 MSM_PIN_FUNCTION(atest_usb2), 927 MSM_PIN_FUNCTION(audio_ref), 928 MSM_PIN_FUNCTION(cam_mclk), 929 MSM_PIN_FUNCTION(cci_async), 930 MSM_PIN_FUNCTION(cci_i2c_scl), 931 MSM_PIN_FUNCTION(cci_i2c_sda), 932 MSM_PIN_FUNCTION(cci_timer), 933 MSM_PIN_FUNCTION(cri_trng), 934 MSM_PIN_FUNCTION(dbg_out), 935 MSM_PIN_FUNCTION(ddr_bist), 936 MSM_PIN_FUNCTION(ddr_pxi0), 937 MSM_PIN_FUNCTION(ddr_pxi1), 938 MSM_PIN_FUNCTION(ddr_pxi2), 939 MSM_PIN_FUNCTION(ddr_pxi3), 940 MSM_PIN_FUNCTION(edp0_hot), 941 MSM_PIN_FUNCTION(edp0_lcd), 942 MSM_PIN_FUNCTION(edp1_lcd), 943 MSM_GPIO_PIN_FUNCTION(egpio), 944 MSM_PIN_FUNCTION(emac0_mcg0), 945 MSM_PIN_FUNCTION(emac0_mcg1), 946 MSM_PIN_FUNCTION(emac0_mcg2), 947 MSM_PIN_FUNCTION(emac0_mcg3), 948 MSM_PIN_FUNCTION(emac0_mdc), 949 MSM_PIN_FUNCTION(emac0_mdio), 950 MSM_PIN_FUNCTION(emac0_ptp_aux), 951 MSM_PIN_FUNCTION(emac0_ptp_pps), 952 MSM_PIN_FUNCTION(gcc_gp1), 953 MSM_PIN_FUNCTION(gcc_gp2), 954 MSM_PIN_FUNCTION(gcc_gp3), 955 MSM_PIN_FUNCTION(gcc_gp4), 956 MSM_PIN_FUNCTION(gcc_gp5), 957 MSM_PIN_FUNCTION(hs0_mi2s), 958 MSM_PIN_FUNCTION(hs1_mi2s), 959 MSM_PIN_FUNCTION(hs2_mi2s), 960 MSM_PIN_FUNCTION(ibi_i3c), 961 MSM_PIN_FUNCTION(jitter_bist), 962 MSM_PIN_FUNCTION(mdp0_vsync0), 963 MSM_PIN_FUNCTION(mdp0_vsync1), 964 MSM_PIN_FUNCTION(mdp0_vsync3), 965 MSM_PIN_FUNCTION(mdp0_vsync6), 966 MSM_PIN_FUNCTION(mdp0_vsync7), 967 MSM_PIN_FUNCTION(mdp_vsync), 968 MSM_PIN_FUNCTION(mi2s1_data0), 969 MSM_PIN_FUNCTION(mi2s1_data1), 970 MSM_PIN_FUNCTION(mi2s1_sck), 971 MSM_PIN_FUNCTION(mi2s1_ws), 972 MSM_PIN_FUNCTION(mi2s2_data0), 973 MSM_PIN_FUNCTION(mi2s2_data1), 974 MSM_PIN_FUNCTION(mi2s2_sck), 975 MSM_PIN_FUNCTION(mi2s2_ws), 976 MSM_PIN_FUNCTION(mi2s_mclk0), 977 MSM_PIN_FUNCTION(mi2s_mclk1), 978 MSM_PIN_FUNCTION(pcie0_clkreq), 979 MSM_PIN_FUNCTION(pcie1_clkreq), 980 MSM_PIN_FUNCTION(phase_flag), 981 MSM_PIN_FUNCTION(pll_bist), 982 MSM_PIN_FUNCTION(pll_clk), 983 MSM_PIN_FUNCTION(prng_rosc0), 984 MSM_PIN_FUNCTION(prng_rosc1), 985 MSM_PIN_FUNCTION(prng_rosc2), 986 MSM_PIN_FUNCTION(prng_rosc3), 987 MSM_PIN_FUNCTION(qdss_cti), 988 MSM_PIN_FUNCTION(qdss_gpio), 989 MSM_PIN_FUNCTION(qup0_se0), 990 MSM_PIN_FUNCTION(qup0_se1), 991 MSM_PIN_FUNCTION(qup0_se2), 992 MSM_PIN_FUNCTION(qup0_se3), 993 MSM_PIN_FUNCTION(qup0_se4), 994 MSM_PIN_FUNCTION(qup0_se5), 995 MSM_PIN_FUNCTION(qup0_se6), 996 MSM_PIN_FUNCTION(qup0_se7), 997 MSM_PIN_FUNCTION(qup1_se0), 998 MSM_PIN_FUNCTION(qup1_se1), 999 MSM_PIN_FUNCTION(qup1_se2), 1000 MSM_PIN_FUNCTION(qup1_se3), 1001 MSM_PIN_FUNCTION(qup1_se4), 1002 MSM_PIN_FUNCTION(qup1_se5), 1003 MSM_PIN_FUNCTION(qup1_se6), 1004 MSM_PIN_FUNCTION(qup1_se7), 1005 MSM_PIN_FUNCTION(qup2_se0), 1006 MSM_PIN_FUNCTION(sailss_emac0), 1007 MSM_PIN_FUNCTION(sailss_ospi), 1008 MSM_PIN_FUNCTION(sgmii_phy), 1009 MSM_PIN_FUNCTION(tb_trig), 1010 MSM_PIN_FUNCTION(tgu_ch0), 1011 MSM_PIN_FUNCTION(tgu_ch1), 1012 MSM_PIN_FUNCTION(tgu_ch2), 1013 MSM_PIN_FUNCTION(tgu_ch3), 1014 MSM_PIN_FUNCTION(tsense_pwm1), 1015 MSM_PIN_FUNCTION(tsense_pwm2), 1016 MSM_PIN_FUNCTION(tsense_pwm3), 1017 MSM_PIN_FUNCTION(tsense_pwm4), 1018 MSM_PIN_FUNCTION(usb2phy_ac), 1019 MSM_PIN_FUNCTION(vsense_trigger), 1020 }; 1021 1022 /* 1023 * Every pin is maintained as a single group, and missing or non-existing pin 1024 * would be maintained as dummy group to synchronize pin group index with 1025 * pin descriptor registered with pinctrl core. 1026 * Clients would not be able to request these dummy pin groups. 1027 */ 1028 static const struct msm_pingroup qcs8300_groups[] = { 1029 [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _, _, _), 1030 [1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _, _, _), 1031 [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _, _, _), 1032 [3] = PINGROUP(3, phase_flag, _, _, _, _, _, _, _, _, _, _), 1033 [4] = PINGROUP(4, sgmii_phy, qdss_cti, _, _, _, _, _, _, _, _, _), 1034 [5] = PINGROUP(5, emac0_mdc, qdss_cti, _, _, _, _, _, _, _, _, _), 1035 [6] = PINGROUP(6, emac0_mdio, _, _, _, _, _, _, _, _, _, _), 1036 [7] = PINGROUP(7, usb2phy_ac, _, _, _, _, _, _, _, _, _, _), 1037 [8] = PINGROUP(8, usb2phy_ac, _, _, _, _, _, _, _, _, _, _), 1038 [9] = PINGROUP(9, phase_flag, _, _, _, _, _, _, _, _, _, _), 1039 [10] = PINGROUP(10, qup2_se0, emac0_mcg0, _, _, _, _, _, _, _, _, _), 1040 [11] = PINGROUP(11, qup2_se0, emac0_mcg1, _, _, _, _, _, _, _, _, _), 1041 [12] = PINGROUP(12, qup2_se0, _, _, _, _, _, _, _, _, _, _), 1042 [13] = PINGROUP(13, qup2_se0, _, _, _, _, _, _, _, _, _, _), 1043 [14] = PINGROUP(14, qup2_se0, tb_trig, _, _, _, _, _, _, _, _, _), 1044 [15] = PINGROUP(15, qup2_se0, _, sailss_ospi, sailss_emac0, _, _, _, _, _, _, _), 1045 [16] = PINGROUP(16, qup2_se0, _, _, sailss_ospi, sailss_emac0, _, _, _, _, _, _), 1046 [17] = PINGROUP(17, qup0_se0, qup0_se1, ibi_i3c, _, _, _, _, _, _, _, _), 1047 [18] = PINGROUP(18, qup0_se0, qup0_se1, ibi_i3c, _, _, _, _, _, _, _, _), 1048 [19] = PINGROUP(19, qup0_se1, qup0_se0, cci_timer, ibi_i3c, _, _, _, _, _, _, _), 1049 [20] = PINGROUP(20, qup0_se1, qup0_se0, cci_timer, ibi_i3c, _, _, _, _, _, _, _), 1050 [21] = PINGROUP(21, qup0_se5, cci_timer, _, _, _, _, _, _, _, _, _), 1051 [22] = PINGROUP(22, pcie1_clkreq, qup0_se5, cci_timer, _, _, _, _, _, _, _, _), 1052 [23] = PINGROUP(23, qup0_se5, cci_timer, qdss_cti, _, _, _, _, _, _, _, _), 1053 [24] = PINGROUP(24, qup0_se5, emac0_ptp_aux, emac0_ptp_pps, qdss_cti, 1054 emac0_mcg2, _, _, _, _, _, _), 1055 [25] = PINGROUP(25, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _), 1056 [26] = PINGROUP(26, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _), 1057 [27] = PINGROUP(27, qup0_se3, _, _, _, _, _, _, _, _, _, _), 1058 [28] = PINGROUP(28, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _), 1059 [29] = PINGROUP(29, qup0_se4, cci_i2c_sda, cci_async, emac0_ptp_pps, 1060 tgu_ch2, _, _, _, _, _, _), 1061 [30] = PINGROUP(30, qup0_se4, cci_i2c_scl, cci_async, emac0_ptp_pps, 1062 tgu_ch3, _, _, _, _, _, _), 1063 [31] = PINGROUP(31, qup0_se4, cci_i2c_sda, cci_async, emac0_ptp_aux, _, _, _, _, _, _, _), 1064 [32] = PINGROUP(32, qup0_se4, cci_i2c_scl, emac0_ptp_aux, mdp_vsync, _, _, _, _, _, _, _), 1065 [33] = PINGROUP(33, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _), 1066 [34] = PINGROUP(34, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _), 1067 [35] = PINGROUP(35, qup0_se2, gcc_gp1, _, _, _, _, _, _, _, _, _), 1068 [36] = PINGROUP(36, qup0_se2, gcc_gp2, qdss_gpio, _, _, _, _, _, _, _, _), 1069 [37] = PINGROUP(37, qup1_se0, ibi_i3c, qup1_se1, aoss_cti, _, _, _, _, _, _, _), 1070 [38] = PINGROUP(38, qup1_se0, ibi_i3c, qup1_se1, aoss_cti, _, _, _, _, _, _, _), 1071 [39] = PINGROUP(39, qup1_se1, ibi_i3c, qup1_se0, aoss_cti, _, _, _, _, _, _, _), 1072 [40] = PINGROUP(40, qup1_se1, ibi_i3c, qup1_se0, aoss_cti, _, _, _, _, _, _, _), 1073 [41] = PINGROUP(41, qup1_se3, _, _, _, _, _, _, _, _, _, _), 1074 [42] = PINGROUP(42, qup1_se3, _, mdp_vsync, _, _, _, _, _, _, _, _), 1075 [43] = PINGROUP(43, qup0_se7, _, tgu_ch0, _, _, _, _, _, _, _, _), 1076 [44] = PINGROUP(44, qup0_se7, _, tgu_ch1, _, _, _, _, _, _, _, _), 1077 [45] = PINGROUP(45, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _), 1078 [46] = PINGROUP(46, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _), 1079 [47] = PINGROUP(47, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _), 1080 [48] = PINGROUP(48, qup1_se4, hs1_mi2s, edp0_lcd, _, _, _, _, _, _, _, _), 1081 [49] = PINGROUP(49, qup1_se5, hs2_mi2s, cci_timer, qdss_cti, edp1_lcd, 1082 ddr_pxi1, _, _, _, _, _), 1083 [50] = PINGROUP(50, qup1_se5, hs2_mi2s, cci_timer, qdss_cti, _, ddr_pxi1, _, _, _, _, _), 1084 [51] = PINGROUP(51, qup1_se5, hs2_mi2s, qdss_cti, _, _, _, _, _, _, _, _), 1085 [52] = PINGROUP(52, qup1_se5, hs2_mi2s, qdss_cti, mdp_vsync, ddr_pxi2, _, _, _, _, _, _), 1086 [53] = PINGROUP(53, ddr_bist, _, _, _, _, _, _, _, _, _, _), 1087 [54] = PINGROUP(54, cci_i2c_sda, phase_flag, ddr_bist, _, _, _, _, _, _, _, _), 1088 [55] = PINGROUP(55, cci_i2c_scl, phase_flag, ddr_bist, _, _, _, _, _, _, _, _), 1089 [56] = PINGROUP(56, phase_flag, ddr_bist, _, _, _, _, _, _, _, _, _), 1090 [57] = PINGROUP(57, cci_i2c_sda, prng_rosc0, qdss_gpio, _, _, _, _, _, _, _, _), 1091 [58] = PINGROUP(58, cci_i2c_scl, prng_rosc1, qdss_gpio, _, _, _, _, _, _, _, _), 1092 [59] = PINGROUP(59, cci_i2c_sda, prng_rosc2, qdss_gpio, _, _, _, _, _, _, _, _), 1093 [60] = PINGROUP(60, cci_i2c_scl, prng_rosc3, qdss_gpio, _, _, _, _, _, _, _, _), 1094 [61] = PINGROUP(61, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _, _, _), 1095 [62] = PINGROUP(62, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _, _, _), 1096 [63] = PINGROUP(63, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _), 1097 [64] = PINGROUP(64, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _), 1098 [65] = PINGROUP(65, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _), 1099 [66] = PINGROUP(66, phase_flag, _, atest_char, _, _, _, _, _, _, _, _), 1100 [67] = PINGROUP(67, cam_mclk, vsense_trigger, atest_usb2, _, _, _, _, _, _, _, _), 1101 [68] = PINGROUP(68, cam_mclk, gcc_gp4, atest_usb2, ddr_pxi0, _, _, _, _, _, _, _), 1102 [69] = PINGROUP(69, cam_mclk, gcc_gp3, atest_usb2, ddr_pxi0, _, _, _, _, _, _, _), 1103 [70] = PINGROUP(70, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _), 1104 [71] = PINGROUP(71, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _), 1105 [72] = PINGROUP(72, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _), 1106 [73] = PINGROUP(73, _, qdss_gpio, _, _, _, _, _, _, _, _, _), 1107 [74] = PINGROUP(74, pll_clk, qdss_gpio, atest_usb2, _, _, _, _, _, _, _, _), 1108 [75] = PINGROUP(75, _, dbg_out, qdss_gpio, atest_usb2, _, _, _, _, _, _, _), 1109 [76] = PINGROUP(76, gcc_gp5, tsense_pwm4, _, _, _, _, _, _, _, _, _), 1110 [77] = PINGROUP(77, gcc_gp5, tsense_pwm3, _, _, _, _, _, _, _, _, _), 1111 [78] = PINGROUP(78, tsense_pwm2, _, _, _, _, _, _, _, _, _, _), 1112 [79] = PINGROUP(79, emac0_ptp_aux, emac0_ptp_pps, emac0_mcg3, _, 1113 tsense_pwm1, _, _, _, _, _, _), 1114 [80] = PINGROUP(80, qup0_se6, mdp0_vsync6, _, atest_usb2, ddr_pxi3, _, _, _, _, _, _), 1115 [81] = PINGROUP(81, qup0_se6, mdp0_vsync7, gcc_gp2, _, atest_usb2, ddr_pxi3, _, _, _, _, _), 1116 [82] = PINGROUP(82, qup0_se6, gcc_gp3, _, _, _, _, _, _, _, _, _), 1117 [83] = PINGROUP(83, qup0_se6, gcc_gp4, _, atest_usb2, ddr_pxi2, _, _, _, _, _, _), 1118 [84] = PINGROUP(84, qup1_se2, gcc_gp1, _, atest_usb2, _, _, _, _, _, _, _), 1119 [85] = PINGROUP(85, qup1_se2, _, atest_usb2, _, _, _, _, _, _, _, _), 1120 [86] = PINGROUP(86, qup1_se2, _, _, _, _, _, _, _, _, _, _), 1121 [87] = PINGROUP(87, qup1_se2, _, atest_usb2, _, _, _, _, _, _, _, _), 1122 [88] = PINGROUP(88, qup1_se2, _, _, _, _, _, _, _, _, _, _), 1123 [89] = PINGROUP(89, qup1_se6, qup1_se7, mdp0_vsync0, _, _, _, _, _, _, _, _), 1124 [90] = PINGROUP(90, qup1_se6, qup1_se7, mdp0_vsync1, cri_trng, _, _, _, _, _, _, _), 1125 [91] = PINGROUP(91, qup1_se7, qup1_se6, mdp0_vsync3, cri_trng, _, _, _, _, _, _, _), 1126 [92] = PINGROUP(92, qup1_se7, qup1_se6, cri_trng, _, atest_usb2, _, _, _, _, _, _), 1127 [93] = PINGROUP(93, atest_char, _, _, _, _, _, _, _, _, _, _), 1128 [94] = PINGROUP(94, edp0_hot, _, _, _, _, _, _, _, _, _, _), 1129 [95] = PINGROUP(95, _, _, _, _, _, _, _, _, _, _, _), 1130 [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _, _, _), 1131 [97] = PINGROUP(97, mi2s_mclk0, jitter_bist, qdss_gpio, _, _, _, _, _, _, _, _), 1132 [98] = PINGROUP(98, mi2s1_sck, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), 1133 [99] = PINGROUP(99, mi2s1_ws, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), 1134 [100] = PINGROUP(100, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), 1135 [101] = PINGROUP(101, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), 1136 [102] = PINGROUP(102, mi2s2_sck, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), 1137 [103] = PINGROUP(103, mi2s2_ws, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), 1138 [104] = PINGROUP(104, mi2s2_data0, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), 1139 [105] = PINGROUP(105, mi2s2_data1, audio_ref, phase_flag, _, qdss_gpio, _, _, _, _, _, _), 1140 [106] = PINGROUP(106, hs0_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), 1141 [107] = PINGROUP(107, hs0_mi2s, pll_bist, phase_flag, _, qdss_gpio, _, _, _, _, _, _), 1142 [108] = PINGROUP(108, hs0_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _), 1143 [109] = PINGROUP(109, hs0_mi2s, mi2s_mclk1, qdss_gpio, _, _, _, _, _, _, _, _), 1144 [110] = PINGROUP(110, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio), 1145 [111] = PINGROUP(111, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio), 1146 [112] = PINGROUP(112, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio), 1147 [113] = PINGROUP(113, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio), 1148 [114] = PINGROUP(114, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio), 1149 [115] = PINGROUP(115, _, _, _, _, _, _, _, _, _, _, egpio), 1150 [116] = PINGROUP(116, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1151 [117] = PINGROUP(117, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1152 [118] = PINGROUP(118, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1153 [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, egpio), 1154 [120] = PINGROUP(120, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1155 [121] = PINGROUP(121, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1156 [122] = PINGROUP(122, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1157 [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _, _, egpio), 1158 [124] = PINGROUP(124, _, _, _, _, _, _, _, _, _, _, egpio), 1159 [125] = PINGROUP(125, phase_flag, _, _, _, _, _, _, _, _, _, egpio), 1160 [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _, _, egpio), 1161 [127] = PINGROUP(127, _, _, _, _, _, _, _, _, _, _, egpio), 1162 [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _, _, egpio), 1163 [129] = PINGROUP(129, _, _, _, _, _, _, _, _, _, _, egpio), 1164 [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _, _, egpio), 1165 [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _, _, egpio), 1166 [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _, _, egpio), 1167 [133] = UFS_RESET(ufs_reset, 0x92000), 1168 [134] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x89000, 15, 0), 1169 [135] = SDC_QDSD_PINGROUP(sdc1_clk, 0x89000, 13, 6), 1170 [136] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x89000, 11, 3), 1171 [137] = SDC_QDSD_PINGROUP(sdc1_data, 0x89000, 9, 0), 1172 }; 1173 1174 static const struct msm_gpio_wakeirq_map qcs8300_pdc_map[] = { 1175 { 0, 169 }, { 1, 174 }, { 2, 221 }, { 3, 176 }, { 4, 171 }, 1176 { 9, 198 }, { 10, 187 }, { 11, 188 }, { 13, 211 }, { 16, 203 }, 1177 { 17, 213 }, { 18, 209 }, { 19, 201 }, { 20, 230 }, { 21, 231 }, 1178 { 22, 175 }, { 23, 170 }, { 24, 232 }, { 28, 235 }, { 29, 216 }, 1179 { 31, 208 }, { 32, 200 }, { 36, 212 }, { 37, 177 }, { 38, 178 }, 1180 { 39, 184 }, { 40, 185 }, { 42, 186 }, { 44, 194 }, { 45, 173 }, 1181 { 48, 195 }, { 51, 215 }, { 52, 197 }, { 53, 192 }, { 56, 193 }, 1182 { 66, 238 }, { 67, 172 }, { 68, 182 }, { 69, 179 }, { 70, 181 }, 1183 { 71, 202 }, { 72, 183 }, { 73, 189 }, { 74, 196 }, { 75, 190 }, 1184 { 76, 191 }, { 77, 204 }, { 78, 206 }, { 79, 207 }, { 83, 214 }, 1185 { 84, 205 }, { 87, 237 }, { 89, 225 }, { 90, 217 }, { 91, 218 }, 1186 { 92, 226 }, { 93, 227 }, { 94, 228 }, { 95, 236 }, { 97, 199 }, 1187 { 98, 229 }, { 99, 180 }, { 100, 220 }, { 101, 239 }, { 102, 219 }, 1188 { 103, 233 }, { 104, 234 }, { 105, 223 }, { 129, 210 }, { 130, 222 }, 1189 }; 1190 1191 static const struct msm_pinctrl_soc_data qcs8300_pinctrl = { 1192 .pins = qcs8300_pins, 1193 .npins = ARRAY_SIZE(qcs8300_pins), 1194 .functions = qcs8300_functions, 1195 .nfunctions = ARRAY_SIZE(qcs8300_functions), 1196 .groups = qcs8300_groups, 1197 .ngroups = ARRAY_SIZE(qcs8300_groups), 1198 .ngpios = 134, 1199 .wakeirq_map = qcs8300_pdc_map, 1200 .nwakeirq_map = ARRAY_SIZE(qcs8300_pdc_map), 1201 .egpio_func = 11, 1202 }; 1203 1204 static int qcs8300_pinctrl_probe(struct platform_device *pdev) 1205 { 1206 return msm_pinctrl_probe(pdev, &qcs8300_pinctrl); 1207 } 1208 1209 static const struct of_device_id qcs8300_pinctrl_of_match[] = { 1210 { .compatible = "qcom,qcs8300-tlmm", }, 1211 { }, 1212 }; 1213 MODULE_DEVICE_TABLE(of, qcs8300_pinctrl_of_match); 1214 1215 static struct platform_driver qcs8300_pinctrl_driver = { 1216 .driver = { 1217 .name = "qcs8300-tlmm", 1218 .of_match_table = qcs8300_pinctrl_of_match, 1219 }, 1220 .probe = qcs8300_pinctrl_probe, 1221 }; 1222 1223 static int __init qcs8300_pinctrl_init(void) 1224 { 1225 return platform_driver_register(&qcs8300_pinctrl_driver); 1226 } 1227 arch_initcall(qcs8300_pinctrl_init); 1228 1229 static void __exit qcs8300_pinctrl_exit(void) 1230 { 1231 platform_driver_unregister(&qcs8300_pinctrl_driver); 1232 } 1233 module_exit(qcs8300_pinctrl_exit); 1234 1235 MODULE_DESCRIPTION("QTI QCS8300 pinctrl driver"); 1236 MODULE_LICENSE("GPL"); 1237