xref: /linux/drivers/pinctrl/qcom/pinctrl-qcs8300.c (revision 7f71507851fc7764b36a3221839607d3a45c2025)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4  */
5 
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9 
10 #include "pinctrl-msm.h"
11 
12 #define REG_SIZE 0x1000
13 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11)\
14 	{						\
15 		.grp = PINCTRL_PINGROUP("gpio" #id,	\
16 			gpio##id##_pins,		\
17 			ARRAY_SIZE(gpio##id##_pins)),	\
18 		.funcs = (int[]){			\
19 			msm_mux_gpio, /* gpio mode */	\
20 			msm_mux_##f1,			\
21 			msm_mux_##f2,			\
22 			msm_mux_##f3,			\
23 			msm_mux_##f4,			\
24 			msm_mux_##f5,			\
25 			msm_mux_##f6,			\
26 			msm_mux_##f7,			\
27 			msm_mux_##f8,			\
28 			msm_mux_##f9,			\
29 			msm_mux_##f10,			\
30 			msm_mux_##f11 /* egpio mode */	\
31 		},					\
32 		.nfuncs = 12,				\
33 		.ctl_reg = REG_SIZE * id,		\
34 		.io_reg = 0x4 + REG_SIZE * id,		\
35 		.intr_cfg_reg = 0x8 + REG_SIZE * id,	\
36 		.intr_status_reg = 0xc + REG_SIZE * id,	\
37 		.intr_target_reg = 0x8 + REG_SIZE * id,	\
38 		.mux_bit = 2,			\
39 		.pull_bit = 0,			\
40 		.drv_bit = 6,			\
41 		.egpio_enable = 12,		\
42 		.egpio_present = 11,		\
43 		.oe_bit = 9,			\
44 		.in_bit = 0,			\
45 		.out_bit = 1,			\
46 		.intr_enable_bit = 0,		\
47 		.intr_status_bit = 0,		\
48 		.intr_target_bit = 5,		\
49 		.intr_target_kpss_val = 3,	\
50 		.intr_raw_status_bit = 4,	\
51 		.intr_polarity_bit = 1,		\
52 		.intr_detection_bit = 2,	\
53 		.intr_detection_width = 2,	\
54 	}
55 
56 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)	\
57 	{						\
58 		.grp = PINCTRL_PINGROUP(#pg_name,	\
59 			pg_name##_pins,			\
60 			ARRAY_SIZE(pg_name##_pins)),	\
61 		.ctl_reg = ctl,				\
62 		.io_reg = 0,				\
63 		.intr_cfg_reg = 0,			\
64 		.intr_status_reg = 0,			\
65 		.intr_target_reg = 0,			\
66 		.mux_bit = -1,				\
67 		.pull_bit = pull,			\
68 		.drv_bit = drv,				\
69 		.oe_bit = -1,				\
70 		.in_bit = -1,				\
71 		.out_bit = -1,				\
72 		.intr_enable_bit = -1,			\
73 		.intr_status_bit = -1,			\
74 		.intr_target_bit = -1,			\
75 		.intr_raw_status_bit = -1,		\
76 		.intr_polarity_bit = -1,		\
77 		.intr_detection_bit = -1,		\
78 		.intr_detection_width = -1,		\
79 	}
80 
81 #define UFS_RESET(pg_name, offset)			\
82 	{						\
83 		.grp = PINCTRL_PINGROUP(#pg_name,	\
84 			pg_name##_pins,			\
85 			ARRAY_SIZE(pg_name##_pins)),	\
86 		.ctl_reg = offset,			\
87 		.io_reg = offset + 0x4,			\
88 		.intr_cfg_reg = 0,			\
89 		.intr_status_reg = 0,			\
90 		.intr_target_reg = 0,			\
91 		.mux_bit = -1,				\
92 		.pull_bit = 3,				\
93 		.drv_bit = 0,				\
94 		.oe_bit = -1,				\
95 		.in_bit = -1,				\
96 		.out_bit = 0,				\
97 		.intr_enable_bit = -1,			\
98 		.intr_status_bit = -1,			\
99 		.intr_target_bit = -1,			\
100 		.intr_raw_status_bit = -1,		\
101 		.intr_polarity_bit = -1,		\
102 		.intr_detection_bit = -1,		\
103 		.intr_detection_width = -1,		\
104 	}
105 
106 #define QUP_I3C(qup_mode, qup_offset)			\
107 	{						\
108 		.mode = qup_mode,			\
109 		.offset = qup_offset,			\
110 	}
111 
112 #define QUP_I3C_6_MODE_OFFSET	0xaf000
113 #define QUP_I3C_7_MODE_OFFSET	0xb0000
114 #define QUP_I3C_13_MODE_OFFSET	0xb1000
115 #define QUP_I3C_14_MODE_OFFSET	0xb2000
116 
117 static const struct pinctrl_pin_desc qcs8300_pins[] = {
118 	PINCTRL_PIN(0, "GPIO_0"),
119 	PINCTRL_PIN(1, "GPIO_1"),
120 	PINCTRL_PIN(2, "GPIO_2"),
121 	PINCTRL_PIN(3, "GPIO_3"),
122 	PINCTRL_PIN(4, "GPIO_4"),
123 	PINCTRL_PIN(5, "GPIO_5"),
124 	PINCTRL_PIN(6, "GPIO_6"),
125 	PINCTRL_PIN(7, "GPIO_7"),
126 	PINCTRL_PIN(8, "GPIO_8"),
127 	PINCTRL_PIN(9, "GPIO_9"),
128 	PINCTRL_PIN(10, "GPIO_10"),
129 	PINCTRL_PIN(11, "GPIO_11"),
130 	PINCTRL_PIN(12, "GPIO_12"),
131 	PINCTRL_PIN(13, "GPIO_13"),
132 	PINCTRL_PIN(14, "GPIO_14"),
133 	PINCTRL_PIN(15, "GPIO_15"),
134 	PINCTRL_PIN(16, "GPIO_16"),
135 	PINCTRL_PIN(17, "GPIO_17"),
136 	PINCTRL_PIN(18, "GPIO_18"),
137 	PINCTRL_PIN(19, "GPIO_19"),
138 	PINCTRL_PIN(20, "GPIO_20"),
139 	PINCTRL_PIN(21, "GPIO_21"),
140 	PINCTRL_PIN(22, "GPIO_22"),
141 	PINCTRL_PIN(23, "GPIO_23"),
142 	PINCTRL_PIN(24, "GPIO_24"),
143 	PINCTRL_PIN(25, "GPIO_25"),
144 	PINCTRL_PIN(26, "GPIO_26"),
145 	PINCTRL_PIN(27, "GPIO_27"),
146 	PINCTRL_PIN(28, "GPIO_28"),
147 	PINCTRL_PIN(29, "GPIO_29"),
148 	PINCTRL_PIN(30, "GPIO_30"),
149 	PINCTRL_PIN(31, "GPIO_31"),
150 	PINCTRL_PIN(32, "GPIO_32"),
151 	PINCTRL_PIN(33, "GPIO_33"),
152 	PINCTRL_PIN(34, "GPIO_34"),
153 	PINCTRL_PIN(35, "GPIO_35"),
154 	PINCTRL_PIN(36, "GPIO_36"),
155 	PINCTRL_PIN(37, "GPIO_37"),
156 	PINCTRL_PIN(38, "GPIO_38"),
157 	PINCTRL_PIN(39, "GPIO_39"),
158 	PINCTRL_PIN(40, "GPIO_40"),
159 	PINCTRL_PIN(41, "GPIO_41"),
160 	PINCTRL_PIN(42, "GPIO_42"),
161 	PINCTRL_PIN(43, "GPIO_43"),
162 	PINCTRL_PIN(44, "GPIO_44"),
163 	PINCTRL_PIN(45, "GPIO_45"),
164 	PINCTRL_PIN(46, "GPIO_46"),
165 	PINCTRL_PIN(47, "GPIO_47"),
166 	PINCTRL_PIN(48, "GPIO_48"),
167 	PINCTRL_PIN(49, "GPIO_49"),
168 	PINCTRL_PIN(50, "GPIO_50"),
169 	PINCTRL_PIN(51, "GPIO_51"),
170 	PINCTRL_PIN(52, "GPIO_52"),
171 	PINCTRL_PIN(53, "GPIO_53"),
172 	PINCTRL_PIN(54, "GPIO_54"),
173 	PINCTRL_PIN(55, "GPIO_55"),
174 	PINCTRL_PIN(56, "GPIO_56"),
175 	PINCTRL_PIN(57, "GPIO_57"),
176 	PINCTRL_PIN(58, "GPIO_58"),
177 	PINCTRL_PIN(59, "GPIO_59"),
178 	PINCTRL_PIN(60, "GPIO_60"),
179 	PINCTRL_PIN(61, "GPIO_61"),
180 	PINCTRL_PIN(62, "GPIO_62"),
181 	PINCTRL_PIN(63, "GPIO_63"),
182 	PINCTRL_PIN(64, "GPIO_64"),
183 	PINCTRL_PIN(65, "GPIO_65"),
184 	PINCTRL_PIN(66, "GPIO_66"),
185 	PINCTRL_PIN(67, "GPIO_67"),
186 	PINCTRL_PIN(68, "GPIO_68"),
187 	PINCTRL_PIN(69, "GPIO_69"),
188 	PINCTRL_PIN(70, "GPIO_70"),
189 	PINCTRL_PIN(71, "GPIO_71"),
190 	PINCTRL_PIN(72, "GPIO_72"),
191 	PINCTRL_PIN(73, "GPIO_73"),
192 	PINCTRL_PIN(74, "GPIO_74"),
193 	PINCTRL_PIN(75, "GPIO_75"),
194 	PINCTRL_PIN(76, "GPIO_76"),
195 	PINCTRL_PIN(77, "GPIO_77"),
196 	PINCTRL_PIN(78, "GPIO_78"),
197 	PINCTRL_PIN(79, "GPIO_79"),
198 	PINCTRL_PIN(80, "GPIO_80"),
199 	PINCTRL_PIN(81, "GPIO_81"),
200 	PINCTRL_PIN(82, "GPIO_82"),
201 	PINCTRL_PIN(83, "GPIO_83"),
202 	PINCTRL_PIN(84, "GPIO_84"),
203 	PINCTRL_PIN(85, "GPIO_85"),
204 	PINCTRL_PIN(86, "GPIO_86"),
205 	PINCTRL_PIN(87, "GPIO_87"),
206 	PINCTRL_PIN(88, "GPIO_88"),
207 	PINCTRL_PIN(89, "GPIO_89"),
208 	PINCTRL_PIN(90, "GPIO_90"),
209 	PINCTRL_PIN(91, "GPIO_91"),
210 	PINCTRL_PIN(92, "GPIO_92"),
211 	PINCTRL_PIN(93, "GPIO_93"),
212 	PINCTRL_PIN(94, "GPIO_94"),
213 	PINCTRL_PIN(95, "GPIO_95"),
214 	PINCTRL_PIN(96, "GPIO_96"),
215 	PINCTRL_PIN(97, "GPIO_97"),
216 	PINCTRL_PIN(98, "GPIO_98"),
217 	PINCTRL_PIN(99, "GPIO_99"),
218 	PINCTRL_PIN(100, "GPIO_100"),
219 	PINCTRL_PIN(101, "GPIO_101"),
220 	PINCTRL_PIN(102, "GPIO_102"),
221 	PINCTRL_PIN(103, "GPIO_103"),
222 	PINCTRL_PIN(104, "GPIO_104"),
223 	PINCTRL_PIN(105, "GPIO_105"),
224 	PINCTRL_PIN(106, "GPIO_106"),
225 	PINCTRL_PIN(107, "GPIO_107"),
226 	PINCTRL_PIN(108, "GPIO_108"),
227 	PINCTRL_PIN(109, "GPIO_109"),
228 	PINCTRL_PIN(110, "GPIO_110"),
229 	PINCTRL_PIN(111, "GPIO_111"),
230 	PINCTRL_PIN(112, "GPIO_112"),
231 	PINCTRL_PIN(113, "GPIO_113"),
232 	PINCTRL_PIN(114, "GPIO_114"),
233 	PINCTRL_PIN(115, "GPIO_115"),
234 	PINCTRL_PIN(116, "GPIO_116"),
235 	PINCTRL_PIN(117, "GPIO_117"),
236 	PINCTRL_PIN(118, "GPIO_118"),
237 	PINCTRL_PIN(119, "GPIO_119"),
238 	PINCTRL_PIN(120, "GPIO_120"),
239 	PINCTRL_PIN(121, "GPIO_121"),
240 	PINCTRL_PIN(122, "GPIO_122"),
241 	PINCTRL_PIN(123, "GPIO_123"),
242 	PINCTRL_PIN(124, "GPIO_124"),
243 	PINCTRL_PIN(125, "GPIO_125"),
244 	PINCTRL_PIN(126, "GPIO_126"),
245 	PINCTRL_PIN(127, "GPIO_127"),
246 	PINCTRL_PIN(128, "GPIO_128"),
247 	PINCTRL_PIN(129, "GPIO_129"),
248 	PINCTRL_PIN(130, "GPIO_130"),
249 	PINCTRL_PIN(131, "GPIO_131"),
250 	PINCTRL_PIN(132, "GPIO_132"),
251 	PINCTRL_PIN(133, "UFS_RESET"),
252 	PINCTRL_PIN(134, "SDC1_RCLK"),
253 	PINCTRL_PIN(135, "SDC1_CLK"),
254 	PINCTRL_PIN(136, "SDC1_CMD"),
255 	PINCTRL_PIN(137, "SDC1_DATA"),
256 };
257 
258 #define DECLARE_MSM_GPIO_PINS(pin) \
259 	static const unsigned int gpio##pin##_pins[] = { pin }
260 DECLARE_MSM_GPIO_PINS(0);
261 DECLARE_MSM_GPIO_PINS(1);
262 DECLARE_MSM_GPIO_PINS(2);
263 DECLARE_MSM_GPIO_PINS(3);
264 DECLARE_MSM_GPIO_PINS(4);
265 DECLARE_MSM_GPIO_PINS(5);
266 DECLARE_MSM_GPIO_PINS(6);
267 DECLARE_MSM_GPIO_PINS(7);
268 DECLARE_MSM_GPIO_PINS(8);
269 DECLARE_MSM_GPIO_PINS(9);
270 DECLARE_MSM_GPIO_PINS(10);
271 DECLARE_MSM_GPIO_PINS(11);
272 DECLARE_MSM_GPIO_PINS(12);
273 DECLARE_MSM_GPIO_PINS(13);
274 DECLARE_MSM_GPIO_PINS(14);
275 DECLARE_MSM_GPIO_PINS(15);
276 DECLARE_MSM_GPIO_PINS(16);
277 DECLARE_MSM_GPIO_PINS(17);
278 DECLARE_MSM_GPIO_PINS(18);
279 DECLARE_MSM_GPIO_PINS(19);
280 DECLARE_MSM_GPIO_PINS(20);
281 DECLARE_MSM_GPIO_PINS(21);
282 DECLARE_MSM_GPIO_PINS(22);
283 DECLARE_MSM_GPIO_PINS(23);
284 DECLARE_MSM_GPIO_PINS(24);
285 DECLARE_MSM_GPIO_PINS(25);
286 DECLARE_MSM_GPIO_PINS(26);
287 DECLARE_MSM_GPIO_PINS(27);
288 DECLARE_MSM_GPIO_PINS(28);
289 DECLARE_MSM_GPIO_PINS(29);
290 DECLARE_MSM_GPIO_PINS(30);
291 DECLARE_MSM_GPIO_PINS(31);
292 DECLARE_MSM_GPIO_PINS(32);
293 DECLARE_MSM_GPIO_PINS(33);
294 DECLARE_MSM_GPIO_PINS(34);
295 DECLARE_MSM_GPIO_PINS(35);
296 DECLARE_MSM_GPIO_PINS(36);
297 DECLARE_MSM_GPIO_PINS(37);
298 DECLARE_MSM_GPIO_PINS(38);
299 DECLARE_MSM_GPIO_PINS(39);
300 DECLARE_MSM_GPIO_PINS(40);
301 DECLARE_MSM_GPIO_PINS(41);
302 DECLARE_MSM_GPIO_PINS(42);
303 DECLARE_MSM_GPIO_PINS(43);
304 DECLARE_MSM_GPIO_PINS(44);
305 DECLARE_MSM_GPIO_PINS(45);
306 DECLARE_MSM_GPIO_PINS(46);
307 DECLARE_MSM_GPIO_PINS(47);
308 DECLARE_MSM_GPIO_PINS(48);
309 DECLARE_MSM_GPIO_PINS(49);
310 DECLARE_MSM_GPIO_PINS(50);
311 DECLARE_MSM_GPIO_PINS(51);
312 DECLARE_MSM_GPIO_PINS(52);
313 DECLARE_MSM_GPIO_PINS(53);
314 DECLARE_MSM_GPIO_PINS(54);
315 DECLARE_MSM_GPIO_PINS(55);
316 DECLARE_MSM_GPIO_PINS(56);
317 DECLARE_MSM_GPIO_PINS(57);
318 DECLARE_MSM_GPIO_PINS(58);
319 DECLARE_MSM_GPIO_PINS(59);
320 DECLARE_MSM_GPIO_PINS(60);
321 DECLARE_MSM_GPIO_PINS(61);
322 DECLARE_MSM_GPIO_PINS(62);
323 DECLARE_MSM_GPIO_PINS(63);
324 DECLARE_MSM_GPIO_PINS(64);
325 DECLARE_MSM_GPIO_PINS(65);
326 DECLARE_MSM_GPIO_PINS(66);
327 DECLARE_MSM_GPIO_PINS(67);
328 DECLARE_MSM_GPIO_PINS(68);
329 DECLARE_MSM_GPIO_PINS(69);
330 DECLARE_MSM_GPIO_PINS(70);
331 DECLARE_MSM_GPIO_PINS(71);
332 DECLARE_MSM_GPIO_PINS(72);
333 DECLARE_MSM_GPIO_PINS(73);
334 DECLARE_MSM_GPIO_PINS(74);
335 DECLARE_MSM_GPIO_PINS(75);
336 DECLARE_MSM_GPIO_PINS(76);
337 DECLARE_MSM_GPIO_PINS(77);
338 DECLARE_MSM_GPIO_PINS(78);
339 DECLARE_MSM_GPIO_PINS(79);
340 DECLARE_MSM_GPIO_PINS(80);
341 DECLARE_MSM_GPIO_PINS(81);
342 DECLARE_MSM_GPIO_PINS(82);
343 DECLARE_MSM_GPIO_PINS(83);
344 DECLARE_MSM_GPIO_PINS(84);
345 DECLARE_MSM_GPIO_PINS(85);
346 DECLARE_MSM_GPIO_PINS(86);
347 DECLARE_MSM_GPIO_PINS(87);
348 DECLARE_MSM_GPIO_PINS(88);
349 DECLARE_MSM_GPIO_PINS(89);
350 DECLARE_MSM_GPIO_PINS(90);
351 DECLARE_MSM_GPIO_PINS(91);
352 DECLARE_MSM_GPIO_PINS(92);
353 DECLARE_MSM_GPIO_PINS(93);
354 DECLARE_MSM_GPIO_PINS(94);
355 DECLARE_MSM_GPIO_PINS(95);
356 DECLARE_MSM_GPIO_PINS(96);
357 DECLARE_MSM_GPIO_PINS(97);
358 DECLARE_MSM_GPIO_PINS(98);
359 DECLARE_MSM_GPIO_PINS(99);
360 DECLARE_MSM_GPIO_PINS(100);
361 DECLARE_MSM_GPIO_PINS(101);
362 DECLARE_MSM_GPIO_PINS(102);
363 DECLARE_MSM_GPIO_PINS(103);
364 DECLARE_MSM_GPIO_PINS(104);
365 DECLARE_MSM_GPIO_PINS(105);
366 DECLARE_MSM_GPIO_PINS(106);
367 DECLARE_MSM_GPIO_PINS(107);
368 DECLARE_MSM_GPIO_PINS(108);
369 DECLARE_MSM_GPIO_PINS(109);
370 DECLARE_MSM_GPIO_PINS(110);
371 DECLARE_MSM_GPIO_PINS(111);
372 DECLARE_MSM_GPIO_PINS(112);
373 DECLARE_MSM_GPIO_PINS(113);
374 DECLARE_MSM_GPIO_PINS(114);
375 DECLARE_MSM_GPIO_PINS(115);
376 DECLARE_MSM_GPIO_PINS(116);
377 DECLARE_MSM_GPIO_PINS(117);
378 DECLARE_MSM_GPIO_PINS(118);
379 DECLARE_MSM_GPIO_PINS(119);
380 DECLARE_MSM_GPIO_PINS(120);
381 DECLARE_MSM_GPIO_PINS(121);
382 DECLARE_MSM_GPIO_PINS(122);
383 DECLARE_MSM_GPIO_PINS(123);
384 DECLARE_MSM_GPIO_PINS(124);
385 DECLARE_MSM_GPIO_PINS(125);
386 DECLARE_MSM_GPIO_PINS(126);
387 DECLARE_MSM_GPIO_PINS(127);
388 DECLARE_MSM_GPIO_PINS(128);
389 DECLARE_MSM_GPIO_PINS(129);
390 DECLARE_MSM_GPIO_PINS(130);
391 DECLARE_MSM_GPIO_PINS(131);
392 DECLARE_MSM_GPIO_PINS(132);
393 
394 static const unsigned int ufs_reset_pins[] = { 133 };
395 static const unsigned int sdc1_rclk_pins[] = { 134 };
396 static const unsigned int sdc1_clk_pins[]  = { 135 };
397 static const unsigned int sdc1_cmd_pins[]  = { 136 };
398 static const unsigned int sdc1_data_pins[] = { 137 };
399 
400 enum qcs8300_functions {
401 	msm_mux_gpio,
402 	msm_mux_aoss_cti,
403 	msm_mux_atest_char,
404 	msm_mux_atest_usb2,
405 	msm_mux_audio_ref,
406 	msm_mux_cam_mclk,
407 	msm_mux_cci_async,
408 	msm_mux_cci_i2c_scl,
409 	msm_mux_cci_i2c_sda,
410 	msm_mux_cci_timer,
411 	msm_mux_cri_trng,
412 	msm_mux_dbg_out,
413 	msm_mux_ddr_bist,
414 	msm_mux_ddr_pxi0,
415 	msm_mux_ddr_pxi1,
416 	msm_mux_ddr_pxi2,
417 	msm_mux_ddr_pxi3,
418 	msm_mux_edp0_hot,
419 	msm_mux_edp0_lcd,
420 	msm_mux_edp1_lcd,
421 	msm_mux_egpio,
422 	msm_mux_emac0_mcg0,
423 	msm_mux_emac0_mcg1,
424 	msm_mux_emac0_mcg2,
425 	msm_mux_emac0_mcg3,
426 	msm_mux_emac0_mdc,
427 	msm_mux_emac0_mdio,
428 	msm_mux_emac0_ptp_aux,
429 	msm_mux_emac0_ptp_pps,
430 	msm_mux_gcc_gp1,
431 	msm_mux_gcc_gp2,
432 	msm_mux_gcc_gp3,
433 	msm_mux_gcc_gp4,
434 	msm_mux_gcc_gp5,
435 	msm_mux_hs0_mi2s,
436 	msm_mux_hs1_mi2s,
437 	msm_mux_hs2_mi2s,
438 	msm_mux_ibi_i3c,
439 	msm_mux_jitter_bist,
440 	msm_mux_mdp0_vsync0,
441 	msm_mux_mdp0_vsync1,
442 	msm_mux_mdp0_vsync3,
443 	msm_mux_mdp0_vsync6,
444 	msm_mux_mdp0_vsync7,
445 	msm_mux_mdp_vsync,
446 	msm_mux_mi2s1_data0,
447 	msm_mux_mi2s1_data1,
448 	msm_mux_mi2s1_sck,
449 	msm_mux_mi2s1_ws,
450 	msm_mux_mi2s2_data0,
451 	msm_mux_mi2s2_data1,
452 	msm_mux_mi2s2_sck,
453 	msm_mux_mi2s2_ws,
454 	msm_mux_mi2s_mclk0,
455 	msm_mux_mi2s_mclk1,
456 	msm_mux_pcie0_clkreq,
457 	msm_mux_pcie1_clkreq,
458 	msm_mux_phase_flag,
459 	msm_mux_pll_bist,
460 	msm_mux_pll_clk,
461 	msm_mux_prng_rosc0,
462 	msm_mux_prng_rosc1,
463 	msm_mux_prng_rosc2,
464 	msm_mux_prng_rosc3,
465 	msm_mux_qdss_cti,
466 	msm_mux_qdss_gpio,
467 	msm_mux_qup0_se0,
468 	msm_mux_qup0_se1,
469 	msm_mux_qup0_se2,
470 	msm_mux_qup0_se3,
471 	msm_mux_qup0_se4,
472 	msm_mux_qup0_se5,
473 	msm_mux_qup0_se6,
474 	msm_mux_qup0_se7,
475 	msm_mux_qup1_se0,
476 	msm_mux_qup1_se1,
477 	msm_mux_qup1_se2,
478 	msm_mux_qup1_se3,
479 	msm_mux_qup1_se4,
480 	msm_mux_qup1_se5,
481 	msm_mux_qup1_se6,
482 	msm_mux_qup1_se7,
483 	msm_mux_qup2_se0,
484 	msm_mux_sailss_emac0,
485 	msm_mux_sailss_ospi,
486 	msm_mux_sgmii_phy,
487 	msm_mux_tb_trig,
488 	msm_mux_tgu_ch0,
489 	msm_mux_tgu_ch1,
490 	msm_mux_tgu_ch2,
491 	msm_mux_tgu_ch3,
492 	msm_mux_tsense_pwm1,
493 	msm_mux_tsense_pwm2,
494 	msm_mux_tsense_pwm3,
495 	msm_mux_tsense_pwm4,
496 	msm_mux_usb2phy_ac,
497 	msm_mux_vsense_trigger,
498 	msm_mux__,
499 };
500 
501 static const char * const gpio_groups[] = {
502 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
503 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
504 	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
505 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
506 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
507 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
508 	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
509 	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
510 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
511 	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
512 	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
513 	"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
514 	"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
515 	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
516 	"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
517 	"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
518 	"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
519 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
520 	"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
521 	"gpio129", "gpio130", "gpio131", "gpio132",
522 };
523 
524 static const char *const aoss_cti_groups[] = {
525 	"gpio37", "gpio38", "gpio39", "gpio40",
526 };
527 
528 static const char * const atest_char_groups[] = {
529 	"gpio66", "gpio70", "gpio71", "gpio72", "gpio93",
530 };
531 
532 static const char * const atest_usb2_groups[] = {
533 	"gpio63", "gpio83", "gpio92", "gpio74", "gpio84", "gpio87", "gpio67",
534 	"gpio75", "gpio85", "gpio65", "gpio68", "gpio80", "gpio64", "gpio69",
535 	"gpio81",
536 };
537 
538 static const char * const audio_ref_groups[] = {
539 	"gpio105",
540 };
541 
542 static const char * const cam_mclk_groups[] = {
543 	"gpio67", "gpio68", "gpio69",
544 };
545 
546 static const char * const cci_async_groups[] = {
547 	"gpio63", "gpio64", "gpio65", "gpio29", "gpio30", "gpio31",
548 };
549 
550 static const char * const cci_i2c_scl_groups[] = {
551 	"gpio58", "gpio30", "gpio60", "gpio32", "gpio62", "gpio55",
552 };
553 
554 static const char * const cci_i2c_sda_groups[] = {
555 	"gpio57", "gpio29", "gpio59", "gpio31", "gpio61", "gpio54",
556 };
557 
558 static const char *const cci_timer_groups[] = {
559 	"gpio63", "gpio64", "gpio65", "gpio49", "gpio50", "gpio19",
560 	"gpio20", "gpio21", "gpio22", "gpio23",
561 };
562 
563 static const char *const cri_trng_groups[] = {
564 	"gpio92", "gpio90", "gpio91",
565 };
566 
567 static const char *const dbg_out_groups[] = {
568 	"gpio75",
569 };
570 
571 static const char * const ddr_bist_groups[] = {
572 	"gpio53", "gpio54", "gpio55", "gpio56",
573 };
574 
575 static const char *const ddr_pxi0_groups[] = {
576 	"gpio68", "gpio69",
577 };
578 
579 static const char *const ddr_pxi1_groups[] = {
580 	"gpio49", "gpio50",
581 };
582 
583 static const char *const ddr_pxi2_groups[] = {
584 	"gpio52", "gpio83",
585 };
586 
587 static const char *const ddr_pxi3_groups[] = {
588 	"gpio80", "gpio81",
589 };
590 
591 static const char *const edp0_hot_groups[] = {
592 	"gpio94",
593 };
594 
595 static const char *const edp0_lcd_groups[] = {
596 	"gpio48",
597 };
598 
599 static const char *const edp1_lcd_groups[] = {
600 	"gpio49",
601 };
602 
603 static const char *const egpio_groups[] = {
604 	"gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115",
605 	"gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
606 	"gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127",
607 	"gpio128", "gpio129", "gpio130", "gpio131", "gpio132",
608 };
609 
610 static const char *const emac0_mcg0_groups[] = {
611 	"gpio10",
612 };
613 
614 static const char *const emac0_mcg1_groups[] = {
615 	"gpio11",
616 };
617 
618 static const char *const emac0_mcg2_groups[] = {
619 	"gpio24",
620 };
621 
622 static const char *const emac0_mcg3_groups[] = {
623 	"gpio79",
624 };
625 
626 static const char *const emac0_mdc_groups[] = {
627 	"gpio5",
628 };
629 
630 static const char *const emac0_mdio_groups[] = {
631 	"gpio6",
632 };
633 
634 static const char * const emac0_ptp_aux_groups[] = {
635 	"gpio24", "gpio31", "gpio32", "gpio79",
636 };
637 
638 static const char * const emac0_ptp_pps_groups[] = {
639 	"gpio24", "gpio29", "gpio30", "gpio79",
640 };
641 
642 static const char *const gcc_gp1_groups[] = {
643 	"gpio35", "gpio84",
644 };
645 
646 static const char *const gcc_gp2_groups[] = {
647 	"gpio36", "gpio81",
648 };
649 
650 static const char *const gcc_gp3_groups[] = {
651 	"gpio69", "gpio82",
652 };
653 
654 static const char *const gcc_gp4_groups[] = {
655 	"gpio68", "gpio83",
656 };
657 
658 static const char *const gcc_gp5_groups[] = {
659 	"gpio76", "gpio77",
660 };
661 
662 static const char * const hs0_mi2s_groups[] = {
663 	"gpio106", "gpio107", "gpio108", "gpio109",
664 };
665 
666 static const char * const hs1_mi2s_groups[] = {
667 	"gpio45", "gpio46", "gpio47", "gpio48",
668 };
669 
670 static const char * const hs2_mi2s_groups[] = {
671 	"gpio49", "gpio50", "gpio51", "gpio52",
672 };
673 
674 static const char * const ibi_i3c_groups[] = {
675 	"gpio17", "gpio18", "gpio19", "gpio20", "gpio37", "gpio38",
676 	"gpio39", "gpio40",
677 };
678 
679 static const char *const jitter_bist_groups[] = {
680 	"gpio97",
681 };
682 
683 static const char *const mdp0_vsync0_groups[] = {
684 	"gpio89",
685 };
686 
687 static const char *const mdp0_vsync1_groups[] = {
688 	"gpio90",
689 };
690 
691 static const char *const mdp0_vsync3_groups[] = {
692 	"gpio91",
693 };
694 
695 static const char *const mdp0_vsync6_groups[] = {
696 	"gpio80",
697 };
698 
699 static const char *const mdp0_vsync7_groups[] = {
700 	"gpio81",
701 };
702 
703 static const char *const mdp_vsync_groups[] = {
704 	"gpio42", "gpio52", "gpio32",
705 };
706 
707 static const char *const mi2s1_data0_groups[] = {
708 	"gpio100",
709 };
710 
711 static const char *const mi2s1_data1_groups[] = {
712 	"gpio101",
713 };
714 
715 static const char *const mi2s1_sck_groups[] = {
716 	"gpio98",
717 };
718 
719 static const char *const mi2s1_ws_groups[] = {
720 	"gpio99",
721 };
722 
723 static const char *const mi2s2_data0_groups[] = {
724 	"gpio104",
725 };
726 
727 static const char *const mi2s2_data1_groups[] = {
728 	"gpio105",
729 };
730 
731 static const char *const mi2s2_sck_groups[] = {
732 	"gpio102",
733 };
734 
735 static const char *const mi2s2_ws_groups[] = {
736 	"gpio103",
737 };
738 
739 static const char *const mi2s_mclk0_groups[] = {
740 	"gpio97",
741 };
742 
743 static const char *const mi2s_mclk1_groups[] = {
744 	"gpio109",
745 };
746 
747 static const char *const pcie0_clkreq_groups[] = {
748 	"gpio1",
749 };
750 
751 static const char *const pcie1_clkreq_groups[] = {
752 	"gpio22",
753 };
754 
755 static const char *const phase_flag_groups[] = {
756 	"gpio66", "gpio56", "gpio118", "gpio117", "gpio116",
757 	"gpio3", "gpio114", "gpio113", "gpio112", "gpio111",
758 	"gpio110", "gpio28", "gpio55", "gpio108", "gpio107",
759 	"gpio106", "gpio105", "gpio104", "gpio103", "gpio102",
760 	"gpio101", "gpio100", "gpio99", "gpio125", "gpio98",
761 	"gpio54", "gpio25", "gpio26", "gpio122", "gpio121",
762 	"gpio120", "gpio9",
763 };
764 
765 static const char *const pll_bist_groups[] = {
766 	"gpio107",
767 };
768 
769 static const char *const pll_clk_groups[] = {
770 	"gpio74",
771 };
772 
773 static const char *const prng_rosc0_groups[] = {
774 	"gpio57",
775 };
776 
777 static const char *const prng_rosc1_groups[] = {
778 	"gpio58",
779 };
780 
781 static const char *const prng_rosc2_groups[] = {
782 	"gpio59",
783 };
784 
785 static const char *const prng_rosc3_groups[] = {
786 	"gpio60",
787 };
788 
789 static const char *const qdss_cti_groups[] = {
790 	"gpio4", "gpio5", "gpio23", "gpio24", "gpio49", "gpio50",
791 	"gpio51", "gpio52",
792 };
793 
794 static const char *const qdss_gpio_groups[] = {
795 	"gpio57", "gpio58", "gpio97", "gpio106",
796 	"gpio59", "gpio107", "gpio60", "gpio108",
797 	"gpio36", "gpio100", "gpio61", "gpio101",
798 	"gpio62", "gpio102", "gpio33", "gpio103",
799 	"gpio34", "gpio104", "gpio75", "gpio105",
800 	"gpio72", "gpio109", "gpio71", "gpio110",
801 	"gpio70", "gpio111", "gpio63", "gpio112",
802 	"gpio64", "gpio113", "gpio65", "gpio114",
803 	"gpio73", "gpio98", "gpio74", "gpio99",
804 };
805 
806 static const char *const qup0_se0_groups[] = {
807 	"gpio17", "gpio18", "gpio19", "gpio20",
808 };
809 
810 static const char *const qup0_se1_groups[] = {
811 	"gpio19", "gpio20", "gpio17", "gpio18",
812 };
813 
814 static const char *const qup0_se2_groups[] = {
815 	"gpio33", "gpio34", "gpio35", "gpio36",
816 };
817 
818 static const char *const qup0_se3_groups[] = {
819 	"gpio25", "gpio26", "gpio27", "gpio28",
820 };
821 
822 static const char *const qup0_se4_groups[] = {
823 	"gpio29", "gpio30", "gpio31", "gpio32",
824 };
825 
826 static const char *const qup0_se5_groups[] = {
827 	"gpio21", "gpio22", "gpio23", "gpio24",
828 };
829 
830 static const char *const qup0_se6_groups[] = {
831 	"gpio80", "gpio81", "gpio82", "gpio83",
832 };
833 
834 static const char *const qup0_se7_groups[] = {
835 	"gpio43", "gpio44", "gpio43", "gpio44",
836 };
837 
838 static const char *const qup1_se0_groups[] = {
839 	"gpio37", "gpio38", "gpio39", "gpio40",
840 };
841 
842 static const char *const qup1_se1_groups[] = {
843 	"gpio39", "gpio40", "gpio37", "gpio38",
844 };
845 
846 static const char *const qup1_se2_groups[] = {
847 	"gpio84", "gpio85", "gpio86", "gpio87", "gpio88",
848 };
849 
850 static const char *const qup1_se3_groups[] = {
851 	"gpio41", "gpio42", "gpio41", "gpio42",
852 };
853 
854 static const char *const qup1_se4_groups[] = {
855 	"gpio45", "gpio46", "gpio47", "gpio48",
856 };
857 
858 static const char *const qup1_se5_groups[] = {
859 	"gpio49", "gpio50", "gpio51", "gpio52",
860 };
861 
862 static const char *const qup1_se6_groups[] = {
863 	"gpio89", "gpio90", "gpio91", "gpio92",
864 };
865 
866 static const char *const qup1_se7_groups[] = {
867 	"gpio91", "gpio92", "gpio89", "gpio90",
868 };
869 
870 static const char *const qup2_se0_groups[] = {
871 	"gpio10", "gpio11", "gpio12", "gpio13",
872 	"gpio14", "gpio15", "gpio16",
873 };
874 
875 static const char *const sailss_emac0_groups[] = {
876 	"gpio15", "gpio16",
877 };
878 
879 static const char *const sailss_ospi_groups[] = {
880 	"gpio15", "gpio16",
881 };
882 
883 static const char *const sgmii_phy_groups[] = {
884 	"gpio4",
885 };
886 
887 static const char *const tb_trig_groups[] = {
888 	"gpio14",
889 };
890 
891 static const char *const tgu_ch0_groups[] = {
892 	"gpio43",
893 };
894 
895 static const char *const tgu_ch1_groups[] = {
896 	"gpio44",
897 };
898 
899 static const char *const tgu_ch2_groups[] = {
900 	"gpio29",
901 };
902 
903 static const char *const tgu_ch3_groups[] = {
904 	"gpio30",
905 };
906 
907 static const char *const tsense_pwm1_groups[] = {
908 	"gpio79",
909 };
910 
911 static const char *const tsense_pwm2_groups[] = {
912 	"gpio78",
913 };
914 
915 static const char *const tsense_pwm3_groups[] = {
916 	"gpio77",
917 };
918 
919 static const char *const tsense_pwm4_groups[] = {
920 	"gpio76",
921 };
922 
923 static const char *const usb2phy_ac_groups[] = {
924 	"gpio7", "gpio8",
925 };
926 
927 static const char *const vsense_trigger_groups[] = {
928 	"gpio67",
929 };
930 
931 static const struct pinfunction qcs8300_functions[] = {
932 	MSM_PIN_FUNCTION(gpio),
933 	MSM_PIN_FUNCTION(aoss_cti),
934 	MSM_PIN_FUNCTION(atest_char),
935 	MSM_PIN_FUNCTION(atest_usb2),
936 	MSM_PIN_FUNCTION(audio_ref),
937 	MSM_PIN_FUNCTION(cam_mclk),
938 	MSM_PIN_FUNCTION(cci_async),
939 	MSM_PIN_FUNCTION(cci_i2c_scl),
940 	MSM_PIN_FUNCTION(cci_i2c_sda),
941 	MSM_PIN_FUNCTION(cci_timer),
942 	MSM_PIN_FUNCTION(cri_trng),
943 	MSM_PIN_FUNCTION(dbg_out),
944 	MSM_PIN_FUNCTION(ddr_bist),
945 	MSM_PIN_FUNCTION(ddr_pxi0),
946 	MSM_PIN_FUNCTION(ddr_pxi1),
947 	MSM_PIN_FUNCTION(ddr_pxi2),
948 	MSM_PIN_FUNCTION(ddr_pxi3),
949 	MSM_PIN_FUNCTION(edp0_hot),
950 	MSM_PIN_FUNCTION(edp0_lcd),
951 	MSM_PIN_FUNCTION(edp1_lcd),
952 	MSM_PIN_FUNCTION(egpio),
953 	MSM_PIN_FUNCTION(emac0_mcg0),
954 	MSM_PIN_FUNCTION(emac0_mcg1),
955 	MSM_PIN_FUNCTION(emac0_mcg2),
956 	MSM_PIN_FUNCTION(emac0_mcg3),
957 	MSM_PIN_FUNCTION(emac0_mdc),
958 	MSM_PIN_FUNCTION(emac0_mdio),
959 	MSM_PIN_FUNCTION(emac0_ptp_aux),
960 	MSM_PIN_FUNCTION(emac0_ptp_pps),
961 	MSM_PIN_FUNCTION(gcc_gp1),
962 	MSM_PIN_FUNCTION(gcc_gp2),
963 	MSM_PIN_FUNCTION(gcc_gp3),
964 	MSM_PIN_FUNCTION(gcc_gp4),
965 	MSM_PIN_FUNCTION(gcc_gp5),
966 	MSM_PIN_FUNCTION(hs0_mi2s),
967 	MSM_PIN_FUNCTION(hs1_mi2s),
968 	MSM_PIN_FUNCTION(hs2_mi2s),
969 	MSM_PIN_FUNCTION(ibi_i3c),
970 	MSM_PIN_FUNCTION(jitter_bist),
971 	MSM_PIN_FUNCTION(mdp0_vsync0),
972 	MSM_PIN_FUNCTION(mdp0_vsync1),
973 	MSM_PIN_FUNCTION(mdp0_vsync3),
974 	MSM_PIN_FUNCTION(mdp0_vsync6),
975 	MSM_PIN_FUNCTION(mdp0_vsync7),
976 	MSM_PIN_FUNCTION(mdp_vsync),
977 	MSM_PIN_FUNCTION(mi2s1_data0),
978 	MSM_PIN_FUNCTION(mi2s1_data1),
979 	MSM_PIN_FUNCTION(mi2s1_sck),
980 	MSM_PIN_FUNCTION(mi2s1_ws),
981 	MSM_PIN_FUNCTION(mi2s2_data0),
982 	MSM_PIN_FUNCTION(mi2s2_data1),
983 	MSM_PIN_FUNCTION(mi2s2_sck),
984 	MSM_PIN_FUNCTION(mi2s2_ws),
985 	MSM_PIN_FUNCTION(mi2s_mclk0),
986 	MSM_PIN_FUNCTION(mi2s_mclk1),
987 	MSM_PIN_FUNCTION(pcie0_clkreq),
988 	MSM_PIN_FUNCTION(pcie1_clkreq),
989 	MSM_PIN_FUNCTION(phase_flag),
990 	MSM_PIN_FUNCTION(pll_bist),
991 	MSM_PIN_FUNCTION(pll_clk),
992 	MSM_PIN_FUNCTION(prng_rosc0),
993 	MSM_PIN_FUNCTION(prng_rosc1),
994 	MSM_PIN_FUNCTION(prng_rosc2),
995 	MSM_PIN_FUNCTION(prng_rosc3),
996 	MSM_PIN_FUNCTION(qdss_cti),
997 	MSM_PIN_FUNCTION(qdss_gpio),
998 	MSM_PIN_FUNCTION(qup0_se0),
999 	MSM_PIN_FUNCTION(qup0_se1),
1000 	MSM_PIN_FUNCTION(qup0_se2),
1001 	MSM_PIN_FUNCTION(qup0_se3),
1002 	MSM_PIN_FUNCTION(qup0_se4),
1003 	MSM_PIN_FUNCTION(qup0_se5),
1004 	MSM_PIN_FUNCTION(qup0_se6),
1005 	MSM_PIN_FUNCTION(qup0_se7),
1006 	MSM_PIN_FUNCTION(qup1_se0),
1007 	MSM_PIN_FUNCTION(qup1_se1),
1008 	MSM_PIN_FUNCTION(qup1_se2),
1009 	MSM_PIN_FUNCTION(qup1_se3),
1010 	MSM_PIN_FUNCTION(qup1_se4),
1011 	MSM_PIN_FUNCTION(qup1_se5),
1012 	MSM_PIN_FUNCTION(qup1_se6),
1013 	MSM_PIN_FUNCTION(qup1_se7),
1014 	MSM_PIN_FUNCTION(qup2_se0),
1015 	MSM_PIN_FUNCTION(sailss_emac0),
1016 	MSM_PIN_FUNCTION(sailss_ospi),
1017 	MSM_PIN_FUNCTION(sgmii_phy),
1018 	MSM_PIN_FUNCTION(tb_trig),
1019 	MSM_PIN_FUNCTION(tgu_ch0),
1020 	MSM_PIN_FUNCTION(tgu_ch1),
1021 	MSM_PIN_FUNCTION(tgu_ch2),
1022 	MSM_PIN_FUNCTION(tgu_ch3),
1023 	MSM_PIN_FUNCTION(tsense_pwm1),
1024 	MSM_PIN_FUNCTION(tsense_pwm2),
1025 	MSM_PIN_FUNCTION(tsense_pwm3),
1026 	MSM_PIN_FUNCTION(tsense_pwm4),
1027 	MSM_PIN_FUNCTION(usb2phy_ac),
1028 	MSM_PIN_FUNCTION(vsense_trigger),
1029 };
1030 
1031 /*
1032  * Every pin is maintained as a single group, and missing or non-existing pin
1033  * would be maintained as dummy group to synchronize pin group index with
1034  * pin descriptor registered with pinctrl core.
1035  * Clients would not be able to request these dummy pin groups.
1036  */
1037 static const struct msm_pingroup qcs8300_groups[] = {
1038 	[0] = PINGROUP(0, _, _, _, _, _, _, _, _, _, _, _),
1039 	[1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _, _, _),
1040 	[2] = PINGROUP(2, _, _, _, _, _, _, _, _, _, _, _),
1041 	[3] = PINGROUP(3, phase_flag, _, _, _, _, _, _, _, _, _, _),
1042 	[4] = PINGROUP(4, sgmii_phy, qdss_cti, _, _, _, _, _, _, _, _, _),
1043 	[5] = PINGROUP(5, emac0_mdc, qdss_cti, _, _, _, _, _, _, _, _, _),
1044 	[6] = PINGROUP(6, emac0_mdio, _, _, _, _, _, _, _, _, _, _),
1045 	[7] = PINGROUP(7, usb2phy_ac, _, _, _, _, _, _, _, _, _, _),
1046 	[8] = PINGROUP(8, usb2phy_ac, _, _, _, _, _, _, _, _, _, _),
1047 	[9] = PINGROUP(9, phase_flag, _, _, _, _, _, _, _, _, _, _),
1048 	[10] = PINGROUP(10, qup2_se0, emac0_mcg0, _, _, _, _, _, _, _, _, _),
1049 	[11] = PINGROUP(11, qup2_se0, emac0_mcg1, _, _, _, _, _, _, _, _, _),
1050 	[12] = PINGROUP(12, qup2_se0, _, _, _, _, _, _, _, _, _, _),
1051 	[13] = PINGROUP(13, qup2_se0, _, _, _, _, _, _, _, _, _, _),
1052 	[14] = PINGROUP(14, qup2_se0, tb_trig, _, _, _, _, _, _, _, _, _),
1053 	[15] = PINGROUP(15, qup2_se0, _, sailss_ospi, sailss_emac0, _, _, _, _, _, _, _),
1054 	[16] = PINGROUP(16, qup2_se0, _, _, sailss_ospi, sailss_emac0, _, _, _, _, _, _),
1055 	[17] = PINGROUP(17, qup0_se0, qup0_se1, ibi_i3c, _, _, _, _, _, _, _, _),
1056 	[18] = PINGROUP(18, qup0_se0, qup0_se1, ibi_i3c, _, _, _, _, _, _, _, _),
1057 	[19] = PINGROUP(19, qup0_se1, qup0_se0, cci_timer, ibi_i3c, _, _, _, _, _, _, _),
1058 	[20] = PINGROUP(20, qup0_se1, qup0_se0, cci_timer, ibi_i3c, _, _, _, _, _, _, _),
1059 	[21] = PINGROUP(21, qup0_se5, cci_timer, _, _, _, _, _, _, _, _, _),
1060 	[22] = PINGROUP(22, pcie1_clkreq, qup0_se5, cci_timer, _, _, _, _, _, _, _, _),
1061 	[23] = PINGROUP(23, qup0_se5, cci_timer, qdss_cti, _, _, _, _, _, _, _, _),
1062 	[24] = PINGROUP(24, qup0_se5, emac0_ptp_aux, emac0_ptp_pps, qdss_cti,
1063 			emac0_mcg2, _, _, _, _, _, _),
1064 	[25] = PINGROUP(25, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _),
1065 	[26] = PINGROUP(26, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _),
1066 	[27] = PINGROUP(27, qup0_se3, _, _, _, _, _, _, _, _, _, _),
1067 	[28] = PINGROUP(28, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _),
1068 	[29] = PINGROUP(29, qup0_se4, cci_i2c_sda, cci_async, emac0_ptp_pps,
1069 			tgu_ch2, _, _, _, _, _, _),
1070 	[30] = PINGROUP(30, qup0_se4, cci_i2c_scl, cci_async, emac0_ptp_pps,
1071 			tgu_ch3, _, _, _, _, _, _),
1072 	[31] = PINGROUP(31, qup0_se4, cci_i2c_sda, cci_async, emac0_ptp_aux, _, _, _, _, _, _, _),
1073 	[32] = PINGROUP(32, qup0_se4, cci_i2c_scl, emac0_ptp_aux, mdp_vsync, _, _, _, _, _, _, _),
1074 	[33] = PINGROUP(33, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _),
1075 	[34] = PINGROUP(34, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _),
1076 	[35] = PINGROUP(35, qup0_se2, gcc_gp1, _, _, _, _, _, _, _, _, _),
1077 	[36] = PINGROUP(36, qup0_se2, gcc_gp2, qdss_gpio, _, _, _, _, _, _, _, _),
1078 	[37] = PINGROUP(37, qup1_se0, ibi_i3c, qup1_se1, aoss_cti, _, _, _, _, _, _, _),
1079 	[38] = PINGROUP(38, qup1_se0, ibi_i3c, qup1_se1, aoss_cti, _, _, _, _, _, _, _),
1080 	[39] = PINGROUP(39, qup1_se1, ibi_i3c, qup1_se0, aoss_cti, _, _, _, _, _, _, _),
1081 	[40] = PINGROUP(40, qup1_se1, ibi_i3c, qup1_se0, aoss_cti, _, _, _, _, _, _, _),
1082 	[41] = PINGROUP(41, qup1_se3, _, _, _, _, _, _, _, _, _, _),
1083 	[42] = PINGROUP(42, qup1_se3, _, mdp_vsync, _, _, _, _, _, _, _, _),
1084 	[43] = PINGROUP(43, qup0_se7, _, tgu_ch0, _, _, _, _, _, _, _, _),
1085 	[44] = PINGROUP(44, qup0_se7, _, tgu_ch1, _, _, _, _, _, _, _, _),
1086 	[45] = PINGROUP(45, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _),
1087 	[46] = PINGROUP(46, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _),
1088 	[47] = PINGROUP(47, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _),
1089 	[48] = PINGROUP(48, qup1_se4, hs1_mi2s, edp0_lcd, _, _, _, _, _, _, _, _),
1090 	[49] = PINGROUP(49, qup1_se5, hs2_mi2s, cci_timer, qdss_cti, edp1_lcd,
1091 			ddr_pxi1, _, _, _, _, _),
1092 	[50] = PINGROUP(50, qup1_se5, hs2_mi2s, cci_timer, qdss_cti, _, ddr_pxi1, _, _, _, _, _),
1093 	[51] = PINGROUP(51, qup1_se5, hs2_mi2s, qdss_cti, _, _, _, _, _, _, _, _),
1094 	[52] = PINGROUP(52, qup1_se5, hs2_mi2s, qdss_cti, mdp_vsync, ddr_pxi2, _, _, _, _, _, _),
1095 	[53] = PINGROUP(53, ddr_bist, _, _, _, _, _, _, _, _, _, _),
1096 	[54] = PINGROUP(54, cci_i2c_sda, phase_flag, ddr_bist, _, _, _, _, _, _, _, _),
1097 	[55] = PINGROUP(55, cci_i2c_scl, phase_flag, ddr_bist, _, _, _, _, _, _, _, _),
1098 	[56] = PINGROUP(56, phase_flag, ddr_bist, _, _, _, _, _, _, _, _, _),
1099 	[57] = PINGROUP(57, cci_i2c_sda, prng_rosc0, qdss_gpio, _, _, _, _, _, _, _, _),
1100 	[58] = PINGROUP(58, cci_i2c_scl, prng_rosc1, qdss_gpio, _, _, _, _, _, _, _, _),
1101 	[59] = PINGROUP(59, cci_i2c_sda, prng_rosc2, qdss_gpio, _, _, _, _, _, _, _, _),
1102 	[60] = PINGROUP(60, cci_i2c_scl, prng_rosc3, qdss_gpio, _, _, _, _, _, _, _, _),
1103 	[61] = PINGROUP(61, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _, _, _),
1104 	[62] = PINGROUP(62, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _, _, _),
1105 	[63] = PINGROUP(63, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _),
1106 	[64] = PINGROUP(64, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _),
1107 	[65] = PINGROUP(65, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _),
1108 	[66] = PINGROUP(66, phase_flag, _, atest_char, _, _, _, _, _, _, _, _),
1109 	[67] = PINGROUP(67, cam_mclk, vsense_trigger, atest_usb2, _, _, _, _, _, _, _, _),
1110 	[68] = PINGROUP(68, cam_mclk, gcc_gp4, atest_usb2, ddr_pxi0, _, _, _, _, _, _, _),
1111 	[69] = PINGROUP(69, cam_mclk, gcc_gp3, atest_usb2, ddr_pxi0, _, _, _, _, _, _, _),
1112 	[70] = PINGROUP(70, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _),
1113 	[71] = PINGROUP(71, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _),
1114 	[72] = PINGROUP(72, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _),
1115 	[73] = PINGROUP(73, _, qdss_gpio, _, _, _, _, _, _, _, _, _),
1116 	[74] = PINGROUP(74, pll_clk, qdss_gpio, atest_usb2, _, _, _, _, _, _, _, _),
1117 	[75] = PINGROUP(75, _, dbg_out, qdss_gpio, atest_usb2, _, _, _, _, _, _, _),
1118 	[76] = PINGROUP(76, gcc_gp5, tsense_pwm4, _, _, _, _, _, _, _, _, _),
1119 	[77] = PINGROUP(77, gcc_gp5, tsense_pwm3, _, _, _, _, _, _, _, _, _),
1120 	[78] = PINGROUP(78, tsense_pwm2, _, _, _, _, _, _, _, _, _, _),
1121 	[79] = PINGROUP(79, emac0_ptp_aux, emac0_ptp_pps, emac0_mcg3, _,
1122 			tsense_pwm1, _, _, _, _, _, _),
1123 	[80] = PINGROUP(80, qup0_se6, mdp0_vsync6, _, atest_usb2, ddr_pxi3, _, _, _, _, _, _),
1124 	[81] = PINGROUP(81, qup0_se6, mdp0_vsync7, gcc_gp2, _, atest_usb2, ddr_pxi3, _, _, _, _, _),
1125 	[82] = PINGROUP(82, qup0_se6, gcc_gp3, _, _, _, _, _, _, _, _, _),
1126 	[83] = PINGROUP(83, qup0_se6, gcc_gp4, _, atest_usb2, ddr_pxi2, _, _, _, _, _, _),
1127 	[84] = PINGROUP(84, qup1_se2, gcc_gp1, _, atest_usb2, _, _, _, _, _, _, _),
1128 	[85] = PINGROUP(85, qup1_se2, _, atest_usb2, _, _, _, _, _, _, _, _),
1129 	[86] = PINGROUP(86, qup1_se2, _, _, _, _, _, _, _, _, _, _),
1130 	[87] = PINGROUP(87, qup1_se2, _, atest_usb2, _, _, _, _, _, _, _, _),
1131 	[88] = PINGROUP(88, qup1_se2, _, _, _, _, _, _, _, _, _, _),
1132 	[89] = PINGROUP(89, qup1_se6, qup1_se7, mdp0_vsync0, _, _, _, _, _, _, _, _),
1133 	[90] = PINGROUP(90, qup1_se6, qup1_se7, mdp0_vsync1, cri_trng, _, _, _, _, _, _, _),
1134 	[91] = PINGROUP(91, qup1_se7, qup1_se6, mdp0_vsync3, cri_trng, _, _, _, _, _, _, _),
1135 	[92] = PINGROUP(92, qup1_se7, qup1_se6, cri_trng, _, atest_usb2, _, _, _, _, _, _),
1136 	[93] = PINGROUP(93, atest_char, _, _, _, _, _, _, _, _, _, _),
1137 	[94] = PINGROUP(94, edp0_hot, _, _, _, _, _, _, _, _, _, _),
1138 	[95] = PINGROUP(95, _, _, _, _, _, _, _, _, _, _, _),
1139 	[96] = PINGROUP(96, _, _, _, _, _, _, _, _, _, _, _),
1140 	[97] = PINGROUP(97, mi2s_mclk0, jitter_bist, qdss_gpio, _, _, _, _, _, _, _, _),
1141 	[98] = PINGROUP(98, mi2s1_sck, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
1142 	[99] = PINGROUP(99, mi2s1_ws, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
1143 	[100] = PINGROUP(100, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
1144 	[101] = PINGROUP(101, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
1145 	[102] = PINGROUP(102, mi2s2_sck, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
1146 	[103] = PINGROUP(103, mi2s2_ws, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
1147 	[104] = PINGROUP(104, mi2s2_data0, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
1148 	[105] = PINGROUP(105, mi2s2_data1, audio_ref, phase_flag, _, qdss_gpio, _, _, _, _, _, _),
1149 	[106] = PINGROUP(106, hs0_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
1150 	[107] = PINGROUP(107, hs0_mi2s, pll_bist, phase_flag, _, qdss_gpio, _, _, _, _, _, _),
1151 	[108] = PINGROUP(108, hs0_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
1152 	[109] = PINGROUP(109, hs0_mi2s, mi2s_mclk1, qdss_gpio, _, _, _, _, _, _, _, _),
1153 	[110] = PINGROUP(110, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
1154 	[111] = PINGROUP(111, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
1155 	[112] = PINGROUP(112, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
1156 	[113] = PINGROUP(113, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
1157 	[114] = PINGROUP(114, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
1158 	[115] = PINGROUP(115, _, _, _, _, _, _, _, _, _, _, egpio),
1159 	[116] = PINGROUP(116, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1160 	[117] = PINGROUP(117, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1161 	[118] = PINGROUP(118, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1162 	[119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, egpio),
1163 	[120] = PINGROUP(120, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1164 	[121] = PINGROUP(121, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1165 	[122] = PINGROUP(122, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1166 	[123] = PINGROUP(123, _, _, _, _, _, _, _, _, _, _, egpio),
1167 	[124] = PINGROUP(124, _, _, _, _, _, _, _, _, _, _, egpio),
1168 	[125] = PINGROUP(125, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1169 	[126] = PINGROUP(126, _, _, _, _, _, _, _, _, _, _, egpio),
1170 	[127] = PINGROUP(127, _, _, _, _, _, _, _, _, _, _, egpio),
1171 	[128] = PINGROUP(128, _, _, _, _, _, _, _, _, _, _, egpio),
1172 	[129] = PINGROUP(129, _, _, _, _, _, _, _, _, _, _, egpio),
1173 	[130] = PINGROUP(130, _, _, _, _, _, _, _, _, _, _, egpio),
1174 	[131] = PINGROUP(131, _, _, _, _, _, _, _, _, _, _, egpio),
1175 	[132] = PINGROUP(132, _, _, _, _, _, _, _, _, _, _, egpio),
1176 	[133] = UFS_RESET(ufs_reset, 0x92000),
1177 	[134] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x89000, 15, 0),
1178 	[135] = SDC_QDSD_PINGROUP(sdc1_clk, 0x89000, 13, 6),
1179 	[136] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x89000, 11, 3),
1180 	[137] = SDC_QDSD_PINGROUP(sdc1_data, 0x89000, 9, 0),
1181 };
1182 
1183 static const struct msm_gpio_wakeirq_map qcs8300_pdc_map[] = {
1184 	{ 0, 169 },   { 1, 174 },   { 2, 221 },   { 3, 176 },   { 4, 171 },
1185 	{ 9, 198 },   { 10, 187 },  { 11, 188 },  { 13, 211 },  { 16, 203 },
1186 	{ 17, 213 },  { 18, 209 },  { 19, 201 },  { 20, 230 },  { 21, 231 },
1187 	{ 22, 175 },  { 23, 170 },  { 24, 232 },  { 28, 235 },  { 29, 216 },
1188 	{ 31, 208 },  { 32, 200 },  { 36, 212 },  { 37, 177 },  { 38, 178 },
1189 	{ 39, 184 },  { 40, 185 },  { 42, 186 },  { 44, 194 },  { 45, 173 },
1190 	{ 48, 195 },  { 51, 215 },  { 52, 197 },  { 53, 192 },  { 56, 193 },
1191 	{ 66, 238 },  { 67, 172 },  { 68, 182 },  { 69, 179 },  { 70, 181 },
1192 	{ 71, 202 },  { 72, 183 },  { 73, 189 },  { 74, 196 },  { 75, 190 },
1193 	{ 76, 191 },  { 77, 204 },  { 78, 206 },  { 79, 207 },  { 83, 214 },
1194 	{ 84, 205 },  { 87, 237 },  { 89, 225 },  { 90, 217 },  { 91, 218 },
1195 	{ 92, 226 },  { 93, 227 },  { 94, 228 },  { 95, 236 },  { 97, 199 },
1196 	{ 98, 229 },  { 99, 180 },  { 100, 220 }, { 101, 239 }, { 102, 219 },
1197 	{ 103, 233 }, { 104, 234 }, { 105, 223 }, { 129, 210 }, { 130, 222 },
1198 };
1199 
1200 static const struct msm_pinctrl_soc_data qcs8300_pinctrl = {
1201 	.pins = qcs8300_pins,
1202 	.npins = ARRAY_SIZE(qcs8300_pins),
1203 	.functions = qcs8300_functions,
1204 	.nfunctions = ARRAY_SIZE(qcs8300_functions),
1205 	.groups = qcs8300_groups,
1206 	.ngroups = ARRAY_SIZE(qcs8300_groups),
1207 	.ngpios = 133,
1208 	.wakeirq_map = qcs8300_pdc_map,
1209 	.nwakeirq_map = ARRAY_SIZE(qcs8300_pdc_map),
1210 	.egpio_func = 11,
1211 };
1212 
1213 static int qcs8300_pinctrl_probe(struct platform_device *pdev)
1214 {
1215 	return msm_pinctrl_probe(pdev, &qcs8300_pinctrl);
1216 }
1217 
1218 static const struct of_device_id qcs8300_pinctrl_of_match[] = {
1219 	{ .compatible = "qcom,qcs8300-tlmm", },
1220 	{ },
1221 };
1222 MODULE_DEVICE_TABLE(of, qcs8300_pinctrl_of_match);
1223 
1224 static struct platform_driver qcs8300_pinctrl_driver = {
1225 	.driver = {
1226 		.name = "qcs8300-tlmm",
1227 		.of_match_table = qcs8300_pinctrl_of_match,
1228 	},
1229 	.probe = qcs8300_pinctrl_probe,
1230 	.remove = msm_pinctrl_remove,
1231 };
1232 
1233 static int __init qcs8300_pinctrl_init(void)
1234 {
1235 	return platform_driver_register(&qcs8300_pinctrl_driver);
1236 }
1237 arch_initcall(qcs8300_pinctrl_init);
1238 
1239 static void __exit qcs8300_pinctrl_exit(void)
1240 {
1241 	platform_driver_unregister(&qcs8300_pinctrl_driver);
1242 }
1243 module_exit(qcs8300_pinctrl_exit);
1244 
1245 MODULE_DESCRIPTION("QTI QCS8300 pinctrl driver");
1246 MODULE_LICENSE("GPL");
1247