1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/platform_device.h> 9 #include <linux/pinctrl/pinctrl.h> 10 11 #include "pinctrl-msm.h" 12 13 #define FUNCTION(fname) \ 14 [msm_mux_##fname] = { \ 15 .name = #fname, \ 16 .groups = fname##_groups, \ 17 .ngroups = ARRAY_SIZE(fname##_groups), \ 18 } 19 20 #define REG_SIZE 0x1000 21 22 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 23 { \ 24 .name = "gpio" #id, \ 25 .pins = gpio##id##_pins, \ 26 .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ 27 .funcs = (int[]){ \ 28 msm_mux_gpio, /* gpio mode */ \ 29 msm_mux_##f1, \ 30 msm_mux_##f2, \ 31 msm_mux_##f3, \ 32 msm_mux_##f4, \ 33 msm_mux_##f5, \ 34 msm_mux_##f6, \ 35 msm_mux_##f7, \ 36 msm_mux_##f8, \ 37 msm_mux_##f9 \ 38 }, \ 39 .nfuncs = 10, \ 40 .ctl_reg = REG_SIZE * id, \ 41 .io_reg = 0x4 + REG_SIZE * id, \ 42 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 43 .intr_status_reg = 0xc + REG_SIZE * id, \ 44 .intr_target_reg = 0x8 + REG_SIZE * id, \ 45 .mux_bit = 2, \ 46 .pull_bit = 0, \ 47 .drv_bit = 6, \ 48 .oe_bit = 9, \ 49 .in_bit = 0, \ 50 .out_bit = 1, \ 51 .intr_enable_bit = 0, \ 52 .intr_status_bit = 0, \ 53 .intr_target_bit = 5, \ 54 .intr_target_kpss_val = 3, \ 55 .intr_raw_status_bit = 4, \ 56 .intr_polarity_bit = 1, \ 57 .intr_detection_bit = 2, \ 58 .intr_detection_width = 2, \ 59 } 60 61 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 62 { \ 63 .name = #pg_name, \ 64 .pins = pg_name##_pins, \ 65 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ 66 .ctl_reg = ctl, \ 67 .io_reg = 0, \ 68 .intr_cfg_reg = 0, \ 69 .intr_status_reg = 0, \ 70 .intr_target_reg = 0, \ 71 .mux_bit = -1, \ 72 .pull_bit = pull, \ 73 .drv_bit = drv, \ 74 .oe_bit = -1, \ 75 .in_bit = -1, \ 76 .out_bit = -1, \ 77 .intr_enable_bit = -1, \ 78 .intr_status_bit = -1, \ 79 .intr_target_bit = -1, \ 80 .intr_raw_status_bit = -1, \ 81 .intr_polarity_bit = -1, \ 82 .intr_detection_bit = -1, \ 83 .intr_detection_width = -1, \ 84 } 85 86 #define UFS_RESET(pg_name, offset) \ 87 { \ 88 .name = #pg_name, \ 89 .pins = pg_name##_pins, \ 90 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ 91 .ctl_reg = offset, \ 92 .io_reg = offset + 0x4, \ 93 .intr_cfg_reg = 0, \ 94 .intr_status_reg = 0, \ 95 .intr_target_reg = 0, \ 96 .mux_bit = -1, \ 97 .pull_bit = 3, \ 98 .drv_bit = 0, \ 99 .oe_bit = -1, \ 100 .in_bit = -1, \ 101 .out_bit = 0, \ 102 .intr_enable_bit = -1, \ 103 .intr_status_bit = -1, \ 104 .intr_target_bit = -1, \ 105 .intr_raw_status_bit = -1, \ 106 .intr_polarity_bit = -1, \ 107 .intr_detection_bit = -1, \ 108 .intr_detection_width = -1, \ 109 } 110 static const struct pinctrl_pin_desc qcm2290_pins[] = { 111 PINCTRL_PIN(0, "GPIO_0"), 112 PINCTRL_PIN(1, "GPIO_1"), 113 PINCTRL_PIN(2, "GPIO_2"), 114 PINCTRL_PIN(3, "GPIO_3"), 115 PINCTRL_PIN(4, "GPIO_4"), 116 PINCTRL_PIN(5, "GPIO_5"), 117 PINCTRL_PIN(6, "GPIO_6"), 118 PINCTRL_PIN(7, "GPIO_7"), 119 PINCTRL_PIN(8, "GPIO_8"), 120 PINCTRL_PIN(9, "GPIO_9"), 121 PINCTRL_PIN(10, "GPIO_10"), 122 PINCTRL_PIN(11, "GPIO_11"), 123 PINCTRL_PIN(12, "GPIO_12"), 124 PINCTRL_PIN(13, "GPIO_13"), 125 PINCTRL_PIN(14, "GPIO_14"), 126 PINCTRL_PIN(15, "GPIO_15"), 127 PINCTRL_PIN(16, "GPIO_16"), 128 PINCTRL_PIN(17, "GPIO_17"), 129 PINCTRL_PIN(18, "GPIO_18"), 130 PINCTRL_PIN(19, "GPIO_19"), 131 PINCTRL_PIN(20, "GPIO_20"), 132 PINCTRL_PIN(21, "GPIO_21"), 133 PINCTRL_PIN(22, "GPIO_22"), 134 PINCTRL_PIN(23, "GPIO_23"), 135 PINCTRL_PIN(24, "GPIO_24"), 136 PINCTRL_PIN(25, "GPIO_25"), 137 PINCTRL_PIN(26, "GPIO_26"), 138 PINCTRL_PIN(27, "GPIO_27"), 139 PINCTRL_PIN(28, "GPIO_28"), 140 PINCTRL_PIN(29, "GPIO_29"), 141 PINCTRL_PIN(30, "GPIO_30"), 142 PINCTRL_PIN(31, "GPIO_31"), 143 PINCTRL_PIN(32, "GPIO_32"), 144 PINCTRL_PIN(33, "GPIO_33"), 145 PINCTRL_PIN(34, "GPIO_34"), 146 PINCTRL_PIN(35, "GPIO_35"), 147 PINCTRL_PIN(36, "GPIO_36"), 148 PINCTRL_PIN(37, "GPIO_37"), 149 PINCTRL_PIN(38, "GPIO_38"), 150 PINCTRL_PIN(39, "GPIO_39"), 151 PINCTRL_PIN(40, "GPIO_40"), 152 PINCTRL_PIN(41, "GPIO_41"), 153 PINCTRL_PIN(42, "GPIO_42"), 154 PINCTRL_PIN(43, "GPIO_43"), 155 PINCTRL_PIN(44, "GPIO_44"), 156 PINCTRL_PIN(45, "GPIO_45"), 157 PINCTRL_PIN(46, "GPIO_46"), 158 PINCTRL_PIN(47, "GPIO_47"), 159 PINCTRL_PIN(48, "GPIO_48"), 160 PINCTRL_PIN(49, "GPIO_49"), 161 PINCTRL_PIN(50, "GPIO_50"), 162 PINCTRL_PIN(51, "GPIO_51"), 163 PINCTRL_PIN(52, "GPIO_52"), 164 PINCTRL_PIN(53, "GPIO_53"), 165 PINCTRL_PIN(54, "GPIO_54"), 166 PINCTRL_PIN(55, "GPIO_55"), 167 PINCTRL_PIN(56, "GPIO_56"), 168 PINCTRL_PIN(57, "GPIO_57"), 169 PINCTRL_PIN(58, "GPIO_58"), 170 PINCTRL_PIN(59, "GPIO_59"), 171 PINCTRL_PIN(60, "GPIO_60"), 172 PINCTRL_PIN(61, "GPIO_61"), 173 PINCTRL_PIN(62, "GPIO_62"), 174 PINCTRL_PIN(63, "GPIO_63"), 175 PINCTRL_PIN(64, "GPIO_64"), 176 PINCTRL_PIN(69, "GPIO_69"), 177 PINCTRL_PIN(70, "GPIO_70"), 178 PINCTRL_PIN(71, "GPIO_71"), 179 PINCTRL_PIN(72, "GPIO_72"), 180 PINCTRL_PIN(73, "GPIO_73"), 181 PINCTRL_PIN(74, "GPIO_74"), 182 PINCTRL_PIN(75, "GPIO_75"), 183 PINCTRL_PIN(76, "GPIO_76"), 184 PINCTRL_PIN(77, "GPIO_77"), 185 PINCTRL_PIN(78, "GPIO_78"), 186 PINCTRL_PIN(79, "GPIO_79"), 187 PINCTRL_PIN(80, "GPIO_80"), 188 PINCTRL_PIN(81, "GPIO_81"), 189 PINCTRL_PIN(82, "GPIO_82"), 190 PINCTRL_PIN(86, "GPIO_86"), 191 PINCTRL_PIN(87, "GPIO_87"), 192 PINCTRL_PIN(88, "GPIO_88"), 193 PINCTRL_PIN(89, "GPIO_89"), 194 PINCTRL_PIN(90, "GPIO_90"), 195 PINCTRL_PIN(91, "GPIO_91"), 196 PINCTRL_PIN(94, "GPIO_94"), 197 PINCTRL_PIN(95, "GPIO_95"), 198 PINCTRL_PIN(96, "GPIO_96"), 199 PINCTRL_PIN(97, "GPIO_97"), 200 PINCTRL_PIN(98, "GPIO_98"), 201 PINCTRL_PIN(99, "GPIO_99"), 202 PINCTRL_PIN(100, "GPIO_100"), 203 PINCTRL_PIN(101, "GPIO_101"), 204 PINCTRL_PIN(102, "GPIO_102"), 205 PINCTRL_PIN(103, "GPIO_103"), 206 PINCTRL_PIN(104, "GPIO_104"), 207 PINCTRL_PIN(105, "GPIO_105"), 208 PINCTRL_PIN(106, "GPIO_106"), 209 PINCTRL_PIN(107, "GPIO_107"), 210 PINCTRL_PIN(108, "GPIO_108"), 211 PINCTRL_PIN(109, "GPIO_109"), 212 PINCTRL_PIN(110, "GPIO_110"), 213 PINCTRL_PIN(111, "GPIO_111"), 214 PINCTRL_PIN(112, "GPIO_112"), 215 PINCTRL_PIN(113, "GPIO_113"), 216 PINCTRL_PIN(114, "GPIO_114"), 217 PINCTRL_PIN(115, "GPIO_115"), 218 PINCTRL_PIN(116, "GPIO_116"), 219 PINCTRL_PIN(117, "GPIO_117"), 220 PINCTRL_PIN(118, "GPIO_118"), 221 PINCTRL_PIN(119, "GPIO_119"), 222 PINCTRL_PIN(120, "GPIO_120"), 223 PINCTRL_PIN(121, "GPIO_121"), 224 PINCTRL_PIN(122, "GPIO_122"), 225 PINCTRL_PIN(123, "GPIO_123"), 226 PINCTRL_PIN(124, "GPIO_124"), 227 PINCTRL_PIN(125, "GPIO_125"), 228 PINCTRL_PIN(126, "GPIO_126"), 229 PINCTRL_PIN(127, "SDC1_RCLK"), 230 PINCTRL_PIN(128, "SDC1_CLK"), 231 PINCTRL_PIN(129, "SDC1_CMD"), 232 PINCTRL_PIN(130, "SDC1_DATA"), 233 PINCTRL_PIN(131, "SDC2_CLK"), 234 PINCTRL_PIN(132, "SDC2_CMD"), 235 PINCTRL_PIN(133, "SDC2_DATA"), 236 }; 237 238 #define DECLARE_MSM_GPIO_PINS(pin) \ 239 static const unsigned int gpio##pin##_pins[] = { pin } 240 DECLARE_MSM_GPIO_PINS(0); 241 DECLARE_MSM_GPIO_PINS(1); 242 DECLARE_MSM_GPIO_PINS(2); 243 DECLARE_MSM_GPIO_PINS(3); 244 DECLARE_MSM_GPIO_PINS(4); 245 DECLARE_MSM_GPIO_PINS(5); 246 DECLARE_MSM_GPIO_PINS(6); 247 DECLARE_MSM_GPIO_PINS(7); 248 DECLARE_MSM_GPIO_PINS(8); 249 DECLARE_MSM_GPIO_PINS(9); 250 DECLARE_MSM_GPIO_PINS(10); 251 DECLARE_MSM_GPIO_PINS(11); 252 DECLARE_MSM_GPIO_PINS(12); 253 DECLARE_MSM_GPIO_PINS(13); 254 DECLARE_MSM_GPIO_PINS(14); 255 DECLARE_MSM_GPIO_PINS(15); 256 DECLARE_MSM_GPIO_PINS(16); 257 DECLARE_MSM_GPIO_PINS(17); 258 DECLARE_MSM_GPIO_PINS(18); 259 DECLARE_MSM_GPIO_PINS(19); 260 DECLARE_MSM_GPIO_PINS(20); 261 DECLARE_MSM_GPIO_PINS(21); 262 DECLARE_MSM_GPIO_PINS(22); 263 DECLARE_MSM_GPIO_PINS(23); 264 DECLARE_MSM_GPIO_PINS(24); 265 DECLARE_MSM_GPIO_PINS(25); 266 DECLARE_MSM_GPIO_PINS(26); 267 DECLARE_MSM_GPIO_PINS(27); 268 DECLARE_MSM_GPIO_PINS(28); 269 DECLARE_MSM_GPIO_PINS(29); 270 DECLARE_MSM_GPIO_PINS(30); 271 DECLARE_MSM_GPIO_PINS(31); 272 DECLARE_MSM_GPIO_PINS(32); 273 DECLARE_MSM_GPIO_PINS(33); 274 DECLARE_MSM_GPIO_PINS(34); 275 DECLARE_MSM_GPIO_PINS(35); 276 DECLARE_MSM_GPIO_PINS(36); 277 DECLARE_MSM_GPIO_PINS(37); 278 DECLARE_MSM_GPIO_PINS(38); 279 DECLARE_MSM_GPIO_PINS(39); 280 DECLARE_MSM_GPIO_PINS(40); 281 DECLARE_MSM_GPIO_PINS(41); 282 DECLARE_MSM_GPIO_PINS(42); 283 DECLARE_MSM_GPIO_PINS(43); 284 DECLARE_MSM_GPIO_PINS(44); 285 DECLARE_MSM_GPIO_PINS(45); 286 DECLARE_MSM_GPIO_PINS(46); 287 DECLARE_MSM_GPIO_PINS(47); 288 DECLARE_MSM_GPIO_PINS(48); 289 DECLARE_MSM_GPIO_PINS(49); 290 DECLARE_MSM_GPIO_PINS(50); 291 DECLARE_MSM_GPIO_PINS(51); 292 DECLARE_MSM_GPIO_PINS(52); 293 DECLARE_MSM_GPIO_PINS(53); 294 DECLARE_MSM_GPIO_PINS(54); 295 DECLARE_MSM_GPIO_PINS(55); 296 DECLARE_MSM_GPIO_PINS(56); 297 DECLARE_MSM_GPIO_PINS(57); 298 DECLARE_MSM_GPIO_PINS(58); 299 DECLARE_MSM_GPIO_PINS(59); 300 DECLARE_MSM_GPIO_PINS(60); 301 DECLARE_MSM_GPIO_PINS(61); 302 DECLARE_MSM_GPIO_PINS(62); 303 DECLARE_MSM_GPIO_PINS(63); 304 DECLARE_MSM_GPIO_PINS(64); 305 DECLARE_MSM_GPIO_PINS(65); 306 DECLARE_MSM_GPIO_PINS(66); 307 DECLARE_MSM_GPIO_PINS(67); 308 DECLARE_MSM_GPIO_PINS(68); 309 DECLARE_MSM_GPIO_PINS(69); 310 DECLARE_MSM_GPIO_PINS(70); 311 DECLARE_MSM_GPIO_PINS(71); 312 DECLARE_MSM_GPIO_PINS(72); 313 DECLARE_MSM_GPIO_PINS(73); 314 DECLARE_MSM_GPIO_PINS(74); 315 DECLARE_MSM_GPIO_PINS(75); 316 DECLARE_MSM_GPIO_PINS(76); 317 DECLARE_MSM_GPIO_PINS(77); 318 DECLARE_MSM_GPIO_PINS(78); 319 DECLARE_MSM_GPIO_PINS(79); 320 DECLARE_MSM_GPIO_PINS(80); 321 DECLARE_MSM_GPIO_PINS(81); 322 DECLARE_MSM_GPIO_PINS(82); 323 DECLARE_MSM_GPIO_PINS(83); 324 DECLARE_MSM_GPIO_PINS(84); 325 DECLARE_MSM_GPIO_PINS(85); 326 DECLARE_MSM_GPIO_PINS(86); 327 DECLARE_MSM_GPIO_PINS(87); 328 DECLARE_MSM_GPIO_PINS(88); 329 DECLARE_MSM_GPIO_PINS(89); 330 DECLARE_MSM_GPIO_PINS(90); 331 DECLARE_MSM_GPIO_PINS(91); 332 DECLARE_MSM_GPIO_PINS(92); 333 DECLARE_MSM_GPIO_PINS(93); 334 DECLARE_MSM_GPIO_PINS(94); 335 DECLARE_MSM_GPIO_PINS(95); 336 DECLARE_MSM_GPIO_PINS(96); 337 DECLARE_MSM_GPIO_PINS(97); 338 DECLARE_MSM_GPIO_PINS(98); 339 DECLARE_MSM_GPIO_PINS(99); 340 DECLARE_MSM_GPIO_PINS(100); 341 DECLARE_MSM_GPIO_PINS(101); 342 DECLARE_MSM_GPIO_PINS(102); 343 DECLARE_MSM_GPIO_PINS(103); 344 DECLARE_MSM_GPIO_PINS(104); 345 DECLARE_MSM_GPIO_PINS(105); 346 DECLARE_MSM_GPIO_PINS(106); 347 DECLARE_MSM_GPIO_PINS(107); 348 DECLARE_MSM_GPIO_PINS(108); 349 DECLARE_MSM_GPIO_PINS(109); 350 DECLARE_MSM_GPIO_PINS(110); 351 DECLARE_MSM_GPIO_PINS(111); 352 DECLARE_MSM_GPIO_PINS(112); 353 DECLARE_MSM_GPIO_PINS(113); 354 DECLARE_MSM_GPIO_PINS(114); 355 DECLARE_MSM_GPIO_PINS(115); 356 DECLARE_MSM_GPIO_PINS(116); 357 DECLARE_MSM_GPIO_PINS(117); 358 DECLARE_MSM_GPIO_PINS(118); 359 DECLARE_MSM_GPIO_PINS(119); 360 DECLARE_MSM_GPIO_PINS(120); 361 DECLARE_MSM_GPIO_PINS(121); 362 DECLARE_MSM_GPIO_PINS(122); 363 DECLARE_MSM_GPIO_PINS(123); 364 DECLARE_MSM_GPIO_PINS(124); 365 DECLARE_MSM_GPIO_PINS(125); 366 DECLARE_MSM_GPIO_PINS(126); 367 368 static const unsigned int sdc1_rclk_pins[] = { 127 }; 369 static const unsigned int sdc1_clk_pins[] = { 128 }; 370 static const unsigned int sdc1_cmd_pins[] = { 129 }; 371 static const unsigned int sdc1_data_pins[] = { 130 }; 372 static const unsigned int sdc2_clk_pins[] = { 131 }; 373 static const unsigned int sdc2_cmd_pins[] = { 132 }; 374 static const unsigned int sdc2_data_pins[] = { 133 }; 375 376 enum qcm2290_functions { 377 msm_mux_adsp_ext, 378 msm_mux_agera_pll, 379 msm_mux_atest, 380 msm_mux_cam_mclk, 381 msm_mux_cci_async, 382 msm_mux_cci_i2c, 383 msm_mux_cci_timer0, 384 msm_mux_cci_timer1, 385 msm_mux_cci_timer2, 386 msm_mux_cci_timer3, 387 msm_mux_char_exec, 388 msm_mux_cri_trng, 389 msm_mux_cri_trng0, 390 msm_mux_cri_trng1, 391 msm_mux_dac_calib, 392 msm_mux_dbg_out, 393 msm_mux_ddr_bist, 394 msm_mux_ddr_pxi0, 395 msm_mux_ddr_pxi1, 396 msm_mux_ddr_pxi2, 397 msm_mux_ddr_pxi3, 398 msm_mux_gcc_gp1, 399 msm_mux_gcc_gp2, 400 msm_mux_gcc_gp3, 401 msm_mux_gpio, 402 msm_mux_gp_pdm0, 403 msm_mux_gp_pdm1, 404 msm_mux_gp_pdm2, 405 msm_mux_gsm0_tx, 406 msm_mux_gsm1_tx, 407 msm_mux_jitter_bist, 408 msm_mux_mdp_vsync, 409 msm_mux_mdp_vsync_out_0, 410 msm_mux_mdp_vsync_out_1, 411 msm_mux_mpm_pwr, 412 msm_mux_mss_lte, 413 msm_mux_m_voc, 414 msm_mux_nav_gpio, 415 msm_mux_pa_indicator, 416 msm_mux_pbs0, 417 msm_mux_pbs1, 418 msm_mux_pbs2, 419 msm_mux_pbs3, 420 msm_mux_pbs4, 421 msm_mux_pbs5, 422 msm_mux_pbs6, 423 msm_mux_pbs7, 424 msm_mux_pbs8, 425 msm_mux_pbs9, 426 msm_mux_pbs10, 427 msm_mux_pbs11, 428 msm_mux_pbs12, 429 msm_mux_pbs13, 430 msm_mux_pbs14, 431 msm_mux_pbs15, 432 msm_mux_pbs_out, 433 msm_mux_phase_flag, 434 msm_mux_pll_bist, 435 msm_mux_pll_bypassnl, 436 msm_mux_pll_reset, 437 msm_mux_prng_rosc, 438 msm_mux_pwm_0, 439 msm_mux_pwm_1, 440 msm_mux_pwm_2, 441 msm_mux_pwm_3, 442 msm_mux_pwm_4, 443 msm_mux_pwm_5, 444 msm_mux_pwm_6, 445 msm_mux_pwm_7, 446 msm_mux_pwm_8, 447 msm_mux_pwm_9, 448 msm_mux_qdss_cti, 449 msm_mux_qdss_gpio, 450 msm_mux_qup0, 451 msm_mux_qup1, 452 msm_mux_qup2, 453 msm_mux_qup3, 454 msm_mux_qup4, 455 msm_mux_qup5, 456 msm_mux_sdc1_tb, 457 msm_mux_sdc2_tb, 458 msm_mux_sd_write, 459 msm_mux_ssbi_wtr1, 460 msm_mux_tgu_ch0, 461 msm_mux_tgu_ch1, 462 msm_mux_tgu_ch2, 463 msm_mux_tgu_ch3, 464 msm_mux_tsense_pwm, 465 msm_mux_uim1_clk, 466 msm_mux_uim1_data, 467 msm_mux_uim1_present, 468 msm_mux_uim1_reset, 469 msm_mux_uim2_clk, 470 msm_mux_uim2_data, 471 msm_mux_uim2_present, 472 msm_mux_uim2_reset, 473 msm_mux_usb_phy, 474 msm_mux_vfr_1, 475 msm_mux_vsense_trigger, 476 msm_mux_wlan1_adc0, 477 msm_mux_wlan1_adc1, 478 msm_mux__, 479 }; 480 481 static const char * const qup0_groups[] = { 482 "gpio0", "gpio1", "gpio2", "gpio3", "gpio82", "gpio86", 483 }; 484 static const char * const gpio_groups[] = { 485 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 486 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 487 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 488 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 489 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 490 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 491 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 492 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 493 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 494 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 495 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 496 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 497 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 498 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 499 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 500 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 501 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 502 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", 503 "gpio123", "gpio124", "gpio125", "gpio126", 504 }; 505 static const char * const ddr_bist_groups[] = { 506 "gpio0", "gpio1", "gpio2", "gpio3", 507 }; 508 static const char * const phase_flag_groups[] = { 509 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", 510 "gpio14", "gpio15", "gpio16", "gpio17", "gpio22", "gpio23", "gpio24", 511 "gpio25", "gpio26", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", 512 "gpio35", "gpio36", "gpio43", "gpio44", "gpio45", "gpio63", "gpio64", 513 "gpio102", "gpio103", "gpio104", "gpio105", 514 }; 515 static const char * const qdss_gpio_groups[] = { 516 "gpio0", "gpio1", "gpio2", "gpio3", "gpio8", "gpio9", "gpio10", 517 "gpio11", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", 518 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", 519 "gpio47", "gpio48", "gpio69", "gpio70", "gpio87", "gpio90", "gpio91", 520 "gpio94", "gpio95", "gpio104", "gpio105", "gpio106", "gpio107", 521 "gpio109", "gpio110", 522 }; 523 static const char * const atest_groups[] = { 524 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", 525 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio29", "gpio30", 526 "gpio31", "gpio32", "gpio33", "gpio86", "gpio89", "gpio100", "gpio101", 527 }; 528 static const char * const mpm_pwr_groups[] = { 529 "gpio1", 530 }; 531 static const char * const m_voc_groups[] = { 532 "gpio0", 533 }; 534 static const char * const dac_calib_groups[] = { 535 "gpio2", 536 "gpio3", 537 "gpio4", 538 "gpio5", 539 "gpio6", 540 "gpio14", 541 "gpio15", 542 "gpio16", 543 "gpio17", 544 "gpio22", 545 "gpio23", 546 "gpio24", 547 "gpio25", 548 "gpio26", 549 "gpio29", 550 "gpio30", 551 "gpio31", 552 "gpio32", 553 "gpio33", 554 "gpio80", 555 "gpio81", 556 "gpio82", 557 "gpio102", 558 "gpio103", 559 "gpio104", 560 "gpio105", 561 }; 562 static const char * const qup1_groups[] = { 563 "gpio4", "gpio5", "gpio69", "gpio70", 564 }; 565 static const char * const cri_trng0_groups[] = { 566 "gpio4", 567 }; 568 static const char * const cri_trng1_groups[] = { 569 "gpio5", 570 }; 571 static const char * const qup2_groups[] = { 572 "gpio6", "gpio7", "gpio71", "gpio80", 573 }; 574 static const char * const qup3_groups[] = { 575 "gpio8", "gpio9", "gpio10", "gpio11", 576 }; 577 static const char * const pbs_out_groups[] = { 578 "gpio8", "gpio9", "gpio52", 579 }; 580 static const char * const pll_bist_groups[] = { 581 "gpio8", "gpio9", 582 }; 583 static const char * const tsense_pwm_groups[] = { 584 "gpio8", 585 }; 586 static const char * const agera_pll_groups[] = { 587 "gpio10", "gpio11", 588 }; 589 static const char * const pbs0_groups[] = { 590 "gpio10", 591 }; 592 static const char * const pbs1_groups[] = { 593 "gpio11", 594 }; 595 static const char * const qup4_groups[] = { 596 "gpio12", "gpio13", "gpio96", "gpio97", 597 }; 598 static const char * const tgu_ch0_groups[] = { 599 "gpio12", 600 }; 601 static const char * const tgu_ch1_groups[] = { 602 "gpio13", 603 }; 604 static const char * const qup5_groups[] = { 605 "gpio14", "gpio15", "gpio16", "gpio17", 606 }; 607 static const char * const tgu_ch2_groups[] = { 608 "gpio14", 609 }; 610 static const char * const tgu_ch3_groups[] = { 611 "gpio15", 612 }; 613 static const char * const sdc2_tb_groups[] = { 614 "gpio18", 615 }; 616 static const char * const cri_trng_groups[] = { 617 "gpio18", 618 }; 619 static const char * const pbs2_groups[] = { 620 "gpio18", 621 }; 622 static const char * const pwm_0_groups[] = { 623 "gpio18", 624 }; 625 static const char * const sdc1_tb_groups[] = { 626 "gpio19", 627 }; 628 static const char * const pbs3_groups[] = { 629 "gpio19", 630 }; 631 static const char * const cam_mclk_groups[] = { 632 "gpio20", "gpio21", "gpio27", "gpio28", 633 }; 634 static const char * const pbs4_groups[] = { 635 "gpio20", 636 }; 637 static const char * const adsp_ext_groups[] = { 638 "gpio21", 639 }; 640 static const char * const pbs5_groups[] = { 641 "gpio21", 642 }; 643 static const char * const cci_i2c_groups[] = { 644 "gpio22", "gpio23", "gpio29", "gpio30", 645 }; 646 static const char * const prng_rosc_groups[] = { 647 "gpio22", "gpio23", 648 }; 649 static const char * const pbs6_groups[] = { 650 "gpio22", 651 }; 652 static const char * const pbs7_groups[] = { 653 "gpio23", 654 }; 655 static const char * const cci_timer1_groups[] = { 656 "gpio24", 657 }; 658 static const char * const gcc_gp1_groups[] = { 659 "gpio24", "gpio86", 660 }; 661 static const char * const pbs8_groups[] = { 662 "gpio24", 663 }; 664 static const char * const cci_async_groups[] = { 665 "gpio25", 666 }; 667 static const char * const cci_timer0_groups[] = { 668 "gpio25", 669 }; 670 static const char * const pbs9_groups[] = { 671 "gpio25", 672 }; 673 static const char * const pbs10_groups[] = { 674 "gpio26", 675 }; 676 static const char * const vsense_trigger_groups[] = { 677 "gpio26", 678 }; 679 static const char * const qdss_cti_groups[] = { 680 "gpio27", "gpio28", "gpio72", "gpio73", "gpio96", "gpio97", 681 }; 682 static const char * const cci_timer2_groups[] = { 683 "gpio28", 684 }; 685 static const char * const pwm_1_groups[] = { 686 "gpio28", 687 }; 688 static const char * const gp_pdm0_groups[] = { 689 "gpio31", "gpio95", 690 }; 691 static const char * const cci_timer3_groups[] = { 692 "gpio32", 693 }; 694 static const char * const gp_pdm1_groups[] = { 695 "gpio32", "gpio96", 696 }; 697 static const char * const gp_pdm2_groups[] = { 698 "gpio33", "gpio97", 699 }; 700 static const char * const char_exec_groups[] = { 701 "gpio37", "gpio38", 702 }; 703 static const char * const nav_gpio_groups[] = { 704 "gpio42", "gpio47", "gpio52", "gpio95", "gpio96", "gpio97", "gpio106", 705 "gpio107", "gpio108", 706 }; 707 static const char * const pbs14_groups[] = { 708 "gpio47", 709 }; 710 static const char * const vfr_1_groups[] = { 711 "gpio48", 712 }; 713 static const char * const pbs15_groups[] = { 714 "gpio48", 715 }; 716 static const char * const pa_indicator_groups[] = { 717 "gpio49", 718 }; 719 static const char * const pwm_2_groups[] = { 720 "gpio51", 721 }; 722 static const char * const gsm1_tx_groups[] = { 723 "gpio53", 724 }; 725 static const char * const ssbi_wtr1_groups[] = { 726 "gpio59", "gpio60", 727 }; 728 static const char * const pll_bypassnl_groups[] = { 729 "gpio62", 730 }; 731 static const char * const pll_reset_groups[] = { 732 "gpio63", 733 }; 734 static const char * const ddr_pxi0_groups[] = { 735 "gpio63", "gpio64", 736 }; 737 static const char * const gsm0_tx_groups[] = { 738 "gpio64", 739 }; 740 static const char * const gcc_gp2_groups[] = { 741 "gpio69", "gpio107", 742 }; 743 static const char * const ddr_pxi1_groups[] = { 744 "gpio69", "gpio70", 745 }; 746 static const char * const gcc_gp3_groups[] = { 747 "gpio70", "gpio106", 748 }; 749 static const char * const dbg_out_groups[] = { 750 "gpio71", 751 }; 752 static const char * const uim2_data_groups[] = { 753 "gpio72", 754 }; 755 static const char * const pwm_3_groups[] = { 756 "gpio72", 757 }; 758 static const char * const uim2_clk_groups[] = { 759 "gpio73", 760 }; 761 static const char * const uim2_reset_groups[] = { 762 "gpio74", 763 }; 764 static const char * const pwm_4_groups[] = { 765 "gpio74", 766 }; 767 static const char * const uim2_present_groups[] = { 768 "gpio75", 769 }; 770 static const char * const pwm_5_groups[] = { 771 "gpio75", 772 }; 773 static const char * const uim1_data_groups[] = { 774 "gpio76", 775 }; 776 static const char * const uim1_clk_groups[] = { 777 "gpio77", 778 }; 779 static const char * const uim1_reset_groups[] = { 780 "gpio78", 781 }; 782 static const char * const uim1_present_groups[] = { 783 "gpio79", 784 }; 785 static const char * const mdp_vsync_groups[] = { 786 "gpio81", "gpio96", "gpio97", 787 }; 788 static const char * const mdp_vsync_out_0_groups[] = { 789 "gpio81", 790 }; 791 static const char * const mdp_vsync_out_1_groups[] = { 792 "gpio81", 793 }; 794 static const char * const pwm_6_groups[] = { 795 "gpio82", 796 }; 797 static const char * const pbs11_groups[] = { 798 "gpio87", 799 }; 800 static const char * const usb_phy_groups[] = { 801 "gpio89", 802 }; 803 static const char * const pwm_7_groups[] = { 804 "gpio89", 805 }; 806 static const char * const mss_lte_groups[] = { 807 "gpio90", "gpio91", 808 }; 809 static const char * const pbs12_groups[] = { 810 "gpio90", 811 }; 812 static const char * const pbs13_groups[] = { 813 "gpio91", 814 }; 815 static const char * const wlan1_adc0_groups[] = { 816 "gpio94", 817 }; 818 static const char * const wlan1_adc1_groups[] = { 819 "gpio95", 820 }; 821 static const char * const sd_write_groups[] = { 822 "gpio96", 823 }; 824 static const char * const jitter_bist_groups[] = { 825 "gpio96", "gpio97", 826 }; 827 static const char * const ddr_pxi2_groups[] = { 828 "gpio102", "gpio103", 829 }; 830 static const char * const ddr_pxi3_groups[] = { 831 "gpio104", "gpio105", 832 }; 833 static const char * const pwm_8_groups[] = { 834 "gpio104", 835 }; 836 static const char * const pwm_9_groups[] = { 837 "gpio115", 838 }; 839 840 static const struct msm_function qcm2290_functions[] = { 841 FUNCTION(adsp_ext), 842 FUNCTION(agera_pll), 843 FUNCTION(atest), 844 FUNCTION(cam_mclk), 845 FUNCTION(cci_async), 846 FUNCTION(cci_i2c), 847 FUNCTION(cci_timer0), 848 FUNCTION(cci_timer1), 849 FUNCTION(cci_timer2), 850 FUNCTION(cci_timer3), 851 FUNCTION(char_exec), 852 FUNCTION(cri_trng), 853 FUNCTION(cri_trng0), 854 FUNCTION(cri_trng1), 855 FUNCTION(dac_calib), 856 FUNCTION(dbg_out), 857 FUNCTION(ddr_bist), 858 FUNCTION(ddr_pxi0), 859 FUNCTION(ddr_pxi1), 860 FUNCTION(ddr_pxi2), 861 FUNCTION(ddr_pxi3), 862 FUNCTION(gcc_gp1), 863 FUNCTION(gcc_gp2), 864 FUNCTION(gcc_gp3), 865 FUNCTION(gpio), 866 FUNCTION(gp_pdm0), 867 FUNCTION(gp_pdm1), 868 FUNCTION(gp_pdm2), 869 FUNCTION(gsm0_tx), 870 FUNCTION(gsm1_tx), 871 FUNCTION(jitter_bist), 872 FUNCTION(mdp_vsync), 873 FUNCTION(mdp_vsync_out_0), 874 FUNCTION(mdp_vsync_out_1), 875 FUNCTION(mpm_pwr), 876 FUNCTION(mss_lte), 877 FUNCTION(m_voc), 878 FUNCTION(nav_gpio), 879 FUNCTION(pa_indicator), 880 FUNCTION(pbs0), 881 FUNCTION(pbs1), 882 FUNCTION(pbs2), 883 FUNCTION(pbs3), 884 FUNCTION(pbs4), 885 FUNCTION(pbs5), 886 FUNCTION(pbs6), 887 FUNCTION(pbs7), 888 FUNCTION(pbs8), 889 FUNCTION(pbs9), 890 FUNCTION(pbs10), 891 FUNCTION(pbs11), 892 FUNCTION(pbs12), 893 FUNCTION(pbs13), 894 FUNCTION(pbs14), 895 FUNCTION(pbs15), 896 FUNCTION(pbs_out), 897 FUNCTION(phase_flag), 898 FUNCTION(pll_bist), 899 FUNCTION(pll_bypassnl), 900 FUNCTION(pll_reset), 901 FUNCTION(prng_rosc), 902 FUNCTION(pwm_0), 903 FUNCTION(pwm_1), 904 FUNCTION(pwm_2), 905 FUNCTION(pwm_3), 906 FUNCTION(pwm_4), 907 FUNCTION(pwm_5), 908 FUNCTION(pwm_6), 909 FUNCTION(pwm_7), 910 FUNCTION(pwm_8), 911 FUNCTION(pwm_9), 912 FUNCTION(qdss_cti), 913 FUNCTION(qdss_gpio), 914 FUNCTION(qup0), 915 FUNCTION(qup1), 916 FUNCTION(qup2), 917 FUNCTION(qup3), 918 FUNCTION(qup4), 919 FUNCTION(qup5), 920 FUNCTION(sdc1_tb), 921 FUNCTION(sdc2_tb), 922 FUNCTION(sd_write), 923 FUNCTION(ssbi_wtr1), 924 FUNCTION(tgu_ch0), 925 FUNCTION(tgu_ch1), 926 FUNCTION(tgu_ch2), 927 FUNCTION(tgu_ch3), 928 FUNCTION(tsense_pwm), 929 FUNCTION(uim1_clk), 930 FUNCTION(uim1_data), 931 FUNCTION(uim1_present), 932 FUNCTION(uim1_reset), 933 FUNCTION(uim2_clk), 934 FUNCTION(uim2_data), 935 FUNCTION(uim2_present), 936 FUNCTION(uim2_reset), 937 FUNCTION(usb_phy), 938 FUNCTION(vfr_1), 939 FUNCTION(vsense_trigger), 940 FUNCTION(wlan1_adc0), 941 FUNCTION(wlan1_adc1), 942 }; 943 944 /* Every pin is maintained as a single group, and missing or non-existing pin 945 * would be maintained as dummy group to synchronize pin group index with 946 * pin descriptor registered with pinctrl core. 947 * Clients would not be able to request these dummy pin groups. 948 */ 949 static const struct msm_pingroup qcm2290_groups[] = { 950 [0] = PINGROUP(0, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _), 951 [1] = PINGROUP(1, qup0, mpm_pwr, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _), 952 [2] = PINGROUP(2, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _), 953 [3] = PINGROUP(3, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _), 954 [4] = PINGROUP(4, qup1, cri_trng0, _, phase_flag, dac_calib, atest, _, _, _), 955 [5] = PINGROUP(5, qup1, cri_trng1, _, phase_flag, dac_calib, atest, _, _, _), 956 [6] = PINGROUP(6, qup2, _, phase_flag, dac_calib, atest, _, _, _, _), 957 [7] = PINGROUP(7, qup2, _, _, _, _, _, _, _, _), 958 [8] = PINGROUP(8, qup3, pbs_out, pll_bist, _, qdss_gpio, _, tsense_pwm, _, _), 959 [9] = PINGROUP(9, qup3, pbs_out, pll_bist, _, qdss_gpio, _, _, _, _), 960 [10] = PINGROUP(10, qup3, agera_pll, _, pbs0, qdss_gpio, _, _, _, _), 961 [11] = PINGROUP(11, qup3, agera_pll, _, pbs1, qdss_gpio, _, _, _, _), 962 [12] = PINGROUP(12, qup4, tgu_ch0, _, _, _, _, _, _, _), 963 [13] = PINGROUP(13, qup4, tgu_ch1, _, _, _, _, _, _, _), 964 [14] = PINGROUP(14, qup5, tgu_ch2, _, phase_flag, qdss_gpio, dac_calib, _, _, _), 965 [15] = PINGROUP(15, qup5, tgu_ch3, _, phase_flag, qdss_gpio, dac_calib, _, _, _), 966 [16] = PINGROUP(16, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _), 967 [17] = PINGROUP(17, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _), 968 [18] = PINGROUP(18, sdc2_tb, cri_trng, pbs2, qdss_gpio, _, pwm_0, _, _, _), 969 [19] = PINGROUP(19, sdc1_tb, pbs3, qdss_gpio, _, _, _, _, _, _), 970 [20] = PINGROUP(20, cam_mclk, pbs4, qdss_gpio, _, _, _, _, _, _), 971 [21] = PINGROUP(21, cam_mclk, adsp_ext, pbs5, qdss_gpio, _, _, _, _, _), 972 [22] = PINGROUP(22, cci_i2c, prng_rosc, _, pbs6, phase_flag, qdss_gpio, dac_calib, atest, _), 973 [23] = PINGROUP(23, cci_i2c, prng_rosc, _, pbs7, phase_flag, qdss_gpio, dac_calib, atest, _), 974 [24] = PINGROUP(24, cci_timer1, gcc_gp1, _, pbs8, phase_flag, qdss_gpio, dac_calib, atest, _), 975 [25] = PINGROUP(25, cci_async, cci_timer0, _, pbs9, phase_flag, qdss_gpio, dac_calib, atest, _), 976 [26] = PINGROUP(26, _, pbs10, phase_flag, qdss_gpio, dac_calib, atest, vsense_trigger, _, _), 977 [27] = PINGROUP(27, cam_mclk, qdss_cti, _, _, _, _, _, _, _), 978 [28] = PINGROUP(28, cam_mclk, cci_timer2, qdss_cti, _, pwm_1, _, _, _, _), 979 [29] = PINGROUP(29, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _), 980 [30] = PINGROUP(30, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _), 981 [31] = PINGROUP(31, gp_pdm0, _, phase_flag, dac_calib, atest, _, _, _, _), 982 [32] = PINGROUP(32, cci_timer3, gp_pdm1, _, phase_flag, dac_calib, atest, _, _, _), 983 [33] = PINGROUP(33, gp_pdm2, _, phase_flag, dac_calib, atest, _, _, _, _), 984 [34] = PINGROUP(34, _, _, _, _, _, _, _, _, _), 985 [35] = PINGROUP(35, _, phase_flag, _, _, _, _, _, _, _), 986 [36] = PINGROUP(36, _, phase_flag, _, _, _, _, _, _, _), 987 [37] = PINGROUP(37, _, _, char_exec, _, _, _, _, _, _), 988 [38] = PINGROUP(38, _, _, _, char_exec, _, _, _, _, _), 989 [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _), 990 [40] = PINGROUP(40, _, _, _, _, _, _, _, _, _), 991 [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _), 992 [42] = PINGROUP(42, _, nav_gpio, _, _, _, _, _, _, _), 993 [43] = PINGROUP(43, _, _, phase_flag, _, _, _, _, _, _), 994 [44] = PINGROUP(44, _, _, phase_flag, _, _, _, _, _, _), 995 [45] = PINGROUP(45, _, _, phase_flag, _, _, _, _, _, _), 996 [46] = PINGROUP(46, _, _, _, _, _, _, _, _, _), 997 [47] = PINGROUP(47, _, nav_gpio, pbs14, qdss_gpio, _, _, _, _, _), 998 [48] = PINGROUP(48, _, vfr_1, _, pbs15, qdss_gpio, _, _, _, _), 999 [49] = PINGROUP(49, _, pa_indicator, _, _, _, _, _, _, _), 1000 [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), 1001 [51] = PINGROUP(51, _, _, _, pwm_2, _, _, _, _, _), 1002 [52] = PINGROUP(52, _, nav_gpio, pbs_out, _, _, _, _, _, _), 1003 [53] = PINGROUP(53, _, gsm1_tx, _, _, _, _, _, _, _), 1004 [54] = PINGROUP(54, _, _, _, _, _, _, _, _, _), 1005 [55] = PINGROUP(55, _, _, _, _, _, _, _, _, _), 1006 [56] = PINGROUP(56, _, _, _, _, _, _, _, _, _), 1007 [57] = PINGROUP(57, _, _, _, _, _, _, _, _, _), 1008 [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), 1009 [59] = PINGROUP(59, _, ssbi_wtr1, _, _, _, _, _, _, _), 1010 [60] = PINGROUP(60, _, ssbi_wtr1, _, _, _, _, _, _, _), 1011 [61] = PINGROUP(61, _, _, _, _, _, _, _, _, _), 1012 [62] = PINGROUP(62, _, pll_bypassnl, _, _, _, _, _, _, _), 1013 [63] = PINGROUP(63, pll_reset, _, phase_flag, ddr_pxi0, _, _, _, _, _), 1014 [64] = PINGROUP(64, gsm0_tx, _, phase_flag, ddr_pxi0, _, _, _, _, _), 1015 [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _), 1016 [66] = PINGROUP(66, _, _, _, _, _, _, _, _, _), 1017 [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _), 1018 [68] = PINGROUP(68, _, _, _, _, _, _, _, _, _), 1019 [69] = PINGROUP(69, qup1, gcc_gp2, qdss_gpio, ddr_pxi1, _, _, _, _, _), 1020 [70] = PINGROUP(70, qup1, gcc_gp3, qdss_gpio, ddr_pxi1, _, _, _, _, _), 1021 [71] = PINGROUP(71, qup2, dbg_out, _, _, _, _, _, _, _), 1022 [72] = PINGROUP(72, uim2_data, qdss_cti, _, pwm_3, _, _, _, _, _), 1023 [73] = PINGROUP(73, uim2_clk, _, qdss_cti, _, _, _, _, _, _), 1024 [74] = PINGROUP(74, uim2_reset, _, _, pwm_4, _, _, _, _, _), 1025 [75] = PINGROUP(75, uim2_present, _, _, pwm_5, _, _, _, _, _), 1026 [76] = PINGROUP(76, uim1_data, _, _, _, _, _, _, _, _), 1027 [77] = PINGROUP(77, uim1_clk, _, _, _, _, _, _, _, _), 1028 [78] = PINGROUP(78, uim1_reset, _, _, _, _, _, _, _, _), 1029 [79] = PINGROUP(79, uim1_present, _, _, _, _, _, _, _, _), 1030 [80] = PINGROUP(80, qup2, dac_calib, _, _, _, _, _, _, _), 1031 [81] = PINGROUP(81, mdp_vsync_out_0, mdp_vsync_out_1, mdp_vsync, dac_calib, _, _, _, _, _), 1032 [82] = PINGROUP(82, qup0, dac_calib, _, pwm_6, _, _, _, _, _), 1033 [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _), 1034 [84] = PINGROUP(84, _, _, _, _, _, _, _, _, _), 1035 [85] = PINGROUP(85, _, _, _, _, _, _, _, _, _), 1036 [86] = PINGROUP(86, qup0, gcc_gp1, atest, _, _, _, _, _, _), 1037 [87] = PINGROUP(87, pbs11, qdss_gpio, _, _, _, _, _, _, _), 1038 [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _), 1039 [89] = PINGROUP(89, usb_phy, atest, _, pwm_7, _, _, _, _, _), 1040 [90] = PINGROUP(90, mss_lte, pbs12, qdss_gpio, _, _, _, _, _, _), 1041 [91] = PINGROUP(91, mss_lte, pbs13, qdss_gpio, _, _, _, _, _, _), 1042 [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), 1043 [93] = PINGROUP(93, _, _, _, _, _, _, _, _, _), 1044 [94] = PINGROUP(94, _, qdss_gpio, wlan1_adc0, _, _, _, _, _, _), 1045 [95] = PINGROUP(95, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _), 1046 [96] = PINGROUP(96, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _), 1047 [97] = PINGROUP(97, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _), 1048 [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _), 1049 [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), 1050 [100] = PINGROUP(100, atest, _, _, _, _, _, _, _, _), 1051 [101] = PINGROUP(101, atest, _, _, _, _, _, _, _, _), 1052 [102] = PINGROUP(102, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), 1053 [103] = PINGROUP(103, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), 1054 [104] = PINGROUP(104, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, pwm_8, _, _), 1055 [105] = PINGROUP(105, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _), 1056 [106] = PINGROUP(106, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _), 1057 [107] = PINGROUP(107, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _), 1058 [108] = PINGROUP(108, nav_gpio, _, _, _, _, _, _, _, _), 1059 [109] = PINGROUP(109, _, qdss_gpio, _, _, _, _, _, _, _), 1060 [110] = PINGROUP(110, _, qdss_gpio, _, _, _, _, _, _, _), 1061 [111] = PINGROUP(111, _, _, _, _, _, _, _, _, _), 1062 [112] = PINGROUP(112, _, _, _, _, _, _, _, _, _), 1063 [113] = PINGROUP(113, _, _, _, _, _, _, _, _, _), 1064 [114] = PINGROUP(114, _, _, _, _, _, _, _, _, _), 1065 [115] = PINGROUP(115, _, pwm_9, _, _, _, _, _, _, _), 1066 [116] = PINGROUP(116, _, _, _, _, _, _, _, _, _), 1067 [117] = PINGROUP(117, _, _, _, _, _, _, _, _, _), 1068 [118] = PINGROUP(118, _, _, _, _, _, _, _, _, _), 1069 [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _), 1070 [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _), 1071 [121] = PINGROUP(121, _, _, _, _, _, _, _, _, _), 1072 [122] = PINGROUP(122, _, _, _, _, _, _, _, _, _), 1073 [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _), 1074 [124] = PINGROUP(124, _, _, _, _, _, _, _, _, _), 1075 [125] = PINGROUP(125, _, _, _, _, _, _, _, _, _), 1076 [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _), 1077 [127] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x84004, 0, 0), 1078 [128] = SDC_QDSD_PINGROUP(sdc1_clk, 0x84000, 13, 6), 1079 [129] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x84000, 11, 3), 1080 [130] = SDC_QDSD_PINGROUP(sdc1_data, 0x84000, 9, 0), 1081 [131] = SDC_QDSD_PINGROUP(sdc2_clk, 0x86000, 14, 6), 1082 [132] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x86000, 11, 3), 1083 [133] = SDC_QDSD_PINGROUP(sdc2_data, 0x86000, 9, 0), 1084 }; 1085 1086 static const struct msm_gpio_wakeirq_map qcm2290_mpm_map[] = { 1087 { 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 }, 1088 { 13, 18 }, { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 }, 1089 { 25, 71 }, { 27, 73 }, { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 }, 1090 { 34, 56 }, { 35, 57 }, { 36, 58 }, { 39, 28 }, { 46, 29 }, { 62, 60 }, 1091 { 63, 61 }, { 64, 62 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 }, 1092 { 79, 36 }, { 80, 21 }, { 81, 38 }, { 86, 19 }, { 87, 42 }, { 88, 43 }, 1093 { 89, 45 }, { 91, 74 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 }, 1094 }; 1095 1096 static const struct msm_pinctrl_soc_data qcm2290_pinctrl = { 1097 .pins = qcm2290_pins, 1098 .npins = ARRAY_SIZE(qcm2290_pins), 1099 .functions = qcm2290_functions, 1100 .nfunctions = ARRAY_SIZE(qcm2290_functions), 1101 .groups = qcm2290_groups, 1102 .ngroups = ARRAY_SIZE(qcm2290_groups), 1103 .ngpios = 127, 1104 .wakeirq_map = qcm2290_mpm_map, 1105 .nwakeirq_map = ARRAY_SIZE(qcm2290_mpm_map), 1106 }; 1107 1108 static int qcm2290_pinctrl_probe(struct platform_device *pdev) 1109 { 1110 return msm_pinctrl_probe(pdev, &qcm2290_pinctrl); 1111 } 1112 1113 static const struct of_device_id qcm2290_pinctrl_of_match[] = { 1114 { .compatible = "qcom,qcm2290-tlmm", }, 1115 { }, 1116 }; 1117 1118 static struct platform_driver qcm2290_pinctrl_driver = { 1119 .driver = { 1120 .name = "qcm2290-pinctrl", 1121 .of_match_table = qcm2290_pinctrl_of_match, 1122 }, 1123 .probe = qcm2290_pinctrl_probe, 1124 .remove = msm_pinctrl_remove, 1125 }; 1126 1127 static int __init qcm2290_pinctrl_init(void) 1128 { 1129 return platform_driver_register(&qcm2290_pinctrl_driver); 1130 } 1131 arch_initcall(qcm2290_pinctrl_init); 1132 1133 static void __exit qcm2290_pinctrl_exit(void) 1134 { 1135 platform_driver_unregister(&qcm2290_pinctrl_driver); 1136 } 1137 module_exit(qcm2290_pinctrl_exit); 1138 1139 MODULE_DESCRIPTION("QTI QCM2290 pinctrl driver"); 1140 MODULE_LICENSE("GPL v2"); 1141 MODULE_DEVICE_TABLE(of, qcm2290_pinctrl_of_match); 1142