1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2013, Sony Mobile Communications AB. 4 */ 5 #ifndef __PINCTRL_MSM_H__ 6 #define __PINCTRL_MSM_H__ 7 8 #include <linux/pm.h> 9 #include <linux/types.h> 10 11 #include <linux/pinctrl/pinctrl.h> 12 13 struct platform_device; 14 15 struct pinctrl_pin_desc; 16 17 #define APQ_PIN_FUNCTION(fname) \ 18 [APQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ 19 fname##_groups, \ 20 ARRAY_SIZE(fname##_groups)) 21 22 #define IPQ_PIN_FUNCTION(fname) \ 23 [IPQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ 24 fname##_groups, \ 25 ARRAY_SIZE(fname##_groups)) 26 27 #define IPQ_GPIO_PIN_FUNCTION(fname) \ 28 [IPQ_MUX_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \ 29 fname##_groups, \ 30 ARRAY_SIZE(fname##_groups)) 31 32 #define MSM_PIN_FUNCTION(fname) \ 33 [msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ 34 fname##_groups, \ 35 ARRAY_SIZE(fname##_groups)) 36 37 #define MSM_GPIO_PIN_FUNCTION(fname) \ 38 [msm_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \ 39 fname##_groups, \ 40 ARRAY_SIZE(fname##_groups)) 41 42 #define QCA_PIN_FUNCTION(fname) \ 43 [qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ 44 fname##_groups, \ 45 ARRAY_SIZE(fname##_groups)) 46 47 #define QCA_GPIO_PIN_FUNCTION(fname) \ 48 [qca_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \ 49 fname##_groups, \ 50 ARRAY_SIZE(fname##_groups)) 51 52 /** 53 * struct msm_pingroup - Qualcomm pingroup definition 54 * @grp: Generic data of the pin group (name and pins) 55 * @funcs: A list of pinmux functions that can be selected for 56 * this group. The index of the selected function is used 57 * for programming the function selector. 58 * Entries should be indices into the groups list of the 59 * struct msm_pinctrl_soc_data. 60 * @ctl_reg: Offset of the register holding control bits for this group. 61 * @io_reg: Offset of the register holding input/output bits for this group. 62 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. 63 * @intr_status_reg: Offset of the register holding the status bits for this group. 64 * @intr_target_reg: Offset of the register specifying routing of the interrupts 65 * from this group. On most SoCs this register is the same as 66 * @intr_cfg_reg; leaving this field as zero causes the driver 67 * to fall back to @intr_cfg_reg automatically. Only set this 68 * explicitly on older SoCs where the interrupt target routing 69 * lives in a separate register (e.g. APQ8064, MSM8960). 70 * @mux_bit: Offset in @ctl_reg for the pinmux function selection. 71 * @pull_bit: Offset in @ctl_reg for the bias configuration. 72 * @drv_bit: Offset in @ctl_reg for the drive strength configuration. 73 * @od_bit: Offset in @ctl_reg for controlling open drain. 74 * @oe_bit: Offset in @ctl_reg for controlling output enable. 75 * @in_bit: Offset in @io_reg for the input bit value. 76 * @out_bit: Offset in @io_reg for the output bit value. 77 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. 78 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt 79 * status. 80 * @intr_wakeup_present_bit: Offset in @intr_target_reg specifying the GPIO can generate 81 * wakeup events. 82 * @intr_wakeup_enable_bit: Offset in @intr_target_reg to enable wakeup events for the GPIO. 83 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. 84 * @intr_target_width: Number of bits used for specifying interrupt routing target. 85 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from 86 * this gpio should get routed to the KPSS processor. 87 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. 88 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. 89 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. 90 * @intr_detection_width: Number of bits used for specifying interrupt type, 91 * Should be 2 for SoCs that can detect both edges in hardware, 92 * otherwise 1. 93 */ 94 struct msm_pingroup { 95 struct pingroup grp; 96 97 unsigned *funcs; 98 unsigned nfuncs; 99 100 u32 ctl_reg; 101 u32 io_reg; 102 u32 intr_cfg_reg; 103 u32 intr_status_reg; 104 u32 intr_target_reg; 105 106 unsigned int tile:2; 107 108 unsigned mux_bit:5; 109 110 unsigned pull_bit:5; 111 unsigned drv_bit:5; 112 unsigned i2c_pull_bit:5; 113 114 unsigned od_bit:5; 115 unsigned egpio_enable:5; 116 unsigned egpio_present:5; 117 unsigned oe_bit:5; 118 unsigned in_bit:5; 119 unsigned out_bit:5; 120 121 unsigned intr_enable_bit:5; 122 unsigned intr_status_bit:5; 123 unsigned intr_ack_high:1; 124 125 unsigned intr_wakeup_present_bit:5; 126 unsigned intr_wakeup_enable_bit:5; 127 unsigned intr_target_bit:5; 128 unsigned intr_target_width:5; 129 unsigned intr_target_kpss_val:5; 130 unsigned intr_raw_status_bit:5; 131 unsigned intr_polarity_bit:5; 132 unsigned intr_detection_bit:5; 133 unsigned intr_detection_width:5; 134 }; 135 136 /** 137 * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins 138 * @gpio: The GPIOs that are wakeup capable 139 * @wakeirq: The interrupt at the always-on interrupt controller 140 */ 141 struct msm_gpio_wakeirq_map { 142 unsigned int gpio; 143 unsigned int wakeirq; 144 }; 145 146 /** 147 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration 148 * @pins: An array describing all pins the pin controller affects. 149 * @npins: The number of entries in @pins. 150 * @functions: An array describing all mux functions the SoC supports. 151 * @nfunctions: The number of entries in @functions. 152 * @groups: An array describing all pin groups the pin SoC supports. 153 * @ngroups: The numbmer of entries in @groups. 154 * @ngpio: The number of pingroups the driver should expose as GPIOs. 155 * @pull_no_keeper: The SoC does not support keeper bias. 156 * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM 157 * @nwakeirq_map: The number of entries in @wakeirq_map 158 * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need 159 * to be aware that their parent can't handle dual 160 * edge interrupts. 161 * @gpio_func: Which function number is GPIO (usually 0). 162 * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in 163 * hardware this is a mux 1-level above the TLMM, we'll treat 164 * it as if this is just another mux state of the TLMM. Since 165 * it doesn't really map to hardware, we'll allocate a virtual 166 * function number for eGPIO and any time we see that function 167 * number used we'll treat it as a request to mux away from 168 * our TLMM towards another owner. 169 */ 170 struct msm_pinctrl_soc_data { 171 const struct pinctrl_pin_desc *pins; 172 unsigned npins; 173 const struct pinfunction *functions; 174 unsigned nfunctions; 175 const struct msm_pingroup *groups; 176 unsigned ngroups; 177 unsigned ngpios; 178 bool pull_no_keeper; 179 const char *const *tiles; 180 unsigned int ntiles; 181 const int *reserved_gpios; 182 const struct msm_gpio_wakeirq_map *wakeirq_map; 183 unsigned int nwakeirq_map; 184 bool wakeirq_dual_edge_errata; 185 unsigned int gpio_func; 186 unsigned int egpio_func; 187 }; 188 189 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; 190 191 int msm_pinctrl_probe(struct platform_device *pdev, 192 const struct msm_pinctrl_soc_data *soc_data); 193 194 #endif 195