1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2013, Sony Mobile Communications AB. 4 */ 5 #ifndef __PINCTRL_MSM_H__ 6 #define __PINCTRL_MSM_H__ 7 8 #include <linux/pm.h> 9 #include <linux/types.h> 10 11 #include <linux/pinctrl/pinctrl.h> 12 13 struct platform_device; 14 15 struct pinctrl_pin_desc; 16 17 #define APQ_PIN_FUNCTION(fname) \ 18 [APQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ 19 fname##_groups, \ 20 ARRAY_SIZE(fname##_groups)) 21 22 #define IPQ_PIN_FUNCTION(fname) \ 23 [IPQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ 24 fname##_groups, \ 25 ARRAY_SIZE(fname##_groups)) 26 27 #define MSM_PIN_FUNCTION(fname) \ 28 [msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ 29 fname##_groups, \ 30 ARRAY_SIZE(fname##_groups)) 31 32 #define MSM_GPIO_PIN_FUNCTION(fname) \ 33 [msm_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \ 34 fname##_groups, \ 35 ARRAY_SIZE(fname##_groups)) 36 37 #define QCA_PIN_FUNCTION(fname) \ 38 [qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ 39 fname##_groups, \ 40 ARRAY_SIZE(fname##_groups)) 41 42 /** 43 * struct msm_pingroup - Qualcomm pingroup definition 44 * @grp: Generic data of the pin group (name and pins) 45 * @funcs: A list of pinmux functions that can be selected for 46 * this group. The index of the selected function is used 47 * for programming the function selector. 48 * Entries should be indices into the groups list of the 49 * struct msm_pinctrl_soc_data. 50 * @ctl_reg: Offset of the register holding control bits for this group. 51 * @io_reg: Offset of the register holding input/output bits for this group. 52 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. 53 * @intr_status_reg: Offset of the register holding the status bits for this group. 54 * @intr_target_reg: Offset of the register specifying routing of the interrupts 55 * from this group. On most SoCs this register is the same as 56 * @intr_cfg_reg; leaving this field as zero causes the driver 57 * to fall back to @intr_cfg_reg automatically. Only set this 58 * explicitly on older SoCs where the interrupt target routing 59 * lives in a separate register (e.g. APQ8064, MSM8960). 60 * @mux_bit: Offset in @ctl_reg for the pinmux function selection. 61 * @pull_bit: Offset in @ctl_reg for the bias configuration. 62 * @drv_bit: Offset in @ctl_reg for the drive strength configuration. 63 * @od_bit: Offset in @ctl_reg for controlling open drain. 64 * @oe_bit: Offset in @ctl_reg for controlling output enable. 65 * @in_bit: Offset in @io_reg for the input bit value. 66 * @out_bit: Offset in @io_reg for the output bit value. 67 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. 68 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt 69 * status. 70 * @intr_wakeup_present_bit: Offset in @intr_target_reg specifying the GPIO can generate 71 * wakeup events. 72 * @intr_wakeup_enable_bit: Offset in @intr_target_reg to enable wakeup events for the GPIO. 73 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. 74 * @intr_target_width: Number of bits used for specifying interrupt routing target. 75 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from 76 * this gpio should get routed to the KPSS processor. 77 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. 78 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. 79 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. 80 * @intr_detection_width: Number of bits used for specifying interrupt type, 81 * Should be 2 for SoCs that can detect both edges in hardware, 82 * otherwise 1. 83 */ 84 struct msm_pingroup { 85 struct pingroup grp; 86 87 unsigned *funcs; 88 unsigned nfuncs; 89 90 u32 ctl_reg; 91 u32 io_reg; 92 u32 intr_cfg_reg; 93 u32 intr_status_reg; 94 u32 intr_target_reg; 95 96 unsigned int tile:2; 97 98 unsigned mux_bit:5; 99 100 unsigned pull_bit:5; 101 unsigned drv_bit:5; 102 unsigned i2c_pull_bit:5; 103 104 unsigned od_bit:5; 105 unsigned egpio_enable:5; 106 unsigned egpio_present:5; 107 unsigned oe_bit:5; 108 unsigned in_bit:5; 109 unsigned out_bit:5; 110 111 unsigned intr_enable_bit:5; 112 unsigned intr_status_bit:5; 113 unsigned intr_ack_high:1; 114 115 unsigned intr_wakeup_present_bit:5; 116 unsigned intr_wakeup_enable_bit:5; 117 unsigned intr_target_bit:5; 118 unsigned intr_target_width:5; 119 unsigned intr_target_kpss_val:5; 120 unsigned intr_raw_status_bit:5; 121 unsigned intr_polarity_bit:5; 122 unsigned intr_detection_bit:5; 123 unsigned intr_detection_width:5; 124 }; 125 126 /** 127 * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins 128 * @gpio: The GPIOs that are wakeup capable 129 * @wakeirq: The interrupt at the always-on interrupt controller 130 */ 131 struct msm_gpio_wakeirq_map { 132 unsigned int gpio; 133 unsigned int wakeirq; 134 }; 135 136 /** 137 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration 138 * @pins: An array describing all pins the pin controller affects. 139 * @npins: The number of entries in @pins. 140 * @functions: An array describing all mux functions the SoC supports. 141 * @nfunctions: The number of entries in @functions. 142 * @groups: An array describing all pin groups the pin SoC supports. 143 * @ngroups: The numbmer of entries in @groups. 144 * @ngpio: The number of pingroups the driver should expose as GPIOs. 145 * @pull_no_keeper: The SoC does not support keeper bias. 146 * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM 147 * @nwakeirq_map: The number of entries in @wakeirq_map 148 * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need 149 * to be aware that their parent can't handle dual 150 * edge interrupts. 151 * @gpio_func: Which function number is GPIO (usually 0). 152 * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in 153 * hardware this is a mux 1-level above the TLMM, we'll treat 154 * it as if this is just another mux state of the TLMM. Since 155 * it doesn't really map to hardware, we'll allocate a virtual 156 * function number for eGPIO and any time we see that function 157 * number used we'll treat it as a request to mux away from 158 * our TLMM towards another owner. 159 */ 160 struct msm_pinctrl_soc_data { 161 const struct pinctrl_pin_desc *pins; 162 unsigned npins; 163 const struct pinfunction *functions; 164 unsigned nfunctions; 165 const struct msm_pingroup *groups; 166 unsigned ngroups; 167 unsigned ngpios; 168 bool pull_no_keeper; 169 const char *const *tiles; 170 unsigned int ntiles; 171 const int *reserved_gpios; 172 const struct msm_gpio_wakeirq_map *wakeirq_map; 173 unsigned int nwakeirq_map; 174 bool wakeirq_dual_edge_errata; 175 unsigned int gpio_func; 176 unsigned int egpio_func; 177 }; 178 179 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; 180 181 int msm_pinctrl_probe(struct platform_device *pdev, 182 const struct msm_pinctrl_soc_data *soc_data); 183 184 #endif 185