1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2013, Sony Mobile Communications AB. 4 */ 5 #ifndef __PINCTRL_MSM_H__ 6 #define __PINCTRL_MSM_H__ 7 8 #include <linux/pm.h> 9 #include <linux/types.h> 10 11 #include <linux/pinctrl/pinctrl.h> 12 13 struct platform_device; 14 15 struct pinctrl_pin_desc; 16 17 #define APQ_PIN_FUNCTION(fname) \ 18 [APQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ 19 fname##_groups, \ 20 ARRAY_SIZE(fname##_groups)) 21 22 #define IPQ_PIN_FUNCTION(fname) \ 23 [IPQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ 24 fname##_groups, \ 25 ARRAY_SIZE(fname##_groups)) 26 27 #define MSM_PIN_FUNCTION(fname) \ 28 [msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ 29 fname##_groups, \ 30 ARRAY_SIZE(fname##_groups)) 31 32 #define MSM_GPIO_PIN_FUNCTION(fname) \ 33 [msm_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \ 34 fname##_groups, \ 35 ARRAY_SIZE(fname##_groups)) 36 37 #define QCA_PIN_FUNCTION(fname) \ 38 [qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ 39 fname##_groups, \ 40 ARRAY_SIZE(fname##_groups)) 41 42 /** 43 * struct msm_pingroup - Qualcomm pingroup definition 44 * @grp: Generic data of the pin group (name and pins) 45 * @funcs: A list of pinmux functions that can be selected for 46 * this group. The index of the selected function is used 47 * for programming the function selector. 48 * Entries should be indices into the groups list of the 49 * struct msm_pinctrl_soc_data. 50 * @ctl_reg: Offset of the register holding control bits for this group. 51 * @io_reg: Offset of the register holding input/output bits for this group. 52 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. 53 * @intr_status_reg: Offset of the register holding the status bits for this group. 54 * @intr_target_reg: Offset of the register specifying routing of the interrupts 55 * from this group. 56 * @mux_bit: Offset in @ctl_reg for the pinmux function selection. 57 * @pull_bit: Offset in @ctl_reg for the bias configuration. 58 * @drv_bit: Offset in @ctl_reg for the drive strength configuration. 59 * @od_bit: Offset in @ctl_reg for controlling open drain. 60 * @oe_bit: Offset in @ctl_reg for controlling output enable. 61 * @in_bit: Offset in @io_reg for the input bit value. 62 * @out_bit: Offset in @io_reg for the output bit value. 63 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. 64 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt 65 * status. 66 * @intr_wakeup_present_bit: Offset in @intr_target_reg specifying the GPIO can generate 67 * wakeup events. 68 * @intr_wakeup_enable_bit: Offset in @intr_target_reg to enable wakeup events for the GPIO. 69 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. 70 * @intr_target_width: Number of bits used for specifying interrupt routing target. 71 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from 72 * this gpio should get routed to the KPSS processor. 73 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. 74 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. 75 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. 76 * @intr_detection_width: Number of bits used for specifying interrupt type, 77 * Should be 2 for SoCs that can detect both edges in hardware, 78 * otherwise 1. 79 */ 80 struct msm_pingroup { 81 struct pingroup grp; 82 83 unsigned *funcs; 84 unsigned nfuncs; 85 86 u32 ctl_reg; 87 u32 io_reg; 88 u32 intr_cfg_reg; 89 u32 intr_status_reg; 90 u32 intr_target_reg; 91 92 unsigned int tile:2; 93 94 unsigned mux_bit:5; 95 96 unsigned pull_bit:5; 97 unsigned drv_bit:5; 98 unsigned i2c_pull_bit:5; 99 100 unsigned od_bit:5; 101 unsigned egpio_enable:5; 102 unsigned egpio_present:5; 103 unsigned oe_bit:5; 104 unsigned in_bit:5; 105 unsigned out_bit:5; 106 107 unsigned intr_enable_bit:5; 108 unsigned intr_status_bit:5; 109 unsigned intr_ack_high:1; 110 111 unsigned intr_wakeup_present_bit:5; 112 unsigned intr_wakeup_enable_bit:5; 113 unsigned intr_target_bit:5; 114 unsigned intr_target_width:5; 115 unsigned intr_target_kpss_val:5; 116 unsigned intr_raw_status_bit:5; 117 unsigned intr_polarity_bit:5; 118 unsigned intr_detection_bit:5; 119 unsigned intr_detection_width:5; 120 }; 121 122 /** 123 * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins 124 * @gpio: The GPIOs that are wakeup capable 125 * @wakeirq: The interrupt at the always-on interrupt controller 126 */ 127 struct msm_gpio_wakeirq_map { 128 unsigned int gpio; 129 unsigned int wakeirq; 130 }; 131 132 /** 133 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration 134 * @pins: An array describing all pins the pin controller affects. 135 * @npins: The number of entries in @pins. 136 * @functions: An array describing all mux functions the SoC supports. 137 * @nfunctions: The number of entries in @functions. 138 * @groups: An array describing all pin groups the pin SoC supports. 139 * @ngroups: The numbmer of entries in @groups. 140 * @ngpio: The number of pingroups the driver should expose as GPIOs. 141 * @pull_no_keeper: The SoC does not support keeper bias. 142 * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM 143 * @nwakeirq_map: The number of entries in @wakeirq_map 144 * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need 145 * to be aware that their parent can't handle dual 146 * edge interrupts. 147 * @gpio_func: Which function number is GPIO (usually 0). 148 * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in 149 * hardware this is a mux 1-level above the TLMM, we'll treat 150 * it as if this is just another mux state of the TLMM. Since 151 * it doesn't really map to hardware, we'll allocate a virtual 152 * function number for eGPIO and any time we see that function 153 * number used we'll treat it as a request to mux away from 154 * our TLMM towards another owner. 155 */ 156 struct msm_pinctrl_soc_data { 157 const struct pinctrl_pin_desc *pins; 158 unsigned npins; 159 const struct pinfunction *functions; 160 unsigned nfunctions; 161 const struct msm_pingroup *groups; 162 unsigned ngroups; 163 unsigned ngpios; 164 bool pull_no_keeper; 165 const char *const *tiles; 166 unsigned int ntiles; 167 const int *reserved_gpios; 168 const struct msm_gpio_wakeirq_map *wakeirq_map; 169 unsigned int nwakeirq_map; 170 bool wakeirq_dual_edge_errata; 171 unsigned int gpio_func; 172 unsigned int egpio_func; 173 }; 174 175 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; 176 177 int msm_pinctrl_probe(struct platform_device *pdev, 178 const struct msm_pinctrl_soc_data *soc_data); 179 180 #endif 181