1 /* 2 * Copyright (c) 2013, Sony Mobile Communications AB. 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 and 7 * only version 2 as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 #include <linux/slab.h> 27 #include <linux/gpio.h> 28 #include <linux/interrupt.h> 29 #include <linux/spinlock.h> 30 #include <linux/reboot.h> 31 32 #include "../core.h" 33 #include "../pinconf.h" 34 #include "pinctrl-msm.h" 35 #include "../pinctrl-utils.h" 36 37 #define MAX_NR_GPIO 300 38 #define PS_HOLD_OFFSET 0x820 39 40 /** 41 * struct msm_pinctrl - state for a pinctrl-msm device 42 * @dev: device handle. 43 * @pctrl: pinctrl handle. 44 * @chip: gpiochip handle. 45 * @restart_nb: restart notifier block. 46 * @irq: parent irq for the TLMM irq_chip. 47 * @lock: Spinlock to protect register resources as well 48 * as msm_pinctrl data structures. 49 * @enabled_irqs: Bitmap of currently enabled irqs. 50 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge 51 * detection. 52 * @soc; Reference to soc_data of platform specific data. 53 * @regs: Base address for the TLMM register map. 54 */ 55 struct msm_pinctrl { 56 struct device *dev; 57 struct pinctrl_dev *pctrl; 58 struct gpio_chip chip; 59 struct notifier_block restart_nb; 60 int irq; 61 62 spinlock_t lock; 63 64 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); 65 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); 66 67 const struct msm_pinctrl_soc_data *soc; 68 void __iomem *regs; 69 }; 70 71 static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc) 72 { 73 return container_of(gc, struct msm_pinctrl, chip); 74 } 75 76 static int msm_get_groups_count(struct pinctrl_dev *pctldev) 77 { 78 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 79 80 return pctrl->soc->ngroups; 81 } 82 83 static const char *msm_get_group_name(struct pinctrl_dev *pctldev, 84 unsigned group) 85 { 86 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 87 88 return pctrl->soc->groups[group].name; 89 } 90 91 static int msm_get_group_pins(struct pinctrl_dev *pctldev, 92 unsigned group, 93 const unsigned **pins, 94 unsigned *num_pins) 95 { 96 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 97 98 *pins = pctrl->soc->groups[group].pins; 99 *num_pins = pctrl->soc->groups[group].npins; 100 return 0; 101 } 102 103 static const struct pinctrl_ops msm_pinctrl_ops = { 104 .get_groups_count = msm_get_groups_count, 105 .get_group_name = msm_get_group_name, 106 .get_group_pins = msm_get_group_pins, 107 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 108 .dt_free_map = pinctrl_utils_dt_free_map, 109 }; 110 111 static int msm_get_functions_count(struct pinctrl_dev *pctldev) 112 { 113 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 114 115 return pctrl->soc->nfunctions; 116 } 117 118 static const char *msm_get_function_name(struct pinctrl_dev *pctldev, 119 unsigned function) 120 { 121 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 122 123 return pctrl->soc->functions[function].name; 124 } 125 126 static int msm_get_function_groups(struct pinctrl_dev *pctldev, 127 unsigned function, 128 const char * const **groups, 129 unsigned * const num_groups) 130 { 131 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 132 133 *groups = pctrl->soc->functions[function].groups; 134 *num_groups = pctrl->soc->functions[function].ngroups; 135 return 0; 136 } 137 138 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, 139 unsigned function, 140 unsigned group) 141 { 142 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 143 const struct msm_pingroup *g; 144 unsigned long flags; 145 u32 val; 146 int i; 147 148 g = &pctrl->soc->groups[group]; 149 150 for (i = 0; i < g->nfuncs; i++) { 151 if (g->funcs[i] == function) 152 break; 153 } 154 155 if (WARN_ON(i == g->nfuncs)) 156 return -EINVAL; 157 158 spin_lock_irqsave(&pctrl->lock, flags); 159 160 val = readl(pctrl->regs + g->ctl_reg); 161 val &= ~(0x7 << g->mux_bit); 162 val |= i << g->mux_bit; 163 writel(val, pctrl->regs + g->ctl_reg); 164 165 spin_unlock_irqrestore(&pctrl->lock, flags); 166 167 return 0; 168 } 169 170 static const struct pinmux_ops msm_pinmux_ops = { 171 .get_functions_count = msm_get_functions_count, 172 .get_function_name = msm_get_function_name, 173 .get_function_groups = msm_get_function_groups, 174 .set_mux = msm_pinmux_set_mux, 175 }; 176 177 static int msm_config_reg(struct msm_pinctrl *pctrl, 178 const struct msm_pingroup *g, 179 unsigned param, 180 unsigned *mask, 181 unsigned *bit) 182 { 183 switch (param) { 184 case PIN_CONFIG_BIAS_DISABLE: 185 case PIN_CONFIG_BIAS_PULL_DOWN: 186 case PIN_CONFIG_BIAS_BUS_HOLD: 187 case PIN_CONFIG_BIAS_PULL_UP: 188 *bit = g->pull_bit; 189 *mask = 3; 190 break; 191 case PIN_CONFIG_DRIVE_STRENGTH: 192 *bit = g->drv_bit; 193 *mask = 7; 194 break; 195 case PIN_CONFIG_OUTPUT: 196 *bit = g->oe_bit; 197 *mask = 1; 198 break; 199 default: 200 dev_err(pctrl->dev, "Invalid config param %04x\n", param); 201 return -ENOTSUPP; 202 } 203 204 return 0; 205 } 206 207 #define MSM_NO_PULL 0 208 #define MSM_PULL_DOWN 1 209 #define MSM_KEEPER 2 210 #define MSM_PULL_UP 3 211 212 static unsigned msm_regval_to_drive(u32 val) 213 { 214 return (val + 1) * 2; 215 } 216 217 static int msm_config_group_get(struct pinctrl_dev *pctldev, 218 unsigned int group, 219 unsigned long *config) 220 { 221 const struct msm_pingroup *g; 222 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 223 unsigned param = pinconf_to_config_param(*config); 224 unsigned mask; 225 unsigned arg; 226 unsigned bit; 227 int ret; 228 u32 val; 229 230 g = &pctrl->soc->groups[group]; 231 232 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 233 if (ret < 0) 234 return ret; 235 236 val = readl(pctrl->regs + g->ctl_reg); 237 arg = (val >> bit) & mask; 238 239 /* Convert register value to pinconf value */ 240 switch (param) { 241 case PIN_CONFIG_BIAS_DISABLE: 242 arg = arg == MSM_NO_PULL; 243 break; 244 case PIN_CONFIG_BIAS_PULL_DOWN: 245 arg = arg == MSM_PULL_DOWN; 246 break; 247 case PIN_CONFIG_BIAS_BUS_HOLD: 248 arg = arg == MSM_KEEPER; 249 break; 250 case PIN_CONFIG_BIAS_PULL_UP: 251 arg = arg == MSM_PULL_UP; 252 break; 253 case PIN_CONFIG_DRIVE_STRENGTH: 254 arg = msm_regval_to_drive(arg); 255 break; 256 case PIN_CONFIG_OUTPUT: 257 /* Pin is not output */ 258 if (!arg) 259 return -EINVAL; 260 261 val = readl(pctrl->regs + g->io_reg); 262 arg = !!(val & BIT(g->in_bit)); 263 break; 264 default: 265 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 266 param); 267 return -EINVAL; 268 } 269 270 *config = pinconf_to_config_packed(param, arg); 271 272 return 0; 273 } 274 275 static int msm_config_group_set(struct pinctrl_dev *pctldev, 276 unsigned group, 277 unsigned long *configs, 278 unsigned num_configs) 279 { 280 const struct msm_pingroup *g; 281 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 282 unsigned long flags; 283 unsigned param; 284 unsigned mask; 285 unsigned arg; 286 unsigned bit; 287 int ret; 288 u32 val; 289 int i; 290 291 g = &pctrl->soc->groups[group]; 292 293 for (i = 0; i < num_configs; i++) { 294 param = pinconf_to_config_param(configs[i]); 295 arg = pinconf_to_config_argument(configs[i]); 296 297 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 298 if (ret < 0) 299 return ret; 300 301 /* Convert pinconf values to register values */ 302 switch (param) { 303 case PIN_CONFIG_BIAS_DISABLE: 304 arg = MSM_NO_PULL; 305 break; 306 case PIN_CONFIG_BIAS_PULL_DOWN: 307 arg = MSM_PULL_DOWN; 308 break; 309 case PIN_CONFIG_BIAS_BUS_HOLD: 310 arg = MSM_KEEPER; 311 break; 312 case PIN_CONFIG_BIAS_PULL_UP: 313 arg = MSM_PULL_UP; 314 break; 315 case PIN_CONFIG_DRIVE_STRENGTH: 316 /* Check for invalid values */ 317 if (arg > 16 || arg < 2 || (arg % 2) != 0) 318 arg = -1; 319 else 320 arg = (arg / 2) - 1; 321 break; 322 case PIN_CONFIG_OUTPUT: 323 /* set output value */ 324 spin_lock_irqsave(&pctrl->lock, flags); 325 val = readl(pctrl->regs + g->io_reg); 326 if (arg) 327 val |= BIT(g->out_bit); 328 else 329 val &= ~BIT(g->out_bit); 330 writel(val, pctrl->regs + g->io_reg); 331 spin_unlock_irqrestore(&pctrl->lock, flags); 332 333 /* enable output */ 334 arg = 1; 335 break; 336 default: 337 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 338 param); 339 return -EINVAL; 340 } 341 342 /* Range-check user-supplied value */ 343 if (arg & ~mask) { 344 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); 345 return -EINVAL; 346 } 347 348 spin_lock_irqsave(&pctrl->lock, flags); 349 val = readl(pctrl->regs + g->ctl_reg); 350 val &= ~(mask << bit); 351 val |= arg << bit; 352 writel(val, pctrl->regs + g->ctl_reg); 353 spin_unlock_irqrestore(&pctrl->lock, flags); 354 } 355 356 return 0; 357 } 358 359 static const struct pinconf_ops msm_pinconf_ops = { 360 .pin_config_group_get = msm_config_group_get, 361 .pin_config_group_set = msm_config_group_set, 362 }; 363 364 static struct pinctrl_desc msm_pinctrl_desc = { 365 .pctlops = &msm_pinctrl_ops, 366 .pmxops = &msm_pinmux_ops, 367 .confops = &msm_pinconf_ops, 368 .owner = THIS_MODULE, 369 }; 370 371 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 372 { 373 const struct msm_pingroup *g; 374 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 375 unsigned long flags; 376 u32 val; 377 378 g = &pctrl->soc->groups[offset]; 379 380 spin_lock_irqsave(&pctrl->lock, flags); 381 382 val = readl(pctrl->regs + g->ctl_reg); 383 val &= ~BIT(g->oe_bit); 384 writel(val, pctrl->regs + g->ctl_reg); 385 386 spin_unlock_irqrestore(&pctrl->lock, flags); 387 388 return 0; 389 } 390 391 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) 392 { 393 const struct msm_pingroup *g; 394 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 395 unsigned long flags; 396 u32 val; 397 398 g = &pctrl->soc->groups[offset]; 399 400 spin_lock_irqsave(&pctrl->lock, flags); 401 402 val = readl(pctrl->regs + g->io_reg); 403 if (value) 404 val |= BIT(g->out_bit); 405 else 406 val &= ~BIT(g->out_bit); 407 writel(val, pctrl->regs + g->io_reg); 408 409 val = readl(pctrl->regs + g->ctl_reg); 410 val |= BIT(g->oe_bit); 411 writel(val, pctrl->regs + g->ctl_reg); 412 413 spin_unlock_irqrestore(&pctrl->lock, flags); 414 415 return 0; 416 } 417 418 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) 419 { 420 const struct msm_pingroup *g; 421 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 422 u32 val; 423 424 g = &pctrl->soc->groups[offset]; 425 426 val = readl(pctrl->regs + g->io_reg); 427 return !!(val & BIT(g->in_bit)); 428 } 429 430 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 431 { 432 const struct msm_pingroup *g; 433 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 434 unsigned long flags; 435 u32 val; 436 437 g = &pctrl->soc->groups[offset]; 438 439 spin_lock_irqsave(&pctrl->lock, flags); 440 441 val = readl(pctrl->regs + g->io_reg); 442 if (value) 443 val |= BIT(g->out_bit); 444 else 445 val &= ~BIT(g->out_bit); 446 writel(val, pctrl->regs + g->io_reg); 447 448 spin_unlock_irqrestore(&pctrl->lock, flags); 449 } 450 451 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) 452 { 453 int gpio = chip->base + offset; 454 return pinctrl_request_gpio(gpio); 455 } 456 457 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) 458 { 459 int gpio = chip->base + offset; 460 return pinctrl_free_gpio(gpio); 461 } 462 463 #ifdef CONFIG_DEBUG_FS 464 #include <linux/seq_file.h> 465 466 static void msm_gpio_dbg_show_one(struct seq_file *s, 467 struct pinctrl_dev *pctldev, 468 struct gpio_chip *chip, 469 unsigned offset, 470 unsigned gpio) 471 { 472 const struct msm_pingroup *g; 473 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); 474 unsigned func; 475 int is_out; 476 int drive; 477 int pull; 478 u32 ctl_reg; 479 480 static const char * const pulls[] = { 481 "no pull", 482 "pull down", 483 "keeper", 484 "pull up" 485 }; 486 487 g = &pctrl->soc->groups[offset]; 488 ctl_reg = readl(pctrl->regs + g->ctl_reg); 489 490 is_out = !!(ctl_reg & BIT(g->oe_bit)); 491 func = (ctl_reg >> g->mux_bit) & 7; 492 drive = (ctl_reg >> g->drv_bit) & 7; 493 pull = (ctl_reg >> g->pull_bit) & 3; 494 495 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); 496 seq_printf(s, " %dmA", msm_regval_to_drive(drive)); 497 seq_printf(s, " %s", pulls[pull]); 498 } 499 500 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 501 { 502 unsigned gpio = chip->base; 503 unsigned i; 504 505 for (i = 0; i < chip->ngpio; i++, gpio++) { 506 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); 507 seq_puts(s, "\n"); 508 } 509 } 510 511 #else 512 #define msm_gpio_dbg_show NULL 513 #endif 514 515 static struct gpio_chip msm_gpio_template = { 516 .direction_input = msm_gpio_direction_input, 517 .direction_output = msm_gpio_direction_output, 518 .get = msm_gpio_get, 519 .set = msm_gpio_set, 520 .request = msm_gpio_request, 521 .free = msm_gpio_free, 522 .dbg_show = msm_gpio_dbg_show, 523 }; 524 525 /* For dual-edge interrupts in software, since some hardware has no 526 * such support: 527 * 528 * At appropriate moments, this function may be called to flip the polarity 529 * settings of both-edge irq lines to try and catch the next edge. 530 * 531 * The attempt is considered successful if: 532 * - the status bit goes high, indicating that an edge was caught, or 533 * - the input value of the gpio doesn't change during the attempt. 534 * If the value changes twice during the process, that would cause the first 535 * test to fail but would force the second, as two opposite 536 * transitions would cause a detection no matter the polarity setting. 537 * 538 * The do-loop tries to sledge-hammer closed the timing hole between 539 * the initial value-read and the polarity-write - if the line value changes 540 * during that window, an interrupt is lost, the new polarity setting is 541 * incorrect, and the first success test will fail, causing a retry. 542 * 543 * Algorithm comes from Google's msmgpio driver. 544 */ 545 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, 546 const struct msm_pingroup *g, 547 struct irq_data *d) 548 { 549 int loop_limit = 100; 550 unsigned val, val2, intstat; 551 unsigned pol; 552 553 do { 554 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 555 556 pol = readl(pctrl->regs + g->intr_cfg_reg); 557 pol ^= BIT(g->intr_polarity_bit); 558 writel(pol, pctrl->regs + g->intr_cfg_reg); 559 560 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); 561 intstat = readl(pctrl->regs + g->intr_status_reg); 562 if (intstat || (val == val2)) 563 return; 564 } while (loop_limit-- > 0); 565 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", 566 val, val2); 567 } 568 569 static void msm_gpio_irq_mask(struct irq_data *d) 570 { 571 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 572 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 573 const struct msm_pingroup *g; 574 unsigned long flags; 575 u32 val; 576 577 g = &pctrl->soc->groups[d->hwirq]; 578 579 spin_lock_irqsave(&pctrl->lock, flags); 580 581 val = readl(pctrl->regs + g->intr_cfg_reg); 582 val &= ~BIT(g->intr_enable_bit); 583 writel(val, pctrl->regs + g->intr_cfg_reg); 584 585 clear_bit(d->hwirq, pctrl->enabled_irqs); 586 587 spin_unlock_irqrestore(&pctrl->lock, flags); 588 } 589 590 static void msm_gpio_irq_unmask(struct irq_data *d) 591 { 592 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 593 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 594 const struct msm_pingroup *g; 595 unsigned long flags; 596 u32 val; 597 598 g = &pctrl->soc->groups[d->hwirq]; 599 600 spin_lock_irqsave(&pctrl->lock, flags); 601 602 val = readl(pctrl->regs + g->intr_status_reg); 603 val &= ~BIT(g->intr_status_bit); 604 writel(val, pctrl->regs + g->intr_status_reg); 605 606 val = readl(pctrl->regs + g->intr_cfg_reg); 607 val |= BIT(g->intr_enable_bit); 608 writel(val, pctrl->regs + g->intr_cfg_reg); 609 610 set_bit(d->hwirq, pctrl->enabled_irqs); 611 612 spin_unlock_irqrestore(&pctrl->lock, flags); 613 } 614 615 static void msm_gpio_irq_ack(struct irq_data *d) 616 { 617 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 618 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 619 const struct msm_pingroup *g; 620 unsigned long flags; 621 u32 val; 622 623 g = &pctrl->soc->groups[d->hwirq]; 624 625 spin_lock_irqsave(&pctrl->lock, flags); 626 627 val = readl(pctrl->regs + g->intr_status_reg); 628 if (g->intr_ack_high) 629 val |= BIT(g->intr_status_bit); 630 else 631 val &= ~BIT(g->intr_status_bit); 632 writel(val, pctrl->regs + g->intr_status_reg); 633 634 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 635 msm_gpio_update_dual_edge_pos(pctrl, g, d); 636 637 spin_unlock_irqrestore(&pctrl->lock, flags); 638 } 639 640 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 641 { 642 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 643 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 644 const struct msm_pingroup *g; 645 unsigned long flags; 646 u32 val; 647 648 g = &pctrl->soc->groups[d->hwirq]; 649 650 spin_lock_irqsave(&pctrl->lock, flags); 651 652 /* 653 * For hw without possibility of detecting both edges 654 */ 655 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) 656 set_bit(d->hwirq, pctrl->dual_edge_irqs); 657 else 658 clear_bit(d->hwirq, pctrl->dual_edge_irqs); 659 660 /* Route interrupts to application cpu */ 661 val = readl(pctrl->regs + g->intr_target_reg); 662 val &= ~(7 << g->intr_target_bit); 663 val |= g->intr_target_kpss_val << g->intr_target_bit; 664 writel(val, pctrl->regs + g->intr_target_reg); 665 666 /* Update configuration for gpio. 667 * RAW_STATUS_EN is left on for all gpio irqs. Due to the 668 * internal circuitry of TLMM, toggling the RAW_STATUS 669 * could cause the INTR_STATUS to be set for EDGE interrupts. 670 */ 671 val = readl(pctrl->regs + g->intr_cfg_reg); 672 val |= BIT(g->intr_raw_status_bit); 673 if (g->intr_detection_width == 2) { 674 val &= ~(3 << g->intr_detection_bit); 675 val &= ~(1 << g->intr_polarity_bit); 676 switch (type) { 677 case IRQ_TYPE_EDGE_RISING: 678 val |= 1 << g->intr_detection_bit; 679 val |= BIT(g->intr_polarity_bit); 680 break; 681 case IRQ_TYPE_EDGE_FALLING: 682 val |= 2 << g->intr_detection_bit; 683 val |= BIT(g->intr_polarity_bit); 684 break; 685 case IRQ_TYPE_EDGE_BOTH: 686 val |= 3 << g->intr_detection_bit; 687 val |= BIT(g->intr_polarity_bit); 688 break; 689 case IRQ_TYPE_LEVEL_LOW: 690 break; 691 case IRQ_TYPE_LEVEL_HIGH: 692 val |= BIT(g->intr_polarity_bit); 693 break; 694 } 695 } else if (g->intr_detection_width == 1) { 696 val &= ~(1 << g->intr_detection_bit); 697 val &= ~(1 << g->intr_polarity_bit); 698 switch (type) { 699 case IRQ_TYPE_EDGE_RISING: 700 val |= BIT(g->intr_detection_bit); 701 val |= BIT(g->intr_polarity_bit); 702 break; 703 case IRQ_TYPE_EDGE_FALLING: 704 val |= BIT(g->intr_detection_bit); 705 break; 706 case IRQ_TYPE_EDGE_BOTH: 707 val |= BIT(g->intr_detection_bit); 708 val |= BIT(g->intr_polarity_bit); 709 break; 710 case IRQ_TYPE_LEVEL_LOW: 711 break; 712 case IRQ_TYPE_LEVEL_HIGH: 713 val |= BIT(g->intr_polarity_bit); 714 break; 715 } 716 } else { 717 BUG(); 718 } 719 writel(val, pctrl->regs + g->intr_cfg_reg); 720 721 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 722 msm_gpio_update_dual_edge_pos(pctrl, g, d); 723 724 spin_unlock_irqrestore(&pctrl->lock, flags); 725 726 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 727 __irq_set_handler_locked(d->irq, handle_level_irq); 728 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 729 __irq_set_handler_locked(d->irq, handle_edge_irq); 730 731 return 0; 732 } 733 734 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 735 { 736 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 737 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 738 unsigned long flags; 739 740 spin_lock_irqsave(&pctrl->lock, flags); 741 742 irq_set_irq_wake(pctrl->irq, on); 743 744 spin_unlock_irqrestore(&pctrl->lock, flags); 745 746 return 0; 747 } 748 749 static struct irq_chip msm_gpio_irq_chip = { 750 .name = "msmgpio", 751 .irq_mask = msm_gpio_irq_mask, 752 .irq_unmask = msm_gpio_irq_unmask, 753 .irq_ack = msm_gpio_irq_ack, 754 .irq_set_type = msm_gpio_irq_set_type, 755 .irq_set_wake = msm_gpio_irq_set_wake, 756 }; 757 758 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 759 { 760 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 761 const struct msm_pingroup *g; 762 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 763 struct irq_chip *chip = irq_get_chip(irq); 764 int irq_pin; 765 int handled = 0; 766 u32 val; 767 int i; 768 769 chained_irq_enter(chip, desc); 770 771 /* 772 * Each pin has it's own IRQ status register, so use 773 * enabled_irq bitmap to limit the number of reads. 774 */ 775 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { 776 g = &pctrl->soc->groups[i]; 777 val = readl(pctrl->regs + g->intr_status_reg); 778 if (val & BIT(g->intr_status_bit)) { 779 irq_pin = irq_find_mapping(gc->irqdomain, i); 780 generic_handle_irq(irq_pin); 781 handled++; 782 } 783 } 784 785 /* No interrupts were flagged */ 786 if (handled == 0) 787 handle_bad_irq(irq, desc); 788 789 chained_irq_exit(chip, desc); 790 } 791 792 static int msm_gpio_init(struct msm_pinctrl *pctrl) 793 { 794 struct gpio_chip *chip; 795 int ret; 796 unsigned ngpio = pctrl->soc->ngpios; 797 798 if (WARN_ON(ngpio > MAX_NR_GPIO)) 799 return -EINVAL; 800 801 chip = &pctrl->chip; 802 chip->base = 0; 803 chip->ngpio = ngpio; 804 chip->label = dev_name(pctrl->dev); 805 chip->dev = pctrl->dev; 806 chip->owner = THIS_MODULE; 807 chip->of_node = pctrl->dev->of_node; 808 809 ret = gpiochip_add(&pctrl->chip); 810 if (ret) { 811 dev_err(pctrl->dev, "Failed register gpiochip\n"); 812 return ret; 813 } 814 815 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); 816 if (ret) { 817 dev_err(pctrl->dev, "Failed to add pin range\n"); 818 gpiochip_remove(&pctrl->chip); 819 return ret; 820 } 821 822 ret = gpiochip_irqchip_add(chip, 823 &msm_gpio_irq_chip, 824 0, 825 handle_edge_irq, 826 IRQ_TYPE_NONE); 827 if (ret) { 828 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); 829 gpiochip_remove(&pctrl->chip); 830 return -ENOSYS; 831 } 832 833 gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, 834 msm_gpio_irq_handler); 835 836 return 0; 837 } 838 839 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, 840 void *data) 841 { 842 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); 843 844 writel(0, pctrl->regs + PS_HOLD_OFFSET); 845 mdelay(1000); 846 return NOTIFY_DONE; 847 } 848 849 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) 850 { 851 int i; 852 const struct msm_function *func = pctrl->soc->functions; 853 854 for (i = 0; i < pctrl->soc->nfunctions; i++) 855 if (!strcmp(func[i].name, "ps_hold")) { 856 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; 857 pctrl->restart_nb.priority = 128; 858 if (register_restart_handler(&pctrl->restart_nb)) 859 dev_err(pctrl->dev, 860 "failed to setup restart handler.\n"); 861 break; 862 } 863 } 864 865 int msm_pinctrl_probe(struct platform_device *pdev, 866 const struct msm_pinctrl_soc_data *soc_data) 867 { 868 struct msm_pinctrl *pctrl; 869 struct resource *res; 870 int ret; 871 872 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 873 if (!pctrl) { 874 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); 875 return -ENOMEM; 876 } 877 pctrl->dev = &pdev->dev; 878 pctrl->soc = soc_data; 879 pctrl->chip = msm_gpio_template; 880 881 spin_lock_init(&pctrl->lock); 882 883 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 884 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 885 if (IS_ERR(pctrl->regs)) 886 return PTR_ERR(pctrl->regs); 887 888 msm_pinctrl_setup_pm_reset(pctrl); 889 890 pctrl->irq = platform_get_irq(pdev, 0); 891 if (pctrl->irq < 0) { 892 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); 893 return pctrl->irq; 894 } 895 896 msm_pinctrl_desc.name = dev_name(&pdev->dev); 897 msm_pinctrl_desc.pins = pctrl->soc->pins; 898 msm_pinctrl_desc.npins = pctrl->soc->npins; 899 pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); 900 if (!pctrl->pctrl) { 901 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 902 return -ENODEV; 903 } 904 905 ret = msm_gpio_init(pctrl); 906 if (ret) { 907 pinctrl_unregister(pctrl->pctrl); 908 return ret; 909 } 910 911 platform_set_drvdata(pdev, pctrl); 912 913 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); 914 915 return 0; 916 } 917 EXPORT_SYMBOL(msm_pinctrl_probe); 918 919 int msm_pinctrl_remove(struct platform_device *pdev) 920 { 921 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); 922 923 gpiochip_remove(&pctrl->chip); 924 pinctrl_unregister(pctrl->pctrl); 925 926 unregister_restart_handler(&pctrl->restart_nb); 927 928 return 0; 929 } 930 EXPORT_SYMBOL(msm_pinctrl_remove); 931 932