1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 11 #include "pinctrl-msm.h" 12 13 #define REG_SIZE 0x1000 14 15 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ 16 { \ 17 .grp = PINCTRL_PINGROUP("gpio" #id, \ 18 gpio##id##_pins, \ 19 ARRAY_SIZE(gpio##id##_pins)), \ 20 .funcs = (int[]){ \ 21 msm_mux_gpio, /* gpio mode */ \ 22 msm_mux_##f1, \ 23 msm_mux_##f2, \ 24 msm_mux_##f3, \ 25 msm_mux_##f4, \ 26 msm_mux_##f5, \ 27 msm_mux_##f6, \ 28 msm_mux_##f7, \ 29 msm_mux_##f8, \ 30 msm_mux_##f9, \ 31 msm_mux_##f10, \ 32 msm_mux_##f11 /* egpio mode */ \ 33 }, \ 34 .nfuncs = 12, \ 35 .ctl_reg = REG_SIZE * id, \ 36 .io_reg = 0x4 + REG_SIZE * id, \ 37 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 38 .intr_status_reg = 0xc + REG_SIZE * id, \ 39 .intr_target_reg = 0x8 + REG_SIZE * id, \ 40 .mux_bit = 2, \ 41 .pull_bit = 0, \ 42 .drv_bit = 6, \ 43 .i2c_pull_bit = 13, \ 44 .egpio_enable = 12, \ 45 .egpio_present = 11, \ 46 .oe_bit = 9, \ 47 .in_bit = 0, \ 48 .out_bit = 1, \ 49 .intr_enable_bit = 0, \ 50 .intr_status_bit = 0, \ 51 .intr_target_bit = 8, \ 52 .intr_wakeup_enable_bit = 7, \ 53 .intr_wakeup_present_bit = 6, \ 54 .intr_target_kpss_val = 3, \ 55 .intr_raw_status_bit = 4, \ 56 .intr_polarity_bit = 1, \ 57 .intr_detection_bit = 2, \ 58 .intr_detection_width = 2, \ 59 } 60 61 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 62 { \ 63 .grp = PINCTRL_PINGROUP(#pg_name, \ 64 pg_name##_pins, \ 65 ARRAY_SIZE(pg_name##_pins)), \ 66 .ctl_reg = ctl, \ 67 .io_reg = 0, \ 68 .intr_cfg_reg = 0, \ 69 .intr_status_reg = 0, \ 70 .intr_target_reg = 0, \ 71 .mux_bit = -1, \ 72 .pull_bit = pull, \ 73 .drv_bit = drv, \ 74 .oe_bit = -1, \ 75 .in_bit = -1, \ 76 .out_bit = -1, \ 77 .intr_enable_bit = -1, \ 78 .intr_status_bit = -1, \ 79 .intr_target_bit = -1, \ 80 .intr_raw_status_bit = -1, \ 81 .intr_polarity_bit = -1, \ 82 .intr_detection_bit = -1, \ 83 .intr_detection_width = -1, \ 84 } 85 86 #define UFS_RESET(pg_name, ctl, io) \ 87 { \ 88 .grp = PINCTRL_PINGROUP(#pg_name, \ 89 pg_name##_pins, \ 90 ARRAY_SIZE(pg_name##_pins)), \ 91 .ctl_reg = ctl, \ 92 .io_reg = io, \ 93 .intr_cfg_reg = 0, \ 94 .intr_status_reg = 0, \ 95 .intr_target_reg = 0, \ 96 .mux_bit = -1, \ 97 .pull_bit = 3, \ 98 .drv_bit = 0, \ 99 .oe_bit = -1, \ 100 .in_bit = -1, \ 101 .out_bit = 0, \ 102 .intr_enable_bit = -1, \ 103 .intr_status_bit = -1, \ 104 .intr_target_bit = -1, \ 105 .intr_raw_status_bit = -1, \ 106 .intr_polarity_bit = -1, \ 107 .intr_detection_bit = -1, \ 108 .intr_detection_width = -1, \ 109 } 110 111 static const struct pinctrl_pin_desc milos_pins[] = { 112 PINCTRL_PIN(0, "GPIO_0"), 113 PINCTRL_PIN(1, "GPIO_1"), 114 PINCTRL_PIN(2, "GPIO_2"), 115 PINCTRL_PIN(3, "GPIO_3"), 116 PINCTRL_PIN(4, "GPIO_4"), 117 PINCTRL_PIN(5, "GPIO_5"), 118 PINCTRL_PIN(6, "GPIO_6"), 119 PINCTRL_PIN(7, "GPIO_7"), 120 PINCTRL_PIN(8, "GPIO_8"), 121 PINCTRL_PIN(9, "GPIO_9"), 122 PINCTRL_PIN(10, "GPIO_10"), 123 PINCTRL_PIN(11, "GPIO_11"), 124 PINCTRL_PIN(12, "GPIO_12"), 125 PINCTRL_PIN(13, "GPIO_13"), 126 PINCTRL_PIN(14, "GPIO_14"), 127 PINCTRL_PIN(15, "GPIO_15"), 128 PINCTRL_PIN(16, "GPIO_16"), 129 PINCTRL_PIN(17, "GPIO_17"), 130 PINCTRL_PIN(18, "GPIO_18"), 131 PINCTRL_PIN(19, "GPIO_19"), 132 PINCTRL_PIN(20, "GPIO_20"), 133 PINCTRL_PIN(21, "GPIO_21"), 134 PINCTRL_PIN(22, "GPIO_22"), 135 PINCTRL_PIN(23, "GPIO_23"), 136 PINCTRL_PIN(24, "GPIO_24"), 137 PINCTRL_PIN(25, "GPIO_25"), 138 PINCTRL_PIN(26, "GPIO_26"), 139 PINCTRL_PIN(27, "GPIO_27"), 140 PINCTRL_PIN(28, "GPIO_28"), 141 PINCTRL_PIN(29, "GPIO_29"), 142 PINCTRL_PIN(30, "GPIO_30"), 143 PINCTRL_PIN(31, "GPIO_31"), 144 PINCTRL_PIN(32, "GPIO_32"), 145 PINCTRL_PIN(33, "GPIO_33"), 146 PINCTRL_PIN(34, "GPIO_34"), 147 PINCTRL_PIN(35, "GPIO_35"), 148 PINCTRL_PIN(36, "GPIO_36"), 149 PINCTRL_PIN(37, "GPIO_37"), 150 PINCTRL_PIN(38, "GPIO_38"), 151 PINCTRL_PIN(39, "GPIO_39"), 152 PINCTRL_PIN(40, "GPIO_40"), 153 PINCTRL_PIN(41, "GPIO_41"), 154 PINCTRL_PIN(42, "GPIO_42"), 155 PINCTRL_PIN(43, "GPIO_43"), 156 PINCTRL_PIN(44, "GPIO_44"), 157 PINCTRL_PIN(45, "GPIO_45"), 158 PINCTRL_PIN(46, "GPIO_46"), 159 PINCTRL_PIN(47, "GPIO_47"), 160 PINCTRL_PIN(48, "GPIO_48"), 161 PINCTRL_PIN(49, "GPIO_49"), 162 PINCTRL_PIN(50, "GPIO_50"), 163 PINCTRL_PIN(51, "GPIO_51"), 164 PINCTRL_PIN(52, "GPIO_52"), 165 PINCTRL_PIN(53, "GPIO_53"), 166 PINCTRL_PIN(54, "GPIO_54"), 167 PINCTRL_PIN(55, "GPIO_55"), 168 PINCTRL_PIN(56, "GPIO_56"), 169 PINCTRL_PIN(57, "GPIO_57"), 170 PINCTRL_PIN(58, "GPIO_58"), 171 PINCTRL_PIN(59, "GPIO_59"), 172 PINCTRL_PIN(60, "GPIO_60"), 173 PINCTRL_PIN(61, "GPIO_61"), 174 PINCTRL_PIN(62, "GPIO_62"), 175 PINCTRL_PIN(63, "GPIO_63"), 176 PINCTRL_PIN(64, "GPIO_64"), 177 PINCTRL_PIN(65, "GPIO_65"), 178 PINCTRL_PIN(66, "GPIO_66"), 179 PINCTRL_PIN(67, "GPIO_67"), 180 PINCTRL_PIN(68, "GPIO_68"), 181 PINCTRL_PIN(69, "GPIO_69"), 182 PINCTRL_PIN(70, "GPIO_70"), 183 PINCTRL_PIN(71, "GPIO_71"), 184 PINCTRL_PIN(72, "GPIO_72"), 185 PINCTRL_PIN(73, "GPIO_73"), 186 PINCTRL_PIN(74, "GPIO_74"), 187 PINCTRL_PIN(75, "GPIO_75"), 188 PINCTRL_PIN(76, "GPIO_76"), 189 PINCTRL_PIN(77, "GPIO_77"), 190 PINCTRL_PIN(78, "GPIO_78"), 191 PINCTRL_PIN(79, "GPIO_79"), 192 PINCTRL_PIN(80, "GPIO_80"), 193 PINCTRL_PIN(81, "GPIO_81"), 194 PINCTRL_PIN(82, "GPIO_82"), 195 PINCTRL_PIN(83, "GPIO_83"), 196 PINCTRL_PIN(84, "GPIO_84"), 197 PINCTRL_PIN(85, "GPIO_85"), 198 PINCTRL_PIN(86, "GPIO_86"), 199 PINCTRL_PIN(87, "GPIO_87"), 200 PINCTRL_PIN(88, "GPIO_88"), 201 PINCTRL_PIN(89, "GPIO_89"), 202 PINCTRL_PIN(90, "GPIO_90"), 203 PINCTRL_PIN(91, "GPIO_91"), 204 PINCTRL_PIN(92, "GPIO_92"), 205 PINCTRL_PIN(93, "GPIO_93"), 206 PINCTRL_PIN(94, "GPIO_94"), 207 PINCTRL_PIN(95, "GPIO_95"), 208 PINCTRL_PIN(96, "GPIO_96"), 209 PINCTRL_PIN(97, "GPIO_97"), 210 PINCTRL_PIN(98, "GPIO_98"), 211 PINCTRL_PIN(99, "GPIO_99"), 212 PINCTRL_PIN(100, "GPIO_100"), 213 PINCTRL_PIN(101, "GPIO_101"), 214 PINCTRL_PIN(102, "GPIO_102"), 215 PINCTRL_PIN(103, "GPIO_103"), 216 PINCTRL_PIN(104, "GPIO_104"), 217 PINCTRL_PIN(105, "GPIO_105"), 218 PINCTRL_PIN(106, "GPIO_106"), 219 PINCTRL_PIN(107, "GPIO_107"), 220 PINCTRL_PIN(108, "GPIO_108"), 221 PINCTRL_PIN(109, "GPIO_109"), 222 PINCTRL_PIN(110, "GPIO_110"), 223 PINCTRL_PIN(111, "GPIO_111"), 224 PINCTRL_PIN(112, "GPIO_112"), 225 PINCTRL_PIN(113, "GPIO_113"), 226 PINCTRL_PIN(114, "GPIO_114"), 227 PINCTRL_PIN(115, "GPIO_115"), 228 PINCTRL_PIN(116, "GPIO_116"), 229 PINCTRL_PIN(117, "GPIO_117"), 230 PINCTRL_PIN(118, "GPIO_118"), 231 PINCTRL_PIN(119, "GPIO_119"), 232 PINCTRL_PIN(120, "GPIO_120"), 233 PINCTRL_PIN(121, "GPIO_121"), 234 PINCTRL_PIN(122, "GPIO_122"), 235 PINCTRL_PIN(123, "GPIO_123"), 236 PINCTRL_PIN(124, "GPIO_124"), 237 PINCTRL_PIN(125, "GPIO_125"), 238 PINCTRL_PIN(126, "GPIO_126"), 239 PINCTRL_PIN(127, "GPIO_127"), 240 PINCTRL_PIN(128, "GPIO_128"), 241 PINCTRL_PIN(129, "GPIO_129"), 242 PINCTRL_PIN(130, "GPIO_130"), 243 PINCTRL_PIN(131, "GPIO_131"), 244 PINCTRL_PIN(132, "GPIO_132"), 245 PINCTRL_PIN(133, "GPIO_133"), 246 PINCTRL_PIN(134, "GPIO_134"), 247 PINCTRL_PIN(135, "GPIO_135"), 248 PINCTRL_PIN(136, "GPIO_136"), 249 PINCTRL_PIN(137, "GPIO_137"), 250 PINCTRL_PIN(138, "GPIO_138"), 251 PINCTRL_PIN(139, "GPIO_139"), 252 PINCTRL_PIN(140, "GPIO_140"), 253 PINCTRL_PIN(141, "GPIO_141"), 254 PINCTRL_PIN(142, "GPIO_142"), 255 PINCTRL_PIN(143, "GPIO_143"), 256 PINCTRL_PIN(144, "GPIO_144"), 257 PINCTRL_PIN(145, "GPIO_145"), 258 PINCTRL_PIN(146, "GPIO_146"), 259 PINCTRL_PIN(147, "GPIO_147"), 260 PINCTRL_PIN(148, "GPIO_148"), 261 PINCTRL_PIN(149, "GPIO_149"), 262 PINCTRL_PIN(150, "GPIO_150"), 263 PINCTRL_PIN(151, "GPIO_151"), 264 PINCTRL_PIN(152, "GPIO_152"), 265 PINCTRL_PIN(153, "GPIO_153"), 266 PINCTRL_PIN(154, "GPIO_154"), 267 PINCTRL_PIN(155, "GPIO_155"), 268 PINCTRL_PIN(156, "GPIO_156"), 269 PINCTRL_PIN(157, "GPIO_157"), 270 PINCTRL_PIN(158, "GPIO_158"), 271 PINCTRL_PIN(159, "GPIO_159"), 272 PINCTRL_PIN(160, "GPIO_160"), 273 PINCTRL_PIN(161, "GPIO_161"), 274 PINCTRL_PIN(162, "GPIO_162"), 275 PINCTRL_PIN(163, "GPIO_163"), 276 PINCTRL_PIN(164, "GPIO_164"), 277 PINCTRL_PIN(165, "GPIO_165"), 278 PINCTRL_PIN(166, "GPIO_166"), 279 PINCTRL_PIN(167, "UFS_RESET"), 280 PINCTRL_PIN(168, "SDC2_CLK"), 281 PINCTRL_PIN(169, "SDC2_CMD"), 282 PINCTRL_PIN(170, "SDC2_DATA"), 283 }; 284 285 #define DECLARE_MSM_GPIO_PINS(pin) \ 286 static const unsigned int gpio##pin##_pins[] = { pin } 287 DECLARE_MSM_GPIO_PINS(0); 288 DECLARE_MSM_GPIO_PINS(1); 289 DECLARE_MSM_GPIO_PINS(2); 290 DECLARE_MSM_GPIO_PINS(3); 291 DECLARE_MSM_GPIO_PINS(4); 292 DECLARE_MSM_GPIO_PINS(5); 293 DECLARE_MSM_GPIO_PINS(6); 294 DECLARE_MSM_GPIO_PINS(7); 295 DECLARE_MSM_GPIO_PINS(8); 296 DECLARE_MSM_GPIO_PINS(9); 297 DECLARE_MSM_GPIO_PINS(10); 298 DECLARE_MSM_GPIO_PINS(11); 299 DECLARE_MSM_GPIO_PINS(12); 300 DECLARE_MSM_GPIO_PINS(13); 301 DECLARE_MSM_GPIO_PINS(14); 302 DECLARE_MSM_GPIO_PINS(15); 303 DECLARE_MSM_GPIO_PINS(16); 304 DECLARE_MSM_GPIO_PINS(17); 305 DECLARE_MSM_GPIO_PINS(18); 306 DECLARE_MSM_GPIO_PINS(19); 307 DECLARE_MSM_GPIO_PINS(20); 308 DECLARE_MSM_GPIO_PINS(21); 309 DECLARE_MSM_GPIO_PINS(22); 310 DECLARE_MSM_GPIO_PINS(23); 311 DECLARE_MSM_GPIO_PINS(24); 312 DECLARE_MSM_GPIO_PINS(25); 313 DECLARE_MSM_GPIO_PINS(26); 314 DECLARE_MSM_GPIO_PINS(27); 315 DECLARE_MSM_GPIO_PINS(28); 316 DECLARE_MSM_GPIO_PINS(29); 317 DECLARE_MSM_GPIO_PINS(30); 318 DECLARE_MSM_GPIO_PINS(31); 319 DECLARE_MSM_GPIO_PINS(32); 320 DECLARE_MSM_GPIO_PINS(33); 321 DECLARE_MSM_GPIO_PINS(34); 322 DECLARE_MSM_GPIO_PINS(35); 323 DECLARE_MSM_GPIO_PINS(36); 324 DECLARE_MSM_GPIO_PINS(37); 325 DECLARE_MSM_GPIO_PINS(38); 326 DECLARE_MSM_GPIO_PINS(39); 327 DECLARE_MSM_GPIO_PINS(40); 328 DECLARE_MSM_GPIO_PINS(41); 329 DECLARE_MSM_GPIO_PINS(42); 330 DECLARE_MSM_GPIO_PINS(43); 331 DECLARE_MSM_GPIO_PINS(44); 332 DECLARE_MSM_GPIO_PINS(45); 333 DECLARE_MSM_GPIO_PINS(46); 334 DECLARE_MSM_GPIO_PINS(47); 335 DECLARE_MSM_GPIO_PINS(48); 336 DECLARE_MSM_GPIO_PINS(49); 337 DECLARE_MSM_GPIO_PINS(50); 338 DECLARE_MSM_GPIO_PINS(51); 339 DECLARE_MSM_GPIO_PINS(52); 340 DECLARE_MSM_GPIO_PINS(53); 341 DECLARE_MSM_GPIO_PINS(54); 342 DECLARE_MSM_GPIO_PINS(55); 343 DECLARE_MSM_GPIO_PINS(56); 344 DECLARE_MSM_GPIO_PINS(57); 345 DECLARE_MSM_GPIO_PINS(58); 346 DECLARE_MSM_GPIO_PINS(59); 347 DECLARE_MSM_GPIO_PINS(60); 348 DECLARE_MSM_GPIO_PINS(61); 349 DECLARE_MSM_GPIO_PINS(62); 350 DECLARE_MSM_GPIO_PINS(63); 351 DECLARE_MSM_GPIO_PINS(64); 352 DECLARE_MSM_GPIO_PINS(65); 353 DECLARE_MSM_GPIO_PINS(66); 354 DECLARE_MSM_GPIO_PINS(67); 355 DECLARE_MSM_GPIO_PINS(68); 356 DECLARE_MSM_GPIO_PINS(69); 357 DECLARE_MSM_GPIO_PINS(70); 358 DECLARE_MSM_GPIO_PINS(71); 359 DECLARE_MSM_GPIO_PINS(72); 360 DECLARE_MSM_GPIO_PINS(73); 361 DECLARE_MSM_GPIO_PINS(74); 362 DECLARE_MSM_GPIO_PINS(75); 363 DECLARE_MSM_GPIO_PINS(76); 364 DECLARE_MSM_GPIO_PINS(77); 365 DECLARE_MSM_GPIO_PINS(78); 366 DECLARE_MSM_GPIO_PINS(79); 367 DECLARE_MSM_GPIO_PINS(80); 368 DECLARE_MSM_GPIO_PINS(81); 369 DECLARE_MSM_GPIO_PINS(82); 370 DECLARE_MSM_GPIO_PINS(83); 371 DECLARE_MSM_GPIO_PINS(84); 372 DECLARE_MSM_GPIO_PINS(85); 373 DECLARE_MSM_GPIO_PINS(86); 374 DECLARE_MSM_GPIO_PINS(87); 375 DECLARE_MSM_GPIO_PINS(88); 376 DECLARE_MSM_GPIO_PINS(89); 377 DECLARE_MSM_GPIO_PINS(90); 378 DECLARE_MSM_GPIO_PINS(91); 379 DECLARE_MSM_GPIO_PINS(92); 380 DECLARE_MSM_GPIO_PINS(93); 381 DECLARE_MSM_GPIO_PINS(94); 382 DECLARE_MSM_GPIO_PINS(95); 383 DECLARE_MSM_GPIO_PINS(96); 384 DECLARE_MSM_GPIO_PINS(97); 385 DECLARE_MSM_GPIO_PINS(98); 386 DECLARE_MSM_GPIO_PINS(99); 387 DECLARE_MSM_GPIO_PINS(100); 388 DECLARE_MSM_GPIO_PINS(101); 389 DECLARE_MSM_GPIO_PINS(102); 390 DECLARE_MSM_GPIO_PINS(103); 391 DECLARE_MSM_GPIO_PINS(104); 392 DECLARE_MSM_GPIO_PINS(105); 393 DECLARE_MSM_GPIO_PINS(106); 394 DECLARE_MSM_GPIO_PINS(107); 395 DECLARE_MSM_GPIO_PINS(108); 396 DECLARE_MSM_GPIO_PINS(109); 397 DECLARE_MSM_GPIO_PINS(110); 398 DECLARE_MSM_GPIO_PINS(111); 399 DECLARE_MSM_GPIO_PINS(112); 400 DECLARE_MSM_GPIO_PINS(113); 401 DECLARE_MSM_GPIO_PINS(114); 402 DECLARE_MSM_GPIO_PINS(115); 403 DECLARE_MSM_GPIO_PINS(116); 404 DECLARE_MSM_GPIO_PINS(117); 405 DECLARE_MSM_GPIO_PINS(118); 406 DECLARE_MSM_GPIO_PINS(119); 407 DECLARE_MSM_GPIO_PINS(120); 408 DECLARE_MSM_GPIO_PINS(121); 409 DECLARE_MSM_GPIO_PINS(122); 410 DECLARE_MSM_GPIO_PINS(123); 411 DECLARE_MSM_GPIO_PINS(124); 412 DECLARE_MSM_GPIO_PINS(125); 413 DECLARE_MSM_GPIO_PINS(126); 414 DECLARE_MSM_GPIO_PINS(127); 415 DECLARE_MSM_GPIO_PINS(128); 416 DECLARE_MSM_GPIO_PINS(129); 417 DECLARE_MSM_GPIO_PINS(130); 418 DECLARE_MSM_GPIO_PINS(131); 419 DECLARE_MSM_GPIO_PINS(132); 420 DECLARE_MSM_GPIO_PINS(133); 421 DECLARE_MSM_GPIO_PINS(134); 422 DECLARE_MSM_GPIO_PINS(135); 423 DECLARE_MSM_GPIO_PINS(136); 424 DECLARE_MSM_GPIO_PINS(137); 425 DECLARE_MSM_GPIO_PINS(138); 426 DECLARE_MSM_GPIO_PINS(139); 427 DECLARE_MSM_GPIO_PINS(140); 428 DECLARE_MSM_GPIO_PINS(141); 429 DECLARE_MSM_GPIO_PINS(142); 430 DECLARE_MSM_GPIO_PINS(143); 431 DECLARE_MSM_GPIO_PINS(144); 432 DECLARE_MSM_GPIO_PINS(145); 433 DECLARE_MSM_GPIO_PINS(146); 434 DECLARE_MSM_GPIO_PINS(147); 435 DECLARE_MSM_GPIO_PINS(148); 436 DECLARE_MSM_GPIO_PINS(149); 437 DECLARE_MSM_GPIO_PINS(150); 438 DECLARE_MSM_GPIO_PINS(151); 439 DECLARE_MSM_GPIO_PINS(152); 440 DECLARE_MSM_GPIO_PINS(153); 441 DECLARE_MSM_GPIO_PINS(154); 442 DECLARE_MSM_GPIO_PINS(155); 443 DECLARE_MSM_GPIO_PINS(156); 444 DECLARE_MSM_GPIO_PINS(157); 445 DECLARE_MSM_GPIO_PINS(158); 446 DECLARE_MSM_GPIO_PINS(159); 447 DECLARE_MSM_GPIO_PINS(160); 448 DECLARE_MSM_GPIO_PINS(161); 449 DECLARE_MSM_GPIO_PINS(162); 450 DECLARE_MSM_GPIO_PINS(163); 451 DECLARE_MSM_GPIO_PINS(164); 452 DECLARE_MSM_GPIO_PINS(165); 453 DECLARE_MSM_GPIO_PINS(166); 454 455 static const unsigned int ufs_reset_pins[] = { 167 }; 456 static const unsigned int sdc2_clk_pins[] = { 168 }; 457 static const unsigned int sdc2_cmd_pins[] = { 169 }; 458 static const unsigned int sdc2_data_pins[] = { 170 }; 459 460 enum milos_functions { 461 msm_mux_gpio, 462 msm_mux_aoss_cti, 463 msm_mux_atest_char, 464 msm_mux_atest_usb, 465 msm_mux_audio_ext_mclk0, 466 msm_mux_audio_ext_mclk1, 467 msm_mux_audio_ref_clk, 468 msm_mux_cam_mclk, 469 msm_mux_cci_async_in0, 470 msm_mux_cci_i2c_scl, 471 msm_mux_cci_i2c_sda, 472 msm_mux_cci_timer, 473 msm_mux_coex_uart1_rx, 474 msm_mux_coex_uart1_tx, 475 msm_mux_dbg_out_clk, 476 msm_mux_ddr_bist_complete, 477 msm_mux_ddr_bist_fail, 478 msm_mux_ddr_bist_start, 479 msm_mux_ddr_bist_stop, 480 msm_mux_ddr_pxi0, 481 msm_mux_ddr_pxi1, 482 msm_mux_dp0_hot, 483 msm_mux_egpio, 484 msm_mux_gcc_gp1, 485 msm_mux_gcc_gp2, 486 msm_mux_gcc_gp3, 487 msm_mux_host2wlan_sol, 488 msm_mux_i2s0_data0, 489 msm_mux_i2s0_data1, 490 msm_mux_i2s0_sck, 491 msm_mux_i2s0_ws, 492 msm_mux_ibi_i3c, 493 msm_mux_jitter_bist, 494 msm_mux_mdp_vsync, 495 msm_mux_mdp_vsync0_out, 496 msm_mux_mdp_vsync1_out, 497 msm_mux_mdp_vsync2_out, 498 msm_mux_mdp_vsync3_out, 499 msm_mux_mdp_vsync_e, 500 msm_mux_nav_gpio0, 501 msm_mux_nav_gpio1, 502 msm_mux_nav_gpio2, 503 msm_mux_pcie0_clk_req_n, 504 msm_mux_pcie1_clk_req_n, 505 msm_mux_phase_flag, 506 msm_mux_pll_bist_sync, 507 msm_mux_pll_clk_aux, 508 msm_mux_prng_rosc0, 509 msm_mux_prng_rosc1, 510 msm_mux_prng_rosc2, 511 msm_mux_prng_rosc3, 512 msm_mux_qdss_cti, 513 msm_mux_qdss_gpio, 514 msm_mux_qlink0_enable, 515 msm_mux_qlink0_request, 516 msm_mux_qlink0_wmss, 517 msm_mux_qlink1_enable, 518 msm_mux_qlink1_request, 519 msm_mux_qlink1_wmss, 520 msm_mux_qspi0, 521 msm_mux_qup0_se0, 522 msm_mux_qup0_se1, 523 msm_mux_qup0_se2, 524 msm_mux_qup0_se3, 525 msm_mux_qup0_se4, 526 msm_mux_qup0_se5, 527 msm_mux_qup0_se6, 528 msm_mux_qup1_se0, 529 msm_mux_qup1_se1, 530 msm_mux_qup1_se2, 531 msm_mux_qup1_se3, 532 msm_mux_qup1_se4, 533 msm_mux_qup1_se5, 534 msm_mux_qup1_se6, 535 msm_mux_resout_gpio_n, 536 msm_mux_sd_write_protect, 537 msm_mux_sdc1_clk, 538 msm_mux_sdc1_cmd, 539 msm_mux_sdc1_data, 540 msm_mux_sdc1_rclk, 541 msm_mux_sdc2_clk, 542 msm_mux_sdc2_cmd, 543 msm_mux_sdc2_data, 544 msm_mux_sdc2_fb_clk, 545 msm_mux_tb_trig_sdc1, 546 msm_mux_tb_trig_sdc2, 547 msm_mux_tgu_ch0_trigout, 548 msm_mux_tgu_ch1_trigout, 549 msm_mux_tmess_prng0, 550 msm_mux_tmess_prng1, 551 msm_mux_tmess_prng2, 552 msm_mux_tmess_prng3, 553 msm_mux_tsense_pwm1, 554 msm_mux_tsense_pwm2, 555 msm_mux_uim0_clk, 556 msm_mux_uim0_data, 557 msm_mux_uim0_present, 558 msm_mux_uim0_reset, 559 msm_mux_uim1_clk_mira, 560 msm_mux_uim1_clk_mirb, 561 msm_mux_uim1_data_mira, 562 msm_mux_uim1_data_mirb, 563 msm_mux_uim1_present_mira, 564 msm_mux_uim1_present_mirb, 565 msm_mux_uim1_reset_mira, 566 msm_mux_uim1_reset_mirb, 567 msm_mux_usb0_hs, 568 msm_mux_usb0_phy_ps, 569 msm_mux_vfr_0, 570 msm_mux_vfr_1, 571 msm_mux_vsense_trigger_mirnat, 572 msm_mux_wcn_sw, 573 msm_mux_wcn_sw_ctrl, 574 msm_mux__, 575 }; 576 577 static const char *const gpio_groups[] = { 578 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 579 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", 580 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", 581 "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", 582 "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 583 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 584 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", 585 "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", 586 "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", 587 "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", 588 "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", 589 "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", 590 "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 591 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", 592 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", 593 "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", 594 "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", 595 "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", 596 "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", 597 "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", 598 "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", 599 "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", 600 "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", 601 "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", 602 "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", 603 "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", 604 "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", 605 "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", 606 }; 607 static const char *const resout_gpio_n_groups[] = { 608 "gpio39", 609 }; 610 static const char *const sdc1_clk_groups[] = { 611 "gpio77", 612 }; 613 static const char *const sdc1_cmd_groups[] = { 614 "gpio78", 615 }; 616 static const char *const sdc1_data_groups[] = { 617 "gpio73", "gpio74", "gpio75", "gpio76", "gpio79", "gpio80", 618 "gpio81", "gpio82", 619 }; 620 static const char *const sdc1_rclk_groups[] = { 621 "gpio72", 622 }; 623 static const char *const aoss_cti_groups[] = { 624 "gpio0", 625 "gpio1", 626 "gpio4", 627 "gpio5", 628 }; 629 static const char *const atest_char_groups[] = { 630 "gpio44", "gpio45", "gpio46", "gpio47", "gpio63", 631 }; 632 static const char *const atest_usb_groups[] = { 633 "gpio23", "gpio24", "gpio60", 634 }; 635 static const char *const audio_ext_mclk0_groups[] = { 636 "gpio23", 637 }; 638 static const char *const audio_ext_mclk1_groups[] = { 639 "gpio24", 640 }; 641 static const char *const audio_ref_clk_groups[] = { 642 "gpio24", 643 }; 644 static const char *const cam_mclk_groups[] = { 645 "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", 646 }; 647 static const char *const cci_async_in0_groups[] = { 648 "gpio86", 649 }; 650 static const char *const cci_i2c_scl_groups[] = { 651 "gpio89", "gpio91", "gpio93", "gpio95", 652 }; 653 static const char *const cci_i2c_sda_groups[] = { 654 "gpio88", "gpio90", "gpio92", "gpio94", 655 }; 656 static const char *const cci_timer_groups[] = { 657 "gpio77", "gpio83", "gpio84", "gpio85", 658 }; 659 static const char *const coex_uart1_rx_groups[] = { 660 "gpio64", 661 }; 662 static const char *const coex_uart1_tx_groups[] = { 663 "gpio63", 664 }; 665 static const char *const dbg_out_clk_groups[] = { 666 "gpio24", 667 }; 668 static const char *const ddr_bist_complete_groups[] = { 669 "gpio137", 670 }; 671 static const char *const ddr_bist_fail_groups[] = { 672 "gpio56", 673 }; 674 static const char *const ddr_bist_start_groups[] = { 675 "gpio133", 676 }; 677 static const char *const ddr_bist_stop_groups[] = { 678 "gpio47", 679 }; 680 static const char *const ddr_pxi0_groups[] = { 681 "gpio23", 682 "gpio24", 683 }; 684 static const char *const ddr_pxi1_groups[] = { 685 "gpio50", 686 "gpio51", 687 }; 688 static const char *const dp0_hot_groups[] = { 689 "gpio75", 690 }; 691 static const char *const egpio_groups[] = { 692 "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", 693 "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", 694 "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", 695 "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", 696 "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", 697 "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", 698 }; 699 static const char *const gcc_gp1_groups[] = { 700 "gpio29", 701 "gpio32", 702 }; 703 static const char *const gcc_gp2_groups[] = { 704 "gpio28", 705 "gpio30", 706 }; 707 static const char *const gcc_gp3_groups[] = { 708 "gpio31", 709 "gpio33", 710 }; 711 static const char *const host2wlan_sol_groups[] = { 712 "gpio46", 713 }; 714 static const char *const i2s0_data0_groups[] = { 715 "gpio16", 716 }; 717 static const char *const i2s0_data1_groups[] = { 718 "gpio17", 719 }; 720 static const char *const i2s0_sck_groups[] = { 721 "gpio15", 722 }; 723 static const char *const i2s0_ws_groups[] = { 724 "gpio18", 725 }; 726 static const char *const ibi_i3c_groups[] = { 727 "gpio0", "gpio1", "gpio4", "gpio5", 728 "gpio32", "gpio33", "gpio36", "gpio37", 729 }; 730 static const char *const jitter_bist_groups[] = { 731 "gpio141", 732 }; 733 static const char *const mdp_vsync_groups[] = { 734 "gpio19", 735 "gpio37", 736 "gpio72", 737 "gpio129", 738 }; 739 static const char *const mdp_vsync0_out_groups[] = { 740 "gpio12", 741 }; 742 static const char *const mdp_vsync1_out_groups[] = { 743 "gpio12", 744 }; 745 static const char *const mdp_vsync2_out_groups[] = { 746 "gpio40", 747 }; 748 static const char *const mdp_vsync3_out_groups[] = { 749 "gpio40", 750 }; 751 static const char *const mdp_vsync_e_groups[] = { 752 "gpio45", 753 }; 754 static const char *const nav_gpio0_groups[] = { 755 "gpio124", 756 }; 757 static const char *const nav_gpio1_groups[] = { 758 "gpio125", 759 }; 760 static const char *const nav_gpio2_groups[] = { 761 "gpio126", 762 }; 763 static const char *const pcie0_clk_req_n_groups[] = { 764 "gpio67", 765 }; 766 static const char *const pcie1_clk_req_n_groups[] = { 767 "gpio70", 768 }; 769 static const char *const phase_flag_groups[] = { 770 "gpio8", "gpio9", "gpio11", "gpio12", "gpio13", "gpio14", 771 "gpio15", "gpio16", "gpio18", "gpio26", "gpio38", "gpio39", 772 "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", 773 "gpio46", "gpio47", "gpio48", "gpio49", "gpio63", "gpio64", 774 "gpio127", "gpio138", "gpio139", "gpio140", "gpio142", "gpio143", 775 "gpio144", "gpio147", 776 }; 777 static const char *const pll_bist_sync_groups[] = { 778 "gpio26", 779 }; 780 static const char *const pll_clk_aux_groups[] = { 781 "gpio36", 782 }; 783 static const char *const prng_rosc0_groups[] = { 784 "gpio66", 785 }; 786 static const char *const prng_rosc1_groups[] = { 787 "gpio67", 788 }; 789 static const char *const prng_rosc2_groups[] = { 790 "gpio68", 791 }; 792 static const char *const prng_rosc3_groups[] = { 793 "gpio69", 794 }; 795 static const char *const qdss_cti_groups[] = { 796 "gpio4", "gpio5", "gpio6", "gpio7", 797 "gpio44", "gpio45", "gpio54", "gpio87", 798 }; 799 static const char *const qdss_gpio_groups[] = { 800 "gpio40", "gpio41", "gpio42", "gpio43", "gpio46", "gpio47", 801 "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", 802 "gpio83", "gpio84", "gpio85", "gpio86", "gpio88", "gpio89", 803 "gpio138", "gpio139", "gpio140", "gpio141", "gpio149", "gpio150", 804 "gpio155", "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", 805 "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", 806 }; 807 static const char *const qlink0_enable_groups[] = { 808 "gpio105", 809 }; 810 static const char *const qlink0_request_groups[] = { 811 "gpio104", 812 }; 813 static const char *const qlink0_wmss_groups[] = { 814 "gpio106", 815 }; 816 static const char *const qlink1_enable_groups[] = { 817 "gpio108", 818 }; 819 static const char *const qlink1_request_groups[] = { 820 "gpio107", 821 }; 822 static const char *const qlink1_wmss_groups[] = { 823 "gpio109", 824 }; 825 static const char *const qspi0_groups[] = { 826 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 827 }; 828 static const char *const qup0_se0_groups[] = { 829 "gpio0", "gpio1", "gpio2", "gpio3", 830 }; 831 static const char *const qup0_se1_groups[] = { 832 "gpio4", "gpio5", "gpio6", "gpio7", 833 }; 834 static const char *const qup0_se2_groups[] = { 835 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 836 }; 837 static const char *const qup0_se3_groups[] = { 838 "gpio15", "gpio16", "gpio17", "gpio18", "gpio23", "gpio24", "gpio26", 839 }; 840 static const char *const qup0_se4_groups[] = { 841 "gpio19", "gpio20", "gpio21", "gpio22", 842 }; 843 static const char *const qup0_se5_groups[] = { 844 "gpio23", "gpio24", "gpio25", "gpio26", 845 }; 846 static const char *const qup0_se6_groups[] = { 847 "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", 848 }; 849 static const char *const qup1_se0_groups[] = { 850 "gpio32", "gpio33", "gpio94", "gpio95", 851 }; 852 static const char *const qup1_se1_groups[] = { 853 "gpio36", "gpio37", "gpio38", "gpio39", 854 }; 855 static const char *const qup1_se2_groups[] = { 856 "gpio36", "gpio37", "gpio38", "gpio40", "gpio41", "gpio42", "gpio43", 857 }; 858 static const char *const qup1_se3_groups[] = { 859 "gpio92", "gpio93", "gpio94", "gpio95", 860 }; 861 static const char *const qup1_se4_groups[] = { 862 "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", 863 }; 864 static const char *const qup1_se5_groups[] = { 865 "gpio55", "gpio56", "gpio59", "gpio60", 866 }; 867 static const char *const qup1_se6_groups[] = { 868 "gpio55", "gpio56", "gpio59", "gpio60", "gpio90", "gpio91", 869 }; 870 static const char *const sd_write_protect_groups[] = { 871 "gpio4", 872 }; 873 static const char *const sdc2_data_groups[] = { 874 "gpio34", 875 "gpio35", 876 "gpio57", 877 "gpio58", 878 }; 879 static const char *const sdc2_clk_groups[] = { 880 "gpio62", 881 }; 882 static const char *const sdc2_cmd_groups[] = { 883 "gpio61", 884 }; 885 static const char *const sdc2_fb_clk_groups[] = { 886 "gpio128", 887 }; 888 static const char *const tb_trig_sdc1_groups[] = { 889 "gpio87", 890 }; 891 static const char *const tb_trig_sdc2_groups[] = { 892 "gpio78", 893 }; 894 static const char *const tgu_ch0_trigout_groups[] = { 895 "gpio87", 896 }; 897 static const char *const tgu_ch1_trigout_groups[] = { 898 "gpio88", 899 }; 900 static const char *const tmess_prng0_groups[] = { 901 "gpio86", 902 }; 903 static const char *const tmess_prng1_groups[] = { 904 "gpio83", 905 }; 906 static const char *const tmess_prng2_groups[] = { 907 "gpio84", 908 }; 909 static const char *const tmess_prng3_groups[] = { 910 "gpio85", 911 }; 912 static const char *const tsense_pwm1_groups[] = { 913 "gpio17", 914 }; 915 static const char *const tsense_pwm2_groups[] = { 916 "gpio17", 917 }; 918 static const char *const uim0_clk_groups[] = { 919 "gpio97", 920 }; 921 static const char *const uim0_data_groups[] = { 922 "gpio96", 923 }; 924 static const char *const uim0_present_groups[] = { 925 "gpio99", 926 }; 927 static const char *const uim0_reset_groups[] = { 928 "gpio98", 929 }; 930 static const char *const uim1_clk_mira_groups[] = { 931 "gpio111", 932 }; 933 static const char *const uim1_clk_mirb_groups[] = { 934 "gpio101", 935 }; 936 static const char *const uim1_data_mira_groups[] = { 937 "gpio110", 938 }; 939 static const char *const uim1_data_mirb_groups[] = { 940 "gpio100", 941 }; 942 static const char *const uim1_present_mira_groups[] = { 943 "gpio113", 944 }; 945 static const char *const uim1_present_mirb_groups[] = { 946 "gpio103", 947 }; 948 static const char *const uim1_reset_mira_groups[] = { 949 "gpio112", 950 }; 951 static const char *const uim1_reset_mirb_groups[] = { 952 "gpio102", 953 }; 954 static const char *const usb0_hs_groups[] = { 955 "gpio125", 956 }; 957 static const char *const usb0_phy_ps_groups[] = { 958 "gpio131", 959 }; 960 static const char *const vfr_0_groups[] = { 961 "gpio56", 962 }; 963 static const char *const vfr_1_groups[] = { 964 "gpio126", 965 }; 966 static const char *const vsense_trigger_mirnat_groups[] = { 967 "gpio94", 968 }; 969 static const char *const wcn_sw_groups[] = { 970 "gpio52", 971 }; 972 static const char *const wcn_sw_ctrl_groups[] = { 973 "gpio45", 974 }; 975 976 static const struct pinfunction milos_functions[] = { 977 MSM_PIN_FUNCTION(gpio), 978 MSM_PIN_FUNCTION(aoss_cti), 979 MSM_PIN_FUNCTION(atest_char), 980 MSM_PIN_FUNCTION(atest_usb), 981 MSM_PIN_FUNCTION(audio_ext_mclk0), 982 MSM_PIN_FUNCTION(audio_ext_mclk1), 983 MSM_PIN_FUNCTION(audio_ref_clk), 984 MSM_PIN_FUNCTION(cam_mclk), 985 MSM_PIN_FUNCTION(cci_async_in0), 986 MSM_PIN_FUNCTION(cci_i2c_scl), 987 MSM_PIN_FUNCTION(cci_i2c_sda), 988 MSM_PIN_FUNCTION(cci_timer), 989 MSM_PIN_FUNCTION(coex_uart1_rx), 990 MSM_PIN_FUNCTION(coex_uart1_tx), 991 MSM_PIN_FUNCTION(dbg_out_clk), 992 MSM_PIN_FUNCTION(ddr_bist_complete), 993 MSM_PIN_FUNCTION(ddr_bist_fail), 994 MSM_PIN_FUNCTION(ddr_bist_start), 995 MSM_PIN_FUNCTION(ddr_bist_stop), 996 MSM_PIN_FUNCTION(ddr_pxi0), 997 MSM_PIN_FUNCTION(ddr_pxi1), 998 MSM_PIN_FUNCTION(dp0_hot), 999 MSM_PIN_FUNCTION(egpio), 1000 MSM_PIN_FUNCTION(gcc_gp1), 1001 MSM_PIN_FUNCTION(gcc_gp2), 1002 MSM_PIN_FUNCTION(gcc_gp3), 1003 MSM_PIN_FUNCTION(host2wlan_sol), 1004 MSM_PIN_FUNCTION(i2s0_data0), 1005 MSM_PIN_FUNCTION(i2s0_data1), 1006 MSM_PIN_FUNCTION(i2s0_sck), 1007 MSM_PIN_FUNCTION(i2s0_ws), 1008 MSM_PIN_FUNCTION(ibi_i3c), 1009 MSM_PIN_FUNCTION(jitter_bist), 1010 MSM_PIN_FUNCTION(mdp_vsync), 1011 MSM_PIN_FUNCTION(mdp_vsync0_out), 1012 MSM_PIN_FUNCTION(mdp_vsync1_out), 1013 MSM_PIN_FUNCTION(mdp_vsync2_out), 1014 MSM_PIN_FUNCTION(mdp_vsync3_out), 1015 MSM_PIN_FUNCTION(mdp_vsync_e), 1016 MSM_PIN_FUNCTION(nav_gpio0), 1017 MSM_PIN_FUNCTION(nav_gpio1), 1018 MSM_PIN_FUNCTION(nav_gpio2), 1019 MSM_PIN_FUNCTION(pcie0_clk_req_n), 1020 MSM_PIN_FUNCTION(pcie1_clk_req_n), 1021 MSM_PIN_FUNCTION(phase_flag), 1022 MSM_PIN_FUNCTION(pll_bist_sync), 1023 MSM_PIN_FUNCTION(pll_clk_aux), 1024 MSM_PIN_FUNCTION(prng_rosc0), 1025 MSM_PIN_FUNCTION(prng_rosc1), 1026 MSM_PIN_FUNCTION(prng_rosc2), 1027 MSM_PIN_FUNCTION(prng_rosc3), 1028 MSM_PIN_FUNCTION(qdss_cti), 1029 MSM_PIN_FUNCTION(qdss_gpio), 1030 MSM_PIN_FUNCTION(qlink0_enable), 1031 MSM_PIN_FUNCTION(qlink0_request), 1032 MSM_PIN_FUNCTION(qlink0_wmss), 1033 MSM_PIN_FUNCTION(qlink1_enable), 1034 MSM_PIN_FUNCTION(qlink1_request), 1035 MSM_PIN_FUNCTION(qlink1_wmss), 1036 MSM_PIN_FUNCTION(qspi0), 1037 MSM_PIN_FUNCTION(qup0_se0), 1038 MSM_PIN_FUNCTION(qup0_se1), 1039 MSM_PIN_FUNCTION(qup0_se2), 1040 MSM_PIN_FUNCTION(qup0_se3), 1041 MSM_PIN_FUNCTION(qup0_se4), 1042 MSM_PIN_FUNCTION(qup0_se5), 1043 MSM_PIN_FUNCTION(qup0_se6), 1044 MSM_PIN_FUNCTION(qup1_se0), 1045 MSM_PIN_FUNCTION(qup1_se1), 1046 MSM_PIN_FUNCTION(qup1_se2), 1047 MSM_PIN_FUNCTION(qup1_se3), 1048 MSM_PIN_FUNCTION(qup1_se4), 1049 MSM_PIN_FUNCTION(qup1_se5), 1050 MSM_PIN_FUNCTION(qup1_se6), 1051 MSM_PIN_FUNCTION(resout_gpio_n), 1052 MSM_PIN_FUNCTION(sd_write_protect), 1053 MSM_PIN_FUNCTION(sdc1_clk), 1054 MSM_PIN_FUNCTION(sdc1_cmd), 1055 MSM_PIN_FUNCTION(sdc1_data), 1056 MSM_PIN_FUNCTION(sdc1_rclk), 1057 MSM_PIN_FUNCTION(sdc2_clk), 1058 MSM_PIN_FUNCTION(sdc2_cmd), 1059 MSM_PIN_FUNCTION(sdc2_data), 1060 MSM_PIN_FUNCTION(sdc2_fb_clk), 1061 MSM_PIN_FUNCTION(tb_trig_sdc1), 1062 MSM_PIN_FUNCTION(tb_trig_sdc2), 1063 MSM_PIN_FUNCTION(tgu_ch0_trigout), 1064 MSM_PIN_FUNCTION(tgu_ch1_trigout), 1065 MSM_PIN_FUNCTION(tmess_prng0), 1066 MSM_PIN_FUNCTION(tmess_prng1), 1067 MSM_PIN_FUNCTION(tmess_prng2), 1068 MSM_PIN_FUNCTION(tmess_prng3), 1069 MSM_PIN_FUNCTION(tsense_pwm1), 1070 MSM_PIN_FUNCTION(tsense_pwm2), 1071 MSM_PIN_FUNCTION(uim0_clk), 1072 MSM_PIN_FUNCTION(uim0_data), 1073 MSM_PIN_FUNCTION(uim0_present), 1074 MSM_PIN_FUNCTION(uim0_reset), 1075 MSM_PIN_FUNCTION(uim1_clk_mira), 1076 MSM_PIN_FUNCTION(uim1_clk_mirb), 1077 MSM_PIN_FUNCTION(uim1_data_mira), 1078 MSM_PIN_FUNCTION(uim1_data_mirb), 1079 MSM_PIN_FUNCTION(uim1_present_mira), 1080 MSM_PIN_FUNCTION(uim1_present_mirb), 1081 MSM_PIN_FUNCTION(uim1_reset_mira), 1082 MSM_PIN_FUNCTION(uim1_reset_mirb), 1083 MSM_PIN_FUNCTION(usb0_hs), 1084 MSM_PIN_FUNCTION(usb0_phy_ps), 1085 MSM_PIN_FUNCTION(vfr_0), 1086 MSM_PIN_FUNCTION(vfr_1), 1087 MSM_PIN_FUNCTION(vsense_trigger_mirnat), 1088 MSM_PIN_FUNCTION(wcn_sw), 1089 MSM_PIN_FUNCTION(wcn_sw_ctrl), 1090 }; 1091 1092 /* 1093 * Every pin is maintained as a single group, and missing or non-existing pin 1094 * would be maintained as dummy group to synchronize pin group index with 1095 * pin descriptor registered with pinctrl core. 1096 * Clients would not be able to request these dummy pin groups. 1097 */ 1098 static const struct msm_pingroup milos_groups[] = { 1099 [0] = PINGROUP(0, qup0_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _), 1100 [1] = PINGROUP(1, qup0_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _), 1101 [2] = PINGROUP(2, qup0_se0, _, _, _, _, _, _, _, _, _, _), 1102 [3] = PINGROUP(3, qup0_se0, _, _, _, _, _, _, _, _, _, _), 1103 [4] = PINGROUP(4, qup0_se1, ibi_i3c, aoss_cti, sd_write_protect, qdss_cti, _, _, _, _, _, _), 1104 [5] = PINGROUP(5, qup0_se1, ibi_i3c, aoss_cti, qdss_cti, _, _, _, _, _, _, _), 1105 [6] = PINGROUP(6, qup0_se1, qdss_cti, _, _, _, _, _, _, _, _, _), 1106 [7] = PINGROUP(7, qup0_se1, qdss_cti, _, _, _, _, _, _, _, _, _), 1107 [8] = PINGROUP(8, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _), 1108 [9] = PINGROUP(9, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _), 1109 [10] = PINGROUP(10, qup0_se2, qspi0, _, _, _, _, _, _, _, _, _), 1110 [11] = PINGROUP(11, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _), 1111 [12] = PINGROUP(12, qup0_se2, qspi0, mdp_vsync0_out, mdp_vsync1_out, _, phase_flag, _, _, _, _, _), 1112 [13] = PINGROUP(13, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _), 1113 [14] = PINGROUP(14, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _), 1114 [15] = PINGROUP(15, qup0_se3, i2s0_sck, _, phase_flag, _, _, _, _, _, _, _), 1115 [16] = PINGROUP(16, qup0_se3, i2s0_data0, _, phase_flag, _, _, _, _, _, _, _), 1116 [17] = PINGROUP(17, qup0_se3, i2s0_data1, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _, _), 1117 [18] = PINGROUP(18, qup0_se3, i2s0_ws, _, phase_flag, _, _, _, _, _, _, _), 1118 [19] = PINGROUP(19, qup0_se4, mdp_vsync, _, _, _, _, _, _, _, _, _), 1119 [20] = PINGROUP(20, qup0_se4, _, _, _, _, _, _, _, _, _, _), 1120 [21] = PINGROUP(21, qup0_se4, _, _, _, _, _, _, _, _, _, _), 1121 [22] = PINGROUP(22, qup0_se4, _, _, _, _, _, _, _, _, _, _), 1122 [23] = PINGROUP(23, qup0_se5, qup0_se3, audio_ext_mclk0, _, atest_usb, ddr_pxi0, _, _, _, _, _), 1123 [24] = PINGROUP(24, qup0_se5, qup0_se3, audio_ext_mclk1, audio_ref_clk, dbg_out_clk, _, atest_usb, ddr_pxi0, _, _, _), 1124 [25] = PINGROUP(25, qup0_se5, _, _, _, _, _, _, _, _, _, _), 1125 [26] = PINGROUP(26, qup0_se5, qup0_se3, pll_bist_sync, _, phase_flag, _, _, _, _, _, _), 1126 [27] = PINGROUP(27, qup0_se6, _, _, _, _, _, _, _, _, _, _), 1127 [28] = PINGROUP(28, qup0_se6, gcc_gp2, _, _, _, _, _, _, _, _, _), 1128 [29] = PINGROUP(29, qup0_se6, gcc_gp1, _, _, _, _, _, _, _, _, _), 1129 [30] = PINGROUP(30, qup0_se6, gcc_gp2, _, _, _, _, _, _, _, _, _), 1130 [31] = PINGROUP(31, qup0_se6, gcc_gp3, _, _, _, _, _, _, _, _, _), 1131 [32] = PINGROUP(32, qup1_se0, ibi_i3c, gcc_gp1, _, _, _, _, _, _, _, _), 1132 [33] = PINGROUP(33, qup1_se0, ibi_i3c, gcc_gp3, _, _, _, _, _, _, _, _), 1133 [34] = PINGROUP(34, sdc2_data, _, _, _, _, _, _, _, _, _, _), 1134 [35] = PINGROUP(35, sdc2_data, _, _, _, _, _, _, _, _, _, _), 1135 [36] = PINGROUP(36, qup1_se1, qup1_se2, ibi_i3c, pll_clk_aux, _, _, _, _, _, _, _), 1136 [37] = PINGROUP(37, qup1_se1, qup1_se2, ibi_i3c, mdp_vsync, _, _, _, _, _, _, _), 1137 [38] = PINGROUP(38, qup1_se1, qup1_se2, _, phase_flag, _, _, _, _, _, _, _), 1138 [39] = PINGROUP(39, qup1_se1, resout_gpio_n, _, phase_flag, _, _, _, _, _, _, _), 1139 [40] = PINGROUP(40, qup1_se2, mdp_vsync2_out, mdp_vsync3_out, _, phase_flag, qdss_gpio, _, _, _, _, _), 1140 [41] = PINGROUP(41, qup1_se2, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _), 1141 [42] = PINGROUP(42, qup1_se2, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _), 1142 [43] = PINGROUP(43, qup1_se2, _, _, phase_flag, qdss_gpio, _, _, _, _, _, _), 1143 [44] = PINGROUP(44, _, _, phase_flag, qdss_cti, atest_char, _, _, _, _, _, _), 1144 [45] = PINGROUP(45, wcn_sw_ctrl, mdp_vsync_e, _, _, phase_flag, qdss_cti, atest_char, _, _, _, _), 1145 [46] = PINGROUP(46, host2wlan_sol, _, phase_flag, qdss_gpio, atest_char, _, _, _, _, _, _), 1146 [47] = PINGROUP(47, ddr_bist_stop, _, phase_flag, qdss_gpio, atest_char, _, _, _, _, _, _), 1147 [48] = PINGROUP(48, qup1_se4, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _), 1148 [49] = PINGROUP(49, qup1_se4, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _), 1149 [50] = PINGROUP(50, qup1_se4, qdss_gpio, ddr_pxi1, _, _, _, _, _, _, _, _), 1150 [51] = PINGROUP(51, qup1_se4, qdss_gpio, ddr_pxi1, _, _, _, _, _, _, _, _), 1151 [52] = PINGROUP(52, qup1_se4, wcn_sw, qdss_gpio, _, _, _, _, _, _, _, _), 1152 [53] = PINGROUP(53, qup1_se4, qdss_gpio, _, _, _, _, _, _, _, _, _), 1153 [54] = PINGROUP(54, qup1_se4, qdss_cti, _, _, _, _, _, _, _, _, _), 1154 [55] = PINGROUP(55, qup1_se5, qup1_se6, _, _, _, _, _, _, _, _, _), 1155 [56] = PINGROUP(56, qup1_se5, qup1_se6, vfr_0, ddr_bist_fail, _, _, _, _, _, _, _), 1156 [57] = PINGROUP(57, sdc2_data, _, _, _, _, _, _, _, _, _, _), 1157 [58] = PINGROUP(58, sdc2_data, _, _, _, _, _, _, _, _, _, _), 1158 [59] = PINGROUP(59, qup1_se6, _, qup1_se5, _, _, _, _, _, _, _, _), 1159 [60] = PINGROUP(60, qup1_se6, _, qup1_se5, atest_usb, _, _, _, _, _, _, _), 1160 [61] = PINGROUP(61, sdc2_cmd, _, _, _, _, _, _, _, _, _, _), 1161 [62] = PINGROUP(62, sdc2_clk, _, _, _, _, _, _, _, _, _, _), 1162 [63] = PINGROUP(63, coex_uart1_tx, _, phase_flag, atest_char, _, _, _, _, _, _, _), 1163 [64] = PINGROUP(64, coex_uart1_rx, _, phase_flag, _, _, _, _, _, _, _, _), 1164 [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _, _, _), 1165 [66] = PINGROUP(66, prng_rosc0, _, _, _, _, _, _, _, _, _, _), 1166 [67] = PINGROUP(67, pcie0_clk_req_n, prng_rosc1, _, _, _, _, _, _, _, _, _), 1167 [68] = PINGROUP(68, prng_rosc2, _, _, _, _, _, _, _, _, _, _), 1168 [69] = PINGROUP(69, prng_rosc3, _, _, _, _, _, _, _, _, _, _), 1169 [70] = PINGROUP(70, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _), 1170 [71] = PINGROUP(71, _, _, _, _, _, _, _, _, _, _, _), 1171 [72] = PINGROUP(72, sdc1_rclk, mdp_vsync, _, _, _, _, _, _, _, _, _), 1172 [73] = PINGROUP(73, sdc1_data, _, _, _, _, _, _, _, _, _, _), 1173 [74] = PINGROUP(74, sdc1_data, _, _, _, _, _, _, _, _, _, _), 1174 [75] = PINGROUP(75, sdc1_data, dp0_hot, _, _, _, _, _, _, _, _, _), 1175 [76] = PINGROUP(76, sdc1_data, _, _, _, _, _, _, _, _, _, _), 1176 [77] = PINGROUP(77, sdc1_clk, cci_timer, _, _, _, _, _, _, _, _, _), 1177 [78] = PINGROUP(78, sdc1_cmd, tb_trig_sdc2, _, _, _, _, _, _, _, _, _), 1178 [79] = PINGROUP(79, sdc1_data, _, _, _, _, _, _, _, _, _, _), 1179 [80] = PINGROUP(80, sdc1_data, _, _, _, _, _, _, _, _, _, _), 1180 [81] = PINGROUP(81, sdc1_data, _, _, _, _, _, _, _, _, _, _), 1181 [82] = PINGROUP(82, sdc1_data, _, _, _, _, _, _, _, _, _, _), 1182 [83] = PINGROUP(83, cam_mclk, cci_timer, tmess_prng1, qdss_gpio, _, _, _, _, _, _, _), 1183 [84] = PINGROUP(84, cam_mclk, cci_timer, tmess_prng2, qdss_gpio, _, _, _, _, _, _, _), 1184 [85] = PINGROUP(85, cam_mclk, cci_timer, tmess_prng3, qdss_gpio, _, _, _, _, _, _, _), 1185 [86] = PINGROUP(86, cam_mclk, cci_async_in0, tmess_prng0, qdss_gpio, _, _, _, _, _, _, _), 1186 [87] = PINGROUP(87, cam_mclk, tb_trig_sdc1, tgu_ch0_trigout, qdss_cti, _, _, _, _, _, _, _), 1187 [88] = PINGROUP(88, cci_i2c_sda, tgu_ch1_trigout, _, qdss_gpio, _, _, _, _, _, _, _), 1188 [89] = PINGROUP(89, cci_i2c_scl, _, qdss_gpio, _, _, _, _, _, _, _, _), 1189 [90] = PINGROUP(90, cci_i2c_sda, qup1_se6, _, _, _, _, _, _, _, _, _), 1190 [91] = PINGROUP(91, cci_i2c_scl, qup1_se6, _, _, _, _, _, _, _, _, _), 1191 [92] = PINGROUP(92, cci_i2c_sda, qup1_se3, _, _, _, _, _, _, _, _, _), 1192 [93] = PINGROUP(93, cci_i2c_scl, qup1_se3, _, _, _, _, _, _, _, _, _), 1193 [94] = PINGROUP(94, cci_i2c_sda, qup1_se3, qup1_se0, _, vsense_trigger_mirnat, _, _, _, _, _, _), 1194 [95] = PINGROUP(95, cci_i2c_scl, qup1_se3, qup1_se0, _, _, _, _, _, _, _, _), 1195 [96] = PINGROUP(96, uim0_data, _, _, _, _, _, _, _, _, _, _), 1196 [97] = PINGROUP(97, uim0_clk, _, _, _, _, _, _, _, _, _, _), 1197 [98] = PINGROUP(98, uim0_reset, _, _, _, _, _, _, _, _, _, _), 1198 [99] = PINGROUP(99, uim0_present, _, _, _, _, _, _, _, _, _, _), 1199 [100] = PINGROUP(100, uim1_data_mirb, _, _, _, _, _, _, _, _, _, _), 1200 [101] = PINGROUP(101, uim1_clk_mirb, _, _, _, _, _, _, _, _, _, _), 1201 [102] = PINGROUP(102, uim1_reset_mirb, _, _, _, _, _, _, _, _, _, _), 1202 [103] = PINGROUP(103, uim1_present_mirb, _, _, _, _, _, _, _, _, _, _), 1203 [104] = PINGROUP(104, qlink0_request, _, _, _, _, _, _, _, _, _, _), 1204 [105] = PINGROUP(105, qlink0_enable, _, _, _, _, _, _, _, _, _, _), 1205 [106] = PINGROUP(106, qlink0_wmss, _, _, _, _, _, _, _, _, _, _), 1206 [107] = PINGROUP(107, qlink1_request, _, _, _, _, _, _, _, _, _, _), 1207 [108] = PINGROUP(108, qlink1_enable, _, _, _, _, _, _, _, _, _, _), 1208 [109] = PINGROUP(109, qlink1_wmss, _, _, _, _, _, _, _, _, _, _), 1209 [110] = PINGROUP(110, uim1_data_mira, _, _, _, _, _, _, _, _, _, _), 1210 [111] = PINGROUP(111, uim1_clk_mira, _, _, _, _, _, _, _, _, _, _), 1211 [112] = PINGROUP(112, uim1_reset_mira, _, _, _, _, _, _, _, _, _, _), 1212 [113] = PINGROUP(113, uim1_present_mira, _, _, _, _, _, _, _, _, _, _), 1213 [114] = PINGROUP(114, _, _, _, _, _, _, _, _, _, _, _), 1214 [115] = PINGROUP(115, _, _, _, _, _, _, _, _, _, _, _), 1215 [116] = PINGROUP(116, _, _, _, _, _, _, _, _, _, _, _), 1216 [117] = PINGROUP(117, _, _, _, _, _, _, _, _, _, _, _), 1217 [118] = PINGROUP(118, _, _, _, _, _, _, _, _, _, _, _), 1218 [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, _), 1219 [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _, _, _), 1220 [121] = PINGROUP(121, _, _, _, _, _, _, _, _, _, _, _), 1221 [122] = PINGROUP(122, _, _, _, _, _, _, _, _, _, _, _), 1222 [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _, _, _), 1223 [124] = PINGROUP(124, nav_gpio0, _, _, _, _, _, _, _, _, _, _), 1224 [125] = PINGROUP(125, nav_gpio1, usb0_hs, _, _, _, _, _, _, _, _, _), 1225 [126] = PINGROUP(126, _, nav_gpio2, vfr_1, _, _, _, _, _, _, _, _), 1226 [127] = PINGROUP(127, _, _, phase_flag, _, _, _, _, _, _, _, _), 1227 [128] = PINGROUP(128, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _), 1228 [129] = PINGROUP(129, mdp_vsync, _, _, _, _, _, _, _, _, _, _), 1229 [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _, _, _), 1230 [131] = PINGROUP(131, usb0_phy_ps, _, _, _, _, _, _, _, _, _, _), 1231 [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _, _, egpio), 1232 [133] = PINGROUP(133, ddr_bist_start, _, _, _, _, _, _, _, _, _, egpio), 1233 [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _, _, egpio), 1234 [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, egpio), 1235 [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, egpio), 1236 [137] = PINGROUP(137, ddr_bist_complete, _, _, _, _, _, _, _, _, _, egpio), 1237 [138] = PINGROUP(138, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _, egpio), 1238 [139] = PINGROUP(139, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _, egpio), 1239 [140] = PINGROUP(140, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _, egpio), 1240 [141] = PINGROUP(141, jitter_bist, qdss_gpio, _, _, _, _, _, _, _, _, egpio), 1241 [142] = PINGROUP(142, _, phase_flag, _, _, _, _, _, _, _, _, egpio), 1242 [143] = PINGROUP(143, _, phase_flag, _, _, _, _, _, _, _, _, egpio), 1243 [144] = PINGROUP(144, _, phase_flag, _, _, _, _, _, _, _, _, egpio), 1244 [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _, _, egpio), 1245 [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _, _, egpio), 1246 [147] = PINGROUP(147, _, phase_flag, _, _, _, _, _, _, _, _, egpio), 1247 [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _, _, egpio), 1248 [149] = PINGROUP(149, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), 1249 [150] = PINGROUP(150, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), 1250 [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, egpio), 1251 [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, egpio), 1252 [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, egpio), 1253 [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, egpio), 1254 [155] = PINGROUP(155, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), 1255 [156] = PINGROUP(156, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), 1256 [157] = PINGROUP(157, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), 1257 [158] = PINGROUP(158, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), 1258 [159] = PINGROUP(159, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), 1259 [160] = PINGROUP(160, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), 1260 [161] = PINGROUP(161, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), 1261 [162] = PINGROUP(162, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), 1262 [163] = PINGROUP(163, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), 1263 [164] = PINGROUP(164, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), 1264 [165] = PINGROUP(165, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), 1265 [166] = PINGROUP(166, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), 1266 [167] = UFS_RESET(ufs_reset, 0xb4004, 0xb5000), 1267 [168] = SDC_QDSD_PINGROUP(sdc2_clk, 0xab000, 0, 6), 1268 [169] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xab000, 12, 3), 1269 [170] = SDC_QDSD_PINGROUP(sdc2_data, 0xab000, 9, 0), 1270 }; 1271 1272 static const struct msm_gpio_wakeirq_map milos_pdc_map[] = { 1273 { 0, 122 }, { 3, 95 }, { 4, 100 }, { 6, 52 }, { 7, 119 }, 1274 { 8, 92 }, { 11, 54 }, { 12, 56 }, { 13, 64 }, { 14, 75 }, 1275 { 15, 82 }, { 18, 89 }, { 19, 90 }, { 22, 93 }, { 23, 94 }, 1276 { 26, 91 }, { 27, 57 }, { 30, 138 }, { 31, 96 }, { 32, 67 }, 1277 { 34, 128 }, { 35, 98 }, { 36, 99 }, { 38, 101 }, { 39, 102 }, 1278 { 40, 69 }, { 43, 103 }, { 44, 104 }, { 45, 126 }, { 47, 59 }, 1279 { 48, 106 }, { 51, 107 }, { 52, 108 }, { 54, 110 }, { 55, 140 }, 1280 { 56, 58 }, { 57, 129 }, { 58, 111 }, { 59, 112 }, { 60, 115 }, 1281 { 61, 113 }, { 62, 114 }, { 64, 105 }, { 65, 55 }, { 67, 116 }, 1282 { 68, 117 }, { 70, 120 }, { 71, 121 }, { 72, 97 }, { 73, 109 }, 1283 { 74, 118 }, { 75, 132 }, { 76, 144 }, { 77, 127 }, { 78, 133 }, 1284 { 79, 134 }, { 80, 135 }, { 81, 124 }, { 82, 136 }, { 87, 60 }, 1285 { 91, 123 }, { 92, 125 }, { 95, 139 }, { 99, 53 }, { 103, 61 }, 1286 { 104, 71 }, { 107, 137 }, { 113, 51 }, { 124, 72 }, { 125, 62 }, 1287 { 126, 73 }, { 128, 63 }, { 129, 130 }, { 130, 65 }, { 131, 66 }, 1288 { 133, 68 }, { 136, 70 }, { 143, 78 }, { 144, 79 }, { 145, 142 }, 1289 { 148, 81 }, { 149, 76 }, { 150, 83 }, { 151, 84 }, { 153, 74 }, 1290 { 155, 131 }, { 158, 85 }, { 159, 77 }, { 161, 80 }, { 162, 143 }, 1291 { 163, 86 }, { 164, 87 }, { 166, 88 }, 1292 }; 1293 1294 static const struct msm_pinctrl_soc_data milos_tlmm = { 1295 .pins = milos_pins, 1296 .npins = ARRAY_SIZE(milos_pins), 1297 .functions = milos_functions, 1298 .nfunctions = ARRAY_SIZE(milos_functions), 1299 .groups = milos_groups, 1300 .ngroups = ARRAY_SIZE(milos_groups), 1301 .ngpios = 168, 1302 .wakeirq_map = milos_pdc_map, 1303 .nwakeirq_map = ARRAY_SIZE(milos_pdc_map), 1304 .egpio_func = 11, 1305 }; 1306 1307 static int milos_tlmm_probe(struct platform_device *pdev) 1308 { 1309 return msm_pinctrl_probe(pdev, &milos_tlmm); 1310 } 1311 1312 static const struct of_device_id milos_tlmm_of_match[] = { 1313 { .compatible = "qcom,milos-tlmm" }, 1314 { /* sentinel */ } 1315 }; 1316 1317 static struct platform_driver milos_tlmm_driver = { 1318 .driver = { 1319 .name = "milos-tlmm", 1320 .of_match_table = milos_tlmm_of_match, 1321 }, 1322 .probe = milos_tlmm_probe, 1323 }; 1324 1325 static int __init milos_tlmm_init(void) 1326 { 1327 return platform_driver_register(&milos_tlmm_driver); 1328 } 1329 arch_initcall(milos_tlmm_init); 1330 1331 static void __exit milos_tlmm_exit(void) 1332 { 1333 platform_driver_unregister(&milos_tlmm_driver); 1334 } 1335 module_exit(milos_tlmm_exit); 1336 1337 MODULE_DESCRIPTION("QTI Milos TLMM driver"); 1338 MODULE_LICENSE("GPL"); 1339 MODULE_DEVICE_TABLE(of, milos_tlmm_of_match); 1340