1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020 Linaro Ltd. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/gpio/driver.h> 10 #include <linux/module.h> 11 #include <linux/of_device.h> 12 #include <linux/seq_file.h> 13 14 #include <linux/pinctrl/pinconf-generic.h> 15 #include <linux/pinctrl/pinconf.h> 16 #include <linux/pinctrl/pinmux.h> 17 18 #include "../pinctrl-utils.h" 19 20 #include "pinctrl-lpass-lpi.h" 21 22 #define MAX_NR_GPIO 23 23 #define GPIO_FUNC 0 24 #define MAX_LPI_NUM_CLKS 2 25 26 struct lpi_pinctrl { 27 struct device *dev; 28 struct pinctrl_dev *ctrl; 29 struct gpio_chip chip; 30 struct pinctrl_desc desc; 31 char __iomem *tlmm_base; 32 char __iomem *slew_base; 33 struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; 34 struct mutex slew_access_lock; 35 DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); 36 const struct lpi_pinctrl_variant_data *data; 37 }; 38 39 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, 40 unsigned int addr) 41 { 42 return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); 43 } 44 45 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, 46 unsigned int addr, unsigned int val) 47 { 48 iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); 49 50 return 0; 51 } 52 53 static const struct pinctrl_ops lpi_gpio_pinctrl_ops = { 54 .get_groups_count = pinctrl_generic_get_group_count, 55 .get_group_name = pinctrl_generic_get_group_name, 56 .get_group_pins = pinctrl_generic_get_group_pins, 57 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 58 .dt_free_map = pinctrl_utils_free_map, 59 }; 60 61 static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev) 62 { 63 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 64 65 return pctrl->data->nfunctions; 66 } 67 68 static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev, 69 unsigned int function) 70 { 71 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 72 73 return pctrl->data->functions[function].name; 74 } 75 76 static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev, 77 unsigned int function, 78 const char *const **groups, 79 unsigned *const num_qgroups) 80 { 81 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 82 83 *groups = pctrl->data->functions[function].groups; 84 *num_qgroups = pctrl->data->functions[function].ngroups; 85 86 return 0; 87 } 88 89 static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, 90 unsigned int group) 91 { 92 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 93 const struct lpi_pingroup *g = &pctrl->data->groups[group]; 94 u32 val; 95 int i, pin = g->pin; 96 97 for (i = 0; i < g->nfuncs; i++) { 98 if (g->funcs[i] == function) 99 break; 100 } 101 102 if (WARN_ON(i == g->nfuncs)) 103 return -EINVAL; 104 105 val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG); 106 107 /* 108 * If this is the first time muxing to GPIO and the direction is 109 * output, make sure that we're not going to be glitching the pin 110 * by reading the current state of the pin and setting it as the 111 * output. 112 */ 113 if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) && 114 !test_and_set_bit(group, pctrl->ever_gpio)) { 115 u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG); 116 117 if (io_val & LPI_GPIO_VALUE_IN_MASK) { 118 if (!(io_val & LPI_GPIO_VALUE_OUT_MASK)) 119 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, 120 io_val | LPI_GPIO_VALUE_OUT_MASK); 121 } else { 122 if (io_val & LPI_GPIO_VALUE_OUT_MASK) 123 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, 124 io_val & ~LPI_GPIO_VALUE_OUT_MASK); 125 } 126 } 127 128 u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); 129 lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); 130 131 return 0; 132 } 133 134 static const struct pinmux_ops lpi_gpio_pinmux_ops = { 135 .get_functions_count = lpi_gpio_get_functions_count, 136 .get_function_name = lpi_gpio_get_function_name, 137 .get_function_groups = lpi_gpio_get_function_groups, 138 .set_mux = lpi_gpio_set_mux, 139 }; 140 141 static int lpi_config_get(struct pinctrl_dev *pctldev, 142 unsigned int pin, unsigned long *config) 143 { 144 unsigned int param = pinconf_to_config_param(*config); 145 struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev); 146 unsigned int arg = 0; 147 int is_out; 148 int pull; 149 u32 ctl_reg; 150 151 ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG); 152 is_out = ctl_reg & LPI_GPIO_OE_MASK; 153 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); 154 155 switch (param) { 156 case PIN_CONFIG_BIAS_DISABLE: 157 if (pull == LPI_GPIO_BIAS_DISABLE) 158 arg = 1; 159 break; 160 case PIN_CONFIG_BIAS_PULL_DOWN: 161 if (pull == LPI_GPIO_PULL_DOWN) 162 arg = 1; 163 break; 164 case PIN_CONFIG_BIAS_BUS_HOLD: 165 if (pull == LPI_GPIO_KEEPER) 166 arg = 1; 167 break; 168 case PIN_CONFIG_BIAS_PULL_UP: 169 if (pull == LPI_GPIO_PULL_UP) 170 arg = 1; 171 break; 172 case PIN_CONFIG_INPUT_ENABLE: 173 case PIN_CONFIG_OUTPUT: 174 if (is_out) 175 arg = 1; 176 break; 177 default: 178 return -EINVAL; 179 } 180 181 *config = pinconf_to_config_packed(param, arg); 182 return 0; 183 } 184 185 static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, 186 unsigned long *configs, unsigned int nconfs) 187 { 188 struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev); 189 unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2; 190 bool value, output_enabled = false; 191 const struct lpi_pingroup *g; 192 unsigned long sval; 193 int i, slew_offset; 194 u32 val; 195 196 g = &pctrl->data->groups[group]; 197 for (i = 0; i < nconfs; i++) { 198 param = pinconf_to_config_param(configs[i]); 199 arg = pinconf_to_config_argument(configs[i]); 200 201 switch (param) { 202 case PIN_CONFIG_BIAS_DISABLE: 203 pullup = LPI_GPIO_BIAS_DISABLE; 204 break; 205 case PIN_CONFIG_BIAS_PULL_DOWN: 206 pullup = LPI_GPIO_PULL_DOWN; 207 break; 208 case PIN_CONFIG_BIAS_BUS_HOLD: 209 pullup = LPI_GPIO_KEEPER; 210 break; 211 case PIN_CONFIG_BIAS_PULL_UP: 212 pullup = LPI_GPIO_PULL_UP; 213 break; 214 case PIN_CONFIG_INPUT_ENABLE: 215 output_enabled = false; 216 break; 217 case PIN_CONFIG_OUTPUT: 218 output_enabled = true; 219 value = arg; 220 break; 221 case PIN_CONFIG_DRIVE_STRENGTH: 222 strength = arg; 223 break; 224 case PIN_CONFIG_SLEW_RATE: 225 if (arg > LPI_SLEW_RATE_MAX) { 226 dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n", 227 arg, group); 228 return -EINVAL; 229 } 230 231 slew_offset = g->slew_offset; 232 if (slew_offset == LPI_NO_SLEW) 233 break; 234 235 mutex_lock(&pctrl->slew_access_lock); 236 237 sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); 238 sval &= ~(LPI_SLEW_RATE_MASK << slew_offset); 239 sval |= arg << slew_offset; 240 iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); 241 242 mutex_unlock(&pctrl->slew_access_lock); 243 break; 244 default: 245 return -EINVAL; 246 } 247 } 248 249 /* 250 * As per Hardware Programming Guide, when configuring pin as output, 251 * set the pin value before setting output-enable (OE). 252 */ 253 if (output_enabled) { 254 val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); 255 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); 256 } 257 258 val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG); 259 260 u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); 261 u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), 262 LPI_GPIO_OUT_STRENGTH_MASK); 263 u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); 264 265 lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); 266 267 return 0; 268 } 269 270 static const struct pinconf_ops lpi_gpio_pinconf_ops = { 271 .is_generic = true, 272 .pin_config_group_get = lpi_config_get, 273 .pin_config_group_set = lpi_config_set, 274 }; 275 276 static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) 277 { 278 struct lpi_pinctrl *state = gpiochip_get_data(chip); 279 unsigned long config; 280 281 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); 282 283 return lpi_config_set(state->ctrl, pin, &config, 1); 284 } 285 286 static int lpi_gpio_direction_output(struct gpio_chip *chip, 287 unsigned int pin, int val) 288 { 289 struct lpi_pinctrl *state = gpiochip_get_data(chip); 290 unsigned long config; 291 292 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); 293 294 return lpi_config_set(state->ctrl, pin, &config, 1); 295 } 296 297 static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) 298 { 299 struct lpi_pinctrl *state = gpiochip_get_data(chip); 300 301 return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) & 302 LPI_GPIO_VALUE_IN_MASK; 303 } 304 305 static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 306 { 307 struct lpi_pinctrl *state = gpiochip_get_data(chip); 308 unsigned long config; 309 310 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); 311 312 lpi_config_set(state->ctrl, pin, &config, 1); 313 } 314 315 #ifdef CONFIG_DEBUG_FS 316 #include <linux/seq_file.h> 317 318 static unsigned int lpi_regval_to_drive(u32 val) 319 { 320 return (val + 1) * 2; 321 } 322 323 static void lpi_gpio_dbg_show_one(struct seq_file *s, 324 struct pinctrl_dev *pctldev, 325 struct gpio_chip *chip, 326 unsigned int offset, 327 unsigned int gpio) 328 { 329 struct lpi_pinctrl *state = gpiochip_get_data(chip); 330 struct pinctrl_pin_desc pindesc; 331 unsigned int func; 332 int is_out; 333 int drive; 334 int pull; 335 u32 ctl_reg; 336 337 static const char * const pulls[] = { 338 "no pull", 339 "pull down", 340 "keeper", 341 "pull up" 342 }; 343 344 pctldev = pctldev ? : state->ctrl; 345 pindesc = pctldev->desc->pins[offset]; 346 ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG); 347 is_out = ctl_reg & LPI_GPIO_OE_MASK; 348 349 func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg); 350 drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg); 351 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); 352 353 seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func); 354 seq_printf(s, " %dmA", lpi_regval_to_drive(drive)); 355 seq_printf(s, " %s", pulls[pull]); 356 } 357 358 static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 359 { 360 unsigned int gpio = chip->base; 361 unsigned int i; 362 363 for (i = 0; i < chip->ngpio; i++, gpio++) { 364 lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio); 365 seq_puts(s, "\n"); 366 } 367 } 368 369 #else 370 #define lpi_gpio_dbg_show NULL 371 #endif 372 373 static const struct gpio_chip lpi_gpio_template = { 374 .direction_input = lpi_gpio_direction_input, 375 .direction_output = lpi_gpio_direction_output, 376 .get = lpi_gpio_get, 377 .set = lpi_gpio_set, 378 .request = gpiochip_generic_request, 379 .free = gpiochip_generic_free, 380 .dbg_show = lpi_gpio_dbg_show, 381 }; 382 383 static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl) 384 { 385 int i, ret; 386 387 for (i = 0; i < pctrl->data->npins; i++) { 388 const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i; 389 390 ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name, 391 (int *)&pin_info->number, 1, NULL); 392 if (ret < 0) 393 goto err_pinctrl; 394 } 395 396 return 0; 397 398 err_pinctrl: 399 for (; i > 0; i--) 400 pinctrl_generic_remove_group(pctrl->ctrl, i - 1); 401 402 return ret; 403 } 404 405 int lpi_pinctrl_probe(struct platform_device *pdev) 406 { 407 const struct lpi_pinctrl_variant_data *data; 408 struct device *dev = &pdev->dev; 409 struct lpi_pinctrl *pctrl; 410 int ret; 411 412 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 413 if (!pctrl) 414 return -ENOMEM; 415 416 platform_set_drvdata(pdev, pctrl); 417 418 data = of_device_get_match_data(dev); 419 if (!data) 420 return -EINVAL; 421 422 if (WARN_ON(data->npins > MAX_NR_GPIO)) 423 return -EINVAL; 424 425 pctrl->data = data; 426 pctrl->dev = &pdev->dev; 427 428 pctrl->clks[0].id = "core"; 429 pctrl->clks[1].id = "audio"; 430 431 pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0); 432 if (IS_ERR(pctrl->tlmm_base)) 433 return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), 434 "TLMM resource not provided\n"); 435 436 pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1); 437 if (IS_ERR(pctrl->slew_base)) 438 return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), 439 "Slew resource not provided\n"); 440 441 if (of_property_read_bool(dev->of_node, "qcom,adsp-bypass-mode")) 442 ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); 443 else 444 ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks); 445 446 if (ret) 447 return ret; 448 449 ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); 450 if (ret) 451 return dev_err_probe(dev, ret, "Can't enable clocks\n"); 452 453 pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops; 454 pctrl->desc.pmxops = &lpi_gpio_pinmux_ops; 455 pctrl->desc.confops = &lpi_gpio_pinconf_ops; 456 pctrl->desc.owner = THIS_MODULE; 457 pctrl->desc.name = dev_name(dev); 458 pctrl->desc.pins = data->pins; 459 pctrl->desc.npins = data->npins; 460 pctrl->chip = lpi_gpio_template; 461 pctrl->chip.parent = dev; 462 pctrl->chip.base = -1; 463 pctrl->chip.ngpio = data->npins; 464 pctrl->chip.label = dev_name(dev); 465 pctrl->chip.can_sleep = false; 466 467 mutex_init(&pctrl->slew_access_lock); 468 469 pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl); 470 if (IS_ERR(pctrl->ctrl)) { 471 ret = PTR_ERR(pctrl->ctrl); 472 dev_err(dev, "failed to add pin controller\n"); 473 goto err_pinctrl; 474 } 475 476 ret = lpi_build_pin_desc_groups(pctrl); 477 if (ret) 478 goto err_pinctrl; 479 480 ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl); 481 if (ret) { 482 dev_err(pctrl->dev, "can't add gpio chip\n"); 483 goto err_pinctrl; 484 } 485 486 return 0; 487 488 err_pinctrl: 489 mutex_destroy(&pctrl->slew_access_lock); 490 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); 491 492 return ret; 493 } 494 EXPORT_SYMBOL_GPL(lpi_pinctrl_probe); 495 496 int lpi_pinctrl_remove(struct platform_device *pdev) 497 { 498 struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev); 499 int i; 500 501 mutex_destroy(&pctrl->slew_access_lock); 502 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); 503 504 for (i = 0; i < pctrl->data->npins; i++) 505 pinctrl_generic_remove_group(pctrl->ctrl, i); 506 507 return 0; 508 } 509 EXPORT_SYMBOL_GPL(lpi_pinctrl_remove); 510 511 MODULE_DESCRIPTION("QTI LPI GPIO pin control driver"); 512 MODULE_LICENSE("GPL"); 513