xref: /linux/drivers/pinctrl/pinctrl-th1520.c (revision b470fde8f77b56ff273c5527484b99499b894e16) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Pinctrl driver for the T-Head TH1520 SoC
4  *
5  * Copyright (C) 2023 Emil Renner Berthing <emil.renner.berthing@canonical.com>
6  */
7 
8 #include <linux/array_size.h>
9 #include <linux/bits.h>
10 #include <linux/cleanup.h>
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/seq_file.h>
19 #include <linux/spinlock.h>
20 
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 
29 #include "core.h"
30 #include "pinmux.h"
31 #include "pinconf.h"
32 
33 #define TH1520_PADCFG_IE	BIT(9)
34 #define TH1520_PADCFG_SL	BIT(8)
35 #define TH1520_PADCFG_ST	BIT(7)
36 #define TH1520_PADCFG_SPU	BIT(6)
37 #define TH1520_PADCFG_PS	BIT(5)
38 #define TH1520_PADCFG_PE	BIT(4)
39 #define TH1520_PADCFG_BIAS	(TH1520_PADCFG_SPU | TH1520_PADCFG_PS | TH1520_PADCFG_PE)
40 #define TH1520_PADCFG_DS	GENMASK(3, 0)
41 
42 #define TH1520_PULL_DOWN_OHM	44000 /* typ. 44kOhm */
43 #define TH1520_PULL_UP_OHM	48000 /* typ. 48kOhm */
44 #define TH1520_PULL_STRONG_OHM	 2100 /* typ. 2.1kOhm */
45 
46 #define TH1520_PAD_NO_PADCFG	BIT(30)
47 #define TH1520_PAD_MUXDATA	GENMASK(29, 0)
48 
49 struct th1520_pad_group {
50 	const char *name;
51 	const struct pinctrl_pin_desc *pins;
52 	unsigned int npins;
53 };
54 
55 struct th1520_pinctrl {
56 	struct pinctrl_desc desc;
57 	struct mutex mutex;	/* serialize adding functions */
58 	raw_spinlock_t lock;	/* serialize register access */
59 	void __iomem *base;
60 	struct pinctrl_dev *pctl;
61 };
62 
63 static void __iomem *th1520_padcfg(struct th1520_pinctrl *thp,
64 				   unsigned int pin)
65 {
66 	return thp->base + 4 * (pin / 2);
67 }
68 
69 static unsigned int th1520_padcfg_shift(unsigned int pin)
70 {
71 	return 16 * (pin & BIT(0));
72 }
73 
74 static void __iomem *th1520_muxcfg(struct th1520_pinctrl *thp,
75 				   unsigned int pin)
76 {
77 	return thp->base + 0x400 + 4 * (pin / 8);
78 }
79 
80 static unsigned int th1520_muxcfg_shift(unsigned int pin)
81 {
82 	return 4 * (pin & GENMASK(2, 0));
83 }
84 
85 enum th1520_muxtype {
86 	TH1520_MUX_____,
87 	TH1520_MUX_GPIO,
88 	TH1520_MUX_PWM,
89 	TH1520_MUX_UART,
90 	TH1520_MUX_IR,
91 	TH1520_MUX_I2C,
92 	TH1520_MUX_SPI,
93 	TH1520_MUX_QSPI,
94 	TH1520_MUX_SDIO,
95 	TH1520_MUX_AUD,
96 	TH1520_MUX_I2S,
97 	TH1520_MUX_MAC0,
98 	TH1520_MUX_MAC1,
99 	TH1520_MUX_DPU0,
100 	TH1520_MUX_DPU1,
101 	TH1520_MUX_ISP,
102 	TH1520_MUX_HDMI,
103 	TH1520_MUX_BSEL,
104 	TH1520_MUX_DBG,
105 	TH1520_MUX_CLK,
106 	TH1520_MUX_JTAG,
107 	TH1520_MUX_ISO,
108 	TH1520_MUX_FUSE,
109 	TH1520_MUX_RST,
110 };
111 
112 static const char *const th1520_muxtype_string[] = {
113 	[TH1520_MUX_GPIO] = "gpio",
114 	[TH1520_MUX_PWM]  = "pwm",
115 	[TH1520_MUX_UART] = "uart",
116 	[TH1520_MUX_IR]   = "ir",
117 	[TH1520_MUX_I2C]  = "i2c",
118 	[TH1520_MUX_SPI]  = "spi",
119 	[TH1520_MUX_QSPI] = "qspi",
120 	[TH1520_MUX_SDIO] = "sdio",
121 	[TH1520_MUX_AUD]  = "audio",
122 	[TH1520_MUX_I2S]  = "i2s",
123 	[TH1520_MUX_MAC0] = "gmac0",
124 	[TH1520_MUX_MAC1] = "gmac1",
125 	[TH1520_MUX_DPU0] = "dpu0",
126 	[TH1520_MUX_DPU1] = "dpu1",
127 	[TH1520_MUX_ISP]  = "isp",
128 	[TH1520_MUX_HDMI] = "hdmi",
129 	[TH1520_MUX_BSEL] = "bootsel",
130 	[TH1520_MUX_DBG]  = "debug",
131 	[TH1520_MUX_CLK]  = "clock",
132 	[TH1520_MUX_JTAG] = "jtag",
133 	[TH1520_MUX_ISO]  = "iso7816",
134 	[TH1520_MUX_FUSE] = "efuse",
135 	[TH1520_MUX_RST]  = "reset",
136 };
137 
138 static enum th1520_muxtype th1520_muxtype_get(const char *str)
139 {
140 	enum th1520_muxtype mt;
141 
142 	for (mt = TH1520_MUX_GPIO; mt < ARRAY_SIZE(th1520_muxtype_string); mt++) {
143 		if (!strcmp(str, th1520_muxtype_string[mt]))
144 			return mt;
145 	}
146 	return TH1520_MUX_____;
147 }
148 
149 #define TH1520_PAD(_nr, _name, m0, m1, m2, m3, m4, m5, _flags) \
150 	{ .number = _nr, .name = #_name, .drv_data = (void *)((_flags) | \
151 		(TH1520_MUX_##m0 <<  0) | (TH1520_MUX_##m1 <<  5) | (TH1520_MUX_##m2 << 10) | \
152 		(TH1520_MUX_##m3 << 15) | (TH1520_MUX_##m4 << 20) | (TH1520_MUX_##m5 << 25)) }
153 
154 static unsigned long th1520_pad_muxdata(void *drv_data)
155 {
156 	return (uintptr_t)drv_data & TH1520_PAD_MUXDATA;
157 }
158 
159 static bool th1520_pad_no_padcfg(void *drv_data)
160 {
161 	return (uintptr_t)drv_data & TH1520_PAD_NO_PADCFG;
162 }
163 
164 static const struct pinctrl_pin_desc th1520_group1_pins[] = {
165 	TH1520_PAD(0,  OSC_CLK_IN,    ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
166 	TH1520_PAD(1,  OSC_CLK_OUT,   ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
167 	TH1520_PAD(2,  SYS_RST_N,     ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
168 	TH1520_PAD(3,  RTC_CLK_IN,    ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
169 	TH1520_PAD(4,  RTC_CLK_OUT,   ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
170 	/* skip number 5 so we can calculate register offsets and shifts from the pin number */
171 	TH1520_PAD(6,  TEST_MODE,     ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
172 	TH1520_PAD(7,  DEBUG_MODE,    DBG,  ____, ____, GPIO, ____, ____, TH1520_PAD_NO_PADCFG),
173 	TH1520_PAD(8,  POR_SEL,       ____, ____, ____, ____, ____, ____, TH1520_PAD_NO_PADCFG),
174 	TH1520_PAD(9,  I2C_AON_SCL,   I2C,  ____, ____, GPIO, ____, ____, 0),
175 	TH1520_PAD(10, I2C_AON_SDA,   I2C,  ____, ____, GPIO, ____, ____, 0),
176 	TH1520_PAD(11, CPU_JTG_TCLK,  JTAG, ____, ____, GPIO, ____, ____, 0),
177 	TH1520_PAD(12, CPU_JTG_TMS,   JTAG, ____, ____, GPIO, ____, ____, 0),
178 	TH1520_PAD(13, CPU_JTG_TDI,   JTAG, ____, ____, GPIO, ____, ____, 0),
179 	TH1520_PAD(14, CPU_JTG_TDO,   JTAG, ____, ____, GPIO, ____, ____, 0),
180 	TH1520_PAD(15, CPU_JTG_TRST,  JTAG, ____, ____, GPIO, ____, ____, 0),
181 	TH1520_PAD(16, AOGPIO_7,      CLK,  AUD,  ____, GPIO, ____, ____, 0),
182 	TH1520_PAD(17, AOGPIO_8,      UART, AUD,  IR,   GPIO, ____, ____, 0),
183 	TH1520_PAD(18, AOGPIO_9,      UART, AUD,  IR,   GPIO, ____, ____, 0),
184 	TH1520_PAD(19, AOGPIO_10,     CLK,  AUD,  ____, GPIO, ____, ____, 0),
185 	TH1520_PAD(20, AOGPIO_11,     GPIO, AUD,  ____, ____, ____, ____, 0),
186 	TH1520_PAD(21, AOGPIO_12,     GPIO, AUD,  ____, ____, ____, ____, 0),
187 	TH1520_PAD(22, AOGPIO_13,     GPIO, AUD,  ____, ____, ____, ____, 0),
188 	TH1520_PAD(23, AOGPIO_14,     GPIO, AUD,  ____, ____, ____, ____, 0),
189 	TH1520_PAD(24, AOGPIO_15,     GPIO, AUD,  ____, ____, ____, ____, 0),
190 	TH1520_PAD(25, AUDIO_PA0,     AUD,  ____, ____, GPIO, ____, ____, 0),
191 	TH1520_PAD(26, AUDIO_PA1,     AUD,  ____, ____, GPIO, ____, ____, 0),
192 	TH1520_PAD(27, AUDIO_PA2,     AUD,  ____, ____, GPIO, ____, ____, 0),
193 	TH1520_PAD(28, AUDIO_PA3,     AUD,  ____, ____, GPIO, ____, ____, 0),
194 	TH1520_PAD(29, AUDIO_PA4,     AUD,  ____, ____, GPIO, ____, ____, 0),
195 	TH1520_PAD(30, AUDIO_PA5,     AUD,  ____, ____, GPIO, ____, ____, 0),
196 	TH1520_PAD(31, AUDIO_PA6,     AUD,  ____, ____, GPIO, ____, ____, 0),
197 	TH1520_PAD(32, AUDIO_PA7,     AUD,  ____, ____, GPIO, ____, ____, 0),
198 	TH1520_PAD(33, AUDIO_PA8,     AUD,  ____, ____, GPIO, ____, ____, 0),
199 	TH1520_PAD(34, AUDIO_PA9,     AUD,  ____, ____, GPIO, ____, ____, 0),
200 	TH1520_PAD(35, AUDIO_PA10,    AUD,  ____, ____, GPIO, ____, ____, 0),
201 	TH1520_PAD(36, AUDIO_PA11,    AUD,  ____, ____, GPIO, ____, ____, 0),
202 	TH1520_PAD(37, AUDIO_PA12,    AUD,  ____, ____, GPIO, ____, ____, 0),
203 	TH1520_PAD(38, AUDIO_PA13,    AUD,  ____, ____, GPIO, ____, ____, 0),
204 	TH1520_PAD(39, AUDIO_PA14,    AUD,  ____, ____, GPIO, ____, ____, 0),
205 	TH1520_PAD(40, AUDIO_PA15,    AUD,  ____, ____, GPIO, ____, ____, 0),
206 	TH1520_PAD(41, AUDIO_PA16,    AUD,  ____, ____, GPIO, ____, ____, 0),
207 	TH1520_PAD(42, AUDIO_PA17,    AUD,  ____, ____, GPIO, ____, ____, 0),
208 	TH1520_PAD(43, AUDIO_PA27,    AUD,  ____, ____, GPIO, ____, ____, 0),
209 	TH1520_PAD(44, AUDIO_PA28,    AUD,  ____, ____, GPIO, ____, ____, 0),
210 	TH1520_PAD(45, AUDIO_PA29,    AUD,  ____, ____, GPIO, ____, ____, 0),
211 	TH1520_PAD(46, AUDIO_PA30,    AUD,  RST,  ____, GPIO, ____, ____, 0),
212 };
213 
214 static const struct pinctrl_pin_desc th1520_group2_pins[] = {
215 	TH1520_PAD(0,  QSPI1_SCLK,    QSPI, ISO,  ____, GPIO, FUSE, ____, 0),
216 	TH1520_PAD(1,  QSPI1_CSN0,    QSPI, ____, I2C,  GPIO, FUSE, ____, 0),
217 	TH1520_PAD(2,  QSPI1_D0_MOSI, QSPI, ISO,  I2C,  GPIO, FUSE, ____, 0),
218 	TH1520_PAD(3,  QSPI1_D1_MISO, QSPI, ISO,  ____, GPIO, FUSE, ____, 0),
219 	TH1520_PAD(4,  QSPI1_D2_WP,   QSPI, ISO,  UART, GPIO, FUSE, ____, 0),
220 	TH1520_PAD(5,  QSPI1_D3_HOLD, QSPI, ISO,  UART, GPIO, ____, ____, 0),
221 	TH1520_PAD(6,  I2C0_SCL,      I2C,  ____, ____, GPIO, ____, ____, 0),
222 	TH1520_PAD(7,  I2C0_SDA,      I2C,  ____, ____, GPIO, ____, ____, 0),
223 	TH1520_PAD(8,  I2C1_SCL,      I2C,  ____, ____, GPIO, ____, ____, 0),
224 	TH1520_PAD(9,  I2C1_SDA,      I2C,  ____, ____, GPIO, ____, ____, 0),
225 	TH1520_PAD(10, UART1_TXD,     UART, ____, ____, GPIO, ____, ____, 0),
226 	TH1520_PAD(11, UART1_RXD,     UART, ____, ____, GPIO, ____, ____, 0),
227 	TH1520_PAD(12, UART4_TXD,     UART, ____, ____, GPIO, ____, ____, 0),
228 	TH1520_PAD(13, UART4_RXD,     UART, ____, ____, GPIO, ____, ____, 0),
229 	TH1520_PAD(14, UART4_CTSN,    UART, ____, ____, GPIO, ____, ____, 0),
230 	TH1520_PAD(15, UART4_RTSN,    UART, ____, ____, GPIO, ____, ____, 0),
231 	TH1520_PAD(16, UART3_TXD,     DBG,  UART, ____, GPIO, ____, ____, 0),
232 	TH1520_PAD(17, UART3_RXD,     DBG,  UART, ____, GPIO, ____, ____, 0),
233 	TH1520_PAD(18, GPIO0_18,      GPIO, I2C,  ____, ____, DPU0, DPU1, 0),
234 	TH1520_PAD(19, GPIO0_19,      GPIO, I2C,  ____, ____, DPU0, DPU1, 0),
235 	TH1520_PAD(20, GPIO0_20,      GPIO, UART, IR,   ____, DPU0, DPU1, 0),
236 	TH1520_PAD(21, GPIO0_21,      GPIO, UART, IR,   ____, DPU0, DPU1, 0),
237 	TH1520_PAD(22, GPIO0_22,      GPIO, JTAG, I2C,  ____, DPU0, DPU1, 0),
238 	TH1520_PAD(23, GPIO0_23,      GPIO, JTAG, I2C,  ____, DPU0, DPU1, 0),
239 	TH1520_PAD(24, GPIO0_24,      GPIO, JTAG, QSPI, ____, DPU0, DPU1, 0),
240 	TH1520_PAD(25, GPIO0_25,      GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
241 	TH1520_PAD(26, GPIO0_26,      GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
242 	TH1520_PAD(27, GPIO0_27,      GPIO, ____, I2C,  ____, DPU0, DPU1, 0),
243 	TH1520_PAD(28, GPIO0_28,      GPIO, ____, I2C,  ____, DPU0, DPU1, 0),
244 	TH1520_PAD(29, GPIO0_29,      GPIO, ____, ____, ____, DPU0, DPU1, 0),
245 	TH1520_PAD(30, GPIO0_30,      GPIO, ____, ____, ____, DPU0, DPU1, 0),
246 	TH1520_PAD(31, GPIO0_31,      GPIO, ____, ____, ____, DPU0, DPU1, 0),
247 	TH1520_PAD(32, GPIO1_0,       GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
248 	TH1520_PAD(33, GPIO1_1,       GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
249 	TH1520_PAD(34, GPIO1_2,       GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
250 	TH1520_PAD(35, GPIO1_3,       GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
251 	TH1520_PAD(36, GPIO1_4,       GPIO, JTAG, ____, ____, DPU0, DPU1, 0),
252 	TH1520_PAD(37, GPIO1_5,       GPIO, ____, ____, ____, DPU0, DPU1, 0),
253 	TH1520_PAD(38, GPIO1_6,       GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
254 	TH1520_PAD(39, GPIO1_7,       GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
255 	TH1520_PAD(40, GPIO1_8,       GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
256 	TH1520_PAD(41, GPIO1_9,       GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
257 	TH1520_PAD(42, GPIO1_10,      GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
258 	TH1520_PAD(43, GPIO1_11,      GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
259 	TH1520_PAD(44, GPIO1_12,      GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
260 	TH1520_PAD(45, GPIO1_13,      GPIO, UART, ____, ____, DPU0, DPU1, 0),
261 	TH1520_PAD(46, GPIO1_14,      GPIO, UART, ____, ____, DPU0, DPU1, 0),
262 	TH1520_PAD(47, GPIO1_15,      GPIO, UART, ____, ____, DPU0, DPU1, 0),
263 	TH1520_PAD(48, GPIO1_16,      GPIO, UART, ____, ____, DPU0, DPU1, 0),
264 	TH1520_PAD(49, CLK_OUT_0,     BSEL, CLK,  ____, GPIO, ____, ____, 0),
265 	TH1520_PAD(50, CLK_OUT_1,     BSEL, CLK,  ____, GPIO, ____, ____, 0),
266 	TH1520_PAD(51, CLK_OUT_2,     BSEL, CLK,  ____, GPIO, ____, ____, 0),
267 	TH1520_PAD(52, CLK_OUT_3,     BSEL, CLK,  ____, GPIO, ____, ____, 0),
268 	TH1520_PAD(53, GPIO1_21,      JTAG, ____, ISP,  GPIO, ____, ____, 0),
269 	TH1520_PAD(54, GPIO1_22,      JTAG, ____, ISP,  GPIO, ____, ____, 0),
270 	TH1520_PAD(55, GPIO1_23,      JTAG, ____, ISP,  GPIO, ____, ____, 0),
271 	TH1520_PAD(56, GPIO1_24,      JTAG, ____, ISP,  GPIO, ____, ____, 0),
272 	TH1520_PAD(57, GPIO1_25,      JTAG, ____, ISP,  GPIO, ____, ____, 0),
273 	TH1520_PAD(58, GPIO1_26,      GPIO, ____, ISP,  ____, ____, ____, 0),
274 	TH1520_PAD(59, GPIO1_27,      GPIO, ____, ISP,  ____, ____, ____, 0),
275 	TH1520_PAD(60, GPIO1_28,      GPIO, ____, ISP,  ____, ____, ____, 0),
276 	TH1520_PAD(61, GPIO1_29,      GPIO, ____, ISP,  ____, ____, ____, 0),
277 	TH1520_PAD(62, GPIO1_30,      GPIO, ____, ISP,  ____, ____, ____, 0),
278 };
279 
280 static const struct pinctrl_pin_desc th1520_group3_pins[] = {
281 	TH1520_PAD(0,  UART0_TXD,     UART, ____, ____, GPIO, ____, ____, 0),
282 	TH1520_PAD(1,  UART0_RXD,     UART, ____, ____, GPIO, ____, ____, 0),
283 	TH1520_PAD(2,  QSPI0_SCLK,    QSPI, PWM,  I2S,  GPIO, ____, ____, 0),
284 	TH1520_PAD(3,  QSPI0_CSN0,    QSPI, PWM,  I2S,  GPIO, ____, ____, 0),
285 	TH1520_PAD(4,  QSPI0_CSN1,    QSPI, PWM,  I2S,  GPIO, ____, ____, 0),
286 	TH1520_PAD(5,  QSPI0_D0_MOSI, QSPI, PWM,  I2S,  GPIO, ____, ____, 0),
287 	TH1520_PAD(6,  QSPI0_D1_MISO, QSPI, PWM,  I2S,  GPIO, ____, ____, 0),
288 	TH1520_PAD(7,  QSPI0_D2_WP,   QSPI, PWM,  I2S,  GPIO, ____, ____, 0),
289 	TH1520_PAD(8,  QSPI0_D3_HOLD, QSPI, ____, I2S,  GPIO, ____, ____, 0),
290 	TH1520_PAD(9,  I2C2_SCL,      I2C,  UART, ____, GPIO, ____, ____, 0),
291 	TH1520_PAD(10, I2C2_SDA,      I2C,  UART, ____, GPIO, ____, ____, 0),
292 	TH1520_PAD(11, I2C3_SCL,      I2C,  ____, ____, GPIO, ____, ____, 0),
293 	TH1520_PAD(12, I2C3_SDA,      I2C,  ____, ____, GPIO, ____, ____, 0),
294 	TH1520_PAD(13, GPIO2_13,      GPIO, SPI,  ____, ____, ____, ____, 0),
295 	TH1520_PAD(14, SPI_SCLK,      SPI,  UART, IR,   GPIO, ____, ____, 0),
296 	TH1520_PAD(15, SPI_CSN,       SPI,  UART, IR,   GPIO, ____, ____, 0),
297 	TH1520_PAD(16, SPI_MOSI,      SPI,  ____, ____, GPIO, ____, ____, 0),
298 	TH1520_PAD(17, SPI_MISO,      SPI,  ____, ____, GPIO, ____, ____, 0),
299 	TH1520_PAD(18, GPIO2_18,      GPIO, MAC1, ____, ____, ____, ____, 0),
300 	TH1520_PAD(19, GPIO2_19,      GPIO, MAC1, ____, ____, ____, ____, 0),
301 	TH1520_PAD(20, GPIO2_20,      GPIO, MAC1, ____, ____, ____, ____, 0),
302 	TH1520_PAD(21, GPIO2_21,      GPIO, MAC1, ____, ____, ____, ____, 0),
303 	TH1520_PAD(22, GPIO2_22,      GPIO, MAC1, ____, ____, ____, ____, 0),
304 	TH1520_PAD(23, GPIO2_23,      GPIO, MAC1, ____, ____, ____, ____, 0),
305 	TH1520_PAD(24, GPIO2_24,      GPIO, MAC1, ____, ____, ____, ____, 0),
306 	TH1520_PAD(25, GPIO2_25,      GPIO, MAC1, ____, ____, ____, ____, 0),
307 	TH1520_PAD(26, SDIO0_WPRTN,   SDIO, ____, ____, GPIO, ____, ____, 0),
308 	TH1520_PAD(27, SDIO0_DETN,    SDIO, ____, ____, GPIO, ____, ____, 0),
309 	TH1520_PAD(28, SDIO1_WPRTN,   SDIO, ____, ____, GPIO, ____, ____, 0),
310 	TH1520_PAD(29, SDIO1_DETN,    SDIO, ____, ____, GPIO, ____, ____, 0),
311 	TH1520_PAD(30, GPIO2_30,      GPIO, MAC1, ____, ____, ____, ____, 0),
312 	TH1520_PAD(31, GPIO2_31,      GPIO, MAC1, ____, ____, ____, ____, 0),
313 	TH1520_PAD(32, GPIO3_0,       GPIO, MAC1, ____, ____, ____, ____, 0),
314 	TH1520_PAD(33, GPIO3_1,       GPIO, MAC1, ____, ____, ____, ____, 0),
315 	TH1520_PAD(34, GPIO3_2,       GPIO, PWM,  ____, ____, ____, ____, 0),
316 	TH1520_PAD(35, GPIO3_3,       GPIO, PWM,  ____, ____, ____, ____, 0),
317 	TH1520_PAD(36, HDMI_SCL,      HDMI, PWM,  ____, GPIO, ____, ____, 0),
318 	TH1520_PAD(37, HDMI_SDA,      HDMI, PWM,  ____, GPIO, ____, ____, 0),
319 	TH1520_PAD(38, HDMI_CEC,      HDMI, ____, ____, GPIO, ____, ____, 0),
320 	TH1520_PAD(39, GMAC0_TX_CLK,  MAC0, ____, ____, GPIO, ____, ____, 0),
321 	TH1520_PAD(40, GMAC0_RX_CLK,  MAC0, ____, ____, GPIO, ____, ____, 0),
322 	TH1520_PAD(41, GMAC0_TXEN,    MAC0, UART, ____, GPIO, ____, ____, 0),
323 	TH1520_PAD(42, GMAC0_TXD0,    MAC0, UART, ____, GPIO, ____, ____, 0),
324 	TH1520_PAD(43, GMAC0_TXD1,    MAC0, UART, ____, GPIO, ____, ____, 0),
325 	TH1520_PAD(44, GMAC0_TXD2,    MAC0, UART, ____, GPIO, ____, ____, 0),
326 	TH1520_PAD(45, GMAC0_TXD3,    MAC0, I2C,  ____, GPIO, ____, ____, 0),
327 	TH1520_PAD(46, GMAC0_RXDV,    MAC0, I2C,  ____, GPIO, ____, ____, 0),
328 	TH1520_PAD(47, GMAC0_RXD0,    MAC0, I2C,  ____, GPIO, ____, ____, 0),
329 	TH1520_PAD(48, GMAC0_RXD1,    MAC0, I2C,  ____, GPIO, ____, ____, 0),
330 	TH1520_PAD(49, GMAC0_RXD2,    MAC0, SPI,  ____, GPIO, ____, ____, 0),
331 	TH1520_PAD(50, GMAC0_RXD3,    MAC0, SPI,  ____, GPIO, ____, ____, 0),
332 	TH1520_PAD(51, GMAC0_MDC,     MAC0, SPI,  MAC1, GPIO, ____, ____, 0),
333 	TH1520_PAD(52, GMAC0_MDIO,    MAC0, SPI,  MAC1, GPIO, ____, ____, 0),
334 	TH1520_PAD(53, GMAC0_COL,     MAC0, PWM,  ____, GPIO, ____, ____, 0),
335 	TH1520_PAD(54, GMAC0_CRS,     MAC0, PWM,  ____, GPIO, ____, ____, 0),
336 };
337 
338 static const struct th1520_pad_group th1520_group1 = {
339 	.name = "th1520-group1",
340 	.pins = th1520_group1_pins,
341 	.npins = ARRAY_SIZE(th1520_group1_pins),
342 };
343 
344 static const struct th1520_pad_group th1520_group2 = {
345 	.name = "th1520-group2",
346 	.pins = th1520_group2_pins,
347 	.npins = ARRAY_SIZE(th1520_group2_pins),
348 };
349 
350 static const struct th1520_pad_group th1520_group3 = {
351 	.name = "th1520-group3",
352 	.pins = th1520_group3_pins,
353 	.npins = ARRAY_SIZE(th1520_group3_pins),
354 };
355 
356 static int th1520_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
357 {
358 	struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
359 
360 	return thp->desc.npins;
361 }
362 
363 static const char *th1520_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
364 						 unsigned int gsel)
365 {
366 	struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
367 
368 	return thp->desc.pins[gsel].name;
369 }
370 
371 static int th1520_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
372 					 unsigned int gsel,
373 					 const unsigned int **pins,
374 					 unsigned int *npins)
375 {
376 	struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
377 
378 	*pins = &thp->desc.pins[gsel].number;
379 	*npins = 1;
380 	return 0;
381 }
382 
383 #ifdef CONFIG_DEBUG_FS
384 static void th1520_pin_dbg_show(struct pinctrl_dev *pctldev,
385 				struct seq_file *s, unsigned int pin)
386 {
387 	struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
388 	void __iomem *padcfg = th1520_padcfg(thp, pin);
389 	void __iomem *muxcfg = th1520_muxcfg(thp, pin);
390 	u32 pad;
391 	u32 mux;
392 
393 	scoped_guard(raw_spinlock_irqsave, &thp->lock) {
394 		pad = readl_relaxed(padcfg);
395 		mux = readl_relaxed(muxcfg);
396 	}
397 
398 	seq_printf(s, "[PADCFG_%03u:0x%x=0x%07x MUXCFG_%03u:0x%x=0x%08x]",
399 		   1 + pin / 2, 0x000 + 4 * (pin / 2), pad,
400 		   1 + pin / 8, 0x400 + 4 * (pin / 8), mux);
401 }
402 #else
403 #define th1520_pin_dbg_show NULL
404 #endif
405 
406 static void th1520_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
407 				       struct pinctrl_map *map, unsigned int nmaps)
408 {
409 	unsigned long *seen = NULL;
410 	unsigned int i;
411 
412 	for (i = 0; i < nmaps; i++) {
413 		if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN &&
414 		    map[i].data.configs.configs != seen) {
415 			seen = map[i].data.configs.configs;
416 			kfree(seen);
417 		}
418 	}
419 
420 	kfree(map);
421 }
422 
423 static int th1520_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
424 					 struct device_node *np,
425 					 struct pinctrl_map **maps,
426 					 unsigned int *num_maps)
427 {
428 	struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
429 	struct pinctrl_map *map;
430 	unsigned long *configs;
431 	unsigned int nconfigs;
432 	unsigned int nmaps;
433 	int ret;
434 
435 	nmaps = 0;
436 	for_each_available_child_of_node_scoped(np, child) {
437 		int npins = of_property_count_strings(child, "pins");
438 
439 		if (npins <= 0) {
440 			dev_err(thp->pctl->dev, "no pins selected for %pOFn.%pOFn\n",
441 				np, child);
442 			return -EINVAL;
443 		}
444 		nmaps += npins;
445 		if (of_property_present(child, "function"))
446 			nmaps += npins;
447 	}
448 
449 	map = kzalloc_objs(*map, nmaps);
450 	if (!map)
451 		return -ENOMEM;
452 
453 	nmaps = 0;
454 	guard(mutex)(&thp->mutex);
455 	for_each_available_child_of_node_scoped(np, child) {
456 		unsigned int rollback = nmaps;
457 		enum th1520_muxtype muxtype;
458 		struct property *prop;
459 		const char *funcname;
460 		const char **pgnames;
461 		const char *pinname;
462 		int npins;
463 
464 		ret = pinconf_generic_parse_dt_config(child, pctldev, &configs, &nconfigs);
465 		if (ret) {
466 			dev_err(thp->pctl->dev, "%pOFn.%pOFn: error parsing pin config\n",
467 				np, child);
468 			goto free_map;
469 		}
470 
471 		if (!of_property_read_string(child, "function", &funcname)) {
472 			muxtype = th1520_muxtype_get(funcname);
473 			if (!muxtype) {
474 				dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown function '%s'\n",
475 					np, child, funcname);
476 				ret = -EINVAL;
477 				goto free_configs;
478 			}
479 
480 			funcname = devm_kasprintf(thp->pctl->dev, GFP_KERNEL, "%pOFn.%pOFn",
481 						  np, child);
482 			if (!funcname) {
483 				ret = -ENOMEM;
484 				goto free_configs;
485 			}
486 
487 			npins = of_property_count_strings(child, "pins");
488 			pgnames = devm_kcalloc(thp->pctl->dev, npins, sizeof(*pgnames), GFP_KERNEL);
489 			if (!pgnames) {
490 				ret = -ENOMEM;
491 				goto free_configs;
492 			}
493 		} else {
494 			funcname = NULL;
495 		}
496 
497 		npins = 0;
498 		of_property_for_each_string(child, "pins", prop, pinname) {
499 			unsigned int i;
500 
501 			for (i = 0; i < thp->desc.npins; i++) {
502 				if (!strcmp(pinname, thp->desc.pins[i].name))
503 					break;
504 			}
505 			if (i == thp->desc.npins) {
506 				nmaps = rollback;
507 				dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown pin '%s'\n",
508 					np, child, pinname);
509 				ret = -EINVAL;
510 				goto free_configs;
511 			}
512 
513 			if (nconfigs) {
514 				map[nmaps].type = PIN_MAP_TYPE_CONFIGS_PIN;
515 				map[nmaps].data.configs.group_or_pin = thp->desc.pins[i].name;
516 				map[nmaps].data.configs.configs = configs;
517 				map[nmaps].data.configs.num_configs = nconfigs;
518 				nmaps += 1;
519 			}
520 			if (funcname) {
521 				pgnames[npins++] = thp->desc.pins[i].name;
522 				map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
523 				map[nmaps].data.mux.function = funcname;
524 				map[nmaps].data.mux.group = thp->desc.pins[i].name;
525 				nmaps += 1;
526 			}
527 		}
528 
529 		if (funcname) {
530 			ret = pinmux_generic_add_function(pctldev, funcname, pgnames,
531 							  npins, (void *)muxtype);
532 			if (ret < 0) {
533 				dev_err(thp->pctl->dev, "error adding function %s\n", funcname);
534 				goto free_map;
535 			}
536 		}
537 	}
538 
539 	*maps = map;
540 	*num_maps = nmaps;
541 	return 0;
542 
543 free_configs:
544 	kfree(configs);
545 free_map:
546 	th1520_pinctrl_dt_free_map(pctldev, map, nmaps);
547 	return ret;
548 }
549 
550 static const struct pinctrl_ops th1520_pinctrl_ops = {
551 	.get_groups_count = th1520_pinctrl_get_groups_count,
552 	.get_group_name = th1520_pinctrl_get_group_name,
553 	.get_group_pins = th1520_pinctrl_get_group_pins,
554 	.pin_dbg_show = th1520_pin_dbg_show,
555 	.dt_node_to_map = th1520_pinctrl_dt_node_to_map,
556 	.dt_free_map = th1520_pinctrl_dt_free_map,
557 };
558 
559 static const u8 th1520_drive_strength_in_ma[16] = {
560 	1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25,
561 };
562 
563 static u16 th1520_drive_strength_from_ma(u32 arg)
564 {
565 	u16 ds;
566 
567 	for (ds = 0; ds < TH1520_PADCFG_DS; ds++) {
568 		if (arg <= th1520_drive_strength_in_ma[ds])
569 			return ds;
570 	}
571 	return TH1520_PADCFG_DS;
572 }
573 
574 static int th1520_padcfg_rmw(struct th1520_pinctrl *thp, unsigned int pin,
575 			     u32 mask, u32 value)
576 {
577 	void __iomem *padcfg = th1520_padcfg(thp, pin);
578 	unsigned int shift = th1520_padcfg_shift(pin);
579 	u32 tmp;
580 
581 	mask <<= shift;
582 	value <<= shift;
583 
584 	scoped_guard(raw_spinlock_irqsave, &thp->lock) {
585 		tmp = readl_relaxed(padcfg);
586 		tmp = (tmp & ~mask) | value;
587 		writel_relaxed(tmp, padcfg);
588 	}
589 	return 0;
590 }
591 
592 static int th1520_pinconf_get(struct pinctrl_dev *pctldev,
593 			      unsigned int pin, unsigned long *config)
594 {
595 	struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
596 	const struct pin_desc *desc = pin_desc_get(pctldev, pin);
597 	bool enabled;
598 	int param;
599 	u32 value;
600 	u32 arg;
601 
602 	if (th1520_pad_no_padcfg(desc->drv_data))
603 		return -ENOTSUPP;
604 
605 	value = readl_relaxed(th1520_padcfg(thp, pin));
606 	value = (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0);
607 
608 	param = pinconf_to_config_param(*config);
609 	switch (param) {
610 	case PIN_CONFIG_BIAS_DISABLE:
611 		enabled = !(value & (TH1520_PADCFG_SPU | TH1520_PADCFG_PE));
612 		arg = 0;
613 		break;
614 	case PIN_CONFIG_BIAS_PULL_DOWN:
615 		enabled = (value & TH1520_PADCFG_BIAS) == TH1520_PADCFG_PE;
616 		arg = enabled ? TH1520_PULL_DOWN_OHM : 0;
617 		break;
618 	case PIN_CONFIG_BIAS_PULL_UP:
619 		if (value & TH1520_PADCFG_SPU) {
620 			enabled = true;
621 			arg = TH1520_PULL_STRONG_OHM;
622 		} else if ((value & (TH1520_PADCFG_PE | TH1520_PADCFG_PS)) ==
623 				    (TH1520_PADCFG_PE | TH1520_PADCFG_PS)) {
624 			enabled = true;
625 			arg = TH1520_PULL_UP_OHM;
626 		} else {
627 			enabled = false;
628 			arg = 0;
629 		}
630 		break;
631 	case PIN_CONFIG_DRIVE_STRENGTH:
632 		enabled = true;
633 		arg = th1520_drive_strength_in_ma[value & TH1520_PADCFG_DS];
634 		break;
635 	case PIN_CONFIG_INPUT_ENABLE:
636 		enabled = value & TH1520_PADCFG_IE;
637 		arg = enabled ? 1 : 0;
638 		break;
639 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
640 		enabled = value & TH1520_PADCFG_ST;
641 		arg = enabled ? 1 : 0;
642 		break;
643 	case PIN_CONFIG_SLEW_RATE:
644 		enabled = value & TH1520_PADCFG_SL;
645 		arg = enabled ? 1 : 0;
646 		break;
647 	default:
648 		return -ENOTSUPP;
649 	}
650 
651 	*config = pinconf_to_config_packed(param, arg);
652 	return enabled ? 0 : -EINVAL;
653 }
654 
655 static int th1520_pinconf_group_get(struct pinctrl_dev *pctldev,
656 				    unsigned int gsel, unsigned long *config)
657 {
658 	struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
659 	unsigned int pin = thp->desc.pins[gsel].number;
660 
661 	return th1520_pinconf_get(pctldev, pin, config);
662 }
663 
664 static int th1520_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
665 			      unsigned long *configs, unsigned int num_configs)
666 {
667 	struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
668 	const struct pin_desc *desc = pin_desc_get(pctldev, pin);
669 	unsigned int i;
670 	u16 mask, value;
671 
672 	if (th1520_pad_no_padcfg(desc->drv_data))
673 		return -ENOTSUPP;
674 
675 	mask = 0;
676 	value = 0;
677 	for (i = 0; i < num_configs; i++) {
678 		int param = pinconf_to_config_param(configs[i]);
679 		u32 arg = pinconf_to_config_argument(configs[i]);
680 
681 		switch (param) {
682 		case PIN_CONFIG_BIAS_DISABLE:
683 			mask |= TH1520_PADCFG_BIAS;
684 			value &= ~TH1520_PADCFG_BIAS;
685 			break;
686 		case PIN_CONFIG_BIAS_PULL_DOWN:
687 			if (arg == 0)
688 				return -ENOTSUPP;
689 			mask |= TH1520_PADCFG_BIAS;
690 			value &= ~TH1520_PADCFG_BIAS;
691 			value |= TH1520_PADCFG_PE;
692 			break;
693 		case PIN_CONFIG_BIAS_PULL_UP:
694 			if (arg == 0)
695 				return -ENOTSUPP;
696 			mask |= TH1520_PADCFG_BIAS;
697 			value &= ~TH1520_PADCFG_BIAS;
698 			if (arg == TH1520_PULL_STRONG_OHM)
699 				value |= TH1520_PADCFG_SPU;
700 			else
701 				value |= TH1520_PADCFG_PE | TH1520_PADCFG_PS;
702 			break;
703 		case PIN_CONFIG_DRIVE_STRENGTH:
704 			mask |= TH1520_PADCFG_DS;
705 			value &= ~TH1520_PADCFG_DS;
706 			value |= th1520_drive_strength_from_ma(arg);
707 			break;
708 		case PIN_CONFIG_INPUT_ENABLE:
709 			mask |= TH1520_PADCFG_IE;
710 			if (arg)
711 				value |= TH1520_PADCFG_IE;
712 			else
713 				value &= ~TH1520_PADCFG_IE;
714 			break;
715 		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
716 			mask |= TH1520_PADCFG_ST;
717 			if (arg)
718 				value |= TH1520_PADCFG_ST;
719 			else
720 				value &= ~TH1520_PADCFG_ST;
721 			break;
722 		case PIN_CONFIG_SLEW_RATE:
723 			mask |= TH1520_PADCFG_SL;
724 			if (arg)
725 				value |= TH1520_PADCFG_SL;
726 			else
727 				value &= ~TH1520_PADCFG_SL;
728 			break;
729 		default:
730 			return -ENOTSUPP;
731 		}
732 	}
733 
734 	return th1520_padcfg_rmw(thp, pin, mask, value);
735 }
736 
737 static int th1520_pinconf_group_set(struct pinctrl_dev *pctldev,
738 				    unsigned int gsel,
739 				    unsigned long *configs,
740 				    unsigned int num_configs)
741 {
742 	struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
743 	unsigned int pin = thp->desc.pins[gsel].number;
744 
745 	return th1520_pinconf_set(pctldev, pin, configs, num_configs);
746 }
747 
748 #ifdef CONFIG_DEBUG_FS
749 static void th1520_pinconf_dbg_show(struct pinctrl_dev *pctldev,
750 				    struct seq_file *s, unsigned int pin)
751 {
752 	struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
753 	u32 value = readl_relaxed(th1520_padcfg(thp, pin));
754 
755 	value = (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0);
756 
757 	seq_printf(s, " [0x%03x]", value);
758 }
759 #else
760 #define th1520_pinconf_dbg_show NULL
761 #endif
762 
763 static const struct pinconf_ops th1520_pinconf_ops = {
764 	.pin_config_get = th1520_pinconf_get,
765 	.pin_config_group_get = th1520_pinconf_group_get,
766 	.pin_config_set = th1520_pinconf_set,
767 	.pin_config_group_set = th1520_pinconf_group_set,
768 	.pin_config_dbg_show = th1520_pinconf_dbg_show,
769 	.is_generic = true,
770 };
771 
772 static int th1520_pinmux_set(struct th1520_pinctrl *thp, unsigned int pin,
773 			     unsigned long muxdata, enum th1520_muxtype muxtype)
774 {
775 	void __iomem *muxcfg = th1520_muxcfg(thp, pin);
776 	unsigned int shift = th1520_muxcfg_shift(pin);
777 	u32 mask, value, tmp;
778 
779 	for (value = 0; muxdata; muxdata >>= 5, value++) {
780 		if ((muxdata & GENMASK(4, 0)) == muxtype)
781 			break;
782 	}
783 	if (!muxdata) {
784 		dev_err(thp->pctl->dev, "invalid mux %s for pin %s\n",
785 			th1520_muxtype_string[muxtype], pin_get_name(thp->pctl, pin));
786 		return -EINVAL;
787 	}
788 
789 	mask = GENMASK(3, 0) << shift;
790 	value = value << shift;
791 
792 	scoped_guard(raw_spinlock_irqsave, &thp->lock) {
793 		tmp = readl_relaxed(muxcfg);
794 		tmp = (tmp & ~mask) | value;
795 		writel_relaxed(tmp, muxcfg);
796 	}
797 	return 0;
798 }
799 
800 static int th1520_pinmux_set_mux(struct pinctrl_dev *pctldev,
801 				 unsigned int fsel, unsigned int gsel)
802 {
803 	struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
804 	const struct function_desc *func = pinmux_generic_get_function(pctldev, fsel);
805 	enum th1520_muxtype muxtype;
806 
807 	if (!func)
808 		return -EINVAL;
809 
810 	muxtype = (uintptr_t)func->data;
811 	return th1520_pinmux_set(thp, thp->desc.pins[gsel].number,
812 				 th1520_pad_muxdata(thp->desc.pins[gsel].drv_data),
813 				 muxtype);
814 }
815 
816 static int th1520_gpio_request_enable(struct pinctrl_dev *pctldev,
817 				      struct pinctrl_gpio_range *range,
818 				      unsigned int offset)
819 {
820 	struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
821 	const struct pin_desc *desc = pin_desc_get(pctldev, offset);
822 
823 	return th1520_pinmux_set(thp, offset,
824 				 th1520_pad_muxdata(desc->drv_data),
825 				 TH1520_MUX_GPIO);
826 }
827 
828 static int th1520_gpio_set_direction(struct pinctrl_dev *pctldev,
829 				     struct pinctrl_gpio_range *range,
830 				     unsigned int offset, bool input)
831 {
832 	struct th1520_pinctrl *thp = pinctrl_dev_get_drvdata(pctldev);
833 
834 	return th1520_padcfg_rmw(thp, offset, TH1520_PADCFG_IE,
835 				 input ? TH1520_PADCFG_IE : 0);
836 }
837 
838 static const struct pinmux_ops th1520_pinmux_ops = {
839 	.get_functions_count = pinmux_generic_get_function_count,
840 	.get_function_name = pinmux_generic_get_function_name,
841 	.get_function_groups = pinmux_generic_get_function_groups,
842 	.set_mux = th1520_pinmux_set_mux,
843 	.gpio_request_enable = th1520_gpio_request_enable,
844 	.gpio_set_direction = th1520_gpio_set_direction,
845 	.strict = true,
846 };
847 
848 static int th1520_pinctrl_probe(struct platform_device *pdev)
849 {
850 	struct device *dev = &pdev->dev;
851 	const struct th1520_pad_group *group;
852 	struct device_node *np = dev->of_node;
853 	struct th1520_pinctrl *thp;
854 	struct clk *clk;
855 	u32 pin_group;
856 	int ret;
857 
858 	thp = devm_kzalloc(dev, sizeof(*thp), GFP_KERNEL);
859 	if (!thp)
860 		return -ENOMEM;
861 
862 	thp->base = devm_platform_ioremap_resource(pdev, 0);
863 	if (IS_ERR(thp->base))
864 		return PTR_ERR(thp->base);
865 
866 	clk = devm_clk_get_enabled(dev, NULL);
867 	if (IS_ERR(clk))
868 		return dev_err_probe(dev, PTR_ERR(clk), "error getting clock\n");
869 
870 	ret = of_property_read_u32(np, "thead,pad-group", &pin_group);
871 	if (ret)
872 		return dev_err_probe(dev, ret, "failed to read the thead,pad-group property\n");
873 
874 	if (pin_group == 1)
875 		group = &th1520_group1;
876 	else if (pin_group == 2)
877 		group = &th1520_group2;
878 	else if (pin_group == 3)
879 		group = &th1520_group3;
880 	else
881 		return dev_err_probe(dev, -EINVAL, "unit address did not match any pad group\n");
882 
883 	thp->desc.name = group->name;
884 	thp->desc.pins = group->pins;
885 	thp->desc.npins = group->npins;
886 	thp->desc.pctlops = &th1520_pinctrl_ops;
887 	thp->desc.pmxops = &th1520_pinmux_ops;
888 	thp->desc.confops = &th1520_pinconf_ops;
889 	thp->desc.owner = THIS_MODULE;
890 	mutex_init(&thp->mutex);
891 	raw_spin_lock_init(&thp->lock);
892 
893 	ret = devm_pinctrl_register_and_init(dev, &thp->desc, thp, &thp->pctl);
894 	if (ret)
895 		return dev_err_probe(dev, ret, "could not register pinctrl driver\n");
896 
897 	return pinctrl_enable(thp->pctl);
898 }
899 
900 static const struct of_device_id th1520_pinctrl_of_match[] = {
901 	{ .compatible = "thead,th1520-pinctrl"},
902 	{ /* sentinel */ }
903 };
904 MODULE_DEVICE_TABLE(of, th1520_pinctrl_of_match);
905 
906 static struct platform_driver th1520_pinctrl_driver = {
907 	.probe = th1520_pinctrl_probe,
908 	.driver = {
909 		.name = "pinctrl-th1520",
910 		.of_match_table = th1520_pinctrl_of_match,
911 	},
912 };
913 module_platform_driver(th1520_pinctrl_driver);
914 
915 MODULE_DESCRIPTION("Pinctrl driver for the T-Head TH1520 SoC");
916 MODULE_AUTHOR("Emil Renner Berthing <emil.renner.berthing@canonical.com>");
917 MODULE_LICENSE("GPL");
918