1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, BayLibre, SAS. All rights reserved. 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 * 6 * Copyright (c) 2010, Code Aurora Forum. All rights reserved. 7 * 8 * Driver for Semtech SX150X I2C GPIO Expanders 9 * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested. 10 * 11 * Author: Gregory Bean <gbean@codeaurora.org> 12 */ 13 14 #include <linux/regmap.h> 15 #include <linux/i2c.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/irq.h> 19 #include <linux/mutex.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 #include <linux/pinctrl/pinconf-generic.h> 28 29 #include "core.h" 30 #include "pinconf.h" 31 #include "pinctrl-utils.h" 32 33 /* The chip models of sx150x */ 34 enum { 35 SX150X_123 = 0, 36 SX150X_456, 37 SX150X_789, 38 }; 39 enum { 40 SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0, 41 SX150X_MAX_REGISTER = 0xad, 42 SX150X_IRQ_TYPE_EDGE_RISING = 0x1, 43 SX150X_IRQ_TYPE_EDGE_FALLING = 0x2, 44 SX150X_789_RESET_KEY1 = 0x12, 45 SX150X_789_RESET_KEY2 = 0x34, 46 }; 47 48 struct sx150x_123_pri { 49 u8 reg_pld_mode; 50 u8 reg_pld_table0; 51 u8 reg_pld_table1; 52 u8 reg_pld_table2; 53 u8 reg_pld_table3; 54 u8 reg_pld_table4; 55 u8 reg_advanced; 56 }; 57 58 struct sx150x_456_pri { 59 u8 reg_pld_mode; 60 u8 reg_pld_table0; 61 u8 reg_pld_table1; 62 u8 reg_pld_table2; 63 u8 reg_pld_table3; 64 u8 reg_pld_table4; 65 u8 reg_advanced; 66 }; 67 68 struct sx150x_789_pri { 69 u8 reg_drain; 70 u8 reg_polarity; 71 u8 reg_clock; 72 u8 reg_misc; 73 u8 reg_reset; 74 u8 ngpios; 75 }; 76 77 struct sx150x_device_data { 78 u8 model; 79 u8 reg_pullup; 80 u8 reg_pulldn; 81 u8 reg_dir; 82 u8 reg_data; 83 u8 reg_irq_mask; 84 u8 reg_irq_src; 85 u8 reg_sense; 86 u8 ngpios; 87 union { 88 struct sx150x_123_pri x123; 89 struct sx150x_456_pri x456; 90 struct sx150x_789_pri x789; 91 } pri; 92 const struct pinctrl_pin_desc *pins; 93 unsigned int npins; 94 }; 95 96 struct sx150x_pinctrl { 97 struct device *dev; 98 struct i2c_client *client; 99 struct pinctrl_dev *pctldev; 100 struct pinctrl_desc pinctrl_desc; 101 struct gpio_chip gpio; 102 struct irq_chip irq_chip; 103 struct regmap *regmap; 104 struct { 105 u32 sense; 106 u32 masked; 107 } irq; 108 struct mutex lock; 109 const struct sx150x_device_data *data; 110 }; 111 112 static const struct pinctrl_pin_desc sx150x_4_pins[] = { 113 PINCTRL_PIN(0, "gpio0"), 114 PINCTRL_PIN(1, "gpio1"), 115 PINCTRL_PIN(2, "gpio2"), 116 PINCTRL_PIN(3, "gpio3"), 117 PINCTRL_PIN(4, "oscio"), 118 }; 119 120 static const struct pinctrl_pin_desc sx150x_8_pins[] = { 121 PINCTRL_PIN(0, "gpio0"), 122 PINCTRL_PIN(1, "gpio1"), 123 PINCTRL_PIN(2, "gpio2"), 124 PINCTRL_PIN(3, "gpio3"), 125 PINCTRL_PIN(4, "gpio4"), 126 PINCTRL_PIN(5, "gpio5"), 127 PINCTRL_PIN(6, "gpio6"), 128 PINCTRL_PIN(7, "gpio7"), 129 PINCTRL_PIN(8, "oscio"), 130 }; 131 132 static const struct pinctrl_pin_desc sx150x_16_pins[] = { 133 PINCTRL_PIN(0, "gpio0"), 134 PINCTRL_PIN(1, "gpio1"), 135 PINCTRL_PIN(2, "gpio2"), 136 PINCTRL_PIN(3, "gpio3"), 137 PINCTRL_PIN(4, "gpio4"), 138 PINCTRL_PIN(5, "gpio5"), 139 PINCTRL_PIN(6, "gpio6"), 140 PINCTRL_PIN(7, "gpio7"), 141 PINCTRL_PIN(8, "gpio8"), 142 PINCTRL_PIN(9, "gpio9"), 143 PINCTRL_PIN(10, "gpio10"), 144 PINCTRL_PIN(11, "gpio11"), 145 PINCTRL_PIN(12, "gpio12"), 146 PINCTRL_PIN(13, "gpio13"), 147 PINCTRL_PIN(14, "gpio14"), 148 PINCTRL_PIN(15, "gpio15"), 149 PINCTRL_PIN(16, "oscio"), 150 }; 151 152 static const struct sx150x_device_data sx1501q_device_data = { 153 .model = SX150X_123, 154 .reg_pullup = 0x02, 155 .reg_pulldn = 0x03, 156 .reg_dir = 0x01, 157 .reg_data = 0x00, 158 .reg_irq_mask = 0x05, 159 .reg_irq_src = 0x08, 160 .reg_sense = 0x07, 161 .pri.x123 = { 162 .reg_pld_mode = 0x10, 163 .reg_pld_table0 = 0x11, 164 .reg_pld_table2 = 0x13, 165 .reg_advanced = 0xad, 166 }, 167 .ngpios = 4, 168 .pins = sx150x_4_pins, 169 .npins = 4, /* oscio not available */ 170 }; 171 172 static const struct sx150x_device_data sx1502q_device_data = { 173 .model = SX150X_123, 174 .reg_pullup = 0x02, 175 .reg_pulldn = 0x03, 176 .reg_dir = 0x01, 177 .reg_data = 0x00, 178 .reg_irq_mask = 0x05, 179 .reg_irq_src = 0x08, 180 .reg_sense = 0x06, 181 .pri.x123 = { 182 .reg_pld_mode = 0x10, 183 .reg_pld_table0 = 0x11, 184 .reg_pld_table1 = 0x12, 185 .reg_pld_table2 = 0x13, 186 .reg_pld_table3 = 0x14, 187 .reg_pld_table4 = 0x15, 188 .reg_advanced = 0xad, 189 }, 190 .ngpios = 8, 191 .pins = sx150x_8_pins, 192 .npins = 8, /* oscio not available */ 193 }; 194 195 static const struct sx150x_device_data sx1503q_device_data = { 196 .model = SX150X_123, 197 .reg_pullup = 0x04, 198 .reg_pulldn = 0x06, 199 .reg_dir = 0x02, 200 .reg_data = 0x00, 201 .reg_irq_mask = 0x08, 202 .reg_irq_src = 0x0e, 203 .reg_sense = 0x0a, 204 .pri.x123 = { 205 .reg_pld_mode = 0x20, 206 .reg_pld_table0 = 0x22, 207 .reg_pld_table1 = 0x24, 208 .reg_pld_table2 = 0x26, 209 .reg_pld_table3 = 0x28, 210 .reg_pld_table4 = 0x2a, 211 .reg_advanced = 0xad, 212 }, 213 .ngpios = 16, 214 .pins = sx150x_16_pins, 215 .npins = 16, /* oscio not available */ 216 }; 217 218 static const struct sx150x_device_data sx1504q_device_data = { 219 .model = SX150X_456, 220 .reg_pullup = 0x02, 221 .reg_pulldn = 0x03, 222 .reg_dir = 0x01, 223 .reg_data = 0x00, 224 .reg_irq_mask = 0x05, 225 .reg_irq_src = 0x08, 226 .reg_sense = 0x07, 227 .pri.x456 = { 228 .reg_pld_mode = 0x10, 229 .reg_pld_table0 = 0x11, 230 .reg_pld_table2 = 0x13, 231 }, 232 .ngpios = 4, 233 .pins = sx150x_4_pins, 234 .npins = 4, /* oscio not available */ 235 }; 236 237 static const struct sx150x_device_data sx1505q_device_data = { 238 .model = SX150X_456, 239 .reg_pullup = 0x02, 240 .reg_pulldn = 0x03, 241 .reg_dir = 0x01, 242 .reg_data = 0x00, 243 .reg_irq_mask = 0x05, 244 .reg_irq_src = 0x08, 245 .reg_sense = 0x06, 246 .pri.x456 = { 247 .reg_pld_mode = 0x10, 248 .reg_pld_table0 = 0x11, 249 .reg_pld_table1 = 0x12, 250 .reg_pld_table2 = 0x13, 251 .reg_pld_table3 = 0x14, 252 .reg_pld_table4 = 0x15, 253 }, 254 .ngpios = 8, 255 .pins = sx150x_8_pins, 256 .npins = 8, /* oscio not available */ 257 }; 258 259 static const struct sx150x_device_data sx1506q_device_data = { 260 .model = SX150X_456, 261 .reg_pullup = 0x04, 262 .reg_pulldn = 0x06, 263 .reg_dir = 0x02, 264 .reg_data = 0x00, 265 .reg_irq_mask = 0x08, 266 .reg_irq_src = 0x0e, 267 .reg_sense = 0x0a, 268 .pri.x456 = { 269 .reg_pld_mode = 0x20, 270 .reg_pld_table0 = 0x22, 271 .reg_pld_table1 = 0x24, 272 .reg_pld_table2 = 0x26, 273 .reg_pld_table3 = 0x28, 274 .reg_pld_table4 = 0x2a, 275 .reg_advanced = 0xad, 276 }, 277 .ngpios = 16, 278 .pins = sx150x_16_pins, 279 .npins = 16, /* oscio not available */ 280 }; 281 282 static const struct sx150x_device_data sx1507q_device_data = { 283 .model = SX150X_789, 284 .reg_pullup = 0x03, 285 .reg_pulldn = 0x04, 286 .reg_dir = 0x07, 287 .reg_data = 0x08, 288 .reg_irq_mask = 0x09, 289 .reg_irq_src = 0x0b, 290 .reg_sense = 0x0a, 291 .pri.x789 = { 292 .reg_drain = 0x05, 293 .reg_polarity = 0x06, 294 .reg_clock = 0x0d, 295 .reg_misc = 0x0e, 296 .reg_reset = 0x7d, 297 }, 298 .ngpios = 4, 299 .pins = sx150x_4_pins, 300 .npins = ARRAY_SIZE(sx150x_4_pins), 301 }; 302 303 static const struct sx150x_device_data sx1508q_device_data = { 304 .model = SX150X_789, 305 .reg_pullup = 0x03, 306 .reg_pulldn = 0x04, 307 .reg_dir = 0x07, 308 .reg_data = 0x08, 309 .reg_irq_mask = 0x09, 310 .reg_irq_src = 0x0c, 311 .reg_sense = 0x0a, 312 .pri.x789 = { 313 .reg_drain = 0x05, 314 .reg_polarity = 0x06, 315 .reg_clock = 0x0f, 316 .reg_misc = 0x10, 317 .reg_reset = 0x7d, 318 }, 319 .ngpios = 8, 320 .pins = sx150x_8_pins, 321 .npins = ARRAY_SIZE(sx150x_8_pins), 322 }; 323 324 static const struct sx150x_device_data sx1509q_device_data = { 325 .model = SX150X_789, 326 .reg_pullup = 0x06, 327 .reg_pulldn = 0x08, 328 .reg_dir = 0x0e, 329 .reg_data = 0x10, 330 .reg_irq_mask = 0x12, 331 .reg_irq_src = 0x18, 332 .reg_sense = 0x14, 333 .pri.x789 = { 334 .reg_drain = 0x0a, 335 .reg_polarity = 0x0c, 336 .reg_clock = 0x1e, 337 .reg_misc = 0x1f, 338 .reg_reset = 0x7d, 339 }, 340 .ngpios = 16, 341 .pins = sx150x_16_pins, 342 .npins = ARRAY_SIZE(sx150x_16_pins), 343 }; 344 345 static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 346 { 347 return 0; 348 } 349 350 static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 351 unsigned int group) 352 { 353 return NULL; 354 } 355 356 static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 357 unsigned int group, 358 const unsigned int **pins, 359 unsigned int *num_pins) 360 { 361 return -ENOTSUPP; 362 } 363 364 static const struct pinctrl_ops sx150x_pinctrl_ops = { 365 .get_groups_count = sx150x_pinctrl_get_groups_count, 366 .get_group_name = sx150x_pinctrl_get_group_name, 367 .get_group_pins = sx150x_pinctrl_get_group_pins, 368 #ifdef CONFIG_OF 369 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 370 .dt_free_map = pinctrl_utils_free_map, 371 #endif 372 }; 373 374 static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin) 375 { 376 if (pin >= pctl->data->npins) 377 return false; 378 379 /* OSCIO pin is only present in 789 devices */ 380 if (pctl->data->model != SX150X_789) 381 return false; 382 383 return !strcmp(pctl->data->pins[pin].name, "oscio"); 384 } 385 386 static int sx150x_gpio_get_direction(struct gpio_chip *chip, 387 unsigned int offset) 388 { 389 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 390 unsigned int value; 391 int ret; 392 393 if (sx150x_pin_is_oscio(pctl, offset)) 394 return false; 395 396 ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value); 397 if (ret < 0) 398 return ret; 399 400 return !!(value & BIT(offset)); 401 } 402 403 static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset) 404 { 405 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 406 unsigned int value; 407 int ret; 408 409 if (sx150x_pin_is_oscio(pctl, offset)) 410 return -EINVAL; 411 412 ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value); 413 if (ret < 0) 414 return ret; 415 416 return !!(value & BIT(offset)); 417 } 418 419 static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset, 420 int value) 421 { 422 return regmap_write_bits(pctl->regmap, pctl->data->reg_data, 423 BIT(offset), value ? BIT(offset) : 0); 424 } 425 426 static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl, 427 int value) 428 { 429 return regmap_write(pctl->regmap, 430 pctl->data->pri.x789.reg_clock, 431 (value ? 0x1f : 0x10)); 432 } 433 434 static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset, 435 int value) 436 { 437 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 438 439 if (sx150x_pin_is_oscio(pctl, offset)) 440 sx150x_gpio_oscio_set(pctl, value); 441 else 442 __sx150x_gpio_set(pctl, offset, value); 443 444 } 445 446 static void sx150x_gpio_set_multiple(struct gpio_chip *chip, 447 unsigned long *mask, 448 unsigned long *bits) 449 { 450 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 451 452 regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits); 453 } 454 455 static int sx150x_gpio_direction_input(struct gpio_chip *chip, 456 unsigned int offset) 457 { 458 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 459 460 if (sx150x_pin_is_oscio(pctl, offset)) 461 return -EINVAL; 462 463 return regmap_write_bits(pctl->regmap, 464 pctl->data->reg_dir, 465 BIT(offset), BIT(offset)); 466 } 467 468 static int sx150x_gpio_direction_output(struct gpio_chip *chip, 469 unsigned int offset, int value) 470 { 471 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 472 int ret; 473 474 if (sx150x_pin_is_oscio(pctl, offset)) 475 return sx150x_gpio_oscio_set(pctl, value); 476 477 ret = __sx150x_gpio_set(pctl, offset, value); 478 if (ret < 0) 479 return ret; 480 481 return regmap_write_bits(pctl->regmap, 482 pctl->data->reg_dir, 483 BIT(offset), 0); 484 } 485 486 static void sx150x_irq_mask(struct irq_data *d) 487 { 488 struct sx150x_pinctrl *pctl = 489 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 490 unsigned int n = d->hwirq; 491 492 pctl->irq.masked |= BIT(n); 493 } 494 495 static void sx150x_irq_unmask(struct irq_data *d) 496 { 497 struct sx150x_pinctrl *pctl = 498 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 499 unsigned int n = d->hwirq; 500 501 pctl->irq.masked &= ~BIT(n); 502 } 503 504 static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl, 505 unsigned int line, unsigned int sense) 506 { 507 /* 508 * Every interrupt line is represented by two bits shifted 509 * proportionally to the line number 510 */ 511 const unsigned int n = line * 2; 512 const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING | 513 SX150X_IRQ_TYPE_EDGE_FALLING) << n); 514 515 pctl->irq.sense &= mask; 516 pctl->irq.sense |= sense << n; 517 } 518 519 static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type) 520 { 521 struct sx150x_pinctrl *pctl = 522 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 523 unsigned int n, val = 0; 524 525 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 526 return -EINVAL; 527 528 n = d->hwirq; 529 530 if (flow_type & IRQ_TYPE_EDGE_RISING) 531 val |= SX150X_IRQ_TYPE_EDGE_RISING; 532 if (flow_type & IRQ_TYPE_EDGE_FALLING) 533 val |= SX150X_IRQ_TYPE_EDGE_FALLING; 534 535 sx150x_irq_set_sense(pctl, n, val); 536 return 0; 537 } 538 539 static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id) 540 { 541 struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id; 542 unsigned long n, status; 543 unsigned int val; 544 int err; 545 546 err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val); 547 if (err < 0) 548 return IRQ_NONE; 549 550 err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val); 551 if (err < 0) 552 return IRQ_NONE; 553 554 status = val; 555 for_each_set_bit(n, &status, pctl->data->ngpios) 556 handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n)); 557 558 return IRQ_HANDLED; 559 } 560 561 static void sx150x_irq_bus_lock(struct irq_data *d) 562 { 563 struct sx150x_pinctrl *pctl = 564 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 565 566 mutex_lock(&pctl->lock); 567 } 568 569 static void sx150x_irq_bus_sync_unlock(struct irq_data *d) 570 { 571 struct sx150x_pinctrl *pctl = 572 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 573 574 regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked); 575 regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense); 576 mutex_unlock(&pctl->lock); 577 } 578 579 static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 580 unsigned long *config) 581 { 582 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 583 unsigned int param = pinconf_to_config_param(*config); 584 int ret; 585 u32 arg; 586 unsigned int data; 587 588 if (sx150x_pin_is_oscio(pctl, pin)) { 589 switch (param) { 590 case PIN_CONFIG_DRIVE_PUSH_PULL: 591 case PIN_CONFIG_OUTPUT: 592 ret = regmap_read(pctl->regmap, 593 pctl->data->pri.x789.reg_clock, 594 &data); 595 if (ret < 0) 596 return ret; 597 598 if (param == PIN_CONFIG_DRIVE_PUSH_PULL) 599 arg = (data & 0x1f) ? 1 : 0; 600 else { 601 if ((data & 0x1f) == 0x1f) 602 arg = 1; 603 else if ((data & 0x1f) == 0x10) 604 arg = 0; 605 else 606 return -EINVAL; 607 } 608 609 break; 610 default: 611 return -ENOTSUPP; 612 } 613 614 goto out; 615 } 616 617 switch (param) { 618 case PIN_CONFIG_BIAS_PULL_DOWN: 619 ret = regmap_read(pctl->regmap, 620 pctl->data->reg_pulldn, 621 &data); 622 data &= BIT(pin); 623 624 if (ret < 0) 625 return ret; 626 627 if (!ret) 628 return -EINVAL; 629 630 arg = 1; 631 break; 632 633 case PIN_CONFIG_BIAS_PULL_UP: 634 ret = regmap_read(pctl->regmap, 635 pctl->data->reg_pullup, 636 &data); 637 data &= BIT(pin); 638 639 if (ret < 0) 640 return ret; 641 642 if (!ret) 643 return -EINVAL; 644 645 arg = 1; 646 break; 647 648 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 649 if (pctl->data->model != SX150X_789) 650 return -ENOTSUPP; 651 652 ret = regmap_read(pctl->regmap, 653 pctl->data->pri.x789.reg_drain, 654 &data); 655 data &= BIT(pin); 656 657 if (ret < 0) 658 return ret; 659 660 if (!data) 661 return -EINVAL; 662 663 arg = 1; 664 break; 665 666 case PIN_CONFIG_DRIVE_PUSH_PULL: 667 if (pctl->data->model != SX150X_789) 668 arg = true; 669 else { 670 ret = regmap_read(pctl->regmap, 671 pctl->data->pri.x789.reg_drain, 672 &data); 673 data &= BIT(pin); 674 675 if (ret < 0) 676 return ret; 677 678 if (data) 679 return -EINVAL; 680 681 arg = 1; 682 } 683 break; 684 685 case PIN_CONFIG_OUTPUT: 686 ret = sx150x_gpio_get_direction(&pctl->gpio, pin); 687 if (ret < 0) 688 return ret; 689 690 if (ret) 691 return -EINVAL; 692 693 ret = sx150x_gpio_get(&pctl->gpio, pin); 694 if (ret < 0) 695 return ret; 696 697 arg = ret; 698 break; 699 700 default: 701 return -ENOTSUPP; 702 } 703 704 out: 705 *config = pinconf_to_config_packed(param, arg); 706 707 return 0; 708 } 709 710 static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 711 unsigned long *configs, unsigned int num_configs) 712 { 713 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 714 enum pin_config_param param; 715 u32 arg; 716 int i; 717 int ret; 718 719 for (i = 0; i < num_configs; i++) { 720 param = pinconf_to_config_param(configs[i]); 721 arg = pinconf_to_config_argument(configs[i]); 722 723 if (sx150x_pin_is_oscio(pctl, pin)) { 724 if (param == PIN_CONFIG_OUTPUT) { 725 ret = sx150x_gpio_direction_output(&pctl->gpio, 726 pin, arg); 727 if (ret < 0) 728 return ret; 729 730 continue; 731 } else 732 return -ENOTSUPP; 733 } 734 735 switch (param) { 736 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 737 case PIN_CONFIG_BIAS_DISABLE: 738 ret = regmap_write_bits(pctl->regmap, 739 pctl->data->reg_pulldn, 740 BIT(pin), 0); 741 if (ret < 0) 742 return ret; 743 744 ret = regmap_write_bits(pctl->regmap, 745 pctl->data->reg_pullup, 746 BIT(pin), 0); 747 if (ret < 0) 748 return ret; 749 750 break; 751 752 case PIN_CONFIG_BIAS_PULL_UP: 753 ret = regmap_write_bits(pctl->regmap, 754 pctl->data->reg_pullup, 755 BIT(pin), BIT(pin)); 756 if (ret < 0) 757 return ret; 758 759 break; 760 761 case PIN_CONFIG_BIAS_PULL_DOWN: 762 ret = regmap_write_bits(pctl->regmap, 763 pctl->data->reg_pulldn, 764 BIT(pin), BIT(pin)); 765 if (ret < 0) 766 return ret; 767 768 break; 769 770 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 771 if (pctl->data->model != SX150X_789 || 772 sx150x_pin_is_oscio(pctl, pin)) 773 return -ENOTSUPP; 774 775 ret = regmap_write_bits(pctl->regmap, 776 pctl->data->pri.x789.reg_drain, 777 BIT(pin), BIT(pin)); 778 if (ret < 0) 779 return ret; 780 781 break; 782 783 case PIN_CONFIG_DRIVE_PUSH_PULL: 784 if (pctl->data->model != SX150X_789 || 785 sx150x_pin_is_oscio(pctl, pin)) 786 return 0; 787 788 ret = regmap_write_bits(pctl->regmap, 789 pctl->data->pri.x789.reg_drain, 790 BIT(pin), 0); 791 if (ret < 0) 792 return ret; 793 794 break; 795 796 case PIN_CONFIG_OUTPUT: 797 ret = sx150x_gpio_direction_output(&pctl->gpio, 798 pin, arg); 799 if (ret < 0) 800 return ret; 801 802 break; 803 804 default: 805 return -ENOTSUPP; 806 } 807 } /* for each config */ 808 809 return 0; 810 } 811 812 static const struct pinconf_ops sx150x_pinconf_ops = { 813 .pin_config_get = sx150x_pinconf_get, 814 .pin_config_set = sx150x_pinconf_set, 815 .is_generic = true, 816 }; 817 818 static const struct i2c_device_id sx150x_id[] = { 819 {"sx1501q", (kernel_ulong_t) &sx1501q_device_data }, 820 {"sx1502q", (kernel_ulong_t) &sx1502q_device_data }, 821 {"sx1503q", (kernel_ulong_t) &sx1503q_device_data }, 822 {"sx1504q", (kernel_ulong_t) &sx1504q_device_data }, 823 {"sx1505q", (kernel_ulong_t) &sx1505q_device_data }, 824 {"sx1506q", (kernel_ulong_t) &sx1506q_device_data }, 825 {"sx1507q", (kernel_ulong_t) &sx1507q_device_data }, 826 {"sx1508q", (kernel_ulong_t) &sx1508q_device_data }, 827 {"sx1509q", (kernel_ulong_t) &sx1509q_device_data }, 828 {} 829 }; 830 831 static const struct of_device_id sx150x_of_match[] = { 832 { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data }, 833 { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data }, 834 { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data }, 835 { .compatible = "semtech,sx1504q", .data = &sx1504q_device_data }, 836 { .compatible = "semtech,sx1505q", .data = &sx1505q_device_data }, 837 { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data }, 838 { .compatible = "semtech,sx1507q", .data = &sx1507q_device_data }, 839 { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data }, 840 { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data }, 841 {}, 842 }; 843 844 static int sx150x_reset(struct sx150x_pinctrl *pctl) 845 { 846 int err; 847 848 err = i2c_smbus_write_byte_data(pctl->client, 849 pctl->data->pri.x789.reg_reset, 850 SX150X_789_RESET_KEY1); 851 if (err < 0) 852 return err; 853 854 err = i2c_smbus_write_byte_data(pctl->client, 855 pctl->data->pri.x789.reg_reset, 856 SX150X_789_RESET_KEY2); 857 return err; 858 } 859 860 static int sx150x_init_misc(struct sx150x_pinctrl *pctl) 861 { 862 u8 reg, value; 863 864 switch (pctl->data->model) { 865 case SX150X_789: 866 reg = pctl->data->pri.x789.reg_misc; 867 value = SX150X_789_REG_MISC_AUTOCLEAR_OFF; 868 break; 869 case SX150X_456: 870 reg = pctl->data->pri.x456.reg_advanced; 871 value = 0x00; 872 873 /* 874 * Only SX1506 has RegAdvanced, SX1504/5 are expected 875 * to initialize this offset to zero 876 */ 877 if (!reg) 878 return 0; 879 break; 880 case SX150X_123: 881 reg = pctl->data->pri.x123.reg_advanced; 882 value = 0x00; 883 break; 884 default: 885 WARN(1, "Unknown chip model %d\n", pctl->data->model); 886 return -EINVAL; 887 } 888 889 return regmap_write(pctl->regmap, reg, value); 890 } 891 892 static int sx150x_init_hw(struct sx150x_pinctrl *pctl) 893 { 894 const u8 reg[] = { 895 [SX150X_789] = pctl->data->pri.x789.reg_polarity, 896 [SX150X_456] = pctl->data->pri.x456.reg_pld_mode, 897 [SX150X_123] = pctl->data->pri.x123.reg_pld_mode, 898 }; 899 int err; 900 901 if (pctl->data->model == SX150X_789 && 902 of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) { 903 err = sx150x_reset(pctl); 904 if (err < 0) 905 return err; 906 } 907 908 err = sx150x_init_misc(pctl); 909 if (err < 0) 910 return err; 911 912 /* Set all pins to work in normal mode */ 913 return regmap_write(pctl->regmap, reg[pctl->data->model], 0); 914 } 915 916 static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl, 917 unsigned int reg) 918 { 919 const struct sx150x_device_data *data = pctl->data; 920 921 if (reg == data->reg_sense) { 922 /* 923 * RegSense packs two bits of configuration per GPIO, 924 * so we'd need to read twice as many bits as there 925 * are GPIO in our chip 926 */ 927 return 2 * data->ngpios; 928 } else if ((data->model == SX150X_789 && 929 (reg == data->pri.x789.reg_misc || 930 reg == data->pri.x789.reg_clock || 931 reg == data->pri.x789.reg_reset)) 932 || 933 (data->model == SX150X_123 && 934 reg == data->pri.x123.reg_advanced) 935 || 936 (data->model == SX150X_456 && 937 data->pri.x456.reg_advanced && 938 reg == data->pri.x456.reg_advanced)) { 939 return 8; 940 } else { 941 return data->ngpios; 942 } 943 } 944 945 static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl, 946 unsigned int reg, unsigned int val) 947 { 948 unsigned int a, b; 949 const struct sx150x_device_data *data = pctl->data; 950 951 /* 952 * Whereas SX1509 presents RegSense in a simple layout as such: 953 * reg [ f f e e d d c c ] 954 * reg + 1 [ b b a a 9 9 8 8 ] 955 * reg + 2 [ 7 7 6 6 5 5 4 4 ] 956 * reg + 3 [ 3 3 2 2 1 1 0 0 ] 957 * 958 * SX1503 and SX1506 deviate from that data layout, instead storing 959 * their contents as follows: 960 * 961 * reg [ f f e e d d c c ] 962 * reg + 1 [ 7 7 6 6 5 5 4 4 ] 963 * reg + 2 [ b b a a 9 9 8 8 ] 964 * reg + 3 [ 3 3 2 2 1 1 0 0 ] 965 * 966 * so, taking that into account, we swap two 967 * inner bytes of a 4-byte result 968 */ 969 970 if (reg == data->reg_sense && 971 data->ngpios == 16 && 972 (data->model == SX150X_123 || 973 data->model == SX150X_456)) { 974 a = val & 0x00ff0000; 975 b = val & 0x0000ff00; 976 977 val &= 0xff0000ff; 978 val |= b << 8; 979 val |= a >> 8; 980 } 981 982 return val; 983 } 984 985 /* 986 * In order to mask the differences between 16 and 8 bit expander 987 * devices we set up a sligthly ficticious regmap that pretends to be 988 * a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh 989 * pair/quartet) registers and transparently reconstructs those 990 * registers via multiple I2C/SMBus reads 991 * 992 * This way the rest of the driver code, interfacing with the chip via 993 * regmap API, can work assuming that each GPIO pin is represented by 994 * a group of bits at an offset proportional to GPIO number within a 995 * given register. 996 */ 997 static int sx150x_regmap_reg_read(void *context, unsigned int reg, 998 unsigned int *result) 999 { 1000 int ret, n; 1001 struct sx150x_pinctrl *pctl = context; 1002 struct i2c_client *i2c = pctl->client; 1003 const int width = sx150x_regmap_reg_width(pctl, reg); 1004 unsigned int idx, val; 1005 1006 /* 1007 * There are four potential cases covered by this function: 1008 * 1009 * 1) 8-pin chip, single configuration bit register 1010 * 1011 * This is trivial the code below just needs to read: 1012 * reg [ 7 6 5 4 3 2 1 0 ] 1013 * 1014 * 2) 8-pin chip, double configuration bit register (RegSense) 1015 * 1016 * The read will be done as follows: 1017 * reg [ 7 7 6 6 5 5 4 4 ] 1018 * reg + 1 [ 3 3 2 2 1 1 0 0 ] 1019 * 1020 * 3) 16-pin chip, single configuration bit register 1021 * 1022 * The read will be done as follows: 1023 * reg [ f e d c b a 9 8 ] 1024 * reg + 1 [ 7 6 5 4 3 2 1 0 ] 1025 * 1026 * 4) 16-pin chip, double configuration bit register (RegSense) 1027 * 1028 * The read will be done as follows: 1029 * reg [ f f e e d d c c ] 1030 * reg + 1 [ b b a a 9 9 8 8 ] 1031 * reg + 2 [ 7 7 6 6 5 5 4 4 ] 1032 * reg + 3 [ 3 3 2 2 1 1 0 0 ] 1033 */ 1034 1035 for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) { 1036 val <<= 8; 1037 1038 ret = i2c_smbus_read_byte_data(i2c, idx); 1039 if (ret < 0) 1040 return ret; 1041 1042 val |= ret; 1043 } 1044 1045 *result = sx150x_maybe_swizzle(pctl, reg, val); 1046 1047 return 0; 1048 } 1049 1050 static int sx150x_regmap_reg_write(void *context, unsigned int reg, 1051 unsigned int val) 1052 { 1053 int ret, n; 1054 struct sx150x_pinctrl *pctl = context; 1055 struct i2c_client *i2c = pctl->client; 1056 const int width = sx150x_regmap_reg_width(pctl, reg); 1057 1058 val = sx150x_maybe_swizzle(pctl, reg, val); 1059 1060 n = (width - 1) & ~7; 1061 do { 1062 const u8 byte = (val >> n) & 0xff; 1063 1064 ret = i2c_smbus_write_byte_data(i2c, reg, byte); 1065 if (ret < 0) 1066 return ret; 1067 1068 reg++; 1069 n -= 8; 1070 } while (n >= 0); 1071 1072 return 0; 1073 } 1074 1075 static bool sx150x_reg_volatile(struct device *dev, unsigned int reg) 1076 { 1077 struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev)); 1078 1079 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data; 1080 } 1081 1082 static const struct regmap_config sx150x_regmap_config = { 1083 .reg_bits = 8, 1084 .val_bits = 32, 1085 1086 .cache_type = REGCACHE_RBTREE, 1087 1088 .reg_read = sx150x_regmap_reg_read, 1089 .reg_write = sx150x_regmap_reg_write, 1090 1091 .max_register = SX150X_MAX_REGISTER, 1092 .volatile_reg = sx150x_reg_volatile, 1093 }; 1094 1095 static int sx150x_probe(struct i2c_client *client, 1096 const struct i2c_device_id *id) 1097 { 1098 static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA | 1099 I2C_FUNC_SMBUS_WRITE_WORD_DATA; 1100 struct device *dev = &client->dev; 1101 struct sx150x_pinctrl *pctl; 1102 int ret; 1103 1104 if (!i2c_check_functionality(client->adapter, i2c_funcs)) 1105 return -ENOSYS; 1106 1107 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1108 if (!pctl) 1109 return -ENOMEM; 1110 1111 i2c_set_clientdata(client, pctl); 1112 1113 pctl->dev = dev; 1114 pctl->client = client; 1115 1116 if (dev->of_node) 1117 pctl->data = of_device_get_match_data(dev); 1118 else 1119 pctl->data = (struct sx150x_device_data *)id->driver_data; 1120 1121 if (!pctl->data) 1122 return -EINVAL; 1123 1124 pctl->regmap = devm_regmap_init(dev, NULL, pctl, 1125 &sx150x_regmap_config); 1126 if (IS_ERR(pctl->regmap)) { 1127 ret = PTR_ERR(pctl->regmap); 1128 dev_err(dev, "Failed to allocate register map: %d\n", 1129 ret); 1130 return ret; 1131 } 1132 1133 mutex_init(&pctl->lock); 1134 1135 ret = sx150x_init_hw(pctl); 1136 if (ret) 1137 return ret; 1138 1139 /* Pinctrl_desc */ 1140 pctl->pinctrl_desc.name = "sx150x-pinctrl"; 1141 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops; 1142 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops; 1143 pctl->pinctrl_desc.pins = pctl->data->pins; 1144 pctl->pinctrl_desc.npins = pctl->data->npins; 1145 pctl->pinctrl_desc.owner = THIS_MODULE; 1146 1147 ret = devm_pinctrl_register_and_init(dev, &pctl->pinctrl_desc, 1148 pctl, &pctl->pctldev); 1149 if (ret) { 1150 dev_err(dev, "Failed to register pinctrl device\n"); 1151 return ret; 1152 } 1153 1154 ret = pinctrl_enable(pctl->pctldev); 1155 if (ret) { 1156 dev_err(dev, "Failed to enable pinctrl device\n"); 1157 return ret; 1158 } 1159 1160 /* Register GPIO controller */ 1161 pctl->gpio.base = -1; 1162 pctl->gpio.ngpio = pctl->data->npins; 1163 pctl->gpio.get_direction = sx150x_gpio_get_direction; 1164 pctl->gpio.direction_input = sx150x_gpio_direction_input; 1165 pctl->gpio.direction_output = sx150x_gpio_direction_output; 1166 pctl->gpio.get = sx150x_gpio_get; 1167 pctl->gpio.set = sx150x_gpio_set; 1168 pctl->gpio.set_config = gpiochip_generic_config; 1169 pctl->gpio.parent = dev; 1170 #ifdef CONFIG_OF_GPIO 1171 pctl->gpio.of_node = dev->of_node; 1172 #endif 1173 pctl->gpio.can_sleep = true; 1174 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL); 1175 if (!pctl->gpio.label) 1176 return -ENOMEM; 1177 1178 /* 1179 * Setting multiple pins is not safe when all pins are not 1180 * handled by the same regmap register. The oscio pin (present 1181 * on the SX150X_789 chips) lives in its own register, so 1182 * would require locking that is not in place at this time. 1183 */ 1184 if (pctl->data->model != SX150X_789) 1185 pctl->gpio.set_multiple = sx150x_gpio_set_multiple; 1186 1187 ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl); 1188 if (ret) 1189 return ret; 1190 1191 ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev), 1192 0, 0, pctl->data->npins); 1193 if (ret) 1194 return ret; 1195 1196 /* Add Interrupt support if an irq is specified */ 1197 if (client->irq > 0) { 1198 pctl->irq_chip.irq_mask = sx150x_irq_mask; 1199 pctl->irq_chip.irq_unmask = sx150x_irq_unmask; 1200 pctl->irq_chip.irq_set_type = sx150x_irq_set_type; 1201 pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock; 1202 pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock; 1203 pctl->irq_chip.name = devm_kstrdup(dev, client->name, 1204 GFP_KERNEL); 1205 if (!pctl->irq_chip.name) 1206 return -ENOMEM; 1207 1208 pctl->irq.masked = ~0; 1209 pctl->irq.sense = 0; 1210 1211 /* 1212 * Because sx150x_irq_threaded_fn invokes all of the 1213 * nested interrrupt handlers via handle_nested_irq, 1214 * any "handler" passed to gpiochip_irqchip_add() 1215 * below is going to be ignored, so the choice of the 1216 * function does not matter that much. 1217 * 1218 * We set it to handle_bad_irq to avoid confusion, 1219 * plus it will be instantly noticeable if it is ever 1220 * called (should not happen) 1221 */ 1222 ret = gpiochip_irqchip_add_nested(&pctl->gpio, 1223 &pctl->irq_chip, 0, 1224 handle_bad_irq, IRQ_TYPE_NONE); 1225 if (ret) { 1226 dev_err(dev, "could not connect irqchip to gpiochip\n"); 1227 return ret; 1228 } 1229 1230 ret = devm_request_threaded_irq(dev, client->irq, NULL, 1231 sx150x_irq_thread_fn, 1232 IRQF_ONESHOT | IRQF_SHARED | 1233 IRQF_TRIGGER_FALLING, 1234 pctl->irq_chip.name, pctl); 1235 if (ret < 0) 1236 return ret; 1237 1238 gpiochip_set_nested_irqchip(&pctl->gpio, 1239 &pctl->irq_chip, 1240 client->irq); 1241 } 1242 1243 return 0; 1244 } 1245 1246 static struct i2c_driver sx150x_driver = { 1247 .driver = { 1248 .name = "sx150x-pinctrl", 1249 .of_match_table = of_match_ptr(sx150x_of_match), 1250 }, 1251 .probe = sx150x_probe, 1252 .id_table = sx150x_id, 1253 }; 1254 1255 static int __init sx150x_init(void) 1256 { 1257 return i2c_add_driver(&sx150x_driver); 1258 } 1259 subsys_initcall(sx150x_init); 1260