1 /* 2 * Copyright (c) 2016, BayLibre, SAS. All rights reserved. 3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * 5 * Copyright (c) 2010, Code Aurora Forum. All rights reserved. 6 * 7 * Driver for Semtech SX150X I2C GPIO Expanders 8 * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested. 9 * 10 * Author: Gregory Bean <gbean@codeaurora.org> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 and 14 * only version 2 as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 */ 21 22 #include <linux/regmap.h> 23 #include <linux/i2c.h> 24 #include <linux/init.h> 25 #include <linux/interrupt.h> 26 #include <linux/irq.h> 27 #include <linux/mutex.h> 28 #include <linux/slab.h> 29 #include <linux/of.h> 30 #include <linux/of_device.h> 31 #include <linux/gpio/driver.h> 32 #include <linux/pinctrl/pinconf.h> 33 #include <linux/pinctrl/pinctrl.h> 34 #include <linux/pinctrl/pinmux.h> 35 #include <linux/pinctrl/pinconf-generic.h> 36 37 #include "core.h" 38 #include "pinconf.h" 39 #include "pinctrl-utils.h" 40 41 /* The chip models of sx150x */ 42 enum { 43 SX150X_123 = 0, 44 SX150X_456, 45 SX150X_789, 46 }; 47 enum { 48 SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0, 49 SX150X_MAX_REGISTER = 0xad, 50 SX150X_IRQ_TYPE_EDGE_RISING = 0x1, 51 SX150X_IRQ_TYPE_EDGE_FALLING = 0x2, 52 SX150X_789_RESET_KEY1 = 0x12, 53 SX150X_789_RESET_KEY2 = 0x34, 54 }; 55 56 struct sx150x_123_pri { 57 u8 reg_pld_mode; 58 u8 reg_pld_table0; 59 u8 reg_pld_table1; 60 u8 reg_pld_table2; 61 u8 reg_pld_table3; 62 u8 reg_pld_table4; 63 u8 reg_advanced; 64 }; 65 66 struct sx150x_456_pri { 67 u8 reg_pld_mode; 68 u8 reg_pld_table0; 69 u8 reg_pld_table1; 70 u8 reg_pld_table2; 71 u8 reg_pld_table3; 72 u8 reg_pld_table4; 73 u8 reg_advanced; 74 }; 75 76 struct sx150x_789_pri { 77 u8 reg_drain; 78 u8 reg_polarity; 79 u8 reg_clock; 80 u8 reg_misc; 81 u8 reg_reset; 82 u8 ngpios; 83 }; 84 85 struct sx150x_device_data { 86 u8 model; 87 u8 reg_pullup; 88 u8 reg_pulldn; 89 u8 reg_dir; 90 u8 reg_data; 91 u8 reg_irq_mask; 92 u8 reg_irq_src; 93 u8 reg_sense; 94 u8 ngpios; 95 union { 96 struct sx150x_123_pri x123; 97 struct sx150x_456_pri x456; 98 struct sx150x_789_pri x789; 99 } pri; 100 const struct pinctrl_pin_desc *pins; 101 unsigned int npins; 102 }; 103 104 struct sx150x_pinctrl { 105 struct device *dev; 106 struct i2c_client *client; 107 struct pinctrl_dev *pctldev; 108 struct pinctrl_desc pinctrl_desc; 109 struct gpio_chip gpio; 110 struct irq_chip irq_chip; 111 struct regmap *regmap; 112 struct { 113 u32 sense; 114 u32 masked; 115 } irq; 116 struct mutex lock; 117 const struct sx150x_device_data *data; 118 }; 119 120 static const struct pinctrl_pin_desc sx150x_4_pins[] = { 121 PINCTRL_PIN(0, "gpio0"), 122 PINCTRL_PIN(1, "gpio1"), 123 PINCTRL_PIN(2, "gpio2"), 124 PINCTRL_PIN(3, "gpio3"), 125 PINCTRL_PIN(4, "oscio"), 126 }; 127 128 static const struct pinctrl_pin_desc sx150x_8_pins[] = { 129 PINCTRL_PIN(0, "gpio0"), 130 PINCTRL_PIN(1, "gpio1"), 131 PINCTRL_PIN(2, "gpio2"), 132 PINCTRL_PIN(3, "gpio3"), 133 PINCTRL_PIN(4, "gpio4"), 134 PINCTRL_PIN(5, "gpio5"), 135 PINCTRL_PIN(6, "gpio6"), 136 PINCTRL_PIN(7, "gpio7"), 137 PINCTRL_PIN(8, "oscio"), 138 }; 139 140 static const struct pinctrl_pin_desc sx150x_16_pins[] = { 141 PINCTRL_PIN(0, "gpio0"), 142 PINCTRL_PIN(1, "gpio1"), 143 PINCTRL_PIN(2, "gpio2"), 144 PINCTRL_PIN(3, "gpio3"), 145 PINCTRL_PIN(4, "gpio4"), 146 PINCTRL_PIN(5, "gpio5"), 147 PINCTRL_PIN(6, "gpio6"), 148 PINCTRL_PIN(7, "gpio7"), 149 PINCTRL_PIN(8, "gpio8"), 150 PINCTRL_PIN(9, "gpio9"), 151 PINCTRL_PIN(10, "gpio10"), 152 PINCTRL_PIN(11, "gpio11"), 153 PINCTRL_PIN(12, "gpio12"), 154 PINCTRL_PIN(13, "gpio13"), 155 PINCTRL_PIN(14, "gpio14"), 156 PINCTRL_PIN(15, "gpio15"), 157 PINCTRL_PIN(16, "oscio"), 158 }; 159 160 static const struct sx150x_device_data sx1501q_device_data = { 161 .model = SX150X_123, 162 .reg_pullup = 0x02, 163 .reg_pulldn = 0x03, 164 .reg_dir = 0x01, 165 .reg_data = 0x00, 166 .reg_irq_mask = 0x05, 167 .reg_irq_src = 0x08, 168 .reg_sense = 0x07, 169 .pri.x123 = { 170 .reg_pld_mode = 0x10, 171 .reg_pld_table0 = 0x11, 172 .reg_pld_table2 = 0x13, 173 .reg_advanced = 0xad, 174 }, 175 .ngpios = 4, 176 .pins = sx150x_4_pins, 177 .npins = 4, /* oscio not available */ 178 }; 179 180 static const struct sx150x_device_data sx1502q_device_data = { 181 .model = SX150X_123, 182 .reg_pullup = 0x02, 183 .reg_pulldn = 0x03, 184 .reg_dir = 0x01, 185 .reg_data = 0x00, 186 .reg_irq_mask = 0x05, 187 .reg_irq_src = 0x08, 188 .reg_sense = 0x06, 189 .pri.x123 = { 190 .reg_pld_mode = 0x10, 191 .reg_pld_table0 = 0x11, 192 .reg_pld_table1 = 0x12, 193 .reg_pld_table2 = 0x13, 194 .reg_pld_table3 = 0x14, 195 .reg_pld_table4 = 0x15, 196 .reg_advanced = 0xad, 197 }, 198 .ngpios = 8, 199 .pins = sx150x_8_pins, 200 .npins = 8, /* oscio not available */ 201 }; 202 203 static const struct sx150x_device_data sx1503q_device_data = { 204 .model = SX150X_123, 205 .reg_pullup = 0x04, 206 .reg_pulldn = 0x06, 207 .reg_dir = 0x02, 208 .reg_data = 0x00, 209 .reg_irq_mask = 0x08, 210 .reg_irq_src = 0x0e, 211 .reg_sense = 0x0a, 212 .pri.x123 = { 213 .reg_pld_mode = 0x20, 214 .reg_pld_table0 = 0x22, 215 .reg_pld_table1 = 0x24, 216 .reg_pld_table2 = 0x26, 217 .reg_pld_table3 = 0x28, 218 .reg_pld_table4 = 0x2a, 219 .reg_advanced = 0xad, 220 }, 221 .ngpios = 16, 222 .pins = sx150x_16_pins, 223 .npins = 16, /* oscio not available */ 224 }; 225 226 static const struct sx150x_device_data sx1504q_device_data = { 227 .model = SX150X_456, 228 .reg_pullup = 0x02, 229 .reg_pulldn = 0x03, 230 .reg_dir = 0x01, 231 .reg_data = 0x00, 232 .reg_irq_mask = 0x05, 233 .reg_irq_src = 0x08, 234 .reg_sense = 0x07, 235 .pri.x456 = { 236 .reg_pld_mode = 0x10, 237 .reg_pld_table0 = 0x11, 238 .reg_pld_table2 = 0x13, 239 }, 240 .ngpios = 4, 241 .pins = sx150x_4_pins, 242 .npins = 4, /* oscio not available */ 243 }; 244 245 static const struct sx150x_device_data sx1505q_device_data = { 246 .model = SX150X_456, 247 .reg_pullup = 0x02, 248 .reg_pulldn = 0x03, 249 .reg_dir = 0x01, 250 .reg_data = 0x00, 251 .reg_irq_mask = 0x05, 252 .reg_irq_src = 0x08, 253 .reg_sense = 0x06, 254 .pri.x456 = { 255 .reg_pld_mode = 0x10, 256 .reg_pld_table0 = 0x11, 257 .reg_pld_table1 = 0x12, 258 .reg_pld_table2 = 0x13, 259 .reg_pld_table3 = 0x14, 260 .reg_pld_table4 = 0x15, 261 }, 262 .ngpios = 8, 263 .pins = sx150x_8_pins, 264 .npins = 8, /* oscio not available */ 265 }; 266 267 static const struct sx150x_device_data sx1506q_device_data = { 268 .model = SX150X_456, 269 .reg_pullup = 0x04, 270 .reg_pulldn = 0x06, 271 .reg_dir = 0x02, 272 .reg_data = 0x00, 273 .reg_irq_mask = 0x08, 274 .reg_irq_src = 0x0e, 275 .reg_sense = 0x0a, 276 .pri.x456 = { 277 .reg_pld_mode = 0x20, 278 .reg_pld_table0 = 0x22, 279 .reg_pld_table1 = 0x24, 280 .reg_pld_table2 = 0x26, 281 .reg_pld_table3 = 0x28, 282 .reg_pld_table4 = 0x2a, 283 .reg_advanced = 0xad, 284 }, 285 .ngpios = 16, 286 .pins = sx150x_16_pins, 287 .npins = 16, /* oscio not available */ 288 }; 289 290 static const struct sx150x_device_data sx1507q_device_data = { 291 .model = SX150X_789, 292 .reg_pullup = 0x03, 293 .reg_pulldn = 0x04, 294 .reg_dir = 0x07, 295 .reg_data = 0x08, 296 .reg_irq_mask = 0x09, 297 .reg_irq_src = 0x0b, 298 .reg_sense = 0x0a, 299 .pri.x789 = { 300 .reg_drain = 0x05, 301 .reg_polarity = 0x06, 302 .reg_clock = 0x0d, 303 .reg_misc = 0x0e, 304 .reg_reset = 0x7d, 305 }, 306 .ngpios = 4, 307 .pins = sx150x_4_pins, 308 .npins = ARRAY_SIZE(sx150x_4_pins), 309 }; 310 311 static const struct sx150x_device_data sx1508q_device_data = { 312 .model = SX150X_789, 313 .reg_pullup = 0x03, 314 .reg_pulldn = 0x04, 315 .reg_dir = 0x07, 316 .reg_data = 0x08, 317 .reg_irq_mask = 0x09, 318 .reg_irq_src = 0x0c, 319 .reg_sense = 0x0a, 320 .pri.x789 = { 321 .reg_drain = 0x05, 322 .reg_polarity = 0x06, 323 .reg_clock = 0x0f, 324 .reg_misc = 0x10, 325 .reg_reset = 0x7d, 326 }, 327 .ngpios = 8, 328 .pins = sx150x_8_pins, 329 .npins = ARRAY_SIZE(sx150x_8_pins), 330 }; 331 332 static const struct sx150x_device_data sx1509q_device_data = { 333 .model = SX150X_789, 334 .reg_pullup = 0x06, 335 .reg_pulldn = 0x08, 336 .reg_dir = 0x0e, 337 .reg_data = 0x10, 338 .reg_irq_mask = 0x12, 339 .reg_irq_src = 0x18, 340 .reg_sense = 0x14, 341 .pri.x789 = { 342 .reg_drain = 0x0a, 343 .reg_polarity = 0x0c, 344 .reg_clock = 0x1e, 345 .reg_misc = 0x1f, 346 .reg_reset = 0x7d, 347 }, 348 .ngpios = 16, 349 .pins = sx150x_16_pins, 350 .npins = ARRAY_SIZE(sx150x_16_pins), 351 }; 352 353 static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 354 { 355 return 0; 356 } 357 358 static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 359 unsigned int group) 360 { 361 return NULL; 362 } 363 364 static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 365 unsigned int group, 366 const unsigned int **pins, 367 unsigned int *num_pins) 368 { 369 return -ENOTSUPP; 370 } 371 372 static const struct pinctrl_ops sx150x_pinctrl_ops = { 373 .get_groups_count = sx150x_pinctrl_get_groups_count, 374 .get_group_name = sx150x_pinctrl_get_group_name, 375 .get_group_pins = sx150x_pinctrl_get_group_pins, 376 #ifdef CONFIG_OF 377 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 378 .dt_free_map = pinctrl_utils_free_map, 379 #endif 380 }; 381 382 static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin) 383 { 384 if (pin >= pctl->data->npins) 385 return false; 386 387 /* OSCIO pin is only present in 789 devices */ 388 if (pctl->data->model != SX150X_789) 389 return false; 390 391 return !strcmp(pctl->data->pins[pin].name, "oscio"); 392 } 393 394 static int sx150x_gpio_get_direction(struct gpio_chip *chip, 395 unsigned int offset) 396 { 397 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 398 unsigned int value; 399 int ret; 400 401 if (sx150x_pin_is_oscio(pctl, offset)) 402 return false; 403 404 ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value); 405 if (ret < 0) 406 return ret; 407 408 return !!(value & BIT(offset)); 409 } 410 411 static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset) 412 { 413 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 414 unsigned int value; 415 int ret; 416 417 if (sx150x_pin_is_oscio(pctl, offset)) 418 return -EINVAL; 419 420 ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value); 421 if (ret < 0) 422 return ret; 423 424 return !!(value & BIT(offset)); 425 } 426 427 static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset, 428 int value) 429 { 430 return regmap_write_bits(pctl->regmap, pctl->data->reg_data, 431 BIT(offset), value ? BIT(offset) : 0); 432 } 433 434 static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl, 435 int value) 436 { 437 return regmap_write(pctl->regmap, 438 pctl->data->pri.x789.reg_clock, 439 (value ? 0x1f : 0x10)); 440 } 441 442 static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset, 443 int value) 444 { 445 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 446 447 if (sx150x_pin_is_oscio(pctl, offset)) 448 sx150x_gpio_oscio_set(pctl, value); 449 else 450 __sx150x_gpio_set(pctl, offset, value); 451 452 } 453 454 static void sx150x_gpio_set_multiple(struct gpio_chip *chip, 455 unsigned long *mask, 456 unsigned long *bits) 457 { 458 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 459 460 regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits); 461 } 462 463 static int sx150x_gpio_direction_input(struct gpio_chip *chip, 464 unsigned int offset) 465 { 466 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 467 468 if (sx150x_pin_is_oscio(pctl, offset)) 469 return -EINVAL; 470 471 return regmap_write_bits(pctl->regmap, 472 pctl->data->reg_dir, 473 BIT(offset), BIT(offset)); 474 } 475 476 static int sx150x_gpio_direction_output(struct gpio_chip *chip, 477 unsigned int offset, int value) 478 { 479 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 480 int ret; 481 482 if (sx150x_pin_is_oscio(pctl, offset)) 483 return sx150x_gpio_oscio_set(pctl, value); 484 485 ret = __sx150x_gpio_set(pctl, offset, value); 486 if (ret < 0) 487 return ret; 488 489 return regmap_write_bits(pctl->regmap, 490 pctl->data->reg_dir, 491 BIT(offset), 0); 492 } 493 494 static void sx150x_irq_mask(struct irq_data *d) 495 { 496 struct sx150x_pinctrl *pctl = 497 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 498 unsigned int n = d->hwirq; 499 500 pctl->irq.masked |= BIT(n); 501 } 502 503 static void sx150x_irq_unmask(struct irq_data *d) 504 { 505 struct sx150x_pinctrl *pctl = 506 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 507 unsigned int n = d->hwirq; 508 509 pctl->irq.masked &= ~BIT(n); 510 } 511 512 static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl, 513 unsigned int line, unsigned int sense) 514 { 515 /* 516 * Every interrupt line is represented by two bits shifted 517 * proportionally to the line number 518 */ 519 const unsigned int n = line * 2; 520 const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING | 521 SX150X_IRQ_TYPE_EDGE_FALLING) << n); 522 523 pctl->irq.sense &= mask; 524 pctl->irq.sense |= sense << n; 525 } 526 527 static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type) 528 { 529 struct sx150x_pinctrl *pctl = 530 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 531 unsigned int n, val = 0; 532 533 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 534 return -EINVAL; 535 536 n = d->hwirq; 537 538 if (flow_type & IRQ_TYPE_EDGE_RISING) 539 val |= SX150X_IRQ_TYPE_EDGE_RISING; 540 if (flow_type & IRQ_TYPE_EDGE_FALLING) 541 val |= SX150X_IRQ_TYPE_EDGE_FALLING; 542 543 sx150x_irq_set_sense(pctl, n, val); 544 return 0; 545 } 546 547 static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id) 548 { 549 struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id; 550 unsigned long n, status; 551 unsigned int val; 552 int err; 553 554 err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val); 555 if (err < 0) 556 return IRQ_NONE; 557 558 err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val); 559 if (err < 0) 560 return IRQ_NONE; 561 562 status = val; 563 for_each_set_bit(n, &status, pctl->data->ngpios) 564 handle_nested_irq(irq_find_mapping(pctl->gpio.irqdomain, n)); 565 566 return IRQ_HANDLED; 567 } 568 569 static void sx150x_irq_bus_lock(struct irq_data *d) 570 { 571 struct sx150x_pinctrl *pctl = 572 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 573 574 mutex_lock(&pctl->lock); 575 } 576 577 static void sx150x_irq_bus_sync_unlock(struct irq_data *d) 578 { 579 struct sx150x_pinctrl *pctl = 580 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 581 582 regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked); 583 regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense); 584 mutex_unlock(&pctl->lock); 585 } 586 587 static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 588 unsigned long *config) 589 { 590 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 591 unsigned int param = pinconf_to_config_param(*config); 592 int ret; 593 u32 arg; 594 unsigned int data; 595 596 if (sx150x_pin_is_oscio(pctl, pin)) { 597 switch (param) { 598 case PIN_CONFIG_DRIVE_PUSH_PULL: 599 case PIN_CONFIG_OUTPUT: 600 ret = regmap_read(pctl->regmap, 601 pctl->data->pri.x789.reg_clock, 602 &data); 603 if (ret < 0) 604 return ret; 605 606 if (param == PIN_CONFIG_DRIVE_PUSH_PULL) 607 arg = (data & 0x1f) ? 1 : 0; 608 else { 609 if ((data & 0x1f) == 0x1f) 610 arg = 1; 611 else if ((data & 0x1f) == 0x10) 612 arg = 0; 613 else 614 return -EINVAL; 615 } 616 617 break; 618 default: 619 return -ENOTSUPP; 620 } 621 622 goto out; 623 } 624 625 switch (param) { 626 case PIN_CONFIG_BIAS_PULL_DOWN: 627 ret = regmap_read(pctl->regmap, 628 pctl->data->reg_pulldn, 629 &data); 630 data &= BIT(pin); 631 632 if (ret < 0) 633 return ret; 634 635 if (!ret) 636 return -EINVAL; 637 638 arg = 1; 639 break; 640 641 case PIN_CONFIG_BIAS_PULL_UP: 642 ret = regmap_read(pctl->regmap, 643 pctl->data->reg_pullup, 644 &data); 645 data &= BIT(pin); 646 647 if (ret < 0) 648 return ret; 649 650 if (!ret) 651 return -EINVAL; 652 653 arg = 1; 654 break; 655 656 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 657 if (pctl->data->model != SX150X_789) 658 return -ENOTSUPP; 659 660 ret = regmap_read(pctl->regmap, 661 pctl->data->pri.x789.reg_drain, 662 &data); 663 data &= BIT(pin); 664 665 if (ret < 0) 666 return ret; 667 668 if (!data) 669 return -EINVAL; 670 671 arg = 1; 672 break; 673 674 case PIN_CONFIG_DRIVE_PUSH_PULL: 675 if (pctl->data->model != SX150X_789) 676 arg = true; 677 else { 678 ret = regmap_read(pctl->regmap, 679 pctl->data->pri.x789.reg_drain, 680 &data); 681 data &= BIT(pin); 682 683 if (ret < 0) 684 return ret; 685 686 if (data) 687 return -EINVAL; 688 689 arg = 1; 690 } 691 break; 692 693 case PIN_CONFIG_OUTPUT: 694 ret = sx150x_gpio_get_direction(&pctl->gpio, pin); 695 if (ret < 0) 696 return ret; 697 698 if (ret) 699 return -EINVAL; 700 701 ret = sx150x_gpio_get(&pctl->gpio, pin); 702 if (ret < 0) 703 return ret; 704 705 arg = ret; 706 break; 707 708 default: 709 return -ENOTSUPP; 710 } 711 712 out: 713 *config = pinconf_to_config_packed(param, arg); 714 715 return 0; 716 } 717 718 static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 719 unsigned long *configs, unsigned int num_configs) 720 { 721 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 722 enum pin_config_param param; 723 u32 arg; 724 int i; 725 int ret; 726 727 for (i = 0; i < num_configs; i++) { 728 param = pinconf_to_config_param(configs[i]); 729 arg = pinconf_to_config_argument(configs[i]); 730 731 if (sx150x_pin_is_oscio(pctl, pin)) { 732 if (param == PIN_CONFIG_OUTPUT) { 733 ret = sx150x_gpio_direction_output(&pctl->gpio, 734 pin, arg); 735 if (ret < 0) 736 return ret; 737 738 continue; 739 } else 740 return -ENOTSUPP; 741 } 742 743 switch (param) { 744 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 745 case PIN_CONFIG_BIAS_DISABLE: 746 ret = regmap_write_bits(pctl->regmap, 747 pctl->data->reg_pulldn, 748 BIT(pin), 0); 749 if (ret < 0) 750 return ret; 751 752 ret = regmap_write_bits(pctl->regmap, 753 pctl->data->reg_pullup, 754 BIT(pin), 0); 755 if (ret < 0) 756 return ret; 757 758 break; 759 760 case PIN_CONFIG_BIAS_PULL_UP: 761 ret = regmap_write_bits(pctl->regmap, 762 pctl->data->reg_pullup, 763 BIT(pin), BIT(pin)); 764 if (ret < 0) 765 return ret; 766 767 break; 768 769 case PIN_CONFIG_BIAS_PULL_DOWN: 770 ret = regmap_write_bits(pctl->regmap, 771 pctl->data->reg_pulldn, 772 BIT(pin), BIT(pin)); 773 if (ret < 0) 774 return ret; 775 776 break; 777 778 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 779 if (pctl->data->model != SX150X_789 || 780 sx150x_pin_is_oscio(pctl, pin)) 781 return -ENOTSUPP; 782 783 ret = regmap_write_bits(pctl->regmap, 784 pctl->data->pri.x789.reg_drain, 785 BIT(pin), BIT(pin)); 786 if (ret < 0) 787 return ret; 788 789 break; 790 791 case PIN_CONFIG_DRIVE_PUSH_PULL: 792 if (pctl->data->model != SX150X_789 || 793 sx150x_pin_is_oscio(pctl, pin)) 794 return 0; 795 796 ret = regmap_write_bits(pctl->regmap, 797 pctl->data->pri.x789.reg_drain, 798 BIT(pin), 0); 799 if (ret < 0) 800 return ret; 801 802 break; 803 804 case PIN_CONFIG_OUTPUT: 805 ret = sx150x_gpio_direction_output(&pctl->gpio, 806 pin, arg); 807 if (ret < 0) 808 return ret; 809 810 break; 811 812 default: 813 return -ENOTSUPP; 814 } 815 } /* for each config */ 816 817 return 0; 818 } 819 820 static const struct pinconf_ops sx150x_pinconf_ops = { 821 .pin_config_get = sx150x_pinconf_get, 822 .pin_config_set = sx150x_pinconf_set, 823 .is_generic = true, 824 }; 825 826 static const struct i2c_device_id sx150x_id[] = { 827 {"sx1501q", (kernel_ulong_t) &sx1501q_device_data }, 828 {"sx1502q", (kernel_ulong_t) &sx1502q_device_data }, 829 {"sx1503q", (kernel_ulong_t) &sx1503q_device_data }, 830 {"sx1504q", (kernel_ulong_t) &sx1504q_device_data }, 831 {"sx1505q", (kernel_ulong_t) &sx1505q_device_data }, 832 {"sx1506q", (kernel_ulong_t) &sx1506q_device_data }, 833 {"sx1507q", (kernel_ulong_t) &sx1507q_device_data }, 834 {"sx1508q", (kernel_ulong_t) &sx1508q_device_data }, 835 {"sx1509q", (kernel_ulong_t) &sx1509q_device_data }, 836 {} 837 }; 838 839 static const struct of_device_id sx150x_of_match[] = { 840 { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data }, 841 { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data }, 842 { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data }, 843 { .compatible = "semtech,sx1504q", .data = &sx1504q_device_data }, 844 { .compatible = "semtech,sx1505q", .data = &sx1505q_device_data }, 845 { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data }, 846 { .compatible = "semtech,sx1507q", .data = &sx1507q_device_data }, 847 { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data }, 848 { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data }, 849 {}, 850 }; 851 852 static int sx150x_reset(struct sx150x_pinctrl *pctl) 853 { 854 int err; 855 856 err = i2c_smbus_write_byte_data(pctl->client, 857 pctl->data->pri.x789.reg_reset, 858 SX150X_789_RESET_KEY1); 859 if (err < 0) 860 return err; 861 862 err = i2c_smbus_write_byte_data(pctl->client, 863 pctl->data->pri.x789.reg_reset, 864 SX150X_789_RESET_KEY2); 865 return err; 866 } 867 868 static int sx150x_init_misc(struct sx150x_pinctrl *pctl) 869 { 870 u8 reg, value; 871 872 switch (pctl->data->model) { 873 case SX150X_789: 874 reg = pctl->data->pri.x789.reg_misc; 875 value = SX150X_789_REG_MISC_AUTOCLEAR_OFF; 876 break; 877 case SX150X_456: 878 reg = pctl->data->pri.x456.reg_advanced; 879 value = 0x00; 880 881 /* 882 * Only SX1506 has RegAdvanced, SX1504/5 are expected 883 * to initialize this offset to zero 884 */ 885 if (!reg) 886 return 0; 887 break; 888 case SX150X_123: 889 reg = pctl->data->pri.x123.reg_advanced; 890 value = 0x00; 891 break; 892 default: 893 WARN(1, "Unknown chip model %d\n", pctl->data->model); 894 return -EINVAL; 895 } 896 897 return regmap_write(pctl->regmap, reg, value); 898 } 899 900 static int sx150x_init_hw(struct sx150x_pinctrl *pctl) 901 { 902 const u8 reg[] = { 903 [SX150X_789] = pctl->data->pri.x789.reg_polarity, 904 [SX150X_456] = pctl->data->pri.x456.reg_pld_mode, 905 [SX150X_123] = pctl->data->pri.x123.reg_pld_mode, 906 }; 907 int err; 908 909 if (pctl->data->model == SX150X_789 && 910 of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) { 911 err = sx150x_reset(pctl); 912 if (err < 0) 913 return err; 914 } 915 916 err = sx150x_init_misc(pctl); 917 if (err < 0) 918 return err; 919 920 /* Set all pins to work in normal mode */ 921 return regmap_write(pctl->regmap, reg[pctl->data->model], 0); 922 } 923 924 static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl, 925 unsigned int reg) 926 { 927 const struct sx150x_device_data *data = pctl->data; 928 929 if (reg == data->reg_sense) { 930 /* 931 * RegSense packs two bits of configuration per GPIO, 932 * so we'd need to read twice as many bits as there 933 * are GPIO in our chip 934 */ 935 return 2 * data->ngpios; 936 } else if ((data->model == SX150X_789 && 937 (reg == data->pri.x789.reg_misc || 938 reg == data->pri.x789.reg_clock || 939 reg == data->pri.x789.reg_reset)) 940 || 941 (data->model == SX150X_123 && 942 reg == data->pri.x123.reg_advanced) 943 || 944 (data->model == SX150X_456 && 945 data->pri.x456.reg_advanced && 946 reg == data->pri.x456.reg_advanced)) { 947 return 8; 948 } else { 949 return data->ngpios; 950 } 951 } 952 953 static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl, 954 unsigned int reg, unsigned int val) 955 { 956 unsigned int a, b; 957 const struct sx150x_device_data *data = pctl->data; 958 959 /* 960 * Whereas SX1509 presents RegSense in a simple layout as such: 961 * reg [ f f e e d d c c ] 962 * reg + 1 [ b b a a 9 9 8 8 ] 963 * reg + 2 [ 7 7 6 6 5 5 4 4 ] 964 * reg + 3 [ 3 3 2 2 1 1 0 0 ] 965 * 966 * SX1503 and SX1506 deviate from that data layout, instead storing 967 * their contents as follows: 968 * 969 * reg [ f f e e d d c c ] 970 * reg + 1 [ 7 7 6 6 5 5 4 4 ] 971 * reg + 2 [ b b a a 9 9 8 8 ] 972 * reg + 3 [ 3 3 2 2 1 1 0 0 ] 973 * 974 * so, taking that into account, we swap two 975 * inner bytes of a 4-byte result 976 */ 977 978 if (reg == data->reg_sense && 979 data->ngpios == 16 && 980 (data->model == SX150X_123 || 981 data->model == SX150X_456)) { 982 a = val & 0x00ff0000; 983 b = val & 0x0000ff00; 984 985 val &= 0xff0000ff; 986 val |= b << 8; 987 val |= a >> 8; 988 } 989 990 return val; 991 } 992 993 /* 994 * In order to mask the differences between 16 and 8 bit expander 995 * devices we set up a sligthly ficticious regmap that pretends to be 996 * a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh 997 * pair/quartet) registers and transparently reconstructs those 998 * registers via multiple I2C/SMBus reads 999 * 1000 * This way the rest of the driver code, interfacing with the chip via 1001 * regmap API, can work assuming that each GPIO pin is represented by 1002 * a group of bits at an offset proportional to GPIO number within a 1003 * given register. 1004 */ 1005 static int sx150x_regmap_reg_read(void *context, unsigned int reg, 1006 unsigned int *result) 1007 { 1008 int ret, n; 1009 struct sx150x_pinctrl *pctl = context; 1010 struct i2c_client *i2c = pctl->client; 1011 const int width = sx150x_regmap_reg_width(pctl, reg); 1012 unsigned int idx, val; 1013 1014 /* 1015 * There are four potential cases covered by this function: 1016 * 1017 * 1) 8-pin chip, single configuration bit register 1018 * 1019 * This is trivial the code below just needs to read: 1020 * reg [ 7 6 5 4 3 2 1 0 ] 1021 * 1022 * 2) 8-pin chip, double configuration bit register (RegSense) 1023 * 1024 * The read will be done as follows: 1025 * reg [ 7 7 6 6 5 5 4 4 ] 1026 * reg + 1 [ 3 3 2 2 1 1 0 0 ] 1027 * 1028 * 3) 16-pin chip, single configuration bit register 1029 * 1030 * The read will be done as follows: 1031 * reg [ f e d c b a 9 8 ] 1032 * reg + 1 [ 7 6 5 4 3 2 1 0 ] 1033 * 1034 * 4) 16-pin chip, double configuration bit register (RegSense) 1035 * 1036 * The read will be done as follows: 1037 * reg [ f f e e d d c c ] 1038 * reg + 1 [ b b a a 9 9 8 8 ] 1039 * reg + 2 [ 7 7 6 6 5 5 4 4 ] 1040 * reg + 3 [ 3 3 2 2 1 1 0 0 ] 1041 */ 1042 1043 for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) { 1044 val <<= 8; 1045 1046 ret = i2c_smbus_read_byte_data(i2c, idx); 1047 if (ret < 0) 1048 return ret; 1049 1050 val |= ret; 1051 } 1052 1053 *result = sx150x_maybe_swizzle(pctl, reg, val); 1054 1055 return 0; 1056 } 1057 1058 static int sx150x_regmap_reg_write(void *context, unsigned int reg, 1059 unsigned int val) 1060 { 1061 int ret, n; 1062 struct sx150x_pinctrl *pctl = context; 1063 struct i2c_client *i2c = pctl->client; 1064 const int width = sx150x_regmap_reg_width(pctl, reg); 1065 1066 val = sx150x_maybe_swizzle(pctl, reg, val); 1067 1068 n = (width - 1) & ~7; 1069 do { 1070 const u8 byte = (val >> n) & 0xff; 1071 1072 ret = i2c_smbus_write_byte_data(i2c, reg, byte); 1073 if (ret < 0) 1074 return ret; 1075 1076 reg++; 1077 n -= 8; 1078 } while (n >= 0); 1079 1080 return 0; 1081 } 1082 1083 static bool sx150x_reg_volatile(struct device *dev, unsigned int reg) 1084 { 1085 struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev)); 1086 1087 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data; 1088 } 1089 1090 const struct regmap_config sx150x_regmap_config = { 1091 .reg_bits = 8, 1092 .val_bits = 32, 1093 1094 .cache_type = REGCACHE_RBTREE, 1095 1096 .reg_read = sx150x_regmap_reg_read, 1097 .reg_write = sx150x_regmap_reg_write, 1098 1099 .max_register = SX150X_MAX_REGISTER, 1100 .volatile_reg = sx150x_reg_volatile, 1101 }; 1102 1103 static int sx150x_probe(struct i2c_client *client, 1104 const struct i2c_device_id *id) 1105 { 1106 static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA | 1107 I2C_FUNC_SMBUS_WRITE_WORD_DATA; 1108 struct device *dev = &client->dev; 1109 struct sx150x_pinctrl *pctl; 1110 int ret; 1111 1112 if (!i2c_check_functionality(client->adapter, i2c_funcs)) 1113 return -ENOSYS; 1114 1115 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1116 if (!pctl) 1117 return -ENOMEM; 1118 1119 i2c_set_clientdata(client, pctl); 1120 1121 pctl->dev = dev; 1122 pctl->client = client; 1123 1124 if (dev->of_node) 1125 pctl->data = of_device_get_match_data(dev); 1126 else 1127 pctl->data = (struct sx150x_device_data *)id->driver_data; 1128 1129 if (!pctl->data) 1130 return -EINVAL; 1131 1132 pctl->regmap = devm_regmap_init(dev, NULL, pctl, 1133 &sx150x_regmap_config); 1134 if (IS_ERR(pctl->regmap)) { 1135 ret = PTR_ERR(pctl->regmap); 1136 dev_err(dev, "Failed to allocate register map: %d\n", 1137 ret); 1138 return ret; 1139 } 1140 1141 mutex_init(&pctl->lock); 1142 1143 ret = sx150x_init_hw(pctl); 1144 if (ret) 1145 return ret; 1146 1147 /* Register GPIO controller */ 1148 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL); 1149 pctl->gpio.base = -1; 1150 pctl->gpio.ngpio = pctl->data->npins; 1151 pctl->gpio.get_direction = sx150x_gpio_get_direction; 1152 pctl->gpio.direction_input = sx150x_gpio_direction_input; 1153 pctl->gpio.direction_output = sx150x_gpio_direction_output; 1154 pctl->gpio.get = sx150x_gpio_get; 1155 pctl->gpio.set = sx150x_gpio_set; 1156 pctl->gpio.set_config = gpiochip_generic_config; 1157 pctl->gpio.parent = dev; 1158 #ifdef CONFIG_OF_GPIO 1159 pctl->gpio.of_node = dev->of_node; 1160 #endif 1161 pctl->gpio.can_sleep = true; 1162 /* 1163 * Setting multiple pins is not safe when all pins are not 1164 * handled by the same regmap register. The oscio pin (present 1165 * on the SX150X_789 chips) lives in its own register, so 1166 * would require locking that is not in place at this time. 1167 */ 1168 if (pctl->data->model != SX150X_789) 1169 pctl->gpio.set_multiple = sx150x_gpio_set_multiple; 1170 1171 ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl); 1172 if (ret) 1173 return ret; 1174 1175 /* Add Interrupt support if an irq is specified */ 1176 if (client->irq > 0) { 1177 pctl->irq_chip.name = devm_kstrdup(dev, client->name, 1178 GFP_KERNEL); 1179 pctl->irq_chip.irq_mask = sx150x_irq_mask; 1180 pctl->irq_chip.irq_unmask = sx150x_irq_unmask; 1181 pctl->irq_chip.irq_set_type = sx150x_irq_set_type; 1182 pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock; 1183 pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock; 1184 1185 pctl->irq.masked = ~0; 1186 pctl->irq.sense = 0; 1187 1188 /* 1189 * Because sx150x_irq_threaded_fn invokes all of the 1190 * nested interrrupt handlers via handle_nested_irq, 1191 * any "handler" passed to gpiochip_irqchip_add() 1192 * below is going to be ignored, so the choice of the 1193 * function does not matter that much. 1194 * 1195 * We set it to handle_bad_irq to avoid confusion, 1196 * plus it will be instantly noticeable if it is ever 1197 * called (should not happen) 1198 */ 1199 ret = gpiochip_irqchip_add_nested(&pctl->gpio, 1200 &pctl->irq_chip, 0, 1201 handle_bad_irq, IRQ_TYPE_NONE); 1202 if (ret) { 1203 dev_err(dev, "could not connect irqchip to gpiochip\n"); 1204 return ret; 1205 } 1206 1207 ret = devm_request_threaded_irq(dev, client->irq, NULL, 1208 sx150x_irq_thread_fn, 1209 IRQF_ONESHOT | IRQF_SHARED | 1210 IRQF_TRIGGER_FALLING, 1211 pctl->irq_chip.name, pctl); 1212 if (ret < 0) 1213 return ret; 1214 1215 gpiochip_set_nested_irqchip(&pctl->gpio, 1216 &pctl->irq_chip, 1217 client->irq); 1218 } 1219 1220 /* Pinctrl_desc */ 1221 pctl->pinctrl_desc.name = "sx150x-pinctrl"; 1222 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops; 1223 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops; 1224 pctl->pinctrl_desc.pins = pctl->data->pins; 1225 pctl->pinctrl_desc.npins = pctl->data->npins; 1226 pctl->pinctrl_desc.owner = THIS_MODULE; 1227 1228 pctl->pctldev = pinctrl_register(&pctl->pinctrl_desc, dev, pctl); 1229 if (IS_ERR(pctl->pctldev)) { 1230 dev_err(dev, "Failed to register pinctrl device\n"); 1231 return PTR_ERR(pctl->pctldev); 1232 } 1233 1234 return 0; 1235 } 1236 1237 static struct i2c_driver sx150x_driver = { 1238 .driver = { 1239 .name = "sx150x-pinctrl", 1240 .of_match_table = of_match_ptr(sx150x_of_match), 1241 }, 1242 .probe = sx150x_probe, 1243 .id_table = sx150x_id, 1244 }; 1245 1246 static int __init sx150x_init(void) 1247 { 1248 return i2c_add_driver(&sx150x_driver); 1249 } 1250 subsys_initcall(sx150x_init); 1251