1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, BayLibre, SAS. All rights reserved. 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 * 6 * Copyright (c) 2010, Code Aurora Forum. All rights reserved. 7 * 8 * Driver for Semtech SX150X I2C GPIO Expanders 9 * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested. 10 * 11 * Author: Gregory Bean <gbean@codeaurora.org> 12 */ 13 14 #include <linux/regmap.h> 15 #include <linux/i2c.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/irq.h> 19 #include <linux/mutex.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/gpio/driver.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 #include <linux/pinctrl/pinconf-generic.h> 27 28 #include "core.h" 29 #include "pinconf.h" 30 #include "pinctrl-utils.h" 31 32 /* The chip models of sx150x */ 33 enum { 34 SX150X_123 = 0, 35 SX150X_456, 36 SX150X_789, 37 }; 38 enum { 39 SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0, 40 SX150X_MAX_REGISTER = 0xad, 41 SX150X_IRQ_TYPE_EDGE_RISING = 0x1, 42 SX150X_IRQ_TYPE_EDGE_FALLING = 0x2, 43 SX150X_789_RESET_KEY1 = 0x12, 44 SX150X_789_RESET_KEY2 = 0x34, 45 }; 46 47 struct sx150x_123_pri { 48 u8 reg_pld_mode; 49 u8 reg_pld_table0; 50 u8 reg_pld_table1; 51 u8 reg_pld_table2; 52 u8 reg_pld_table3; 53 u8 reg_pld_table4; 54 u8 reg_advanced; 55 }; 56 57 struct sx150x_456_pri { 58 u8 reg_pld_mode; 59 u8 reg_pld_table0; 60 u8 reg_pld_table1; 61 u8 reg_pld_table2; 62 u8 reg_pld_table3; 63 u8 reg_pld_table4; 64 u8 reg_advanced; 65 }; 66 67 struct sx150x_789_pri { 68 u8 reg_drain; 69 u8 reg_polarity; 70 u8 reg_clock; 71 u8 reg_misc; 72 u8 reg_reset; 73 u8 ngpios; 74 }; 75 76 struct sx150x_device_data { 77 u8 model; 78 u8 reg_pullup; 79 u8 reg_pulldn; 80 u8 reg_dir; 81 u8 reg_data; 82 u8 reg_irq_mask; 83 u8 reg_irq_src; 84 u8 reg_sense; 85 u8 ngpios; 86 union { 87 struct sx150x_123_pri x123; 88 struct sx150x_456_pri x456; 89 struct sx150x_789_pri x789; 90 } pri; 91 const struct pinctrl_pin_desc *pins; 92 unsigned int npins; 93 }; 94 95 struct sx150x_pinctrl { 96 struct device *dev; 97 struct i2c_client *client; 98 struct pinctrl_dev *pctldev; 99 struct pinctrl_desc pinctrl_desc; 100 struct gpio_chip gpio; 101 struct regmap *regmap; 102 struct { 103 u32 sense; 104 u32 masked; 105 } irq; 106 struct mutex lock; 107 const struct sx150x_device_data *data; 108 }; 109 110 static const struct pinctrl_pin_desc sx150x_4_pins[] = { 111 PINCTRL_PIN(0, "gpio0"), 112 PINCTRL_PIN(1, "gpio1"), 113 PINCTRL_PIN(2, "gpio2"), 114 PINCTRL_PIN(3, "gpio3"), 115 PINCTRL_PIN(4, "oscio"), 116 }; 117 118 static const struct pinctrl_pin_desc sx150x_8_pins[] = { 119 PINCTRL_PIN(0, "gpio0"), 120 PINCTRL_PIN(1, "gpio1"), 121 PINCTRL_PIN(2, "gpio2"), 122 PINCTRL_PIN(3, "gpio3"), 123 PINCTRL_PIN(4, "gpio4"), 124 PINCTRL_PIN(5, "gpio5"), 125 PINCTRL_PIN(6, "gpio6"), 126 PINCTRL_PIN(7, "gpio7"), 127 PINCTRL_PIN(8, "oscio"), 128 }; 129 130 static const struct pinctrl_pin_desc sx150x_16_pins[] = { 131 PINCTRL_PIN(0, "gpio0"), 132 PINCTRL_PIN(1, "gpio1"), 133 PINCTRL_PIN(2, "gpio2"), 134 PINCTRL_PIN(3, "gpio3"), 135 PINCTRL_PIN(4, "gpio4"), 136 PINCTRL_PIN(5, "gpio5"), 137 PINCTRL_PIN(6, "gpio6"), 138 PINCTRL_PIN(7, "gpio7"), 139 PINCTRL_PIN(8, "gpio8"), 140 PINCTRL_PIN(9, "gpio9"), 141 PINCTRL_PIN(10, "gpio10"), 142 PINCTRL_PIN(11, "gpio11"), 143 PINCTRL_PIN(12, "gpio12"), 144 PINCTRL_PIN(13, "gpio13"), 145 PINCTRL_PIN(14, "gpio14"), 146 PINCTRL_PIN(15, "gpio15"), 147 PINCTRL_PIN(16, "oscio"), 148 }; 149 150 static const struct sx150x_device_data sx1501q_device_data = { 151 .model = SX150X_123, 152 .reg_pullup = 0x02, 153 .reg_pulldn = 0x03, 154 .reg_dir = 0x01, 155 .reg_data = 0x00, 156 .reg_irq_mask = 0x05, 157 .reg_irq_src = 0x08, 158 .reg_sense = 0x07, 159 .pri.x123 = { 160 .reg_pld_mode = 0x10, 161 .reg_pld_table0 = 0x11, 162 .reg_pld_table2 = 0x13, 163 .reg_advanced = 0xad, 164 }, 165 .ngpios = 4, 166 .pins = sx150x_4_pins, 167 .npins = 4, /* oscio not available */ 168 }; 169 170 static const struct sx150x_device_data sx1502q_device_data = { 171 .model = SX150X_123, 172 .reg_pullup = 0x02, 173 .reg_pulldn = 0x03, 174 .reg_dir = 0x01, 175 .reg_data = 0x00, 176 .reg_irq_mask = 0x05, 177 .reg_irq_src = 0x08, 178 .reg_sense = 0x06, 179 .pri.x123 = { 180 .reg_pld_mode = 0x10, 181 .reg_pld_table0 = 0x11, 182 .reg_pld_table1 = 0x12, 183 .reg_pld_table2 = 0x13, 184 .reg_pld_table3 = 0x14, 185 .reg_pld_table4 = 0x15, 186 .reg_advanced = 0xad, 187 }, 188 .ngpios = 8, 189 .pins = sx150x_8_pins, 190 .npins = 8, /* oscio not available */ 191 }; 192 193 static const struct sx150x_device_data sx1503q_device_data = { 194 .model = SX150X_123, 195 .reg_pullup = 0x04, 196 .reg_pulldn = 0x06, 197 .reg_dir = 0x02, 198 .reg_data = 0x00, 199 .reg_irq_mask = 0x08, 200 .reg_irq_src = 0x0e, 201 .reg_sense = 0x0a, 202 .pri.x123 = { 203 .reg_pld_mode = 0x20, 204 .reg_pld_table0 = 0x22, 205 .reg_pld_table1 = 0x24, 206 .reg_pld_table2 = 0x26, 207 .reg_pld_table3 = 0x28, 208 .reg_pld_table4 = 0x2a, 209 .reg_advanced = 0xad, 210 }, 211 .ngpios = 16, 212 .pins = sx150x_16_pins, 213 .npins = 16, /* oscio not available */ 214 }; 215 216 static const struct sx150x_device_data sx1504q_device_data = { 217 .model = SX150X_456, 218 .reg_pullup = 0x02, 219 .reg_pulldn = 0x03, 220 .reg_dir = 0x01, 221 .reg_data = 0x00, 222 .reg_irq_mask = 0x05, 223 .reg_irq_src = 0x08, 224 .reg_sense = 0x07, 225 .pri.x456 = { 226 .reg_pld_mode = 0x10, 227 .reg_pld_table0 = 0x11, 228 .reg_pld_table2 = 0x13, 229 }, 230 .ngpios = 4, 231 .pins = sx150x_4_pins, 232 .npins = 4, /* oscio not available */ 233 }; 234 235 static const struct sx150x_device_data sx1505q_device_data = { 236 .model = SX150X_456, 237 .reg_pullup = 0x02, 238 .reg_pulldn = 0x03, 239 .reg_dir = 0x01, 240 .reg_data = 0x00, 241 .reg_irq_mask = 0x05, 242 .reg_irq_src = 0x08, 243 .reg_sense = 0x06, 244 .pri.x456 = { 245 .reg_pld_mode = 0x10, 246 .reg_pld_table0 = 0x11, 247 .reg_pld_table1 = 0x12, 248 .reg_pld_table2 = 0x13, 249 .reg_pld_table3 = 0x14, 250 .reg_pld_table4 = 0x15, 251 }, 252 .ngpios = 8, 253 .pins = sx150x_8_pins, 254 .npins = 8, /* oscio not available */ 255 }; 256 257 static const struct sx150x_device_data sx1506q_device_data = { 258 .model = SX150X_456, 259 .reg_pullup = 0x04, 260 .reg_pulldn = 0x06, 261 .reg_dir = 0x02, 262 .reg_data = 0x00, 263 .reg_irq_mask = 0x08, 264 .reg_irq_src = 0x0e, 265 .reg_sense = 0x0a, 266 .pri.x456 = { 267 .reg_pld_mode = 0x20, 268 .reg_pld_table0 = 0x22, 269 .reg_pld_table1 = 0x24, 270 .reg_pld_table2 = 0x26, 271 .reg_pld_table3 = 0x28, 272 .reg_pld_table4 = 0x2a, 273 .reg_advanced = 0xad, 274 }, 275 .ngpios = 16, 276 .pins = sx150x_16_pins, 277 .npins = 16, /* oscio not available */ 278 }; 279 280 static const struct sx150x_device_data sx1507q_device_data = { 281 .model = SX150X_789, 282 .reg_pullup = 0x03, 283 .reg_pulldn = 0x04, 284 .reg_dir = 0x07, 285 .reg_data = 0x08, 286 .reg_irq_mask = 0x09, 287 .reg_irq_src = 0x0b, 288 .reg_sense = 0x0a, 289 .pri.x789 = { 290 .reg_drain = 0x05, 291 .reg_polarity = 0x06, 292 .reg_clock = 0x0d, 293 .reg_misc = 0x0e, 294 .reg_reset = 0x7d, 295 }, 296 .ngpios = 4, 297 .pins = sx150x_4_pins, 298 .npins = ARRAY_SIZE(sx150x_4_pins), 299 }; 300 301 static const struct sx150x_device_data sx1508q_device_data = { 302 .model = SX150X_789, 303 .reg_pullup = 0x03, 304 .reg_pulldn = 0x04, 305 .reg_dir = 0x07, 306 .reg_data = 0x08, 307 .reg_irq_mask = 0x09, 308 .reg_irq_src = 0x0c, 309 .reg_sense = 0x0a, 310 .pri.x789 = { 311 .reg_drain = 0x05, 312 .reg_polarity = 0x06, 313 .reg_clock = 0x0f, 314 .reg_misc = 0x10, 315 .reg_reset = 0x7d, 316 }, 317 .ngpios = 8, 318 .pins = sx150x_8_pins, 319 .npins = ARRAY_SIZE(sx150x_8_pins), 320 }; 321 322 static const struct sx150x_device_data sx1509q_device_data = { 323 .model = SX150X_789, 324 .reg_pullup = 0x06, 325 .reg_pulldn = 0x08, 326 .reg_dir = 0x0e, 327 .reg_data = 0x10, 328 .reg_irq_mask = 0x12, 329 .reg_irq_src = 0x18, 330 .reg_sense = 0x14, 331 .pri.x789 = { 332 .reg_drain = 0x0a, 333 .reg_polarity = 0x0c, 334 .reg_clock = 0x1e, 335 .reg_misc = 0x1f, 336 .reg_reset = 0x7d, 337 }, 338 .ngpios = 16, 339 .pins = sx150x_16_pins, 340 .npins = ARRAY_SIZE(sx150x_16_pins), 341 }; 342 343 static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 344 { 345 return 0; 346 } 347 348 static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 349 unsigned int group) 350 { 351 return NULL; 352 } 353 354 static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 355 unsigned int group, 356 const unsigned int **pins, 357 unsigned int *num_pins) 358 { 359 return -ENOTSUPP; 360 } 361 362 static const struct pinctrl_ops sx150x_pinctrl_ops = { 363 .get_groups_count = sx150x_pinctrl_get_groups_count, 364 .get_group_name = sx150x_pinctrl_get_group_name, 365 .get_group_pins = sx150x_pinctrl_get_group_pins, 366 #ifdef CONFIG_OF 367 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 368 .dt_free_map = pinctrl_utils_free_map, 369 #endif 370 }; 371 372 static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin) 373 { 374 if (pin >= pctl->data->npins) 375 return false; 376 377 /* OSCIO pin is only present in 789 devices */ 378 if (pctl->data->model != SX150X_789) 379 return false; 380 381 return !strcmp(pctl->data->pins[pin].name, "oscio"); 382 } 383 384 static int sx150x_gpio_get_direction(struct gpio_chip *chip, 385 unsigned int offset) 386 { 387 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 388 unsigned int value; 389 int ret; 390 391 if (sx150x_pin_is_oscio(pctl, offset)) 392 return GPIO_LINE_DIRECTION_OUT; 393 394 ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value); 395 if (ret < 0) 396 return ret; 397 398 if (value & BIT(offset)) 399 return GPIO_LINE_DIRECTION_IN; 400 401 return GPIO_LINE_DIRECTION_OUT; 402 } 403 404 static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset) 405 { 406 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 407 unsigned int value; 408 int ret; 409 410 if (sx150x_pin_is_oscio(pctl, offset)) 411 return -EINVAL; 412 413 ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value); 414 if (ret < 0) 415 return ret; 416 417 return !!(value & BIT(offset)); 418 } 419 420 static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset, 421 int value) 422 { 423 return regmap_write_bits(pctl->regmap, pctl->data->reg_data, 424 BIT(offset), value ? BIT(offset) : 0); 425 } 426 427 static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl, 428 int value) 429 { 430 return regmap_write(pctl->regmap, 431 pctl->data->pri.x789.reg_clock, 432 (value ? 0x1f : 0x10)); 433 } 434 435 static int sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset, 436 int value) 437 { 438 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 439 440 if (sx150x_pin_is_oscio(pctl, offset)) 441 return sx150x_gpio_oscio_set(pctl, value); 442 443 return __sx150x_gpio_set(pctl, offset, value); 444 } 445 446 static int sx150x_gpio_set_multiple(struct gpio_chip *chip, 447 unsigned long *mask, 448 unsigned long *bits) 449 { 450 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 451 452 return regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, 453 *bits); 454 } 455 456 static int sx150x_gpio_direction_input(struct gpio_chip *chip, 457 unsigned int offset) 458 { 459 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 460 461 if (sx150x_pin_is_oscio(pctl, offset)) 462 return -EINVAL; 463 464 return regmap_write_bits(pctl->regmap, 465 pctl->data->reg_dir, 466 BIT(offset), BIT(offset)); 467 } 468 469 static int sx150x_gpio_direction_output(struct gpio_chip *chip, 470 unsigned int offset, int value) 471 { 472 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 473 int ret; 474 475 if (sx150x_pin_is_oscio(pctl, offset)) 476 return sx150x_gpio_oscio_set(pctl, value); 477 478 ret = __sx150x_gpio_set(pctl, offset, value); 479 if (ret < 0) 480 return ret; 481 482 return regmap_write_bits(pctl->regmap, 483 pctl->data->reg_dir, 484 BIT(offset), 0); 485 } 486 487 static void sx150x_irq_mask(struct irq_data *d) 488 { 489 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 490 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); 491 unsigned int n = irqd_to_hwirq(d); 492 493 pctl->irq.masked |= BIT(n); 494 gpiochip_disable_irq(gc, n); 495 } 496 497 static void sx150x_irq_unmask(struct irq_data *d) 498 { 499 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 500 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); 501 unsigned int n = irqd_to_hwirq(d); 502 503 gpiochip_enable_irq(gc, n); 504 pctl->irq.masked &= ~BIT(n); 505 } 506 507 static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl, 508 unsigned int line, unsigned int sense) 509 { 510 /* 511 * Every interrupt line is represented by two bits shifted 512 * proportionally to the line number 513 */ 514 const unsigned int n = line * 2; 515 const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING | 516 SX150X_IRQ_TYPE_EDGE_FALLING) << n); 517 518 pctl->irq.sense &= mask; 519 pctl->irq.sense |= sense << n; 520 } 521 522 static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type) 523 { 524 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 525 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); 526 unsigned int n, val = 0; 527 528 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 529 return -EINVAL; 530 531 n = irqd_to_hwirq(d); 532 533 if (flow_type & IRQ_TYPE_EDGE_RISING) 534 val |= SX150X_IRQ_TYPE_EDGE_RISING; 535 if (flow_type & IRQ_TYPE_EDGE_FALLING) 536 val |= SX150X_IRQ_TYPE_EDGE_FALLING; 537 538 sx150x_irq_set_sense(pctl, n, val); 539 return 0; 540 } 541 542 static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id) 543 { 544 struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id; 545 unsigned long n, status; 546 unsigned int val; 547 int err; 548 549 err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val); 550 if (err < 0) 551 return IRQ_NONE; 552 553 err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val); 554 if (err < 0) 555 return IRQ_NONE; 556 557 status = val; 558 for_each_set_bit(n, &status, pctl->data->ngpios) 559 handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n)); 560 561 return IRQ_HANDLED; 562 } 563 564 static void sx150x_irq_bus_lock(struct irq_data *d) 565 { 566 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 567 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); 568 569 mutex_lock(&pctl->lock); 570 } 571 572 static void sx150x_irq_bus_sync_unlock(struct irq_data *d) 573 { 574 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 575 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); 576 577 regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked); 578 regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense); 579 mutex_unlock(&pctl->lock); 580 } 581 582 583 static void sx150x_irq_print_chip(struct irq_data *d, struct seq_file *p) 584 { 585 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 586 struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); 587 588 seq_puts(p, pctl->client->name); 589 } 590 591 static const struct irq_chip sx150x_irq_chip = { 592 .irq_mask = sx150x_irq_mask, 593 .irq_unmask = sx150x_irq_unmask, 594 .irq_set_type = sx150x_irq_set_type, 595 .irq_bus_lock = sx150x_irq_bus_lock, 596 .irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock, 597 .irq_print_chip = sx150x_irq_print_chip, 598 .flags = IRQCHIP_IMMUTABLE, 599 GPIOCHIP_IRQ_RESOURCE_HELPERS, 600 }; 601 602 static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 603 unsigned long *config) 604 { 605 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 606 unsigned int param = pinconf_to_config_param(*config); 607 int ret; 608 u32 arg; 609 unsigned int data; 610 611 if (sx150x_pin_is_oscio(pctl, pin)) { 612 switch (param) { 613 case PIN_CONFIG_DRIVE_PUSH_PULL: 614 case PIN_CONFIG_LEVEL: 615 ret = regmap_read(pctl->regmap, 616 pctl->data->pri.x789.reg_clock, 617 &data); 618 if (ret < 0) 619 return ret; 620 621 if (param == PIN_CONFIG_DRIVE_PUSH_PULL) 622 arg = (data & 0x1f) ? 1 : 0; 623 else { 624 if ((data & 0x1f) == 0x1f) 625 arg = 1; 626 else if ((data & 0x1f) == 0x10) 627 arg = 0; 628 else 629 return -EINVAL; 630 } 631 632 break; 633 default: 634 return -ENOTSUPP; 635 } 636 637 goto out; 638 } 639 640 switch (param) { 641 case PIN_CONFIG_BIAS_PULL_DOWN: 642 ret = regmap_read(pctl->regmap, 643 pctl->data->reg_pulldn, 644 &data); 645 data &= BIT(pin); 646 647 if (ret < 0) 648 return ret; 649 650 if (!ret) 651 return -EINVAL; 652 653 arg = 1; 654 break; 655 656 case PIN_CONFIG_BIAS_PULL_UP: 657 ret = regmap_read(pctl->regmap, 658 pctl->data->reg_pullup, 659 &data); 660 data &= BIT(pin); 661 662 if (ret < 0) 663 return ret; 664 665 if (!ret) 666 return -EINVAL; 667 668 arg = 1; 669 break; 670 671 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 672 if (pctl->data->model != SX150X_789) 673 return -ENOTSUPP; 674 675 ret = regmap_read(pctl->regmap, 676 pctl->data->pri.x789.reg_drain, 677 &data); 678 data &= BIT(pin); 679 680 if (ret < 0) 681 return ret; 682 683 if (!data) 684 return -EINVAL; 685 686 arg = 1; 687 break; 688 689 case PIN_CONFIG_DRIVE_PUSH_PULL: 690 if (pctl->data->model != SX150X_789) 691 arg = true; 692 else { 693 ret = regmap_read(pctl->regmap, 694 pctl->data->pri.x789.reg_drain, 695 &data); 696 data &= BIT(pin); 697 698 if (ret < 0) 699 return ret; 700 701 if (data) 702 return -EINVAL; 703 704 arg = 1; 705 } 706 break; 707 708 case PIN_CONFIG_LEVEL: 709 ret = sx150x_gpio_get_direction(&pctl->gpio, pin); 710 if (ret < 0) 711 return ret; 712 713 if (ret == GPIO_LINE_DIRECTION_IN) 714 return -EINVAL; 715 716 ret = sx150x_gpio_get(&pctl->gpio, pin); 717 if (ret < 0) 718 return ret; 719 720 arg = ret; 721 break; 722 723 default: 724 return -ENOTSUPP; 725 } 726 727 out: 728 *config = pinconf_to_config_packed(param, arg); 729 730 return 0; 731 } 732 733 static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 734 unsigned long *configs, unsigned int num_configs) 735 { 736 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 737 enum pin_config_param param; 738 u32 arg; 739 int i; 740 int ret; 741 742 for (i = 0; i < num_configs; i++) { 743 param = pinconf_to_config_param(configs[i]); 744 arg = pinconf_to_config_argument(configs[i]); 745 746 if (sx150x_pin_is_oscio(pctl, pin)) { 747 if (param == PIN_CONFIG_LEVEL) { 748 ret = sx150x_gpio_direction_output(&pctl->gpio, 749 pin, arg); 750 if (ret < 0) 751 return ret; 752 753 continue; 754 } else 755 return -ENOTSUPP; 756 } 757 758 switch (param) { 759 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 760 case PIN_CONFIG_BIAS_DISABLE: 761 ret = regmap_write_bits(pctl->regmap, 762 pctl->data->reg_pulldn, 763 BIT(pin), 0); 764 if (ret < 0) 765 return ret; 766 767 ret = regmap_write_bits(pctl->regmap, 768 pctl->data->reg_pullup, 769 BIT(pin), 0); 770 if (ret < 0) 771 return ret; 772 773 break; 774 775 case PIN_CONFIG_BIAS_PULL_UP: 776 ret = regmap_write_bits(pctl->regmap, 777 pctl->data->reg_pullup, 778 BIT(pin), BIT(pin)); 779 if (ret < 0) 780 return ret; 781 782 break; 783 784 case PIN_CONFIG_BIAS_PULL_DOWN: 785 ret = regmap_write_bits(pctl->regmap, 786 pctl->data->reg_pulldn, 787 BIT(pin), BIT(pin)); 788 if (ret < 0) 789 return ret; 790 791 break; 792 793 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 794 if (pctl->data->model != SX150X_789 || 795 sx150x_pin_is_oscio(pctl, pin)) 796 return -ENOTSUPP; 797 798 ret = regmap_write_bits(pctl->regmap, 799 pctl->data->pri.x789.reg_drain, 800 BIT(pin), BIT(pin)); 801 if (ret < 0) 802 return ret; 803 804 break; 805 806 case PIN_CONFIG_DRIVE_PUSH_PULL: 807 if (pctl->data->model != SX150X_789 || 808 sx150x_pin_is_oscio(pctl, pin)) 809 return 0; 810 811 ret = regmap_write_bits(pctl->regmap, 812 pctl->data->pri.x789.reg_drain, 813 BIT(pin), 0); 814 if (ret < 0) 815 return ret; 816 817 break; 818 819 case PIN_CONFIG_LEVEL: 820 ret = sx150x_gpio_direction_output(&pctl->gpio, 821 pin, arg); 822 if (ret < 0) 823 return ret; 824 825 break; 826 827 default: 828 return -ENOTSUPP; 829 } 830 } /* for each config */ 831 832 return 0; 833 } 834 835 static const struct pinconf_ops sx150x_pinconf_ops = { 836 .pin_config_get = sx150x_pinconf_get, 837 .pin_config_set = sx150x_pinconf_set, 838 .is_generic = true, 839 }; 840 841 static const struct i2c_device_id sx150x_id[] = { 842 {"sx1501q", (kernel_ulong_t) &sx1501q_device_data }, 843 {"sx1502q", (kernel_ulong_t) &sx1502q_device_data }, 844 {"sx1503q", (kernel_ulong_t) &sx1503q_device_data }, 845 {"sx1504q", (kernel_ulong_t) &sx1504q_device_data }, 846 {"sx1505q", (kernel_ulong_t) &sx1505q_device_data }, 847 {"sx1506q", (kernel_ulong_t) &sx1506q_device_data }, 848 {"sx1507q", (kernel_ulong_t) &sx1507q_device_data }, 849 {"sx1508q", (kernel_ulong_t) &sx1508q_device_data }, 850 {"sx1509q", (kernel_ulong_t) &sx1509q_device_data }, 851 {} 852 }; 853 854 static const struct of_device_id sx150x_of_match[] = { 855 { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data }, 856 { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data }, 857 { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data }, 858 { .compatible = "semtech,sx1504q", .data = &sx1504q_device_data }, 859 { .compatible = "semtech,sx1505q", .data = &sx1505q_device_data }, 860 { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data }, 861 { .compatible = "semtech,sx1507q", .data = &sx1507q_device_data }, 862 { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data }, 863 { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data }, 864 {}, 865 }; 866 MODULE_DEVICE_TABLE(of, sx150x_of_match); 867 868 static int sx150x_reset(struct sx150x_pinctrl *pctl) 869 { 870 int err; 871 872 err = i2c_smbus_write_byte_data(pctl->client, 873 pctl->data->pri.x789.reg_reset, 874 SX150X_789_RESET_KEY1); 875 if (err < 0) 876 return err; 877 878 err = i2c_smbus_write_byte_data(pctl->client, 879 pctl->data->pri.x789.reg_reset, 880 SX150X_789_RESET_KEY2); 881 return err; 882 } 883 884 static int sx150x_init_misc(struct sx150x_pinctrl *pctl) 885 { 886 u8 reg, value; 887 888 switch (pctl->data->model) { 889 case SX150X_789: 890 reg = pctl->data->pri.x789.reg_misc; 891 value = SX150X_789_REG_MISC_AUTOCLEAR_OFF; 892 break; 893 case SX150X_456: 894 reg = pctl->data->pri.x456.reg_advanced; 895 value = 0x00; 896 897 /* 898 * Only SX1506 has RegAdvanced, SX1504/5 are expected 899 * to initialize this offset to zero 900 */ 901 if (!reg) 902 return 0; 903 break; 904 case SX150X_123: 905 reg = pctl->data->pri.x123.reg_advanced; 906 value = 0x00; 907 break; 908 default: 909 WARN(1, "Unknown chip model %d\n", pctl->data->model); 910 return -EINVAL; 911 } 912 913 return regmap_write(pctl->regmap, reg, value); 914 } 915 916 static int sx150x_init_hw(struct sx150x_pinctrl *pctl) 917 { 918 const u8 reg[] = { 919 [SX150X_789] = pctl->data->pri.x789.reg_polarity, 920 [SX150X_456] = pctl->data->pri.x456.reg_pld_mode, 921 [SX150X_123] = pctl->data->pri.x123.reg_pld_mode, 922 }; 923 int err; 924 925 if (pctl->data->model == SX150X_789 && 926 of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) { 927 err = sx150x_reset(pctl); 928 if (err < 0) 929 return err; 930 } 931 932 err = sx150x_init_misc(pctl); 933 if (err < 0) 934 return err; 935 936 /* Set all pins to work in normal mode */ 937 return regmap_write(pctl->regmap, reg[pctl->data->model], 0); 938 } 939 940 static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl, 941 unsigned int reg) 942 { 943 const struct sx150x_device_data *data = pctl->data; 944 945 if (reg == data->reg_sense) { 946 /* 947 * RegSense packs two bits of configuration per GPIO, 948 * so we'd need to read twice as many bits as there 949 * are GPIO in our chip 950 */ 951 return 2 * data->ngpios; 952 } else if ((data->model == SX150X_789 && 953 (reg == data->pri.x789.reg_misc || 954 reg == data->pri.x789.reg_clock || 955 reg == data->pri.x789.reg_reset)) 956 || 957 (data->model == SX150X_123 && 958 reg == data->pri.x123.reg_advanced) 959 || 960 (data->model == SX150X_456 && 961 data->pri.x456.reg_advanced && 962 reg == data->pri.x456.reg_advanced)) { 963 return 8; 964 } else { 965 return data->ngpios; 966 } 967 } 968 969 static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl, 970 unsigned int reg, unsigned int val) 971 { 972 unsigned int a, b; 973 const struct sx150x_device_data *data = pctl->data; 974 975 /* 976 * Whereas SX1509 presents RegSense in a simple layout as such: 977 * reg [ f f e e d d c c ] 978 * reg + 1 [ b b a a 9 9 8 8 ] 979 * reg + 2 [ 7 7 6 6 5 5 4 4 ] 980 * reg + 3 [ 3 3 2 2 1 1 0 0 ] 981 * 982 * SX1503 and SX1506 deviate from that data layout, instead storing 983 * their contents as follows: 984 * 985 * reg [ f f e e d d c c ] 986 * reg + 1 [ 7 7 6 6 5 5 4 4 ] 987 * reg + 2 [ b b a a 9 9 8 8 ] 988 * reg + 3 [ 3 3 2 2 1 1 0 0 ] 989 * 990 * so, taking that into account, we swap two 991 * inner bytes of a 4-byte result 992 */ 993 994 if (reg == data->reg_sense && 995 data->ngpios == 16 && 996 (data->model == SX150X_123 || 997 data->model == SX150X_456)) { 998 a = val & 0x00ff0000; 999 b = val & 0x0000ff00; 1000 1001 val &= 0xff0000ff; 1002 val |= b << 8; 1003 val |= a >> 8; 1004 } 1005 1006 return val; 1007 } 1008 1009 /* 1010 * In order to mask the differences between 16 and 8 bit expander 1011 * devices we set up a sligthly ficticious regmap that pretends to be 1012 * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh 1013 * pair/quartet) registers and transparently reconstructs those 1014 * registers via multiple I2C/SMBus reads 1015 * 1016 * This way the rest of the driver code, interfacing with the chip via 1017 * regmap API, can work assuming that each GPIO pin is represented by 1018 * a group of bits at an offset proportional to GPIO number within a 1019 * given register. 1020 */ 1021 static int sx150x_regmap_reg_read(void *context, unsigned int reg, 1022 unsigned int *result) 1023 { 1024 int ret, n; 1025 struct sx150x_pinctrl *pctl = context; 1026 struct i2c_client *i2c = pctl->client; 1027 const int width = sx150x_regmap_reg_width(pctl, reg); 1028 unsigned int idx, val; 1029 1030 /* 1031 * There are four potential cases covered by this function: 1032 * 1033 * 1) 8-pin chip, single configuration bit register 1034 * 1035 * This is trivial the code below just needs to read: 1036 * reg [ 7 6 5 4 3 2 1 0 ] 1037 * 1038 * 2) 8-pin chip, double configuration bit register (RegSense) 1039 * 1040 * The read will be done as follows: 1041 * reg [ 7 7 6 6 5 5 4 4 ] 1042 * reg + 1 [ 3 3 2 2 1 1 0 0 ] 1043 * 1044 * 3) 16-pin chip, single configuration bit register 1045 * 1046 * The read will be done as follows: 1047 * reg [ f e d c b a 9 8 ] 1048 * reg + 1 [ 7 6 5 4 3 2 1 0 ] 1049 * 1050 * 4) 16-pin chip, double configuration bit register (RegSense) 1051 * 1052 * The read will be done as follows: 1053 * reg [ f f e e d d c c ] 1054 * reg + 1 [ b b a a 9 9 8 8 ] 1055 * reg + 2 [ 7 7 6 6 5 5 4 4 ] 1056 * reg + 3 [ 3 3 2 2 1 1 0 0 ] 1057 */ 1058 1059 for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) { 1060 val <<= 8; 1061 1062 ret = i2c_smbus_read_byte_data(i2c, idx); 1063 if (ret < 0) 1064 return ret; 1065 1066 val |= ret; 1067 } 1068 1069 *result = sx150x_maybe_swizzle(pctl, reg, val); 1070 1071 return 0; 1072 } 1073 1074 static int sx150x_regmap_reg_write(void *context, unsigned int reg, 1075 unsigned int val) 1076 { 1077 int ret, n; 1078 struct sx150x_pinctrl *pctl = context; 1079 struct i2c_client *i2c = pctl->client; 1080 const int width = sx150x_regmap_reg_width(pctl, reg); 1081 1082 val = sx150x_maybe_swizzle(pctl, reg, val); 1083 1084 n = (width - 1) & ~7; 1085 do { 1086 const u8 byte = (val >> n) & 0xff; 1087 1088 ret = i2c_smbus_write_byte_data(i2c, reg, byte); 1089 if (ret < 0) 1090 return ret; 1091 1092 reg++; 1093 n -= 8; 1094 } while (n >= 0); 1095 1096 return 0; 1097 } 1098 1099 static bool sx150x_reg_volatile(struct device *dev, unsigned int reg) 1100 { 1101 struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev)); 1102 1103 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data; 1104 } 1105 1106 static const struct regmap_config sx150x_regmap_config = { 1107 .reg_bits = 8, 1108 .val_bits = 32, 1109 1110 .cache_type = REGCACHE_MAPLE, 1111 1112 .reg_read = sx150x_regmap_reg_read, 1113 .reg_write = sx150x_regmap_reg_write, 1114 1115 .max_register = SX150X_MAX_REGISTER, 1116 .volatile_reg = sx150x_reg_volatile, 1117 }; 1118 1119 static int sx150x_probe(struct i2c_client *client) 1120 { 1121 static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA | 1122 I2C_FUNC_SMBUS_WRITE_WORD_DATA; 1123 struct device *dev = &client->dev; 1124 struct sx150x_pinctrl *pctl; 1125 int ret; 1126 1127 if (!i2c_check_functionality(client->adapter, i2c_funcs)) 1128 return -ENOSYS; 1129 1130 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1131 if (!pctl) 1132 return -ENOMEM; 1133 1134 i2c_set_clientdata(client, pctl); 1135 1136 pctl->dev = dev; 1137 pctl->client = client; 1138 1139 pctl->data = i2c_get_match_data(client); 1140 if (!pctl->data) 1141 return -EINVAL; 1142 1143 pctl->regmap = devm_regmap_init(dev, NULL, pctl, 1144 &sx150x_regmap_config); 1145 if (IS_ERR(pctl->regmap)) { 1146 ret = PTR_ERR(pctl->regmap); 1147 dev_err(dev, "Failed to allocate register map: %d\n", 1148 ret); 1149 return ret; 1150 } 1151 1152 mutex_init(&pctl->lock); 1153 1154 ret = sx150x_init_hw(pctl); 1155 if (ret) 1156 return ret; 1157 1158 /* Pinctrl_desc */ 1159 pctl->pinctrl_desc.name = "sx150x-pinctrl"; 1160 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops; 1161 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops; 1162 pctl->pinctrl_desc.pins = pctl->data->pins; 1163 pctl->pinctrl_desc.npins = pctl->data->npins; 1164 pctl->pinctrl_desc.owner = THIS_MODULE; 1165 1166 ret = devm_pinctrl_register_and_init(dev, &pctl->pinctrl_desc, 1167 pctl, &pctl->pctldev); 1168 if (ret) { 1169 dev_err(dev, "Failed to register pinctrl device\n"); 1170 return ret; 1171 } 1172 1173 /* Register GPIO controller */ 1174 pctl->gpio.base = -1; 1175 pctl->gpio.ngpio = pctl->data->npins; 1176 pctl->gpio.get_direction = sx150x_gpio_get_direction; 1177 pctl->gpio.direction_input = sx150x_gpio_direction_input; 1178 pctl->gpio.direction_output = sx150x_gpio_direction_output; 1179 pctl->gpio.get = sx150x_gpio_get; 1180 pctl->gpio.set = sx150x_gpio_set; 1181 pctl->gpio.set_config = gpiochip_generic_config; 1182 pctl->gpio.parent = dev; 1183 pctl->gpio.can_sleep = true; 1184 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL); 1185 if (!pctl->gpio.label) 1186 return -ENOMEM; 1187 1188 /* 1189 * Setting multiple pins is not safe when all pins are not 1190 * handled by the same regmap register. The oscio pin (present 1191 * on the SX150X_789 chips) lives in its own register, so 1192 * would require locking that is not in place at this time. 1193 */ 1194 if (pctl->data->model != SX150X_789) 1195 pctl->gpio.set_multiple = sx150x_gpio_set_multiple; 1196 1197 /* Add Interrupt support if an irq is specified */ 1198 if (client->irq > 0) { 1199 struct gpio_irq_chip *girq; 1200 1201 pctl->irq.masked = ~0; 1202 pctl->irq.sense = 0; 1203 /* 1204 * Because sx150x_irq_threaded_fn invokes all of the 1205 * nested interrupt handlers via handle_nested_irq, 1206 * any "handler" assigned to struct gpio_irq_chip 1207 * below is going to be ignored, so the choice of the 1208 * function does not matter that much. 1209 * 1210 * We set it to handle_bad_irq to avoid confusion, 1211 * plus it will be instantly noticeable if it is ever 1212 * called (should not happen) 1213 */ 1214 girq = &pctl->gpio.irq; 1215 gpio_irq_chip_set_chip(girq, &sx150x_irq_chip); 1216 /* This will let us handle the parent IRQ in the driver */ 1217 girq->parent_handler = NULL; 1218 girq->num_parents = 0; 1219 girq->parents = NULL; 1220 girq->default_type = IRQ_TYPE_NONE; 1221 girq->handler = handle_bad_irq; 1222 girq->threaded = true; 1223 1224 ret = devm_request_threaded_irq(dev, client->irq, NULL, 1225 sx150x_irq_thread_fn, 1226 IRQF_ONESHOT | IRQF_SHARED | 1227 IRQF_TRIGGER_FALLING, 1228 client->name, pctl); 1229 if (ret < 0) 1230 return ret; 1231 } 1232 1233 ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl); 1234 if (ret) 1235 return ret; 1236 1237 /* 1238 * Pin control functions need to be enabled AFTER registering the 1239 * GPIO chip because sx150x_pinconf_set() calls 1240 * sx150x_gpio_direction_output(). 1241 */ 1242 ret = pinctrl_enable(pctl->pctldev); 1243 if (ret) { 1244 dev_err(dev, "Failed to enable pinctrl device\n"); 1245 return ret; 1246 } 1247 1248 ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev), 1249 0, 0, pctl->data->npins); 1250 if (ret) 1251 return ret; 1252 1253 return 0; 1254 } 1255 1256 static struct i2c_driver sx150x_driver = { 1257 .driver = { 1258 .name = "sx150x-pinctrl", 1259 .of_match_table = sx150x_of_match, 1260 }, 1261 .probe = sx150x_probe, 1262 .id_table = sx150x_id, 1263 }; 1264 1265 static int __init sx150x_init(void) 1266 { 1267 return i2c_add_driver(&sx150x_driver); 1268 } 1269 subsys_initcall(sx150x_init); 1270 1271 MODULE_DESCRIPTION("Semtech SX150x I2C GPIO expander pinctrl driver"); 1272 MODULE_LICENSE("GPL"); 1273