1 /* 2 * Copyright (c) 2016, BayLibre, SAS. All rights reserved. 3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * 5 * Copyright (c) 2010, Code Aurora Forum. All rights reserved. 6 * 7 * Driver for Semtech SX150X I2C GPIO Expanders 8 * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested. 9 * 10 * Author: Gregory Bean <gbean@codeaurora.org> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 and 14 * only version 2 as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 */ 21 22 #include <linux/regmap.h> 23 #include <linux/i2c.h> 24 #include <linux/init.h> 25 #include <linux/interrupt.h> 26 #include <linux/irq.h> 27 #include <linux/mutex.h> 28 #include <linux/slab.h> 29 #include <linux/of.h> 30 #include <linux/of_device.h> 31 #include <linux/gpio/driver.h> 32 #include <linux/pinctrl/pinconf.h> 33 #include <linux/pinctrl/pinctrl.h> 34 #include <linux/pinctrl/pinmux.h> 35 #include <linux/pinctrl/pinconf-generic.h> 36 37 #include "core.h" 38 #include "pinconf.h" 39 #include "pinctrl-utils.h" 40 41 /* The chip models of sx150x */ 42 enum { 43 SX150X_123 = 0, 44 SX150X_456, 45 SX150X_789, 46 }; 47 enum { 48 SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0, 49 SX150X_MAX_REGISTER = 0xad, 50 SX150X_IRQ_TYPE_EDGE_RISING = 0x1, 51 SX150X_IRQ_TYPE_EDGE_FALLING = 0x2, 52 SX150X_789_RESET_KEY1 = 0x12, 53 SX150X_789_RESET_KEY2 = 0x34, 54 }; 55 56 struct sx150x_123_pri { 57 u8 reg_pld_mode; 58 u8 reg_pld_table0; 59 u8 reg_pld_table1; 60 u8 reg_pld_table2; 61 u8 reg_pld_table3; 62 u8 reg_pld_table4; 63 u8 reg_advanced; 64 }; 65 66 struct sx150x_456_pri { 67 u8 reg_pld_mode; 68 u8 reg_pld_table0; 69 u8 reg_pld_table1; 70 u8 reg_pld_table2; 71 u8 reg_pld_table3; 72 u8 reg_pld_table4; 73 u8 reg_advanced; 74 }; 75 76 struct sx150x_789_pri { 77 u8 reg_drain; 78 u8 reg_polarity; 79 u8 reg_clock; 80 u8 reg_misc; 81 u8 reg_reset; 82 u8 ngpios; 83 }; 84 85 struct sx150x_device_data { 86 u8 model; 87 u8 reg_pullup; 88 u8 reg_pulldn; 89 u8 reg_dir; 90 u8 reg_data; 91 u8 reg_irq_mask; 92 u8 reg_irq_src; 93 u8 reg_sense; 94 u8 ngpios; 95 union { 96 struct sx150x_123_pri x123; 97 struct sx150x_456_pri x456; 98 struct sx150x_789_pri x789; 99 } pri; 100 const struct pinctrl_pin_desc *pins; 101 unsigned int npins; 102 }; 103 104 struct sx150x_pinctrl { 105 struct device *dev; 106 struct i2c_client *client; 107 struct pinctrl_dev *pctldev; 108 struct pinctrl_desc pinctrl_desc; 109 struct gpio_chip gpio; 110 struct irq_chip irq_chip; 111 struct regmap *regmap; 112 struct { 113 u32 sense; 114 u32 masked; 115 } irq; 116 struct mutex lock; 117 const struct sx150x_device_data *data; 118 }; 119 120 static const struct pinctrl_pin_desc sx150x_4_pins[] = { 121 PINCTRL_PIN(0, "gpio0"), 122 PINCTRL_PIN(1, "gpio1"), 123 PINCTRL_PIN(2, "gpio2"), 124 PINCTRL_PIN(3, "gpio3"), 125 PINCTRL_PIN(4, "oscio"), 126 }; 127 128 static const struct pinctrl_pin_desc sx150x_8_pins[] = { 129 PINCTRL_PIN(0, "gpio0"), 130 PINCTRL_PIN(1, "gpio1"), 131 PINCTRL_PIN(2, "gpio2"), 132 PINCTRL_PIN(3, "gpio3"), 133 PINCTRL_PIN(4, "gpio4"), 134 PINCTRL_PIN(5, "gpio5"), 135 PINCTRL_PIN(6, "gpio6"), 136 PINCTRL_PIN(7, "gpio7"), 137 PINCTRL_PIN(8, "oscio"), 138 }; 139 140 static const struct pinctrl_pin_desc sx150x_16_pins[] = { 141 PINCTRL_PIN(0, "gpio0"), 142 PINCTRL_PIN(1, "gpio1"), 143 PINCTRL_PIN(2, "gpio2"), 144 PINCTRL_PIN(3, "gpio3"), 145 PINCTRL_PIN(4, "gpio4"), 146 PINCTRL_PIN(5, "gpio5"), 147 PINCTRL_PIN(6, "gpio6"), 148 PINCTRL_PIN(7, "gpio7"), 149 PINCTRL_PIN(8, "gpio8"), 150 PINCTRL_PIN(9, "gpio9"), 151 PINCTRL_PIN(10, "gpio10"), 152 PINCTRL_PIN(11, "gpio11"), 153 PINCTRL_PIN(12, "gpio12"), 154 PINCTRL_PIN(13, "gpio13"), 155 PINCTRL_PIN(14, "gpio14"), 156 PINCTRL_PIN(15, "gpio15"), 157 PINCTRL_PIN(16, "oscio"), 158 }; 159 160 static const struct sx150x_device_data sx1501q_device_data = { 161 .model = SX150X_123, 162 .reg_pullup = 0x02, 163 .reg_pulldn = 0x03, 164 .reg_dir = 0x01, 165 .reg_data = 0x00, 166 .reg_irq_mask = 0x05, 167 .reg_irq_src = 0x08, 168 .reg_sense = 0x07, 169 .pri.x123 = { 170 .reg_pld_mode = 0x10, 171 .reg_pld_table0 = 0x11, 172 .reg_pld_table2 = 0x13, 173 .reg_advanced = 0xad, 174 }, 175 .ngpios = 4, 176 .pins = sx150x_4_pins, 177 .npins = 4, /* oscio not available */ 178 }; 179 180 static const struct sx150x_device_data sx1502q_device_data = { 181 .model = SX150X_123, 182 .reg_pullup = 0x02, 183 .reg_pulldn = 0x03, 184 .reg_dir = 0x01, 185 .reg_data = 0x00, 186 .reg_irq_mask = 0x05, 187 .reg_irq_src = 0x08, 188 .reg_sense = 0x06, 189 .pri.x123 = { 190 .reg_pld_mode = 0x10, 191 .reg_pld_table0 = 0x11, 192 .reg_pld_table1 = 0x12, 193 .reg_pld_table2 = 0x13, 194 .reg_pld_table3 = 0x14, 195 .reg_pld_table4 = 0x15, 196 .reg_advanced = 0xad, 197 }, 198 .ngpios = 8, 199 .pins = sx150x_8_pins, 200 .npins = 8, /* oscio not available */ 201 }; 202 203 static const struct sx150x_device_data sx1503q_device_data = { 204 .model = SX150X_123, 205 .reg_pullup = 0x04, 206 .reg_pulldn = 0x06, 207 .reg_dir = 0x02, 208 .reg_data = 0x00, 209 .reg_irq_mask = 0x08, 210 .reg_irq_src = 0x0e, 211 .reg_sense = 0x0a, 212 .pri.x123 = { 213 .reg_pld_mode = 0x20, 214 .reg_pld_table0 = 0x22, 215 .reg_pld_table1 = 0x24, 216 .reg_pld_table2 = 0x26, 217 .reg_pld_table3 = 0x28, 218 .reg_pld_table4 = 0x2a, 219 .reg_advanced = 0xad, 220 }, 221 .ngpios = 16, 222 .pins = sx150x_16_pins, 223 .npins = 16, /* oscio not available */ 224 }; 225 226 static const struct sx150x_device_data sx1504q_device_data = { 227 .model = SX150X_456, 228 .reg_pullup = 0x02, 229 .reg_pulldn = 0x03, 230 .reg_dir = 0x01, 231 .reg_data = 0x00, 232 .reg_irq_mask = 0x05, 233 .reg_irq_src = 0x08, 234 .reg_sense = 0x07, 235 .pri.x456 = { 236 .reg_pld_mode = 0x10, 237 .reg_pld_table0 = 0x11, 238 .reg_pld_table2 = 0x13, 239 }, 240 .ngpios = 4, 241 .pins = sx150x_4_pins, 242 .npins = 4, /* oscio not available */ 243 }; 244 245 static const struct sx150x_device_data sx1505q_device_data = { 246 .model = SX150X_456, 247 .reg_pullup = 0x02, 248 .reg_pulldn = 0x03, 249 .reg_dir = 0x01, 250 .reg_data = 0x00, 251 .reg_irq_mask = 0x05, 252 .reg_irq_src = 0x08, 253 .reg_sense = 0x06, 254 .pri.x456 = { 255 .reg_pld_mode = 0x10, 256 .reg_pld_table0 = 0x11, 257 .reg_pld_table1 = 0x12, 258 .reg_pld_table2 = 0x13, 259 .reg_pld_table3 = 0x14, 260 .reg_pld_table4 = 0x15, 261 }, 262 .ngpios = 8, 263 .pins = sx150x_8_pins, 264 .npins = 8, /* oscio not available */ 265 }; 266 267 static const struct sx150x_device_data sx1506q_device_data = { 268 .model = SX150X_456, 269 .reg_pullup = 0x04, 270 .reg_pulldn = 0x06, 271 .reg_dir = 0x02, 272 .reg_data = 0x00, 273 .reg_irq_mask = 0x08, 274 .reg_irq_src = 0x0e, 275 .reg_sense = 0x0a, 276 .pri.x456 = { 277 .reg_pld_mode = 0x20, 278 .reg_pld_table0 = 0x22, 279 .reg_pld_table1 = 0x24, 280 .reg_pld_table2 = 0x26, 281 .reg_pld_table3 = 0x28, 282 .reg_pld_table4 = 0x2a, 283 .reg_advanced = 0xad, 284 }, 285 .ngpios = 16, 286 .pins = sx150x_16_pins, 287 .npins = 16, /* oscio not available */ 288 }; 289 290 static const struct sx150x_device_data sx1507q_device_data = { 291 .model = SX150X_789, 292 .reg_pullup = 0x03, 293 .reg_pulldn = 0x04, 294 .reg_dir = 0x07, 295 .reg_data = 0x08, 296 .reg_irq_mask = 0x09, 297 .reg_irq_src = 0x0b, 298 .reg_sense = 0x0a, 299 .pri.x789 = { 300 .reg_drain = 0x05, 301 .reg_polarity = 0x06, 302 .reg_clock = 0x0d, 303 .reg_misc = 0x0e, 304 .reg_reset = 0x7d, 305 }, 306 .ngpios = 4, 307 .pins = sx150x_4_pins, 308 .npins = ARRAY_SIZE(sx150x_4_pins), 309 }; 310 311 static const struct sx150x_device_data sx1508q_device_data = { 312 .model = SX150X_789, 313 .reg_pullup = 0x03, 314 .reg_pulldn = 0x04, 315 .reg_dir = 0x07, 316 .reg_data = 0x08, 317 .reg_irq_mask = 0x09, 318 .reg_irq_src = 0x0c, 319 .reg_sense = 0x0a, 320 .pri.x789 = { 321 .reg_drain = 0x05, 322 .reg_polarity = 0x06, 323 .reg_clock = 0x0f, 324 .reg_misc = 0x10, 325 .reg_reset = 0x7d, 326 }, 327 .ngpios = 8, 328 .pins = sx150x_8_pins, 329 .npins = ARRAY_SIZE(sx150x_8_pins), 330 }; 331 332 static const struct sx150x_device_data sx1509q_device_data = { 333 .model = SX150X_789, 334 .reg_pullup = 0x06, 335 .reg_pulldn = 0x08, 336 .reg_dir = 0x0e, 337 .reg_data = 0x10, 338 .reg_irq_mask = 0x12, 339 .reg_irq_src = 0x18, 340 .reg_sense = 0x14, 341 .pri.x789 = { 342 .reg_drain = 0x0a, 343 .reg_polarity = 0x0c, 344 .reg_clock = 0x1e, 345 .reg_misc = 0x1f, 346 .reg_reset = 0x7d, 347 }, 348 .ngpios = 16, 349 .pins = sx150x_16_pins, 350 .npins = ARRAY_SIZE(sx150x_16_pins), 351 }; 352 353 static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 354 { 355 return 0; 356 } 357 358 static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 359 unsigned int group) 360 { 361 return NULL; 362 } 363 364 static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 365 unsigned int group, 366 const unsigned int **pins, 367 unsigned int *num_pins) 368 { 369 return -ENOTSUPP; 370 } 371 372 static const struct pinctrl_ops sx150x_pinctrl_ops = { 373 .get_groups_count = sx150x_pinctrl_get_groups_count, 374 .get_group_name = sx150x_pinctrl_get_group_name, 375 .get_group_pins = sx150x_pinctrl_get_group_pins, 376 #ifdef CONFIG_OF 377 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 378 .dt_free_map = pinctrl_utils_free_map, 379 #endif 380 }; 381 382 static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin) 383 { 384 if (pin >= pctl->data->npins) 385 return false; 386 387 /* OSCIO pin is only present in 789 devices */ 388 if (pctl->data->model != SX150X_789) 389 return false; 390 391 return !strcmp(pctl->data->pins[pin].name, "oscio"); 392 } 393 394 static int sx150x_gpio_get_direction(struct gpio_chip *chip, 395 unsigned int offset) 396 { 397 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 398 unsigned int value; 399 int ret; 400 401 if (sx150x_pin_is_oscio(pctl, offset)) 402 return false; 403 404 ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value); 405 if (ret < 0) 406 return ret; 407 408 return !!(value & BIT(offset)); 409 } 410 411 static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset) 412 { 413 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 414 unsigned int value; 415 int ret; 416 417 if (sx150x_pin_is_oscio(pctl, offset)) 418 return -EINVAL; 419 420 ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value); 421 if (ret < 0) 422 return ret; 423 424 return !!(value & BIT(offset)); 425 } 426 427 static int sx150x_gpio_set_single_ended(struct gpio_chip *chip, 428 unsigned int offset, 429 enum single_ended_mode mode) 430 { 431 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 432 int ret; 433 434 switch (mode) { 435 case LINE_MODE_PUSH_PULL: 436 if (pctl->data->model != SX150X_789 || 437 sx150x_pin_is_oscio(pctl, offset)) 438 return 0; 439 440 ret = regmap_write_bits(pctl->regmap, 441 pctl->data->pri.x789.reg_drain, 442 BIT(offset), 0); 443 break; 444 445 case LINE_MODE_OPEN_DRAIN: 446 if (pctl->data->model != SX150X_789 || 447 sx150x_pin_is_oscio(pctl, offset)) 448 return -ENOTSUPP; 449 450 ret = regmap_write_bits(pctl->regmap, 451 pctl->data->pri.x789.reg_drain, 452 BIT(offset), BIT(offset)); 453 break; 454 default: 455 ret = -ENOTSUPP; 456 break; 457 } 458 459 return ret; 460 } 461 462 static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset, 463 int value) 464 { 465 return regmap_write_bits(pctl->regmap, pctl->data->reg_data, 466 BIT(offset), value ? BIT(offset) : 0); 467 } 468 469 static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl, 470 int value) 471 { 472 return regmap_write(pctl->regmap, 473 pctl->data->pri.x789.reg_clock, 474 (value ? 0x1f : 0x10)); 475 } 476 477 static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset, 478 int value) 479 { 480 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 481 482 if (sx150x_pin_is_oscio(pctl, offset)) 483 sx150x_gpio_oscio_set(pctl, value); 484 else 485 __sx150x_gpio_set(pctl, offset, value); 486 487 } 488 489 static void sx150x_gpio_set_multiple(struct gpio_chip *chip, 490 unsigned long *mask, 491 unsigned long *bits) 492 { 493 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 494 495 regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits); 496 } 497 498 static int sx150x_gpio_direction_input(struct gpio_chip *chip, 499 unsigned int offset) 500 { 501 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 502 503 if (sx150x_pin_is_oscio(pctl, offset)) 504 return -EINVAL; 505 506 return regmap_write_bits(pctl->regmap, 507 pctl->data->reg_dir, 508 BIT(offset), BIT(offset)); 509 } 510 511 static int sx150x_gpio_direction_output(struct gpio_chip *chip, 512 unsigned int offset, int value) 513 { 514 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); 515 int ret; 516 517 if (sx150x_pin_is_oscio(pctl, offset)) 518 return sx150x_gpio_oscio_set(pctl, value); 519 520 ret = __sx150x_gpio_set(pctl, offset, value); 521 if (ret < 0) 522 return ret; 523 524 return regmap_write_bits(pctl->regmap, 525 pctl->data->reg_dir, 526 BIT(offset), 0); 527 } 528 529 static void sx150x_irq_mask(struct irq_data *d) 530 { 531 struct sx150x_pinctrl *pctl = 532 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 533 unsigned int n = d->hwirq; 534 535 pctl->irq.masked |= BIT(n); 536 } 537 538 static void sx150x_irq_unmask(struct irq_data *d) 539 { 540 struct sx150x_pinctrl *pctl = 541 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 542 unsigned int n = d->hwirq; 543 544 pctl->irq.masked &= ~BIT(n); 545 } 546 547 static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl, 548 unsigned int line, unsigned int sense) 549 { 550 /* 551 * Every interrupt line is represented by two bits shifted 552 * proportionally to the line number 553 */ 554 const unsigned int n = line * 2; 555 const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING | 556 SX150X_IRQ_TYPE_EDGE_FALLING) << n); 557 558 pctl->irq.sense &= mask; 559 pctl->irq.sense |= sense << n; 560 } 561 562 static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type) 563 { 564 struct sx150x_pinctrl *pctl = 565 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 566 unsigned int n, val = 0; 567 568 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 569 return -EINVAL; 570 571 n = d->hwirq; 572 573 if (flow_type & IRQ_TYPE_EDGE_RISING) 574 val |= SX150X_IRQ_TYPE_EDGE_RISING; 575 if (flow_type & IRQ_TYPE_EDGE_FALLING) 576 val |= SX150X_IRQ_TYPE_EDGE_FALLING; 577 578 sx150x_irq_set_sense(pctl, n, val); 579 return 0; 580 } 581 582 static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id) 583 { 584 struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id; 585 unsigned long n, status; 586 unsigned int val; 587 int err; 588 589 err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val); 590 if (err < 0) 591 return IRQ_NONE; 592 593 err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val); 594 if (err < 0) 595 return IRQ_NONE; 596 597 status = val; 598 for_each_set_bit(n, &status, pctl->data->ngpios) 599 handle_nested_irq(irq_find_mapping(pctl->gpio.irqdomain, n)); 600 601 return IRQ_HANDLED; 602 } 603 604 static void sx150x_irq_bus_lock(struct irq_data *d) 605 { 606 struct sx150x_pinctrl *pctl = 607 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 608 609 mutex_lock(&pctl->lock); 610 } 611 612 static void sx150x_irq_bus_sync_unlock(struct irq_data *d) 613 { 614 struct sx150x_pinctrl *pctl = 615 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 616 617 regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked); 618 regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense); 619 mutex_unlock(&pctl->lock); 620 } 621 622 static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 623 unsigned long *config) 624 { 625 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 626 unsigned int param = pinconf_to_config_param(*config); 627 int ret; 628 u32 arg; 629 unsigned int data; 630 631 if (sx150x_pin_is_oscio(pctl, pin)) { 632 switch (param) { 633 case PIN_CONFIG_DRIVE_PUSH_PULL: 634 case PIN_CONFIG_OUTPUT: 635 ret = regmap_read(pctl->regmap, 636 pctl->data->pri.x789.reg_clock, 637 &data); 638 if (ret < 0) 639 return ret; 640 641 if (param == PIN_CONFIG_DRIVE_PUSH_PULL) 642 arg = (data & 0x1f) ? 1 : 0; 643 else { 644 if ((data & 0x1f) == 0x1f) 645 arg = 1; 646 else if ((data & 0x1f) == 0x10) 647 arg = 0; 648 else 649 return -EINVAL; 650 } 651 652 break; 653 default: 654 return -ENOTSUPP; 655 } 656 657 goto out; 658 } 659 660 switch (param) { 661 case PIN_CONFIG_BIAS_PULL_DOWN: 662 ret = regmap_read(pctl->regmap, 663 pctl->data->reg_pulldn, 664 &data); 665 data &= BIT(pin); 666 667 if (ret < 0) 668 return ret; 669 670 if (!ret) 671 return -EINVAL; 672 673 arg = 1; 674 break; 675 676 case PIN_CONFIG_BIAS_PULL_UP: 677 ret = regmap_read(pctl->regmap, 678 pctl->data->reg_pullup, 679 &data); 680 data &= BIT(pin); 681 682 if (ret < 0) 683 return ret; 684 685 if (!ret) 686 return -EINVAL; 687 688 arg = 1; 689 break; 690 691 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 692 if (pctl->data->model != SX150X_789) 693 return -ENOTSUPP; 694 695 ret = regmap_read(pctl->regmap, 696 pctl->data->pri.x789.reg_drain, 697 &data); 698 data &= BIT(pin); 699 700 if (ret < 0) 701 return ret; 702 703 if (!data) 704 return -EINVAL; 705 706 arg = 1; 707 break; 708 709 case PIN_CONFIG_DRIVE_PUSH_PULL: 710 if (pctl->data->model != SX150X_789) 711 arg = true; 712 else { 713 ret = regmap_read(pctl->regmap, 714 pctl->data->pri.x789.reg_drain, 715 &data); 716 data &= BIT(pin); 717 718 if (ret < 0) 719 return ret; 720 721 if (data) 722 return -EINVAL; 723 724 arg = 1; 725 } 726 break; 727 728 case PIN_CONFIG_OUTPUT: 729 ret = sx150x_gpio_get_direction(&pctl->gpio, pin); 730 if (ret < 0) 731 return ret; 732 733 if (ret) 734 return -EINVAL; 735 736 ret = sx150x_gpio_get(&pctl->gpio, pin); 737 if (ret < 0) 738 return ret; 739 740 arg = ret; 741 break; 742 743 default: 744 return -ENOTSUPP; 745 } 746 747 out: 748 *config = pinconf_to_config_packed(param, arg); 749 750 return 0; 751 } 752 753 static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 754 unsigned long *configs, unsigned int num_configs) 755 { 756 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 757 enum pin_config_param param; 758 u32 arg; 759 int i; 760 int ret; 761 762 for (i = 0; i < num_configs; i++) { 763 param = pinconf_to_config_param(configs[i]); 764 arg = pinconf_to_config_argument(configs[i]); 765 766 if (sx150x_pin_is_oscio(pctl, pin)) { 767 if (param == PIN_CONFIG_OUTPUT) { 768 ret = sx150x_gpio_direction_output(&pctl->gpio, 769 pin, arg); 770 if (ret < 0) 771 return ret; 772 773 continue; 774 } else 775 return -ENOTSUPP; 776 } 777 778 switch (param) { 779 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 780 case PIN_CONFIG_BIAS_DISABLE: 781 ret = regmap_write_bits(pctl->regmap, 782 pctl->data->reg_pulldn, 783 BIT(pin), 0); 784 if (ret < 0) 785 return ret; 786 787 ret = regmap_write_bits(pctl->regmap, 788 pctl->data->reg_pullup, 789 BIT(pin), 0); 790 if (ret < 0) 791 return ret; 792 793 break; 794 795 case PIN_CONFIG_BIAS_PULL_UP: 796 ret = regmap_write_bits(pctl->regmap, 797 pctl->data->reg_pullup, 798 BIT(pin), BIT(pin)); 799 if (ret < 0) 800 return ret; 801 802 break; 803 804 case PIN_CONFIG_BIAS_PULL_DOWN: 805 ret = regmap_write_bits(pctl->regmap, 806 pctl->data->reg_pulldn, 807 BIT(pin), BIT(pin)); 808 if (ret < 0) 809 return ret; 810 811 break; 812 813 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 814 ret = sx150x_gpio_set_single_ended(&pctl->gpio, 815 pin, LINE_MODE_OPEN_DRAIN); 816 if (ret < 0) 817 return ret; 818 819 break; 820 821 case PIN_CONFIG_DRIVE_PUSH_PULL: 822 ret = sx150x_gpio_set_single_ended(&pctl->gpio, 823 pin, LINE_MODE_PUSH_PULL); 824 if (ret < 0) 825 return ret; 826 827 break; 828 829 case PIN_CONFIG_OUTPUT: 830 ret = sx150x_gpio_direction_output(&pctl->gpio, 831 pin, arg); 832 if (ret < 0) 833 return ret; 834 835 break; 836 837 default: 838 return -ENOTSUPP; 839 } 840 } /* for each config */ 841 842 return 0; 843 } 844 845 static const struct pinconf_ops sx150x_pinconf_ops = { 846 .pin_config_get = sx150x_pinconf_get, 847 .pin_config_set = sx150x_pinconf_set, 848 .is_generic = true, 849 }; 850 851 static const struct i2c_device_id sx150x_id[] = { 852 {"sx1501q", (kernel_ulong_t) &sx1501q_device_data }, 853 {"sx1502q", (kernel_ulong_t) &sx1502q_device_data }, 854 {"sx1503q", (kernel_ulong_t) &sx1503q_device_data }, 855 {"sx1504q", (kernel_ulong_t) &sx1504q_device_data }, 856 {"sx1505q", (kernel_ulong_t) &sx1505q_device_data }, 857 {"sx1506q", (kernel_ulong_t) &sx1506q_device_data }, 858 {"sx1507q", (kernel_ulong_t) &sx1507q_device_data }, 859 {"sx1508q", (kernel_ulong_t) &sx1508q_device_data }, 860 {"sx1509q", (kernel_ulong_t) &sx1509q_device_data }, 861 {} 862 }; 863 864 static const struct of_device_id sx150x_of_match[] = { 865 { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data }, 866 { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data }, 867 { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data }, 868 { .compatible = "semtech,sx1504q", .data = &sx1504q_device_data }, 869 { .compatible = "semtech,sx1505q", .data = &sx1505q_device_data }, 870 { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data }, 871 { .compatible = "semtech,sx1507q", .data = &sx1507q_device_data }, 872 { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data }, 873 { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data }, 874 {}, 875 }; 876 877 static int sx150x_reset(struct sx150x_pinctrl *pctl) 878 { 879 int err; 880 881 err = i2c_smbus_write_byte_data(pctl->client, 882 pctl->data->pri.x789.reg_reset, 883 SX150X_789_RESET_KEY1); 884 if (err < 0) 885 return err; 886 887 err = i2c_smbus_write_byte_data(pctl->client, 888 pctl->data->pri.x789.reg_reset, 889 SX150X_789_RESET_KEY2); 890 return err; 891 } 892 893 static int sx150x_init_misc(struct sx150x_pinctrl *pctl) 894 { 895 u8 reg, value; 896 897 switch (pctl->data->model) { 898 case SX150X_789: 899 reg = pctl->data->pri.x789.reg_misc; 900 value = SX150X_789_REG_MISC_AUTOCLEAR_OFF; 901 break; 902 case SX150X_456: 903 reg = pctl->data->pri.x456.reg_advanced; 904 value = 0x00; 905 906 /* 907 * Only SX1506 has RegAdvanced, SX1504/5 are expected 908 * to initialize this offset to zero 909 */ 910 if (!reg) 911 return 0; 912 break; 913 case SX150X_123: 914 reg = pctl->data->pri.x123.reg_advanced; 915 value = 0x00; 916 break; 917 default: 918 WARN(1, "Unknown chip model %d\n", pctl->data->model); 919 return -EINVAL; 920 } 921 922 return regmap_write(pctl->regmap, reg, value); 923 } 924 925 static int sx150x_init_hw(struct sx150x_pinctrl *pctl) 926 { 927 const u8 reg[] = { 928 [SX150X_789] = pctl->data->pri.x789.reg_polarity, 929 [SX150X_456] = pctl->data->pri.x456.reg_pld_mode, 930 [SX150X_123] = pctl->data->pri.x123.reg_pld_mode, 931 }; 932 int err; 933 934 if (pctl->data->model == SX150X_789 && 935 of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) { 936 err = sx150x_reset(pctl); 937 if (err < 0) 938 return err; 939 } 940 941 err = sx150x_init_misc(pctl); 942 if (err < 0) 943 return err; 944 945 /* Set all pins to work in normal mode */ 946 return regmap_write(pctl->regmap, reg[pctl->data->model], 0); 947 } 948 949 static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl, 950 unsigned int reg) 951 { 952 const struct sx150x_device_data *data = pctl->data; 953 954 if (reg == data->reg_sense) { 955 /* 956 * RegSense packs two bits of configuration per GPIO, 957 * so we'd need to read twice as many bits as there 958 * are GPIO in our chip 959 */ 960 return 2 * data->ngpios; 961 } else if ((data->model == SX150X_789 && 962 (reg == data->pri.x789.reg_misc || 963 reg == data->pri.x789.reg_clock || 964 reg == data->pri.x789.reg_reset)) 965 || 966 (data->model == SX150X_123 && 967 reg == data->pri.x123.reg_advanced) 968 || 969 (data->model == SX150X_456 && 970 data->pri.x456.reg_advanced && 971 reg == data->pri.x456.reg_advanced)) { 972 return 8; 973 } else { 974 return data->ngpios; 975 } 976 } 977 978 static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl, 979 unsigned int reg, unsigned int val) 980 { 981 unsigned int a, b; 982 const struct sx150x_device_data *data = pctl->data; 983 984 /* 985 * Whereas SX1509 presents RegSense in a simple layout as such: 986 * reg [ f f e e d d c c ] 987 * reg + 1 [ b b a a 9 9 8 8 ] 988 * reg + 2 [ 7 7 6 6 5 5 4 4 ] 989 * reg + 3 [ 3 3 2 2 1 1 0 0 ] 990 * 991 * SX1503 and SX1506 deviate from that data layout, instead storing 992 * their contents as follows: 993 * 994 * reg [ f f e e d d c c ] 995 * reg + 1 [ 7 7 6 6 5 5 4 4 ] 996 * reg + 2 [ b b a a 9 9 8 8 ] 997 * reg + 3 [ 3 3 2 2 1 1 0 0 ] 998 * 999 * so, taking that into account, we swap two 1000 * inner bytes of a 4-byte result 1001 */ 1002 1003 if (reg == data->reg_sense && 1004 data->ngpios == 16 && 1005 (data->model == SX150X_123 || 1006 data->model == SX150X_456)) { 1007 a = val & 0x00ff0000; 1008 b = val & 0x0000ff00; 1009 1010 val &= 0xff0000ff; 1011 val |= b << 8; 1012 val |= a >> 8; 1013 } 1014 1015 return val; 1016 } 1017 1018 /* 1019 * In order to mask the differences between 16 and 8 bit expander 1020 * devices we set up a sligthly ficticious regmap that pretends to be 1021 * a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh 1022 * pair/quartet) registers and transparently reconstructs those 1023 * registers via multiple I2C/SMBus reads 1024 * 1025 * This way the rest of the driver code, interfacing with the chip via 1026 * regmap API, can work assuming that each GPIO pin is represented by 1027 * a group of bits at an offset proportional to GPIO number within a 1028 * given register. 1029 */ 1030 static int sx150x_regmap_reg_read(void *context, unsigned int reg, 1031 unsigned int *result) 1032 { 1033 int ret, n; 1034 struct sx150x_pinctrl *pctl = context; 1035 struct i2c_client *i2c = pctl->client; 1036 const int width = sx150x_regmap_reg_width(pctl, reg); 1037 unsigned int idx, val; 1038 1039 /* 1040 * There are four potential cases covered by this function: 1041 * 1042 * 1) 8-pin chip, single configuration bit register 1043 * 1044 * This is trivial the code below just needs to read: 1045 * reg [ 7 6 5 4 3 2 1 0 ] 1046 * 1047 * 2) 8-pin chip, double configuration bit register (RegSense) 1048 * 1049 * The read will be done as follows: 1050 * reg [ 7 7 6 6 5 5 4 4 ] 1051 * reg + 1 [ 3 3 2 2 1 1 0 0 ] 1052 * 1053 * 3) 16-pin chip, single configuration bit register 1054 * 1055 * The read will be done as follows: 1056 * reg [ f e d c b a 9 8 ] 1057 * reg + 1 [ 7 6 5 4 3 2 1 0 ] 1058 * 1059 * 4) 16-pin chip, double configuration bit register (RegSense) 1060 * 1061 * The read will be done as follows: 1062 * reg [ f f e e d d c c ] 1063 * reg + 1 [ b b a a 9 9 8 8 ] 1064 * reg + 2 [ 7 7 6 6 5 5 4 4 ] 1065 * reg + 3 [ 3 3 2 2 1 1 0 0 ] 1066 */ 1067 1068 for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) { 1069 val <<= 8; 1070 1071 ret = i2c_smbus_read_byte_data(i2c, idx); 1072 if (ret < 0) 1073 return ret; 1074 1075 val |= ret; 1076 } 1077 1078 *result = sx150x_maybe_swizzle(pctl, reg, val); 1079 1080 return 0; 1081 } 1082 1083 static int sx150x_regmap_reg_write(void *context, unsigned int reg, 1084 unsigned int val) 1085 { 1086 int ret, n; 1087 struct sx150x_pinctrl *pctl = context; 1088 struct i2c_client *i2c = pctl->client; 1089 const int width = sx150x_regmap_reg_width(pctl, reg); 1090 1091 val = sx150x_maybe_swizzle(pctl, reg, val); 1092 1093 n = (width - 1) & ~7; 1094 do { 1095 const u8 byte = (val >> n) & 0xff; 1096 1097 ret = i2c_smbus_write_byte_data(i2c, reg, byte); 1098 if (ret < 0) 1099 return ret; 1100 1101 reg++; 1102 n -= 8; 1103 } while (n >= 0); 1104 1105 return 0; 1106 } 1107 1108 static bool sx150x_reg_volatile(struct device *dev, unsigned int reg) 1109 { 1110 struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev)); 1111 1112 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data; 1113 } 1114 1115 const struct regmap_config sx150x_regmap_config = { 1116 .reg_bits = 8, 1117 .val_bits = 32, 1118 1119 .cache_type = REGCACHE_RBTREE, 1120 1121 .reg_read = sx150x_regmap_reg_read, 1122 .reg_write = sx150x_regmap_reg_write, 1123 1124 .max_register = SX150X_MAX_REGISTER, 1125 .volatile_reg = sx150x_reg_volatile, 1126 }; 1127 1128 static int sx150x_probe(struct i2c_client *client, 1129 const struct i2c_device_id *id) 1130 { 1131 static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA | 1132 I2C_FUNC_SMBUS_WRITE_WORD_DATA; 1133 struct device *dev = &client->dev; 1134 struct sx150x_pinctrl *pctl; 1135 int ret; 1136 1137 if (!i2c_check_functionality(client->adapter, i2c_funcs)) 1138 return -ENOSYS; 1139 1140 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1141 if (!pctl) 1142 return -ENOMEM; 1143 1144 i2c_set_clientdata(client, pctl); 1145 1146 pctl->dev = dev; 1147 pctl->client = client; 1148 1149 if (dev->of_node) 1150 pctl->data = of_device_get_match_data(dev); 1151 else 1152 pctl->data = (struct sx150x_device_data *)id->driver_data; 1153 1154 if (!pctl->data) 1155 return -EINVAL; 1156 1157 pctl->regmap = devm_regmap_init(dev, NULL, pctl, 1158 &sx150x_regmap_config); 1159 if (IS_ERR(pctl->regmap)) { 1160 ret = PTR_ERR(pctl->regmap); 1161 dev_err(dev, "Failed to allocate register map: %d\n", 1162 ret); 1163 return ret; 1164 } 1165 1166 mutex_init(&pctl->lock); 1167 1168 ret = sx150x_init_hw(pctl); 1169 if (ret) 1170 return ret; 1171 1172 /* Register GPIO controller */ 1173 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL); 1174 pctl->gpio.base = -1; 1175 pctl->gpio.ngpio = pctl->data->npins; 1176 pctl->gpio.get_direction = sx150x_gpio_get_direction; 1177 pctl->gpio.direction_input = sx150x_gpio_direction_input; 1178 pctl->gpio.direction_output = sx150x_gpio_direction_output; 1179 pctl->gpio.get = sx150x_gpio_get; 1180 pctl->gpio.set = sx150x_gpio_set; 1181 pctl->gpio.set_single_ended = sx150x_gpio_set_single_ended; 1182 pctl->gpio.parent = dev; 1183 #ifdef CONFIG_OF_GPIO 1184 pctl->gpio.of_node = dev->of_node; 1185 #endif 1186 pctl->gpio.can_sleep = true; 1187 /* 1188 * Setting multiple pins is not safe when all pins are not 1189 * handled by the same regmap register. The oscio pin (present 1190 * on the SX150X_789 chips) lives in its own register, so 1191 * would require locking that is not in place at this time. 1192 */ 1193 if (pctl->data->model != SX150X_789) 1194 pctl->gpio.set_multiple = sx150x_gpio_set_multiple; 1195 1196 ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl); 1197 if (ret) 1198 return ret; 1199 1200 /* Add Interrupt support if an irq is specified */ 1201 if (client->irq > 0) { 1202 pctl->irq_chip.name = devm_kstrdup(dev, client->name, 1203 GFP_KERNEL); 1204 pctl->irq_chip.irq_mask = sx150x_irq_mask; 1205 pctl->irq_chip.irq_unmask = sx150x_irq_unmask; 1206 pctl->irq_chip.irq_set_type = sx150x_irq_set_type; 1207 pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock; 1208 pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock; 1209 1210 pctl->irq.masked = ~0; 1211 pctl->irq.sense = 0; 1212 1213 /* 1214 * Because sx150x_irq_threaded_fn invokes all of the 1215 * nested interrrupt handlers via handle_nested_irq, 1216 * any "handler" passed to gpiochip_irqchip_add() 1217 * below is going to be ignored, so the choice of the 1218 * function does not matter that much. 1219 * 1220 * We set it to handle_bad_irq to avoid confusion, 1221 * plus it will be instantly noticeable if it is ever 1222 * called (should not happen) 1223 */ 1224 ret = gpiochip_irqchip_add_nested(&pctl->gpio, 1225 &pctl->irq_chip, 0, 1226 handle_bad_irq, IRQ_TYPE_NONE); 1227 if (ret) { 1228 dev_err(dev, "could not connect irqchip to gpiochip\n"); 1229 return ret; 1230 } 1231 1232 ret = devm_request_threaded_irq(dev, client->irq, NULL, 1233 sx150x_irq_thread_fn, 1234 IRQF_ONESHOT | IRQF_SHARED | 1235 IRQF_TRIGGER_FALLING, 1236 pctl->irq_chip.name, pctl); 1237 if (ret < 0) 1238 return ret; 1239 1240 gpiochip_set_nested_irqchip(&pctl->gpio, 1241 &pctl->irq_chip, 1242 client->irq); 1243 } 1244 1245 /* Pinctrl_desc */ 1246 pctl->pinctrl_desc.name = "sx150x-pinctrl"; 1247 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops; 1248 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops; 1249 pctl->pinctrl_desc.pins = pctl->data->pins; 1250 pctl->pinctrl_desc.npins = pctl->data->npins; 1251 pctl->pinctrl_desc.owner = THIS_MODULE; 1252 1253 pctl->pctldev = pinctrl_register(&pctl->pinctrl_desc, dev, pctl); 1254 if (IS_ERR(pctl->pctldev)) { 1255 dev_err(dev, "Failed to register pinctrl device\n"); 1256 return PTR_ERR(pctl->pctldev); 1257 } 1258 1259 return 0; 1260 } 1261 1262 static struct i2c_driver sx150x_driver = { 1263 .driver = { 1264 .name = "sx150x-pinctrl", 1265 .of_match_table = of_match_ptr(sx150x_of_match), 1266 }, 1267 .probe = sx150x_probe, 1268 .id_table = sx150x_id, 1269 }; 1270 1271 static int __init sx150x_init(void) 1272 { 1273 return i2c_add_driver(&sx150x_driver); 1274 } 1275 subsys_initcall(sx150x_init); 1276