1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander 4 * 5 * Copyright (C) 2019 STMicroelectronics 6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>. 7 */ 8 #include <linux/gpio/driver.h> 9 #include <linux/interrupt.h> 10 #include <linux/mfd/stmfx.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/seq_file.h> 14 #include <linux/string_choices.h> 15 16 #include <linux/pinctrl/pinconf.h> 17 #include <linux/pinctrl/pinmux.h> 18 19 #include "core.h" 20 #include "pinctrl-utils.h" 21 22 /* GPIOs expander */ 23 /* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */ 24 #define STMFX_REG_GPIO_STATE STMFX_REG_GPIO_STATE1 /* R */ 25 /* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */ 26 #define STMFX_REG_GPIO_DIR STMFX_REG_GPIO_DIR1 /* RW */ 27 /* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */ 28 #define STMFX_REG_GPIO_TYPE STMFX_REG_GPIO_TYPE1 /* RW */ 29 /* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */ 30 #define STMFX_REG_GPIO_PUPD STMFX_REG_GPIO_PUPD1 /* RW */ 31 /* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */ 32 #define STMFX_REG_GPO_SET STMFX_REG_GPO_SET1 /* RW */ 33 /* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */ 34 #define STMFX_REG_GPO_CLR STMFX_REG_GPO_CLR1 /* RW */ 35 /* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */ 36 #define STMFX_REG_IRQ_GPI_SRC STMFX_REG_IRQ_GPI_SRC1 /* RW */ 37 /* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */ 38 #define STMFX_REG_IRQ_GPI_EVT STMFX_REG_IRQ_GPI_EVT1 /* RW */ 39 /* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */ 40 #define STMFX_REG_IRQ_GPI_TYPE STMFX_REG_IRQ_GPI_TYPE1 /* RW */ 41 /* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/ 42 #define STMFX_REG_IRQ_GPI_PENDING STMFX_REG_IRQ_GPI_PENDING1 /* R */ 43 /* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */ 44 #define STMFX_REG_IRQ_GPI_ACK STMFX_REG_IRQ_GPI_ACK1 /* RW */ 45 46 #define NR_GPIO_REGS 3 47 #define NR_GPIOS_PER_REG 8 48 #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG) 49 #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG) 50 #define get_mask(offset) (BIT(get_shift(offset))) 51 52 /* 53 * STMFX pinctrl can have up to 24 pins if STMFX other functions are not used. 54 * Pins availability is managed thanks to gpio-ranges property. 55 */ 56 static const struct pinctrl_pin_desc stmfx_pins[] = { 57 PINCTRL_PIN(0, "gpio0"), 58 PINCTRL_PIN(1, "gpio1"), 59 PINCTRL_PIN(2, "gpio2"), 60 PINCTRL_PIN(3, "gpio3"), 61 PINCTRL_PIN(4, "gpio4"), 62 PINCTRL_PIN(5, "gpio5"), 63 PINCTRL_PIN(6, "gpio6"), 64 PINCTRL_PIN(7, "gpio7"), 65 PINCTRL_PIN(8, "gpio8"), 66 PINCTRL_PIN(9, "gpio9"), 67 PINCTRL_PIN(10, "gpio10"), 68 PINCTRL_PIN(11, "gpio11"), 69 PINCTRL_PIN(12, "gpio12"), 70 PINCTRL_PIN(13, "gpio13"), 71 PINCTRL_PIN(14, "gpio14"), 72 PINCTRL_PIN(15, "gpio15"), 73 PINCTRL_PIN(16, "agpio0"), 74 PINCTRL_PIN(17, "agpio1"), 75 PINCTRL_PIN(18, "agpio2"), 76 PINCTRL_PIN(19, "agpio3"), 77 PINCTRL_PIN(20, "agpio4"), 78 PINCTRL_PIN(21, "agpio5"), 79 PINCTRL_PIN(22, "agpio6"), 80 PINCTRL_PIN(23, "agpio7"), 81 }; 82 83 struct stmfx_pinctrl { 84 struct device *dev; 85 struct stmfx *stmfx; 86 struct pinctrl_dev *pctl_dev; 87 struct pinctrl_desc pctl_desc; 88 struct gpio_chip gpio_chip; 89 struct mutex lock; /* IRQ bus lock */ 90 unsigned long gpio_valid_mask; 91 /* Cache of IRQ_GPI_* registers for bus_lock */ 92 u8 irq_gpi_src[NR_GPIO_REGS]; 93 u8 irq_gpi_type[NR_GPIO_REGS]; 94 u8 irq_gpi_evt[NR_GPIO_REGS]; 95 u8 irq_toggle_edge[NR_GPIO_REGS]; 96 #ifdef CONFIG_PM 97 /* Backup of GPIO_* registers for suspend/resume */ 98 u8 bkp_gpio_state[NR_GPIO_REGS]; 99 u8 bkp_gpio_dir[NR_GPIO_REGS]; 100 u8 bkp_gpio_type[NR_GPIO_REGS]; 101 u8 bkp_gpio_pupd[NR_GPIO_REGS]; 102 #endif 103 }; 104 105 static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset) 106 { 107 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 108 u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset); 109 u32 mask = get_mask(offset); 110 u32 value; 111 int ret; 112 113 ret = regmap_read(pctl->stmfx->map, reg, &value); 114 115 return ret ? ret : !!(value & mask); 116 } 117 118 static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 119 { 120 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 121 u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR; 122 u32 mask = get_mask(offset); 123 124 regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset), 125 mask, mask); 126 } 127 128 static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 129 { 130 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 131 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 132 u32 mask = get_mask(offset); 133 u32 val; 134 int ret; 135 136 ret = regmap_read(pctl->stmfx->map, reg, &val); 137 /* 138 * On stmfx, gpio pins direction is (0)input, (1)output. 139 */ 140 if (ret) 141 return ret; 142 143 if (val & mask) 144 return GPIO_LINE_DIRECTION_OUT; 145 146 return GPIO_LINE_DIRECTION_IN; 147 } 148 149 static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 150 { 151 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 152 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 153 u32 mask = get_mask(offset); 154 155 return regmap_write_bits(pctl->stmfx->map, reg, mask, 0); 156 } 157 158 static int stmfx_gpio_direction_output(struct gpio_chip *gc, 159 unsigned int offset, int value) 160 { 161 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 162 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 163 u32 mask = get_mask(offset); 164 165 stmfx_gpio_set(gc, offset, value); 166 167 return regmap_write_bits(pctl->stmfx->map, reg, mask, mask); 168 } 169 170 static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl, 171 unsigned int offset) 172 { 173 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); 174 u32 pupd, mask = get_mask(offset); 175 int ret; 176 177 ret = regmap_read(pctl->stmfx->map, reg, &pupd); 178 if (ret) 179 return ret; 180 181 return !!(pupd & mask); 182 } 183 184 static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl, 185 unsigned int offset, u32 pupd) 186 { 187 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); 188 u32 mask = get_mask(offset); 189 190 return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0); 191 } 192 193 static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl, 194 unsigned int offset) 195 { 196 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); 197 u32 type, mask = get_mask(offset); 198 int ret; 199 200 ret = regmap_read(pctl->stmfx->map, reg, &type); 201 if (ret) 202 return ret; 203 204 return !!(type & mask); 205 } 206 207 static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl, 208 unsigned int offset, u32 type) 209 { 210 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); 211 u32 mask = get_mask(offset); 212 213 return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0); 214 } 215 216 static int stmfx_pinconf_get(struct pinctrl_dev *pctldev, 217 unsigned int pin, unsigned long *config) 218 { 219 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 220 u32 param = pinconf_to_config_param(*config); 221 struct pinctrl_gpio_range *range; 222 u32 arg = 0; 223 int ret, dir, type, pupd; 224 225 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 226 if (!range) 227 return -EINVAL; 228 229 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin); 230 if (dir < 0) 231 return dir; 232 233 /* 234 * Currently the gpiolib IN is 1 and OUT is 0 but let's not count 235 * on it just to be on the safe side also in the future :) 236 */ 237 dir = (dir == GPIO_LINE_DIRECTION_IN) ? 1 : 0; 238 239 type = stmfx_pinconf_get_type(pctl, pin); 240 if (type < 0) 241 return type; 242 pupd = stmfx_pinconf_get_pupd(pctl, pin); 243 if (pupd < 0) 244 return pupd; 245 246 switch (param) { 247 case PIN_CONFIG_BIAS_DISABLE: 248 if ((!dir && (!type || !pupd)) || (dir && !type)) 249 arg = 1; 250 break; 251 case PIN_CONFIG_BIAS_PULL_DOWN: 252 if (dir && type && !pupd) 253 arg = 1; 254 break; 255 case PIN_CONFIG_BIAS_PULL_UP: 256 if (type && pupd) 257 arg = 1; 258 break; 259 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 260 if ((!dir && type) || (dir && !type)) 261 arg = 1; 262 break; 263 case PIN_CONFIG_DRIVE_PUSH_PULL: 264 if ((!dir && !type) || (dir && type)) 265 arg = 1; 266 break; 267 case PIN_CONFIG_OUTPUT: 268 if (dir) 269 return -EINVAL; 270 271 ret = stmfx_gpio_get(&pctl->gpio_chip, pin); 272 if (ret < 0) 273 return ret; 274 275 arg = ret; 276 break; 277 default: 278 return -ENOTSUPP; 279 } 280 281 *config = pinconf_to_config_packed(param, arg); 282 283 return 0; 284 } 285 286 static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 287 unsigned long *configs, unsigned int num_configs) 288 { 289 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 290 struct pinctrl_gpio_range *range; 291 enum pin_config_param param; 292 u32 arg; 293 int i, ret; 294 295 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 296 if (!range) { 297 dev_err(pctldev->dev, "pin %d is not available\n", pin); 298 return -EINVAL; 299 } 300 301 for (i = 0; i < num_configs; i++) { 302 param = pinconf_to_config_param(configs[i]); 303 arg = pinconf_to_config_argument(configs[i]); 304 305 switch (param) { 306 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 307 case PIN_CONFIG_BIAS_DISABLE: 308 case PIN_CONFIG_DRIVE_PUSH_PULL: 309 ret = stmfx_pinconf_set_type(pctl, pin, 0); 310 if (ret) 311 return ret; 312 break; 313 case PIN_CONFIG_BIAS_PULL_DOWN: 314 ret = stmfx_pinconf_set_type(pctl, pin, 1); 315 if (ret) 316 return ret; 317 ret = stmfx_pinconf_set_pupd(pctl, pin, 0); 318 if (ret) 319 return ret; 320 break; 321 case PIN_CONFIG_BIAS_PULL_UP: 322 ret = stmfx_pinconf_set_type(pctl, pin, 1); 323 if (ret) 324 return ret; 325 ret = stmfx_pinconf_set_pupd(pctl, pin, 1); 326 if (ret) 327 return ret; 328 break; 329 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 330 ret = stmfx_pinconf_set_type(pctl, pin, 1); 331 if (ret) 332 return ret; 333 break; 334 case PIN_CONFIG_OUTPUT: 335 ret = stmfx_gpio_direction_output(&pctl->gpio_chip, 336 pin, arg); 337 if (ret) 338 return ret; 339 break; 340 default: 341 return -ENOTSUPP; 342 } 343 } 344 345 return 0; 346 } 347 348 static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 349 struct seq_file *s, unsigned int offset) 350 { 351 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 352 struct pinctrl_gpio_range *range; 353 int dir, type, pupd, val; 354 355 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset); 356 if (!range) 357 return; 358 359 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset); 360 if (dir < 0) 361 return; 362 type = stmfx_pinconf_get_type(pctl, offset); 363 if (type < 0) 364 return; 365 pupd = stmfx_pinconf_get_pupd(pctl, offset); 366 if (pupd < 0) 367 return; 368 val = stmfx_gpio_get(&pctl->gpio_chip, offset); 369 if (val < 0) 370 return; 371 372 if (dir == GPIO_LINE_DIRECTION_OUT) { 373 seq_printf(s, "output %s ", str_high_low(val)); 374 if (type) 375 seq_printf(s, "open drain %s internal pull-up ", 376 pupd ? "with" : "without"); 377 else 378 seq_puts(s, "push pull no pull "); 379 } else { 380 seq_printf(s, "input %s ", str_high_low(val)); 381 if (type) 382 seq_printf(s, "with internal pull-%s ", 383 pupd ? "up" : "down"); 384 else 385 seq_printf(s, "%s ", pupd ? "floating" : "analog"); 386 } 387 } 388 389 static const struct pinconf_ops stmfx_pinconf_ops = { 390 .pin_config_get = stmfx_pinconf_get, 391 .pin_config_set = stmfx_pinconf_set, 392 .pin_config_dbg_show = stmfx_pinconf_dbg_show, 393 }; 394 395 static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 396 { 397 return 0; 398 } 399 400 static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 401 unsigned int selector) 402 { 403 return NULL; 404 } 405 406 static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 407 unsigned int selector, 408 const unsigned int **pins, 409 unsigned int *num_pins) 410 { 411 return -ENOTSUPP; 412 } 413 414 static const struct pinctrl_ops stmfx_pinctrl_ops = { 415 .get_groups_count = stmfx_pinctrl_get_groups_count, 416 .get_group_name = stmfx_pinctrl_get_group_name, 417 .get_group_pins = stmfx_pinctrl_get_group_pins, 418 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 419 .dt_free_map = pinctrl_utils_free_map, 420 }; 421 422 static void stmfx_pinctrl_irq_mask(struct irq_data *data) 423 { 424 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 425 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 426 u32 reg = get_reg(data->hwirq); 427 u32 mask = get_mask(data->hwirq); 428 429 pctl->irq_gpi_src[reg] &= ~mask; 430 gpiochip_disable_irq(gpio_chip, irqd_to_hwirq(data)); 431 } 432 433 static void stmfx_pinctrl_irq_unmask(struct irq_data *data) 434 { 435 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 436 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 437 u32 reg = get_reg(data->hwirq); 438 u32 mask = get_mask(data->hwirq); 439 440 gpiochip_enable_irq(gpio_chip, irqd_to_hwirq(data)); 441 pctl->irq_gpi_src[reg] |= mask; 442 } 443 444 static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type) 445 { 446 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 447 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 448 u32 reg = get_reg(data->hwirq); 449 u32 mask = get_mask(data->hwirq); 450 451 if (type == IRQ_TYPE_NONE) 452 return -EINVAL; 453 454 if (type & IRQ_TYPE_EDGE_BOTH) { 455 pctl->irq_gpi_evt[reg] |= mask; 456 irq_set_handler_locked(data, handle_edge_irq); 457 } else { 458 pctl->irq_gpi_evt[reg] &= ~mask; 459 irq_set_handler_locked(data, handle_level_irq); 460 } 461 462 if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH)) 463 pctl->irq_gpi_type[reg] |= mask; 464 else 465 pctl->irq_gpi_type[reg] &= ~mask; 466 467 /* 468 * In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current 469 * GPIO value to set the right edge trigger. But in atomic context 470 * here we can't access registers over I2C. That's why (type & 471 * IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock. 472 */ 473 474 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 475 pctl->irq_toggle_edge[reg] |= mask; 476 else 477 pctl->irq_toggle_edge[reg] &= mask; 478 479 return 0; 480 } 481 482 static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data) 483 { 484 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 485 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 486 487 mutex_lock(&pctl->lock); 488 } 489 490 static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data) 491 { 492 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 493 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 494 u32 reg = get_reg(data->hwirq); 495 u32 mask = get_mask(data->hwirq); 496 497 /* 498 * In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value 499 * (this couldn't be done in .irq_set_type because of atomic context) 500 * to set the right irq trigger type. 501 */ 502 if (pctl->irq_toggle_edge[reg] & mask) { 503 if (stmfx_gpio_get(gpio_chip, data->hwirq)) 504 pctl->irq_gpi_type[reg] &= ~mask; 505 else 506 pctl->irq_gpi_type[reg] |= mask; 507 } 508 509 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT, 510 pctl->irq_gpi_evt, NR_GPIO_REGS); 511 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE, 512 pctl->irq_gpi_type, NR_GPIO_REGS); 513 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 514 pctl->irq_gpi_src, NR_GPIO_REGS); 515 516 mutex_unlock(&pctl->lock); 517 } 518 519 static int stmfx_gpio_irq_request_resources(struct irq_data *data) 520 { 521 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 522 int ret; 523 524 ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq); 525 if (ret) 526 return ret; 527 528 return gpiochip_reqres_irq(gpio_chip, data->hwirq); 529 } 530 531 static void stmfx_gpio_irq_release_resources(struct irq_data *data) 532 { 533 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 534 535 return gpiochip_relres_irq(gpio_chip, data->hwirq); 536 } 537 538 static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl, 539 unsigned int offset) 540 { 541 u32 reg = get_reg(offset); 542 u32 mask = get_mask(offset); 543 int val; 544 545 if (!(pctl->irq_toggle_edge[reg] & mask)) 546 return; 547 548 val = stmfx_gpio_get(&pctl->gpio_chip, offset); 549 if (val < 0) 550 return; 551 552 if (val) { 553 pctl->irq_gpi_type[reg] &= mask; 554 regmap_write_bits(pctl->stmfx->map, 555 STMFX_REG_IRQ_GPI_TYPE + reg, 556 mask, 0); 557 558 } else { 559 pctl->irq_gpi_type[reg] |= mask; 560 regmap_write_bits(pctl->stmfx->map, 561 STMFX_REG_IRQ_GPI_TYPE + reg, 562 mask, mask); 563 } 564 } 565 566 static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id) 567 { 568 struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id; 569 struct gpio_chip *gc = &pctl->gpio_chip; 570 u8 pending[NR_GPIO_REGS]; 571 u8 src[NR_GPIO_REGS] = {0, 0, 0}; 572 unsigned long n, status; 573 int i, ret; 574 575 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING, 576 &pending, NR_GPIO_REGS); 577 if (ret) 578 return IRQ_NONE; 579 580 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 581 src, NR_GPIO_REGS); 582 583 BUILD_BUG_ON(NR_GPIO_REGS > sizeof(status)); 584 for (i = 0, status = 0; i < NR_GPIO_REGS; i++) 585 status |= (unsigned long)pending[i] << (i * 8); 586 for_each_set_bit(n, &status, gc->ngpio) { 587 handle_nested_irq(irq_find_mapping(gc->irq.domain, n)); 588 stmfx_pinctrl_irq_toggle_trigger(pctl, n); 589 } 590 591 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 592 pctl->irq_gpi_src, NR_GPIO_REGS); 593 594 return IRQ_HANDLED; 595 } 596 597 static void stmfx_pinctrl_irq_print_chip(struct irq_data *d, struct seq_file *p) 598 { 599 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(d); 600 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 601 602 seq_printf(p, dev_name(pctl->dev)); 603 } 604 605 static const struct irq_chip stmfx_pinctrl_irq_chip = { 606 .irq_mask = stmfx_pinctrl_irq_mask, 607 .irq_unmask = stmfx_pinctrl_irq_unmask, 608 .irq_set_type = stmfx_pinctrl_irq_set_type, 609 .irq_bus_lock = stmfx_pinctrl_irq_bus_lock, 610 .irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock, 611 .irq_request_resources = stmfx_gpio_irq_request_resources, 612 .irq_release_resources = stmfx_gpio_irq_release_resources, 613 .irq_print_chip = stmfx_pinctrl_irq_print_chip, 614 .flags = IRQCHIP_IMMUTABLE, 615 }; 616 617 static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl) 618 { 619 struct pinctrl_gpio_range *gpio_range; 620 struct pinctrl_dev *pctl_dev = pctl->pctl_dev; 621 u32 func = STMFX_FUNC_GPIO; 622 623 pctl->gpio_valid_mask = GENMASK(15, 0); 624 625 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16); 626 if (gpio_range) { 627 func |= STMFX_FUNC_ALTGPIO_LOW; 628 pctl->gpio_valid_mask |= GENMASK(19, 16); 629 } 630 631 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20); 632 if (gpio_range) { 633 func |= STMFX_FUNC_ALTGPIO_HIGH; 634 pctl->gpio_valid_mask |= GENMASK(23, 20); 635 } 636 637 return stmfx_function_enable(pctl->stmfx, func); 638 } 639 640 static int stmfx_pinctrl_probe(struct platform_device *pdev) 641 { 642 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); 643 struct device_node *np = pdev->dev.of_node; 644 struct stmfx_pinctrl *pctl; 645 struct gpio_irq_chip *girq; 646 int irq, ret; 647 648 pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL); 649 if (!pctl) 650 return -ENOMEM; 651 652 platform_set_drvdata(pdev, pctl); 653 654 pctl->dev = &pdev->dev; 655 pctl->stmfx = stmfx; 656 657 if (!of_property_present(np, "gpio-ranges")) { 658 dev_err(pctl->dev, "missing required gpio-ranges property\n"); 659 return -EINVAL; 660 } 661 662 irq = platform_get_irq(pdev, 0); 663 if (irq < 0) 664 return irq; 665 666 mutex_init(&pctl->lock); 667 668 /* Register pin controller */ 669 pctl->pctl_desc.name = "stmfx-pinctrl"; 670 pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops; 671 pctl->pctl_desc.confops = &stmfx_pinconf_ops; 672 pctl->pctl_desc.pins = stmfx_pins; 673 pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins); 674 pctl->pctl_desc.owner = THIS_MODULE; 675 pctl->pctl_desc.link_consumers = true; 676 677 ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc, 678 pctl, &pctl->pctl_dev); 679 if (ret) { 680 dev_err(pctl->dev, "pinctrl registration failed\n"); 681 return ret; 682 } 683 684 ret = pinctrl_enable(pctl->pctl_dev); 685 if (ret) { 686 dev_err(pctl->dev, "pinctrl enable failed\n"); 687 return ret; 688 } 689 690 /* Register gpio controller */ 691 pctl->gpio_chip.label = "stmfx-gpio"; 692 pctl->gpio_chip.parent = pctl->dev; 693 pctl->gpio_chip.get_direction = stmfx_gpio_get_direction; 694 pctl->gpio_chip.direction_input = stmfx_gpio_direction_input; 695 pctl->gpio_chip.direction_output = stmfx_gpio_direction_output; 696 pctl->gpio_chip.get = stmfx_gpio_get; 697 pctl->gpio_chip.set = stmfx_gpio_set; 698 pctl->gpio_chip.set_config = gpiochip_generic_config; 699 pctl->gpio_chip.base = -1; 700 pctl->gpio_chip.ngpio = pctl->pctl_desc.npins; 701 pctl->gpio_chip.can_sleep = true; 702 703 girq = &pctl->gpio_chip.irq; 704 gpio_irq_chip_set_chip(girq, &stmfx_pinctrl_irq_chip); 705 /* This will let us handle the parent IRQ in the driver */ 706 girq->parent_handler = NULL; 707 girq->num_parents = 0; 708 girq->parents = NULL; 709 girq->default_type = IRQ_TYPE_NONE; 710 girq->handler = handle_bad_irq; 711 girq->threaded = true; 712 713 ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl); 714 if (ret) { 715 dev_err(pctl->dev, "gpio_chip registration failed\n"); 716 return ret; 717 } 718 719 ret = stmfx_pinctrl_gpio_function_enable(pctl); 720 if (ret) 721 return ret; 722 723 ret = devm_request_threaded_irq(pctl->dev, irq, NULL, 724 stmfx_pinctrl_irq_thread_fn, 725 IRQF_ONESHOT, 726 dev_name(pctl->dev), pctl); 727 if (ret) { 728 dev_err(pctl->dev, "cannot request irq%d\n", irq); 729 return ret; 730 } 731 732 dev_info(pctl->dev, 733 "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask)); 734 735 return 0; 736 } 737 738 static void stmfx_pinctrl_remove(struct platform_device *pdev) 739 { 740 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); 741 int ret; 742 743 ret = stmfx_function_disable(stmfx, 744 STMFX_FUNC_GPIO | 745 STMFX_FUNC_ALTGPIO_LOW | 746 STMFX_FUNC_ALTGPIO_HIGH); 747 if (ret) 748 dev_err(&pdev->dev, "Failed to disable pins (%pe)\n", 749 ERR_PTR(ret)); 750 } 751 752 #ifdef CONFIG_PM_SLEEP 753 static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl) 754 { 755 int ret; 756 757 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE, 758 &pctl->bkp_gpio_state, NR_GPIO_REGS); 759 if (ret) 760 return ret; 761 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR, 762 &pctl->bkp_gpio_dir, NR_GPIO_REGS); 763 if (ret) 764 return ret; 765 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE, 766 &pctl->bkp_gpio_type, NR_GPIO_REGS); 767 if (ret) 768 return ret; 769 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD, 770 &pctl->bkp_gpio_pupd, NR_GPIO_REGS); 771 if (ret) 772 return ret; 773 774 return 0; 775 } 776 777 static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl) 778 { 779 int ret; 780 781 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR, 782 pctl->bkp_gpio_dir, NR_GPIO_REGS); 783 if (ret) 784 return ret; 785 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE, 786 pctl->bkp_gpio_type, NR_GPIO_REGS); 787 if (ret) 788 return ret; 789 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD, 790 pctl->bkp_gpio_pupd, NR_GPIO_REGS); 791 if (ret) 792 return ret; 793 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET, 794 pctl->bkp_gpio_state, NR_GPIO_REGS); 795 if (ret) 796 return ret; 797 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT, 798 pctl->irq_gpi_evt, NR_GPIO_REGS); 799 if (ret) 800 return ret; 801 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE, 802 pctl->irq_gpi_type, NR_GPIO_REGS); 803 if (ret) 804 return ret; 805 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 806 pctl->irq_gpi_src, NR_GPIO_REGS); 807 if (ret) 808 return ret; 809 810 return 0; 811 } 812 813 static int stmfx_pinctrl_suspend(struct device *dev) 814 { 815 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev); 816 int ret; 817 818 ret = stmfx_pinctrl_backup_regs(pctl); 819 if (ret) { 820 dev_err(pctl->dev, "registers backup failure\n"); 821 return ret; 822 } 823 824 return 0; 825 } 826 827 static int stmfx_pinctrl_resume(struct device *dev) 828 { 829 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev); 830 int ret; 831 832 ret = stmfx_pinctrl_restore_regs(pctl); 833 if (ret) { 834 dev_err(pctl->dev, "registers restoration failure\n"); 835 return ret; 836 } 837 838 return 0; 839 } 840 #endif 841 842 static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops, 843 stmfx_pinctrl_suspend, stmfx_pinctrl_resume); 844 845 static const struct of_device_id stmfx_pinctrl_of_match[] = { 846 { .compatible = "st,stmfx-0300-pinctrl", }, 847 {}, 848 }; 849 MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match); 850 851 static struct platform_driver stmfx_pinctrl_driver = { 852 .driver = { 853 .name = "stmfx-pinctrl", 854 .of_match_table = stmfx_pinctrl_of_match, 855 .pm = &stmfx_pinctrl_dev_pm_ops, 856 }, 857 .probe = stmfx_pinctrl_probe, 858 .remove_new = stmfx_pinctrl_remove, 859 }; 860 module_platform_driver(stmfx_pinctrl_driver); 861 862 MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver"); 863 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); 864 MODULE_LICENSE("GPL v2"); 865