1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander 4 * 5 * Copyright (C) 2019 STMicroelectronics 6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>. 7 */ 8 #include <linux/gpio/driver.h> 9 #include <linux/interrupt.h> 10 #include <linux/mfd/stmfx.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pinctrl/pinconf.h> 14 #include <linux/pinctrl/pinmux.h> 15 16 #include "core.h" 17 #include "pinctrl-utils.h" 18 19 /* GPIOs expander */ 20 /* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */ 21 #define STMFX_REG_GPIO_STATE STMFX_REG_GPIO_STATE1 /* R */ 22 /* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */ 23 #define STMFX_REG_GPIO_DIR STMFX_REG_GPIO_DIR1 /* RW */ 24 /* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */ 25 #define STMFX_REG_GPIO_TYPE STMFX_REG_GPIO_TYPE1 /* RW */ 26 /* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */ 27 #define STMFX_REG_GPIO_PUPD STMFX_REG_GPIO_PUPD1 /* RW */ 28 /* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */ 29 #define STMFX_REG_GPO_SET STMFX_REG_GPO_SET1 /* RW */ 30 /* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */ 31 #define STMFX_REG_GPO_CLR STMFX_REG_GPO_CLR1 /* RW */ 32 /* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */ 33 #define STMFX_REG_IRQ_GPI_SRC STMFX_REG_IRQ_GPI_SRC1 /* RW */ 34 /* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */ 35 #define STMFX_REG_IRQ_GPI_EVT STMFX_REG_IRQ_GPI_EVT1 /* RW */ 36 /* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */ 37 #define STMFX_REG_IRQ_GPI_TYPE STMFX_REG_IRQ_GPI_TYPE1 /* RW */ 38 /* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/ 39 #define STMFX_REG_IRQ_GPI_PENDING STMFX_REG_IRQ_GPI_PENDING1 /* R */ 40 /* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */ 41 #define STMFX_REG_IRQ_GPI_ACK STMFX_REG_IRQ_GPI_ACK1 /* RW */ 42 43 #define NR_GPIO_REGS 3 44 #define NR_GPIOS_PER_REG 8 45 #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG) 46 #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG) 47 #define get_mask(offset) (BIT(get_shift(offset))) 48 49 /* 50 * STMFX pinctrl can have up to 24 pins if STMFX other functions are not used. 51 * Pins availability is managed thanks to gpio-ranges property. 52 */ 53 static const struct pinctrl_pin_desc stmfx_pins[] = { 54 PINCTRL_PIN(0, "gpio0"), 55 PINCTRL_PIN(1, "gpio1"), 56 PINCTRL_PIN(2, "gpio2"), 57 PINCTRL_PIN(3, "gpio3"), 58 PINCTRL_PIN(4, "gpio4"), 59 PINCTRL_PIN(5, "gpio5"), 60 PINCTRL_PIN(6, "gpio6"), 61 PINCTRL_PIN(7, "gpio7"), 62 PINCTRL_PIN(8, "gpio8"), 63 PINCTRL_PIN(9, "gpio9"), 64 PINCTRL_PIN(10, "gpio10"), 65 PINCTRL_PIN(11, "gpio11"), 66 PINCTRL_PIN(12, "gpio12"), 67 PINCTRL_PIN(13, "gpio13"), 68 PINCTRL_PIN(14, "gpio14"), 69 PINCTRL_PIN(15, "gpio15"), 70 PINCTRL_PIN(16, "agpio0"), 71 PINCTRL_PIN(17, "agpio1"), 72 PINCTRL_PIN(18, "agpio2"), 73 PINCTRL_PIN(19, "agpio3"), 74 PINCTRL_PIN(20, "agpio4"), 75 PINCTRL_PIN(21, "agpio5"), 76 PINCTRL_PIN(22, "agpio6"), 77 PINCTRL_PIN(23, "agpio7"), 78 }; 79 80 struct stmfx_pinctrl { 81 struct device *dev; 82 struct stmfx *stmfx; 83 struct pinctrl_dev *pctl_dev; 84 struct pinctrl_desc pctl_desc; 85 struct gpio_chip gpio_chip; 86 struct irq_chip irq_chip; 87 struct mutex lock; /* IRQ bus lock */ 88 unsigned long gpio_valid_mask; 89 /* Cache of IRQ_GPI_* registers for bus_lock */ 90 u8 irq_gpi_src[NR_GPIO_REGS]; 91 u8 irq_gpi_type[NR_GPIO_REGS]; 92 u8 irq_gpi_evt[NR_GPIO_REGS]; 93 u8 irq_toggle_edge[NR_GPIO_REGS]; 94 #ifdef CONFIG_PM 95 /* Backup of GPIO_* registers for suspend/resume */ 96 u8 bkp_gpio_state[NR_GPIO_REGS]; 97 u8 bkp_gpio_dir[NR_GPIO_REGS]; 98 u8 bkp_gpio_type[NR_GPIO_REGS]; 99 u8 bkp_gpio_pupd[NR_GPIO_REGS]; 100 #endif 101 }; 102 103 static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset) 104 { 105 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 106 u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset); 107 u32 mask = get_mask(offset); 108 u32 value; 109 int ret; 110 111 ret = regmap_read(pctl->stmfx->map, reg, &value); 112 113 return ret ? ret : !!(value & mask); 114 } 115 116 static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 117 { 118 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 119 u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR; 120 u32 mask = get_mask(offset); 121 122 regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset), 123 mask, mask); 124 } 125 126 static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 127 { 128 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 129 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 130 u32 mask = get_mask(offset); 131 u32 val; 132 int ret; 133 134 ret = regmap_read(pctl->stmfx->map, reg, &val); 135 /* 136 * On stmfx, gpio pins direction is (0)input, (1)output. 137 */ 138 if (ret) 139 return ret; 140 141 if (val & mask) 142 return GPIO_LINE_DIRECTION_OUT; 143 144 return GPIO_LINE_DIRECTION_IN; 145 } 146 147 static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 148 { 149 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 150 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 151 u32 mask = get_mask(offset); 152 153 return regmap_write_bits(pctl->stmfx->map, reg, mask, 0); 154 } 155 156 static int stmfx_gpio_direction_output(struct gpio_chip *gc, 157 unsigned int offset, int value) 158 { 159 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 160 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 161 u32 mask = get_mask(offset); 162 163 stmfx_gpio_set(gc, offset, value); 164 165 return regmap_write_bits(pctl->stmfx->map, reg, mask, mask); 166 } 167 168 static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl, 169 unsigned int offset) 170 { 171 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); 172 u32 pupd, mask = get_mask(offset); 173 int ret; 174 175 ret = regmap_read(pctl->stmfx->map, reg, &pupd); 176 if (ret) 177 return ret; 178 179 return !!(pupd & mask); 180 } 181 182 static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl, 183 unsigned int offset, u32 pupd) 184 { 185 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); 186 u32 mask = get_mask(offset); 187 188 return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0); 189 } 190 191 static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl, 192 unsigned int offset) 193 { 194 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); 195 u32 type, mask = get_mask(offset); 196 int ret; 197 198 ret = regmap_read(pctl->stmfx->map, reg, &type); 199 if (ret) 200 return ret; 201 202 return !!(type & mask); 203 } 204 205 static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl, 206 unsigned int offset, u32 type) 207 { 208 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); 209 u32 mask = get_mask(offset); 210 211 return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0); 212 } 213 214 static int stmfx_pinconf_get(struct pinctrl_dev *pctldev, 215 unsigned int pin, unsigned long *config) 216 { 217 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 218 u32 param = pinconf_to_config_param(*config); 219 struct pinctrl_gpio_range *range; 220 u32 arg = 0; 221 int ret, dir, type, pupd; 222 223 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 224 if (!range) 225 return -EINVAL; 226 227 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin); 228 if (dir < 0) 229 return dir; 230 231 /* 232 * Currently the gpiolib IN is 1 and OUT is 0 but let's not count 233 * on it just to be on the safe side also in the future :) 234 */ 235 dir = (dir == GPIO_LINE_DIRECTION_IN) ? 1 : 0; 236 237 type = stmfx_pinconf_get_type(pctl, pin); 238 if (type < 0) 239 return type; 240 pupd = stmfx_pinconf_get_pupd(pctl, pin); 241 if (pupd < 0) 242 return pupd; 243 244 switch (param) { 245 case PIN_CONFIG_BIAS_DISABLE: 246 if ((!dir && (!type || !pupd)) || (dir && !type)) 247 arg = 1; 248 break; 249 case PIN_CONFIG_BIAS_PULL_DOWN: 250 if (dir && type && !pupd) 251 arg = 1; 252 break; 253 case PIN_CONFIG_BIAS_PULL_UP: 254 if (type && pupd) 255 arg = 1; 256 break; 257 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 258 if ((!dir && type) || (dir && !type)) 259 arg = 1; 260 break; 261 case PIN_CONFIG_DRIVE_PUSH_PULL: 262 if ((!dir && !type) || (dir && type)) 263 arg = 1; 264 break; 265 case PIN_CONFIG_OUTPUT: 266 if (dir) 267 return -EINVAL; 268 269 ret = stmfx_gpio_get(&pctl->gpio_chip, pin); 270 if (ret < 0) 271 return ret; 272 273 arg = ret; 274 break; 275 default: 276 return -ENOTSUPP; 277 } 278 279 *config = pinconf_to_config_packed(param, arg); 280 281 return 0; 282 } 283 284 static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 285 unsigned long *configs, unsigned int num_configs) 286 { 287 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 288 struct pinctrl_gpio_range *range; 289 enum pin_config_param param; 290 u32 arg; 291 int i, ret; 292 293 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 294 if (!range) { 295 dev_err(pctldev->dev, "pin %d is not available\n", pin); 296 return -EINVAL; 297 } 298 299 for (i = 0; i < num_configs; i++) { 300 param = pinconf_to_config_param(configs[i]); 301 arg = pinconf_to_config_argument(configs[i]); 302 303 switch (param) { 304 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 305 case PIN_CONFIG_BIAS_DISABLE: 306 case PIN_CONFIG_DRIVE_PUSH_PULL: 307 ret = stmfx_pinconf_set_type(pctl, pin, 0); 308 if (ret) 309 return ret; 310 break; 311 case PIN_CONFIG_BIAS_PULL_DOWN: 312 ret = stmfx_pinconf_set_type(pctl, pin, 1); 313 if (ret) 314 return ret; 315 ret = stmfx_pinconf_set_pupd(pctl, pin, 0); 316 if (ret) 317 return ret; 318 break; 319 case PIN_CONFIG_BIAS_PULL_UP: 320 ret = stmfx_pinconf_set_type(pctl, pin, 1); 321 if (ret) 322 return ret; 323 ret = stmfx_pinconf_set_pupd(pctl, pin, 1); 324 if (ret) 325 return ret; 326 break; 327 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 328 ret = stmfx_pinconf_set_type(pctl, pin, 1); 329 if (ret) 330 return ret; 331 break; 332 case PIN_CONFIG_OUTPUT: 333 ret = stmfx_gpio_direction_output(&pctl->gpio_chip, 334 pin, arg); 335 if (ret) 336 return ret; 337 break; 338 default: 339 return -ENOTSUPP; 340 } 341 } 342 343 return 0; 344 } 345 346 static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 347 struct seq_file *s, unsigned int offset) 348 { 349 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 350 struct pinctrl_gpio_range *range; 351 int dir, type, pupd, val; 352 353 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset); 354 if (!range) 355 return; 356 357 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset); 358 if (dir < 0) 359 return; 360 type = stmfx_pinconf_get_type(pctl, offset); 361 if (type < 0) 362 return; 363 pupd = stmfx_pinconf_get_pupd(pctl, offset); 364 if (pupd < 0) 365 return; 366 val = stmfx_gpio_get(&pctl->gpio_chip, offset); 367 if (val < 0) 368 return; 369 370 if (dir == GPIO_LINE_DIRECTION_OUT) { 371 seq_printf(s, "output %s ", val ? "high" : "low"); 372 if (type) 373 seq_printf(s, "open drain %s internal pull-up ", 374 pupd ? "with" : "without"); 375 else 376 seq_puts(s, "push pull no pull "); 377 } else { 378 seq_printf(s, "input %s ", val ? "high" : "low"); 379 if (type) 380 seq_printf(s, "with internal pull-%s ", 381 pupd ? "up" : "down"); 382 else 383 seq_printf(s, "%s ", pupd ? "floating" : "analog"); 384 } 385 } 386 387 static const struct pinconf_ops stmfx_pinconf_ops = { 388 .pin_config_get = stmfx_pinconf_get, 389 .pin_config_set = stmfx_pinconf_set, 390 .pin_config_dbg_show = stmfx_pinconf_dbg_show, 391 }; 392 393 static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 394 { 395 return 0; 396 } 397 398 static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 399 unsigned int selector) 400 { 401 return NULL; 402 } 403 404 static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 405 unsigned int selector, 406 const unsigned int **pins, 407 unsigned int *num_pins) 408 { 409 return -ENOTSUPP; 410 } 411 412 static const struct pinctrl_ops stmfx_pinctrl_ops = { 413 .get_groups_count = stmfx_pinctrl_get_groups_count, 414 .get_group_name = stmfx_pinctrl_get_group_name, 415 .get_group_pins = stmfx_pinctrl_get_group_pins, 416 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 417 .dt_free_map = pinctrl_utils_free_map, 418 }; 419 420 static void stmfx_pinctrl_irq_mask(struct irq_data *data) 421 { 422 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 423 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 424 u32 reg = get_reg(data->hwirq); 425 u32 mask = get_mask(data->hwirq); 426 427 pctl->irq_gpi_src[reg] &= ~mask; 428 } 429 430 static void stmfx_pinctrl_irq_unmask(struct irq_data *data) 431 { 432 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 433 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 434 u32 reg = get_reg(data->hwirq); 435 u32 mask = get_mask(data->hwirq); 436 437 pctl->irq_gpi_src[reg] |= mask; 438 } 439 440 static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type) 441 { 442 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 443 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 444 u32 reg = get_reg(data->hwirq); 445 u32 mask = get_mask(data->hwirq); 446 447 if (type == IRQ_TYPE_NONE) 448 return -EINVAL; 449 450 if (type & IRQ_TYPE_EDGE_BOTH) { 451 pctl->irq_gpi_evt[reg] |= mask; 452 irq_set_handler_locked(data, handle_edge_irq); 453 } else { 454 pctl->irq_gpi_evt[reg] &= ~mask; 455 irq_set_handler_locked(data, handle_level_irq); 456 } 457 458 if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH)) 459 pctl->irq_gpi_type[reg] |= mask; 460 else 461 pctl->irq_gpi_type[reg] &= ~mask; 462 463 /* 464 * In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current 465 * GPIO value to set the right edge trigger. But in atomic context 466 * here we can't access registers over I2C. That's why (type & 467 * IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock. 468 */ 469 470 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 471 pctl->irq_toggle_edge[reg] |= mask; 472 else 473 pctl->irq_toggle_edge[reg] &= mask; 474 475 return 0; 476 } 477 478 static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data) 479 { 480 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 481 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 482 483 mutex_lock(&pctl->lock); 484 } 485 486 static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data) 487 { 488 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 489 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 490 u32 reg = get_reg(data->hwirq); 491 u32 mask = get_mask(data->hwirq); 492 493 /* 494 * In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value 495 * (this couldn't be done in .irq_set_type because of atomic context) 496 * to set the right irq trigger type. 497 */ 498 if (pctl->irq_toggle_edge[reg] & mask) { 499 if (stmfx_gpio_get(gpio_chip, data->hwirq)) 500 pctl->irq_gpi_type[reg] &= ~mask; 501 else 502 pctl->irq_gpi_type[reg] |= mask; 503 } 504 505 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT, 506 pctl->irq_gpi_evt, NR_GPIO_REGS); 507 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE, 508 pctl->irq_gpi_type, NR_GPIO_REGS); 509 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 510 pctl->irq_gpi_src, NR_GPIO_REGS); 511 512 mutex_unlock(&pctl->lock); 513 } 514 515 static int stmfx_gpio_irq_request_resources(struct irq_data *data) 516 { 517 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 518 int ret; 519 520 ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq); 521 if (ret) 522 return ret; 523 524 return gpiochip_reqres_irq(gpio_chip, data->hwirq); 525 } 526 527 static void stmfx_gpio_irq_release_resources(struct irq_data *data) 528 { 529 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 530 531 return gpiochip_relres_irq(gpio_chip, data->hwirq); 532 } 533 534 static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl, 535 unsigned int offset) 536 { 537 u32 reg = get_reg(offset); 538 u32 mask = get_mask(offset); 539 int val; 540 541 if (!(pctl->irq_toggle_edge[reg] & mask)) 542 return; 543 544 val = stmfx_gpio_get(&pctl->gpio_chip, offset); 545 if (val < 0) 546 return; 547 548 if (val) { 549 pctl->irq_gpi_type[reg] &= mask; 550 regmap_write_bits(pctl->stmfx->map, 551 STMFX_REG_IRQ_GPI_TYPE + reg, 552 mask, 0); 553 554 } else { 555 pctl->irq_gpi_type[reg] |= mask; 556 regmap_write_bits(pctl->stmfx->map, 557 STMFX_REG_IRQ_GPI_TYPE + reg, 558 mask, mask); 559 } 560 } 561 562 static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id) 563 { 564 struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id; 565 struct gpio_chip *gc = &pctl->gpio_chip; 566 u8 pending[NR_GPIO_REGS]; 567 u8 src[NR_GPIO_REGS] = {0, 0, 0}; 568 unsigned long n, status; 569 int i, ret; 570 571 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING, 572 &pending, NR_GPIO_REGS); 573 if (ret) 574 return IRQ_NONE; 575 576 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 577 src, NR_GPIO_REGS); 578 579 BUILD_BUG_ON(NR_GPIO_REGS > sizeof(status)); 580 for (i = 0, status = 0; i < NR_GPIO_REGS; i++) 581 status |= (unsigned long)pending[i] << (i * 8); 582 for_each_set_bit(n, &status, gc->ngpio) { 583 handle_nested_irq(irq_find_mapping(gc->irq.domain, n)); 584 stmfx_pinctrl_irq_toggle_trigger(pctl, n); 585 } 586 587 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 588 pctl->irq_gpi_src, NR_GPIO_REGS); 589 590 return IRQ_HANDLED; 591 } 592 593 static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl) 594 { 595 struct pinctrl_gpio_range *gpio_range; 596 struct pinctrl_dev *pctl_dev = pctl->pctl_dev; 597 u32 func = STMFX_FUNC_GPIO; 598 599 pctl->gpio_valid_mask = GENMASK(15, 0); 600 601 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16); 602 if (gpio_range) { 603 func |= STMFX_FUNC_ALTGPIO_LOW; 604 pctl->gpio_valid_mask |= GENMASK(19, 16); 605 } 606 607 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20); 608 if (gpio_range) { 609 func |= STMFX_FUNC_ALTGPIO_HIGH; 610 pctl->gpio_valid_mask |= GENMASK(23, 20); 611 } 612 613 return stmfx_function_enable(pctl->stmfx, func); 614 } 615 616 static int stmfx_pinctrl_probe(struct platform_device *pdev) 617 { 618 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); 619 struct device_node *np = pdev->dev.of_node; 620 struct stmfx_pinctrl *pctl; 621 struct gpio_irq_chip *girq; 622 int irq, ret; 623 624 pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL); 625 if (!pctl) 626 return -ENOMEM; 627 628 platform_set_drvdata(pdev, pctl); 629 630 pctl->dev = &pdev->dev; 631 pctl->stmfx = stmfx; 632 633 if (!of_find_property(np, "gpio-ranges", NULL)) { 634 dev_err(pctl->dev, "missing required gpio-ranges property\n"); 635 return -EINVAL; 636 } 637 638 irq = platform_get_irq(pdev, 0); 639 if (irq <= 0) 640 return -ENXIO; 641 642 mutex_init(&pctl->lock); 643 644 /* Register pin controller */ 645 pctl->pctl_desc.name = "stmfx-pinctrl"; 646 pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops; 647 pctl->pctl_desc.confops = &stmfx_pinconf_ops; 648 pctl->pctl_desc.pins = stmfx_pins; 649 pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins); 650 pctl->pctl_desc.owner = THIS_MODULE; 651 pctl->pctl_desc.link_consumers = true; 652 653 ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc, 654 pctl, &pctl->pctl_dev); 655 if (ret) { 656 dev_err(pctl->dev, "pinctrl registration failed\n"); 657 return ret; 658 } 659 660 ret = pinctrl_enable(pctl->pctl_dev); 661 if (ret) { 662 dev_err(pctl->dev, "pinctrl enable failed\n"); 663 return ret; 664 } 665 666 /* Register gpio controller */ 667 pctl->gpio_chip.label = "stmfx-gpio"; 668 pctl->gpio_chip.parent = pctl->dev; 669 pctl->gpio_chip.get_direction = stmfx_gpio_get_direction; 670 pctl->gpio_chip.direction_input = stmfx_gpio_direction_input; 671 pctl->gpio_chip.direction_output = stmfx_gpio_direction_output; 672 pctl->gpio_chip.get = stmfx_gpio_get; 673 pctl->gpio_chip.set = stmfx_gpio_set; 674 pctl->gpio_chip.set_config = gpiochip_generic_config; 675 pctl->gpio_chip.base = -1; 676 pctl->gpio_chip.ngpio = pctl->pctl_desc.npins; 677 pctl->gpio_chip.can_sleep = true; 678 679 pctl->irq_chip.name = dev_name(pctl->dev); 680 pctl->irq_chip.irq_mask = stmfx_pinctrl_irq_mask; 681 pctl->irq_chip.irq_unmask = stmfx_pinctrl_irq_unmask; 682 pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type; 683 pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock; 684 pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock; 685 pctl->irq_chip.irq_request_resources = stmfx_gpio_irq_request_resources; 686 pctl->irq_chip.irq_release_resources = stmfx_gpio_irq_release_resources; 687 688 girq = &pctl->gpio_chip.irq; 689 girq->chip = &pctl->irq_chip; 690 /* This will let us handle the parent IRQ in the driver */ 691 girq->parent_handler = NULL; 692 girq->num_parents = 0; 693 girq->parents = NULL; 694 girq->default_type = IRQ_TYPE_NONE; 695 girq->handler = handle_bad_irq; 696 girq->threaded = true; 697 698 ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl); 699 if (ret) { 700 dev_err(pctl->dev, "gpio_chip registration failed\n"); 701 return ret; 702 } 703 704 ret = stmfx_pinctrl_gpio_function_enable(pctl); 705 if (ret) 706 return ret; 707 708 ret = devm_request_threaded_irq(pctl->dev, irq, NULL, 709 stmfx_pinctrl_irq_thread_fn, 710 IRQF_ONESHOT, 711 pctl->irq_chip.name, pctl); 712 if (ret) { 713 dev_err(pctl->dev, "cannot request irq%d\n", irq); 714 return ret; 715 } 716 717 dev_info(pctl->dev, 718 "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask)); 719 720 return 0; 721 } 722 723 static int stmfx_pinctrl_remove(struct platform_device *pdev) 724 { 725 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); 726 727 return stmfx_function_disable(stmfx, 728 STMFX_FUNC_GPIO | 729 STMFX_FUNC_ALTGPIO_LOW | 730 STMFX_FUNC_ALTGPIO_HIGH); 731 } 732 733 #ifdef CONFIG_PM_SLEEP 734 static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl) 735 { 736 int ret; 737 738 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE, 739 &pctl->bkp_gpio_state, NR_GPIO_REGS); 740 if (ret) 741 return ret; 742 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR, 743 &pctl->bkp_gpio_dir, NR_GPIO_REGS); 744 if (ret) 745 return ret; 746 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE, 747 &pctl->bkp_gpio_type, NR_GPIO_REGS); 748 if (ret) 749 return ret; 750 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD, 751 &pctl->bkp_gpio_pupd, NR_GPIO_REGS); 752 if (ret) 753 return ret; 754 755 return 0; 756 } 757 758 static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl) 759 { 760 int ret; 761 762 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR, 763 pctl->bkp_gpio_dir, NR_GPIO_REGS); 764 if (ret) 765 return ret; 766 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE, 767 pctl->bkp_gpio_type, NR_GPIO_REGS); 768 if (ret) 769 return ret; 770 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD, 771 pctl->bkp_gpio_pupd, NR_GPIO_REGS); 772 if (ret) 773 return ret; 774 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET, 775 pctl->bkp_gpio_state, NR_GPIO_REGS); 776 if (ret) 777 return ret; 778 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT, 779 pctl->irq_gpi_evt, NR_GPIO_REGS); 780 if (ret) 781 return ret; 782 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE, 783 pctl->irq_gpi_type, NR_GPIO_REGS); 784 if (ret) 785 return ret; 786 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 787 pctl->irq_gpi_src, NR_GPIO_REGS); 788 if (ret) 789 return ret; 790 791 return 0; 792 } 793 794 static int stmfx_pinctrl_suspend(struct device *dev) 795 { 796 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev); 797 int ret; 798 799 ret = stmfx_pinctrl_backup_regs(pctl); 800 if (ret) { 801 dev_err(pctl->dev, "registers backup failure\n"); 802 return ret; 803 } 804 805 return 0; 806 } 807 808 static int stmfx_pinctrl_resume(struct device *dev) 809 { 810 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev); 811 int ret; 812 813 ret = stmfx_pinctrl_restore_regs(pctl); 814 if (ret) { 815 dev_err(pctl->dev, "registers restoration failure\n"); 816 return ret; 817 } 818 819 return 0; 820 } 821 #endif 822 823 static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops, 824 stmfx_pinctrl_suspend, stmfx_pinctrl_resume); 825 826 static const struct of_device_id stmfx_pinctrl_of_match[] = { 827 { .compatible = "st,stmfx-0300-pinctrl", }, 828 {}, 829 }; 830 MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match); 831 832 static struct platform_driver stmfx_pinctrl_driver = { 833 .driver = { 834 .name = "stmfx-pinctrl", 835 .of_match_table = stmfx_pinctrl_of_match, 836 .pm = &stmfx_pinctrl_dev_pm_ops, 837 }, 838 .probe = stmfx_pinctrl_probe, 839 .remove = stmfx_pinctrl_remove, 840 }; 841 module_platform_driver(stmfx_pinctrl_driver); 842 843 MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver"); 844 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); 845 MODULE_LICENSE("GPL v2"); 846