1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 STMicroelectronics (R&D) Limited. 4 * Authors: 5 * Srinivas Kandagatla <srinivas.kandagatla@st.com> 6 */ 7 8 #include <linux/err.h> 9 #include <linux/gpio/driver.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 #include <linux/platform_device.h> 18 #include <linux/regmap.h> 19 #include <linux/seq_file.h> 20 #include <linux/slab.h> 21 #include <linux/string_helpers.h> 22 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 28 #include "core.h" 29 30 /* PIO Block registers */ 31 /* PIO output */ 32 #define REG_PIO_POUT 0x00 33 /* Set bits of POUT */ 34 #define REG_PIO_SET_POUT 0x04 35 /* Clear bits of POUT */ 36 #define REG_PIO_CLR_POUT 0x08 37 /* PIO input */ 38 #define REG_PIO_PIN 0x10 39 /* PIO configuration */ 40 #define REG_PIO_PC(n) (0x20 + (n) * 0x10) 41 /* Set bits of PC[2:0] */ 42 #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10) 43 /* Clear bits of PC[2:0] */ 44 #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10) 45 /* PIO input comparison */ 46 #define REG_PIO_PCOMP 0x50 47 /* Set bits of PCOMP */ 48 #define REG_PIO_SET_PCOMP 0x54 49 /* Clear bits of PCOMP */ 50 #define REG_PIO_CLR_PCOMP 0x58 51 /* PIO input comparison mask */ 52 #define REG_PIO_PMASK 0x60 53 /* Set bits of PMASK */ 54 #define REG_PIO_SET_PMASK 0x64 55 /* Clear bits of PMASK */ 56 #define REG_PIO_CLR_PMASK 0x68 57 58 #define ST_GPIO_DIRECTION_BIDIR 0x1 59 #define ST_GPIO_DIRECTION_OUT 0x2 60 #define ST_GPIO_DIRECTION_IN 0x4 61 62 /* 63 * Packed style retime configuration. 64 * There are two registers cfg0 and cfg1 in this style for each bank. 65 * Each field in this register is 8 bit corresponding to 8 pins in the bank. 66 */ 67 #define RT_P_CFGS_PER_BANK 2 68 #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7) 69 #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23) 70 #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31) 71 #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7) 72 #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15) 73 #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) 74 #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) 75 76 /* 77 * Dedicated style retime Configuration register 78 * each register is dedicated per pin. 79 */ 80 #define RT_D_CFGS_PER_BANK 8 81 #define RT_D_CFG_CLK_SHIFT 0 82 #define RT_D_CFG_CLK_MASK (0x3 << 0) 83 #define RT_D_CFG_CLKNOTDATA_SHIFT 2 84 #define RT_D_CFG_CLKNOTDATA_MASK BIT(2) 85 #define RT_D_CFG_DELAY_SHIFT 3 86 #define RT_D_CFG_DELAY_MASK (0xf << 3) 87 #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7 88 #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7) 89 #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8 90 #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8) 91 #define RT_D_CFG_INVERTCLK_SHIFT 9 92 #define RT_D_CFG_INVERTCLK_MASK BIT(9) 93 #define RT_D_CFG_RETIME_SHIFT 10 94 #define RT_D_CFG_RETIME_MASK BIT(10) 95 96 /* 97 * Pinconf is represented in an opaque unsigned long variable. 98 * Below is the bit allocation details for each possible configuration. 99 * All the bit fields can be encapsulated into four variables 100 * (direction, retime-type, retime-clk, retime-delay) 101 * 102 * +----------------+ 103 *[31:28]| reserved-3 | 104 * +----------------+------------- 105 *[27] | oe | | 106 * +----------------+ v 107 *[26] | pu | [Direction ] 108 * +----------------+ ^ 109 *[25] | od | | 110 * +----------------+------------- 111 *[24] | reserved-2 | 112 * +----------------+------------- 113 *[23] | retime | | 114 * +----------------+ | 115 *[22] | retime-invclk | | 116 * +----------------+ v 117 *[21] |retime-clknotdat| [Retime-type ] 118 * +----------------+ ^ 119 *[20] | retime-de | | 120 * +----------------+------------- 121 *[19:18]| retime-clk |------>[Retime-Clk ] 122 * +----------------+ 123 *[17:16]| reserved-1 | 124 * +----------------+ 125 *[15..0]| retime-delay |------>[Retime Delay] 126 * +----------------+ 127 */ 128 129 #define ST_PINCONF_UNPACK(conf, param)\ 130 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \ 131 & ST_PINCONF_ ##param ##_MASK) 132 133 #define ST_PINCONF_PACK(conf, val, param) (conf |=\ 134 ((val & ST_PINCONF_ ##param ##_MASK) << \ 135 ST_PINCONF_ ##param ##_SHIFT)) 136 137 /* Output enable */ 138 #define ST_PINCONF_OE_MASK 0x1 139 #define ST_PINCONF_OE_SHIFT 27 140 #define ST_PINCONF_OE BIT(27) 141 #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE) 142 #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE) 143 144 /* Pull Up */ 145 #define ST_PINCONF_PU_MASK 0x1 146 #define ST_PINCONF_PU_SHIFT 26 147 #define ST_PINCONF_PU BIT(26) 148 #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU) 149 #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU) 150 151 /* Open Drain */ 152 #define ST_PINCONF_OD_MASK 0x1 153 #define ST_PINCONF_OD_SHIFT 25 154 #define ST_PINCONF_OD BIT(25) 155 #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD) 156 #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD) 157 158 #define ST_PINCONF_RT_MASK 0x1 159 #define ST_PINCONF_RT_SHIFT 23 160 #define ST_PINCONF_RT BIT(23) 161 #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT) 162 #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT) 163 164 #define ST_PINCONF_RT_INVERTCLK_MASK 0x1 165 #define ST_PINCONF_RT_INVERTCLK_SHIFT 22 166 #define ST_PINCONF_RT_INVERTCLK BIT(22) 167 #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \ 168 ST_PINCONF_UNPACK(conf, RT_INVERTCLK) 169 #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \ 170 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK) 171 172 #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1 173 #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21 174 #define ST_PINCONF_RT_CLKNOTDATA BIT(21) 175 #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \ 176 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA) 177 #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \ 178 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA) 179 180 #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1 181 #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20 182 #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20) 183 #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \ 184 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE) 185 #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \ 186 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE) 187 188 #define ST_PINCONF_RT_CLK_MASK 0x3 189 #define ST_PINCONF_RT_CLK_SHIFT 18 190 #define ST_PINCONF_RT_CLK BIT(18) 191 #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK) 192 #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK) 193 194 /* RETIME_DELAY in Pico Secs */ 195 #define ST_PINCONF_RT_DELAY_MASK 0xffff 196 #define ST_PINCONF_RT_DELAY_SHIFT 0 197 #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY) 198 #define ST_PINCONF_PACK_RT_DELAY(conf, val) \ 199 ST_PINCONF_PACK(conf, val, RT_DELAY) 200 201 #define ST_GPIO_PINS_PER_BANK (8) 202 #define OF_GPIO_ARGS_MIN (4) 203 #define OF_RT_ARGS_MIN (2) 204 205 #define gpio_range_to_bank(chip) \ 206 container_of(chip, struct st_gpio_bank, range) 207 208 #define pc_to_bank(pc) \ 209 container_of(pc, struct st_gpio_bank, pc) 210 211 enum st_retime_style { 212 st_retime_style_none, 213 st_retime_style_packed, 214 st_retime_style_dedicated, 215 }; 216 217 struct st_retime_dedicated { 218 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK]; 219 }; 220 221 struct st_retime_packed { 222 struct regmap_field *clk1notclk0; 223 struct regmap_field *delay_0; 224 struct regmap_field *delay_1; 225 struct regmap_field *invertclk; 226 struct regmap_field *retime; 227 struct regmap_field *clknotdata; 228 struct regmap_field *double_edge; 229 }; 230 231 struct st_pio_control { 232 u32 rt_pin_mask; 233 struct regmap_field *alt, *oe, *pu, *od; 234 /* retiming */ 235 union { 236 struct st_retime_packed rt_p; 237 struct st_retime_dedicated rt_d; 238 } rt; 239 }; 240 241 struct st_pctl_data { 242 const enum st_retime_style rt_style; 243 const unsigned int *input_delays; 244 const int ninput_delays; 245 const unsigned int *output_delays; 246 const int noutput_delays; 247 /* register offset information */ 248 const int alt, oe, pu, od, rt; 249 }; 250 251 struct st_pinconf { 252 int pin; 253 const char *name; 254 unsigned long config; 255 int altfunc; 256 }; 257 258 struct st_pmx_func { 259 const char *name; 260 const char **groups; 261 unsigned ngroups; 262 }; 263 264 struct st_pctl_group { 265 const char *name; 266 unsigned int *pins; 267 unsigned npins; 268 struct st_pinconf *pin_conf; 269 }; 270 271 /* 272 * Edge triggers are not supported at hardware level, it is supported by 273 * software by exploiting the level trigger support in hardware. 274 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration 275 * of each gpio pin in a GPIO bank. 276 * 277 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of 278 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank. 279 * 280 * bit allocation per pin is: 281 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31] 282 * -------------------------------------------------------- 283 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 | 284 * -------------------------------------------------------- 285 * 286 * A pin can have one of following the values in its edge configuration field. 287 * 288 * ------- ---------------------------- 289 * [0-3] - Description 290 * ------- ---------------------------- 291 * 0000 - No edge IRQ. 292 * 0001 - Falling edge IRQ. 293 * 0010 - Rising edge IRQ. 294 * 0011 - Rising and Falling edge IRQ. 295 * ------- ---------------------------- 296 */ 297 298 #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4 299 #define ST_IRQ_EDGE_MASK 0xf 300 #define ST_IRQ_EDGE_FALLING BIT(0) 301 #define ST_IRQ_EDGE_RISING BIT(1) 302 #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) 303 304 #define ST_IRQ_RISING_EDGE_CONF(pin) \ 305 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 306 307 #define ST_IRQ_FALLING_EDGE_CONF(pin) \ 308 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 309 310 #define ST_IRQ_BOTH_EDGE_CONF(pin) \ 311 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 312 313 #define ST_IRQ_EDGE_CONF(conf, pin) \ 314 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK) 315 316 struct st_gpio_bank { 317 struct gpio_chip gpio_chip; 318 struct pinctrl_gpio_range range; 319 void __iomem *base; 320 struct st_pio_control pc; 321 unsigned long irq_edge_conf; 322 spinlock_t lock; 323 }; 324 325 struct st_pinctrl { 326 struct device *dev; 327 struct pinctrl_dev *pctl; 328 struct st_gpio_bank *banks; 329 int nbanks; 330 struct st_pmx_func *functions; 331 int nfunctions; 332 struct st_pctl_group *groups; 333 int ngroups; 334 struct regmap *regmap; 335 const struct st_pctl_data *data; 336 void __iomem *irqmux_base; 337 }; 338 339 /* SOC specific data */ 340 341 static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250, 342 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; 343 344 static const struct st_pctl_data stih407_data = { 345 .rt_style = st_retime_style_dedicated, 346 .input_delays = stih407_delays, 347 .ninput_delays = ARRAY_SIZE(stih407_delays), 348 .output_delays = stih407_delays, 349 .noutput_delays = ARRAY_SIZE(stih407_delays), 350 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, 351 }; 352 353 static const struct st_pctl_data stih407_flashdata = { 354 .rt_style = st_retime_style_none, 355 .input_delays = stih407_delays, 356 .ninput_delays = ARRAY_SIZE(stih407_delays), 357 .output_delays = stih407_delays, 358 .noutput_delays = ARRAY_SIZE(stih407_delays), 359 .alt = 0, 360 .oe = -1, /* Not Available */ 361 .pu = -1, /* Not Available */ 362 .od = 60, 363 .rt = 100, 364 }; 365 366 static struct st_pio_control *st_get_pio_control( 367 struct pinctrl_dev *pctldev, int pin) 368 { 369 struct pinctrl_gpio_range *range = 370 pinctrl_find_gpio_range_from_pin(pctldev, pin); 371 struct st_gpio_bank *bank = gpio_range_to_bank(range); 372 373 return &bank->pc; 374 } 375 376 /* Low level functions.. */ 377 static inline int st_gpio_pin(int gpio) 378 { 379 return gpio%ST_GPIO_PINS_PER_BANK; 380 } 381 382 static void st_pinconf_set_config(struct st_pio_control *pc, 383 int pin, unsigned long config) 384 { 385 struct regmap_field *output_enable = pc->oe; 386 struct regmap_field *pull_up = pc->pu; 387 struct regmap_field *open_drain = pc->od; 388 unsigned int oe_value, pu_value, od_value; 389 unsigned long mask = BIT(pin); 390 391 if (output_enable) { 392 regmap_field_read(output_enable, &oe_value); 393 oe_value &= ~mask; 394 if (config & ST_PINCONF_OE) 395 oe_value |= mask; 396 regmap_field_write(output_enable, oe_value); 397 } 398 399 if (pull_up) { 400 regmap_field_read(pull_up, &pu_value); 401 pu_value &= ~mask; 402 if (config & ST_PINCONF_PU) 403 pu_value |= mask; 404 regmap_field_write(pull_up, pu_value); 405 } 406 407 if (open_drain) { 408 regmap_field_read(open_drain, &od_value); 409 od_value &= ~mask; 410 if (config & ST_PINCONF_OD) 411 od_value |= mask; 412 regmap_field_write(open_drain, od_value); 413 } 414 } 415 416 static void st_pctl_set_function(struct st_pio_control *pc, 417 int pin_id, int function) 418 { 419 struct regmap_field *alt = pc->alt; 420 unsigned int val; 421 int pin = st_gpio_pin(pin_id); 422 int offset = pin * 4; 423 424 if (!alt) 425 return; 426 427 regmap_field_read(alt, &val); 428 val &= ~(0xf << offset); 429 val |= function << offset; 430 regmap_field_write(alt, val); 431 } 432 433 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin) 434 { 435 struct regmap_field *alt = pc->alt; 436 unsigned int val; 437 int offset = pin * 4; 438 439 if (!alt) 440 return 0; 441 442 regmap_field_read(alt, &val); 443 444 return (val >> offset) & 0xf; 445 } 446 447 static unsigned long st_pinconf_delay_to_bit(unsigned int delay, 448 const struct st_pctl_data *data, unsigned long config) 449 { 450 const unsigned int *delay_times; 451 int num_delay_times, i, closest_index = -1; 452 unsigned int closest_divergence = UINT_MAX; 453 454 if (ST_PINCONF_UNPACK_OE(config)) { 455 delay_times = data->output_delays; 456 num_delay_times = data->noutput_delays; 457 } else { 458 delay_times = data->input_delays; 459 num_delay_times = data->ninput_delays; 460 } 461 462 for (i = 0; i < num_delay_times; i++) { 463 unsigned int divergence = abs(delay - delay_times[i]); 464 465 if (divergence == 0) 466 return i; 467 468 if (divergence < closest_divergence) { 469 closest_divergence = divergence; 470 closest_index = i; 471 } 472 } 473 474 pr_warn("Attempt to set delay %d, closest available %d\n", 475 delay, delay_times[closest_index]); 476 477 return closest_index; 478 } 479 480 static unsigned long st_pinconf_bit_to_delay(unsigned int index, 481 const struct st_pctl_data *data, unsigned long output) 482 { 483 const unsigned int *delay_times; 484 int num_delay_times; 485 486 if (output) { 487 delay_times = data->output_delays; 488 num_delay_times = data->noutput_delays; 489 } else { 490 delay_times = data->input_delays; 491 num_delay_times = data->ninput_delays; 492 } 493 494 if (index < num_delay_times) { 495 return delay_times[index]; 496 } else { 497 pr_warn("Delay not found in/out delay list\n"); 498 return 0; 499 } 500 } 501 502 static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field, 503 int enable, int pin) 504 { 505 unsigned int val = 0; 506 507 regmap_field_read(field, &val); 508 if (enable) 509 val |= BIT(pin); 510 else 511 val &= ~BIT(pin); 512 regmap_field_write(field, val); 513 } 514 515 static void st_pinconf_set_retime_packed(struct st_pinctrl *info, 516 struct st_pio_control *pc, unsigned long config, int pin) 517 { 518 const struct st_pctl_data *data = info->data; 519 struct st_retime_packed *rt_p = &pc->rt.rt_p; 520 unsigned int delay; 521 522 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, 523 ST_PINCONF_UNPACK_RT_CLK(config), pin); 524 525 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, 526 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); 527 528 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, 529 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); 530 531 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, 532 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); 533 534 st_regmap_field_bit_set_clear_pin(rt_p->retime, 535 ST_PINCONF_UNPACK_RT(config), pin); 536 537 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config), 538 data, config); 539 /* 2 bit delay, lsb */ 540 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); 541 /* 2 bit delay, msb */ 542 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); 543 } 544 545 static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info, 546 struct st_pio_control *pc, unsigned long config, int pin) 547 { 548 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1; 549 int clk = ST_PINCONF_UNPACK_RT_CLK(config); 550 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config); 551 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config); 552 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config); 553 int retime = ST_PINCONF_UNPACK_RT(config); 554 555 unsigned long delay = st_pinconf_delay_to_bit( 556 ST_PINCONF_UNPACK_RT_DELAY(config), 557 info->data, config); 558 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 559 560 unsigned long retime_config = 561 ((clk) << RT_D_CFG_CLK_SHIFT) | 562 ((delay) << RT_D_CFG_DELAY_SHIFT) | 563 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) | 564 ((retime) << RT_D_CFG_RETIME_SHIFT) | 565 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) | 566 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) | 567 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT); 568 569 regmap_field_write(rt_d->rt[pin], retime_config); 570 } 571 572 static void st_pinconf_get_direction(struct st_pio_control *pc, 573 int pin, unsigned long *config) 574 { 575 unsigned int oe_value, pu_value, od_value; 576 577 if (pc->oe) { 578 regmap_field_read(pc->oe, &oe_value); 579 if (oe_value & BIT(pin)) 580 ST_PINCONF_PACK_OE(*config); 581 } 582 583 if (pc->pu) { 584 regmap_field_read(pc->pu, &pu_value); 585 if (pu_value & BIT(pin)) 586 ST_PINCONF_PACK_PU(*config); 587 } 588 589 if (pc->od) { 590 regmap_field_read(pc->od, &od_value); 591 if (od_value & BIT(pin)) 592 ST_PINCONF_PACK_OD(*config); 593 } 594 } 595 596 static int st_pinconf_get_retime_packed(struct st_pinctrl *info, 597 struct st_pio_control *pc, int pin, unsigned long *config) 598 { 599 const struct st_pctl_data *data = info->data; 600 struct st_retime_packed *rt_p = &pc->rt.rt_p; 601 unsigned int delay_bits, delay, delay0, delay1, val; 602 int output = ST_PINCONF_UNPACK_OE(*config); 603 604 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) 605 ST_PINCONF_PACK_RT(*config); 606 607 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) 608 ST_PINCONF_PACK_RT_CLK(*config, 1); 609 610 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) 611 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 612 613 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) 614 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 615 616 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) 617 ST_PINCONF_PACK_RT_INVERTCLK(*config); 618 619 regmap_field_read(rt_p->delay_0, &delay0); 620 regmap_field_read(rt_p->delay_1, &delay1); 621 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | 622 (((delay0 & BIT(pin)) ? 1 : 0)); 623 delay = st_pinconf_bit_to_delay(delay_bits, data, output); 624 ST_PINCONF_PACK_RT_DELAY(*config, delay); 625 626 return 0; 627 } 628 629 static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info, 630 struct st_pio_control *pc, int pin, unsigned long *config) 631 { 632 unsigned int value; 633 unsigned long delay_bits, delay, rt_clk; 634 int output = ST_PINCONF_UNPACK_OE(*config); 635 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 636 637 regmap_field_read(rt_d->rt[pin], &value); 638 639 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT; 640 ST_PINCONF_PACK_RT_CLK(*config, rt_clk); 641 642 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT; 643 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); 644 ST_PINCONF_PACK_RT_DELAY(*config, delay); 645 646 if (value & RT_D_CFG_CLKNOTDATA_MASK) 647 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 648 649 if (value & RT_D_CFG_DOUBLE_EDGE_MASK) 650 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 651 652 if (value & RT_D_CFG_INVERTCLK_MASK) 653 ST_PINCONF_PACK_RT_INVERTCLK(*config); 654 655 if (value & RT_D_CFG_RETIME_MASK) 656 ST_PINCONF_PACK_RT(*config); 657 658 return 0; 659 } 660 661 /* GPIO related functions */ 662 663 static inline void __st_gpio_set(struct st_gpio_bank *bank, 664 unsigned offset, int value) 665 { 666 if (value) 667 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); 668 else 669 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); 670 } 671 672 static void st_gpio_direction(struct st_gpio_bank *bank, 673 unsigned int gpio, unsigned int direction) 674 { 675 int offset = st_gpio_pin(gpio); 676 int i = 0; 677 /** 678 * There are three configuration registers (PIOn_PC0, PIOn_PC1 679 * and PIOn_PC2) for each port. These are used to configure the 680 * PIO port pins. Each pin can be configured as an input, output, 681 * bidirectional, or alternative function pin. Three bits, one bit 682 * from each of the three registers, configure the corresponding bit of 683 * the port. Valid bit settings is: 684 * 685 * PC2 PC1 PC0 Direction. 686 * 0 0 0 [Input Weak pull-up] 687 * 0 0 or 1 1 [Bidirection] 688 * 0 1 0 [Output] 689 * 1 0 0 [Input] 690 * 691 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits 692 * individually. 693 */ 694 for (i = 0; i <= 2; i++) { 695 if (direction & BIT(i)) 696 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); 697 else 698 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); 699 } 700 } 701 702 static int st_gpio_get(struct gpio_chip *chip, unsigned offset) 703 { 704 struct st_gpio_bank *bank = gpiochip_get_data(chip); 705 706 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); 707 } 708 709 static int st_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 710 { 711 struct st_gpio_bank *bank = gpiochip_get_data(chip); 712 __st_gpio_set(bank, offset, value); 713 714 return 0; 715 } 716 717 static int st_gpio_direction_output(struct gpio_chip *chip, 718 unsigned offset, int value) 719 { 720 struct st_gpio_bank *bank = gpiochip_get_data(chip); 721 722 __st_gpio_set(bank, offset, value); 723 724 return pinctrl_gpio_direction_output(chip, offset); 725 } 726 727 static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 728 { 729 struct st_gpio_bank *bank = gpiochip_get_data(chip); 730 struct st_pio_control pc = bank->pc; 731 unsigned long config; 732 unsigned int direction = 0; 733 unsigned int function; 734 unsigned int value; 735 int i = 0; 736 737 /* Alternate function direction is handled by Pinctrl */ 738 function = st_pctl_get_pin_function(&pc, offset); 739 if (function) { 740 st_pinconf_get_direction(&pc, offset, &config); 741 if (ST_PINCONF_UNPACK_OE(config)) 742 return GPIO_LINE_DIRECTION_OUT; 743 744 return GPIO_LINE_DIRECTION_IN; 745 } 746 747 /* 748 * GPIO direction is handled differently 749 * - See st_gpio_direction() above for an explanation 750 */ 751 for (i = 0; i <= 2; i++) { 752 value = readl(bank->base + REG_PIO_PC(i)); 753 direction |= ((value >> offset) & 0x1) << i; 754 } 755 756 if (direction == ST_GPIO_DIRECTION_IN) 757 return GPIO_LINE_DIRECTION_IN; 758 759 return GPIO_LINE_DIRECTION_OUT; 760 } 761 762 /* Pinctrl Groups */ 763 static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev) 764 { 765 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 766 767 return info->ngroups; 768 } 769 770 static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev, 771 unsigned selector) 772 { 773 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 774 775 return info->groups[selector].name; 776 } 777 778 static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev, 779 unsigned selector, const unsigned **pins, unsigned *npins) 780 { 781 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 782 783 if (selector >= info->ngroups) 784 return -EINVAL; 785 786 *pins = info->groups[selector].pins; 787 *npins = info->groups[selector].npins; 788 789 return 0; 790 } 791 792 static inline const struct st_pctl_group *st_pctl_find_group_by_name( 793 const struct st_pinctrl *info, const char *name) 794 { 795 int i; 796 797 for (i = 0; i < info->ngroups; i++) { 798 if (!strcmp(info->groups[i].name, name)) 799 return &info->groups[i]; 800 } 801 802 return NULL; 803 } 804 805 static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 806 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps) 807 { 808 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 809 const struct st_pctl_group *grp; 810 struct device *dev = info->dev; 811 struct pinctrl_map *new_map; 812 struct device_node *parent; 813 int map_num, i; 814 815 grp = st_pctl_find_group_by_name(info, np->name); 816 if (!grp) { 817 dev_err(dev, "unable to find group for node %pOFn\n", np); 818 return -EINVAL; 819 } 820 821 map_num = grp->npins + 1; 822 new_map = devm_kcalloc(dev, map_num, sizeof(*new_map), GFP_KERNEL); 823 if (!new_map) 824 return -ENOMEM; 825 826 parent = of_get_parent(np); 827 if (!parent) { 828 devm_kfree(dev, new_map); 829 return -EINVAL; 830 } 831 832 *map = new_map; 833 *num_maps = map_num; 834 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 835 new_map[0].data.mux.function = parent->name; 836 new_map[0].data.mux.group = np->name; 837 of_node_put(parent); 838 839 /* create config map per pin */ 840 new_map++; 841 for (i = 0; i < grp->npins; i++) { 842 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 843 new_map[i].data.configs.group_or_pin = 844 pin_get_name(pctldev, grp->pins[i]); 845 new_map[i].data.configs.configs = &grp->pin_conf[i].config; 846 new_map[i].data.configs.num_configs = 1; 847 } 848 dev_info(dev, "maps: function %s group %s num %d\n", 849 (*map)->data.mux.function, grp->name, map_num); 850 851 return 0; 852 } 853 854 static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev, 855 struct pinctrl_map *map, unsigned num_maps) 856 { 857 } 858 859 static const struct pinctrl_ops st_pctlops = { 860 .get_groups_count = st_pctl_get_groups_count, 861 .get_group_pins = st_pctl_get_group_pins, 862 .get_group_name = st_pctl_get_group_name, 863 .dt_node_to_map = st_pctl_dt_node_to_map, 864 .dt_free_map = st_pctl_dt_free_map, 865 }; 866 867 /* Pinmux */ 868 static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 869 { 870 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 871 872 return info->nfunctions; 873 } 874 875 static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev, 876 unsigned selector) 877 { 878 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 879 880 return info->functions[selector].name; 881 } 882 883 static int st_pmx_get_groups(struct pinctrl_dev *pctldev, 884 unsigned selector, const char * const **grps, unsigned * const ngrps) 885 { 886 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 887 *grps = info->functions[selector].groups; 888 *ngrps = info->functions[selector].ngroups; 889 890 return 0; 891 } 892 893 static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, 894 unsigned group) 895 { 896 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 897 struct st_pinconf *conf = info->groups[group].pin_conf; 898 struct st_pio_control *pc; 899 int i; 900 901 for (i = 0; i < info->groups[group].npins; i++) { 902 pc = st_get_pio_control(pctldev, conf[i].pin); 903 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); 904 } 905 906 return 0; 907 } 908 909 static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, 910 struct pinctrl_gpio_range *range, unsigned gpio, 911 bool input) 912 { 913 struct st_gpio_bank *bank = gpio_range_to_bank(range); 914 /* 915 * When a PIO bank is used in its primary function mode (altfunc = 0) 916 * Output Enable (OE), Open Drain(OD), and Pull Up (PU) 917 * for the primary PIO functions are driven by the related PIO block 918 */ 919 st_pctl_set_function(&bank->pc, gpio, 0); 920 st_gpio_direction(bank, gpio, input ? 921 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT); 922 923 return 0; 924 } 925 926 static const struct pinmux_ops st_pmxops = { 927 .get_functions_count = st_pmx_get_funcs_count, 928 .get_function_name = st_pmx_get_fname, 929 .get_function_groups = st_pmx_get_groups, 930 .set_mux = st_pmx_set_mux, 931 .gpio_set_direction = st_pmx_set_gpio_direction, 932 .strict = true, 933 }; 934 935 /* Pinconf */ 936 static void st_pinconf_get_retime(struct st_pinctrl *info, 937 struct st_pio_control *pc, int pin, unsigned long *config) 938 { 939 if (info->data->rt_style == st_retime_style_packed) 940 st_pinconf_get_retime_packed(info, pc, pin, config); 941 else if (info->data->rt_style == st_retime_style_dedicated) 942 if ((BIT(pin) & pc->rt_pin_mask)) 943 st_pinconf_get_retime_dedicated(info, pc, 944 pin, config); 945 } 946 947 static void st_pinconf_set_retime(struct st_pinctrl *info, 948 struct st_pio_control *pc, int pin, unsigned long config) 949 { 950 if (info->data->rt_style == st_retime_style_packed) 951 st_pinconf_set_retime_packed(info, pc, config, pin); 952 else if (info->data->rt_style == st_retime_style_dedicated) 953 if ((BIT(pin) & pc->rt_pin_mask)) 954 st_pinconf_set_retime_dedicated(info, pc, 955 config, pin); 956 } 957 958 static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id, 959 unsigned long *configs, unsigned num_configs) 960 { 961 int pin = st_gpio_pin(pin_id); 962 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 963 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 964 int i; 965 966 for (i = 0; i < num_configs; i++) { 967 st_pinconf_set_config(pc, pin, configs[i]); 968 st_pinconf_set_retime(info, pc, pin, configs[i]); 969 } /* for each config */ 970 971 return 0; 972 } 973 974 static int st_pinconf_get(struct pinctrl_dev *pctldev, 975 unsigned pin_id, unsigned long *config) 976 { 977 int pin = st_gpio_pin(pin_id); 978 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 979 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 980 981 *config = 0; 982 st_pinconf_get_direction(pc, pin, config); 983 st_pinconf_get_retime(info, pc, pin, config); 984 985 return 0; 986 } 987 988 static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, 989 struct seq_file *s, unsigned pin_id) 990 __must_hold(&pctldev->mutex) 991 { 992 struct st_pio_control *pc; 993 unsigned long config; 994 unsigned int function; 995 int offset = st_gpio_pin(pin_id); 996 char f[16]; 997 int oe; 998 999 mutex_unlock(&pctldev->mutex); 1000 pc = st_get_pio_control(pctldev, pin_id); 1001 st_pinconf_get(pctldev, pin_id, &config); 1002 mutex_lock(&pctldev->mutex); 1003 1004 function = st_pctl_get_pin_function(pc, offset); 1005 if (function) 1006 snprintf(f, 10, "Alt Fn %u", function); 1007 else 1008 snprintf(f, 5, "GPIO"); 1009 1010 oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset); 1011 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n" 1012 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," 1013 "de:%ld,rt-clk:%ld,rt-delay:%ld]", 1014 (oe == GPIO_LINE_DIRECTION_OUT), 1015 ST_PINCONF_UNPACK_PU(config), 1016 ST_PINCONF_UNPACK_OD(config), 1017 f, 1018 ST_PINCONF_UNPACK_RT(config), 1019 ST_PINCONF_UNPACK_RT_INVERTCLK(config), 1020 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), 1021 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), 1022 ST_PINCONF_UNPACK_RT_CLK(config), 1023 ST_PINCONF_UNPACK_RT_DELAY(config)); 1024 } 1025 1026 static const struct pinconf_ops st_confops = { 1027 .pin_config_get = st_pinconf_get, 1028 .pin_config_set = st_pinconf_set, 1029 .pin_config_dbg_show = st_pinconf_dbg_show, 1030 }; 1031 1032 static void st_pctl_dt_child_count(struct st_pinctrl *info, 1033 struct device_node *np) 1034 { 1035 struct device_node *child; 1036 for_each_child_of_node(np, child) { 1037 if (of_property_read_bool(child, "gpio-controller")) { 1038 info->nbanks++; 1039 } else { 1040 info->nfunctions++; 1041 info->ngroups += of_get_child_count(child); 1042 } 1043 } 1044 } 1045 1046 static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info, 1047 int bank, struct st_pio_control *pc) 1048 { 1049 struct device *dev = info->dev; 1050 struct regmap *rm = info->regmap; 1051 const struct st_pctl_data *data = info->data; 1052 /* 2 registers per bank */ 1053 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; 1054 struct st_retime_packed *rt_p = &pc->rt.rt_p; 1055 /* cfg0 */ 1056 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg); 1057 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg); 1058 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg); 1059 /* cfg1 */ 1060 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4); 1061 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4); 1062 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4); 1063 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4); 1064 1065 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); 1066 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); 1067 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); 1068 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); 1069 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); 1070 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); 1071 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); 1072 1073 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || 1074 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || 1075 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || 1076 IS_ERR(rt_p->double_edge)) 1077 return -EINVAL; 1078 1079 return 0; 1080 } 1081 1082 static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info, 1083 int bank, struct st_pio_control *pc) 1084 { 1085 struct device *dev = info->dev; 1086 struct regmap *rm = info->regmap; 1087 const struct st_pctl_data *data = info->data; 1088 /* 8 registers per bank */ 1089 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; 1090 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 1091 unsigned int j; 1092 u32 pin_mask = pc->rt_pin_mask; 1093 1094 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) { 1095 if (BIT(j) & pin_mask) { 1096 struct reg_field reg = REG_FIELD(reg_offset, 0, 31); 1097 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); 1098 if (IS_ERR(rt_d->rt[j])) 1099 return -EINVAL; 1100 reg_offset += 4; 1101 } 1102 } 1103 return 0; 1104 } 1105 1106 static int st_pctl_dt_setup_retime(struct st_pinctrl *info, 1107 int bank, struct st_pio_control *pc) 1108 { 1109 const struct st_pctl_data *data = info->data; 1110 if (data->rt_style == st_retime_style_packed) 1111 return st_pctl_dt_setup_retime_packed(info, bank, pc); 1112 else if (data->rt_style == st_retime_style_dedicated) 1113 return st_pctl_dt_setup_retime_dedicated(info, bank, pc); 1114 1115 return -EINVAL; 1116 } 1117 1118 1119 static struct regmap_field *st_pc_get_value(struct device *dev, 1120 struct regmap *regmap, int bank, 1121 int data, int lsb, int msb) 1122 { 1123 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); 1124 1125 if (data < 0) 1126 return NULL; 1127 1128 return devm_regmap_field_alloc(dev, regmap, reg); 1129 } 1130 1131 static void st_parse_syscfgs(struct st_pinctrl *info, int bank, 1132 struct device_node *np) 1133 { 1134 const struct st_pctl_data *data = info->data; 1135 /** 1136 * For a given shared register like OE/PU/OD, there are 8 bits per bank 1137 * 0:7 belongs to bank0, 8:15 belongs to bank1 ... 1138 * So each register is shared across 4 banks. 1139 */ 1140 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; 1141 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; 1142 struct st_pio_control *pc = &info->banks[bank].pc; 1143 struct device *dev = info->dev; 1144 struct regmap *regmap = info->regmap; 1145 1146 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); 1147 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); 1148 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); 1149 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); 1150 1151 /* retime avaiable for all pins by default */ 1152 pc->rt_pin_mask = 0xff; 1153 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); 1154 st_pctl_dt_setup_retime(info, bank, pc); 1155 1156 return; 1157 } 1158 1159 static int st_pctl_dt_calculate_pin(struct st_pinctrl *info, 1160 phandle bank, unsigned int offset) 1161 { 1162 struct device_node *np; 1163 struct gpio_chip *chip; 1164 int retval = -EINVAL; 1165 int i; 1166 1167 np = of_find_node_by_phandle(bank); 1168 if (!np) 1169 return -EINVAL; 1170 1171 for (i = 0; i < info->nbanks; i++) { 1172 chip = &info->banks[i].gpio_chip; 1173 if (chip->fwnode == of_fwnode_handle(np)) { 1174 if (offset < chip->ngpio) 1175 retval = chip->base + offset; 1176 break; 1177 } 1178 } 1179 1180 of_node_put(np); 1181 return retval; 1182 } 1183 1184 /* 1185 * Each pin is represented in of the below forms. 1186 * <bank offset mux direction rt_type rt_delay rt_clk> 1187 */ 1188 static int st_pctl_dt_parse_groups(struct device_node *np, 1189 struct st_pctl_group *grp, struct st_pinctrl *info, int idx) 1190 { 1191 /* bank pad direction val altfunction */ 1192 const __be32 *list; 1193 struct property *pp; 1194 struct device *dev = info->dev; 1195 struct st_pinconf *conf; 1196 struct device_node *pins __free(device_node) = NULL; 1197 phandle bank; 1198 unsigned int offset; 1199 int i = 0, npins = 0, nr_props; 1200 1201 pins = of_get_child_by_name(np, "st,pins"); 1202 if (!pins) 1203 return -ENODATA; 1204 1205 for_each_property_of_node(pins, pp) { 1206 /* Skip those we do not want to proceed */ 1207 if (!strcmp(pp->name, "name")) 1208 continue; 1209 1210 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) { 1211 npins++; 1212 } else { 1213 pr_warn("Invalid st,pins in %pOFn node\n", np); 1214 return -EINVAL; 1215 } 1216 } 1217 1218 grp->npins = npins; 1219 grp->name = np->name; 1220 grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL); 1221 grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL); 1222 1223 if (!grp->pins || !grp->pin_conf) 1224 return -ENOMEM; 1225 1226 /* <bank offset mux direction rt_type rt_delay rt_clk> */ 1227 for_each_property_of_node(pins, pp) { 1228 if (!strcmp(pp->name, "name")) 1229 continue; 1230 nr_props = pp->length/sizeof(u32); 1231 list = pp->value; 1232 conf = &grp->pin_conf[i]; 1233 1234 /* bank & offset */ 1235 bank = be32_to_cpup(list++); 1236 offset = be32_to_cpup(list++); 1237 conf->pin = st_pctl_dt_calculate_pin(info, bank, offset); 1238 conf->name = pp->name; 1239 grp->pins[i] = conf->pin; 1240 /* mux */ 1241 conf->altfunc = be32_to_cpup(list++); 1242 conf->config = 0; 1243 /* direction */ 1244 conf->config |= be32_to_cpup(list++); 1245 /* rt_type rt_delay rt_clk */ 1246 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) { 1247 /* rt_type */ 1248 conf->config |= be32_to_cpup(list++); 1249 /* rt_delay */ 1250 conf->config |= be32_to_cpup(list++); 1251 /* rt_clk */ 1252 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) 1253 conf->config |= be32_to_cpup(list++); 1254 } 1255 i++; 1256 } 1257 1258 return 0; 1259 } 1260 1261 static int st_pctl_parse_functions(struct device_node *np, 1262 struct st_pinctrl *info, u32 index, int *grp_index) 1263 { 1264 struct device *dev = info->dev; 1265 struct st_pmx_func *func; 1266 struct st_pctl_group *grp; 1267 int ret, i; 1268 1269 func = &info->functions[index]; 1270 func->name = np->name; 1271 func->ngroups = of_get_child_count(np); 1272 if (func->ngroups == 0) 1273 return dev_err_probe(dev, -EINVAL, "No groups defined\n"); 1274 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 1275 if (!func->groups) 1276 return -ENOMEM; 1277 1278 i = 0; 1279 for_each_child_of_node_scoped(np, child) { 1280 func->groups[i] = child->name; 1281 grp = &info->groups[*grp_index]; 1282 *grp_index += 1; 1283 ret = st_pctl_dt_parse_groups(child, grp, info, i++); 1284 if (ret) 1285 return ret; 1286 } 1287 dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); 1288 1289 return 0; 1290 } 1291 1292 static void st_gpio_irq_mask(struct irq_data *d) 1293 { 1294 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1295 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1296 1297 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK); 1298 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 1299 } 1300 1301 static void st_gpio_irq_unmask(struct irq_data *d) 1302 { 1303 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1304 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1305 1306 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 1307 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK); 1308 } 1309 1310 static int st_gpio_irq_request_resources(struct irq_data *d) 1311 { 1312 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1313 1314 pinctrl_gpio_direction_input(gc, d->hwirq); 1315 1316 return gpiochip_reqres_irq(gc, d->hwirq); 1317 } 1318 1319 static void st_gpio_irq_release_resources(struct irq_data *d) 1320 { 1321 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1322 1323 gpiochip_relres_irq(gc, d->hwirq); 1324 } 1325 1326 static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) 1327 { 1328 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1329 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1330 unsigned long flags; 1331 int comp, pin = d->hwirq; 1332 u32 val; 1333 u32 pin_edge_conf = 0; 1334 1335 switch (type) { 1336 case IRQ_TYPE_LEVEL_HIGH: 1337 comp = 0; 1338 break; 1339 case IRQ_TYPE_EDGE_FALLING: 1340 comp = 0; 1341 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); 1342 break; 1343 case IRQ_TYPE_LEVEL_LOW: 1344 comp = 1; 1345 break; 1346 case IRQ_TYPE_EDGE_RISING: 1347 comp = 1; 1348 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); 1349 break; 1350 case IRQ_TYPE_EDGE_BOTH: 1351 comp = st_gpio_get(&bank->gpio_chip, pin); 1352 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); 1353 break; 1354 default: 1355 return -EINVAL; 1356 } 1357 1358 spin_lock_irqsave(&bank->lock, flags); 1359 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( 1360 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); 1361 bank->irq_edge_conf |= pin_edge_conf; 1362 spin_unlock_irqrestore(&bank->lock, flags); 1363 1364 val = readl(bank->base + REG_PIO_PCOMP); 1365 val &= ~BIT(pin); 1366 val |= (comp << pin); 1367 writel(val, bank->base + REG_PIO_PCOMP); 1368 1369 return 0; 1370 } 1371 1372 /* 1373 * As edge triggers are not supported at hardware level, it is supported by 1374 * software by exploiting the level trigger support in hardware. 1375 * 1376 * Steps for detection raising edge interrupt in software. 1377 * 1378 * Step 1: CONFIGURE pin to detect level LOW interrupts. 1379 * 1380 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler, 1381 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt. 1382 * IGNORE calling the actual interrupt handler for the pin at this stage. 1383 * 1384 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler 1385 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then 1386 * DISPATCH the interrupt to the interrupt handler of the pin. 1387 * 1388 * step-1 ________ __________ 1389 * | | step - 3 1390 * | | 1391 * step -2 |_____| 1392 * 1393 * falling edge is also detected int the same way. 1394 * 1395 */ 1396 static void __gpio_irq_handler(struct st_gpio_bank *bank) 1397 { 1398 unsigned long port_in, port_mask, port_comp, active_irqs; 1399 unsigned long bank_edge_mask, flags; 1400 int n, val, ecfg; 1401 1402 spin_lock_irqsave(&bank->lock, flags); 1403 bank_edge_mask = bank->irq_edge_conf; 1404 spin_unlock_irqrestore(&bank->lock, flags); 1405 1406 for (;;) { 1407 port_in = readl(bank->base + REG_PIO_PIN); 1408 port_comp = readl(bank->base + REG_PIO_PCOMP); 1409 port_mask = readl(bank->base + REG_PIO_PMASK); 1410 1411 active_irqs = (port_in ^ port_comp) & port_mask; 1412 1413 if (active_irqs == 0) 1414 break; 1415 1416 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { 1417 /* check if we are detecting fake edges ... */ 1418 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n); 1419 1420 if (ecfg) { 1421 /* edge detection. */ 1422 val = st_gpio_get(&bank->gpio_chip, n); 1423 1424 writel(BIT(n), 1425 val ? bank->base + REG_PIO_SET_PCOMP : 1426 bank->base + REG_PIO_CLR_PCOMP); 1427 1428 if (ecfg != ST_IRQ_EDGE_BOTH && 1429 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) 1430 continue; 1431 } 1432 1433 generic_handle_domain_irq(bank->gpio_chip.irq.domain, n); 1434 } 1435 } 1436 } 1437 1438 static void st_gpio_irq_handler(struct irq_desc *desc) 1439 { 1440 /* interrupt dedicated per bank */ 1441 struct irq_chip *chip = irq_desc_get_chip(desc); 1442 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1443 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1444 1445 chained_irq_enter(chip, desc); 1446 __gpio_irq_handler(bank); 1447 chained_irq_exit(chip, desc); 1448 } 1449 1450 static void st_gpio_irqmux_handler(struct irq_desc *desc) 1451 { 1452 struct irq_chip *chip = irq_desc_get_chip(desc); 1453 struct st_pinctrl *info = irq_desc_get_handler_data(desc); 1454 unsigned long status; 1455 int n; 1456 1457 chained_irq_enter(chip, desc); 1458 1459 status = readl(info->irqmux_base); 1460 1461 for_each_set_bit(n, &status, info->nbanks) 1462 __gpio_irq_handler(&info->banks[n]); 1463 1464 chained_irq_exit(chip, desc); 1465 } 1466 1467 static const struct gpio_chip st_gpio_template = { 1468 .request = gpiochip_generic_request, 1469 .free = gpiochip_generic_free, 1470 .get = st_gpio_get, 1471 .set = st_gpio_set, 1472 .direction_input = pinctrl_gpio_direction_input, 1473 .direction_output = st_gpio_direction_output, 1474 .get_direction = st_gpio_get_direction, 1475 .ngpio = ST_GPIO_PINS_PER_BANK, 1476 }; 1477 1478 static const struct irq_chip st_gpio_irqchip = { 1479 .name = "GPIO", 1480 .irq_request_resources = st_gpio_irq_request_resources, 1481 .irq_release_resources = st_gpio_irq_release_resources, 1482 .irq_disable = st_gpio_irq_mask, 1483 .irq_mask = st_gpio_irq_mask, 1484 .irq_unmask = st_gpio_irq_unmask, 1485 .irq_set_type = st_gpio_irq_set_type, 1486 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 1487 }; 1488 1489 static int st_gpiolib_register_bank(struct st_pinctrl *info, 1490 int bank_nr, struct device_node *np) 1491 { 1492 struct st_gpio_bank *bank = &info->banks[bank_nr]; 1493 struct pinctrl_gpio_range *range = &bank->range; 1494 struct device *dev = info->dev; 1495 int bank_num = of_alias_get_id(np, "gpio"); 1496 struct resource res, irq_res; 1497 int err; 1498 1499 if (of_address_to_resource(np, 0, &res)) 1500 return -ENODEV; 1501 1502 bank->base = devm_ioremap_resource(dev, &res); 1503 if (IS_ERR(bank->base)) 1504 return PTR_ERR(bank->base); 1505 1506 bank->gpio_chip = st_gpio_template; 1507 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; 1508 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; 1509 bank->gpio_chip.fwnode = of_fwnode_handle(np); 1510 bank->gpio_chip.parent = dev; 1511 spin_lock_init(&bank->lock); 1512 1513 of_property_read_string(np, "st,bank-name", &range->name); 1514 bank->gpio_chip.label = range->name; 1515 1516 range->id = bank_num; 1517 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; 1518 range->npins = bank->gpio_chip.ngpio; 1519 range->gc = &bank->gpio_chip; 1520 1521 /** 1522 * GPIO bank can have one of the two possible types of 1523 * interrupt-wirings. 1524 * 1525 * First type is via irqmux, single interrupt is used by multiple 1526 * gpio banks. This reduces number of overall interrupts numbers 1527 * required. All these banks belong to a single pincontroller. 1528 * _________ 1529 * | |----> [gpio-bank (n) ] 1530 * | |----> [gpio-bank (n + 1)] 1531 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] 1532 * | |----> [gpio-bank (... )] 1533 * |_________|----> [gpio-bank (n + 7)] 1534 * 1535 * Second type has a dedicated interrupt per each gpio bank. 1536 * 1537 * [irqN]----> [gpio-bank (n)] 1538 */ 1539 1540 if (of_irq_to_resource(np, 0, &irq_res) > 0) { 1541 struct gpio_irq_chip *girq; 1542 int gpio_irq = irq_res.start; 1543 1544 /* This is not a valid IRQ */ 1545 if (gpio_irq <= 0) { 1546 dev_err(dev, "invalid IRQ for %pOF bank\n", np); 1547 goto skip_irq; 1548 } 1549 /* We need to have a mux as well */ 1550 if (!info->irqmux_base) { 1551 dev_err(dev, "no irqmux for %pOF bank\n", np); 1552 goto skip_irq; 1553 } 1554 1555 girq = &bank->gpio_chip.irq; 1556 gpio_irq_chip_set_chip(girq, &st_gpio_irqchip); 1557 girq->parent_handler = st_gpio_irq_handler; 1558 girq->num_parents = 1; 1559 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 1560 GFP_KERNEL); 1561 if (!girq->parents) 1562 return -ENOMEM; 1563 girq->parents[0] = gpio_irq; 1564 girq->default_type = IRQ_TYPE_NONE; 1565 girq->handler = handle_simple_irq; 1566 } 1567 1568 skip_irq: 1569 err = gpiochip_add_data(&bank->gpio_chip, bank); 1570 if (err) 1571 return dev_err_probe(dev, err, "Failed to add gpiochip(%d)!\n", bank_num); 1572 dev_info(dev, "%s bank added.\n", range->name); 1573 1574 return 0; 1575 } 1576 1577 static const struct of_device_id st_pctl_of_match[] = { 1578 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data}, 1579 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data}, 1580 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data}, 1581 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata}, 1582 { /* sentinel */ } 1583 }; 1584 1585 static int st_pctl_probe_dt(struct platform_device *pdev, 1586 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) 1587 { 1588 struct device *dev = &pdev->dev; 1589 int ret = 0; 1590 int i = 0, j = 0, k = 0, bank; 1591 struct pinctrl_pin_desc *pdesc; 1592 struct device_node *np = dev->of_node; 1593 int grp_index = 0; 1594 int irq = 0; 1595 1596 st_pctl_dt_child_count(info, np); 1597 if (!info->nbanks) 1598 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); 1599 1600 dev_info(dev, "nbanks = %d\n", info->nbanks); 1601 dev_info(dev, "nfunctions = %d\n", info->nfunctions); 1602 dev_info(dev, "ngroups = %d\n", info->ngroups); 1603 1604 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 1605 1606 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 1607 1608 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); 1609 1610 if (!info->functions || !info->groups || !info->banks) 1611 return -ENOMEM; 1612 1613 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1614 if (IS_ERR(info->regmap)) 1615 return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n"); 1616 info->data = of_match_node(st_pctl_of_match, np)->data; 1617 1618 irq = platform_get_irq(pdev, 0); 1619 1620 if (irq > 0) { 1621 info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux"); 1622 if (IS_ERR(info->irqmux_base)) 1623 return PTR_ERR(info->irqmux_base); 1624 1625 irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler, 1626 info); 1627 } 1628 1629 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; 1630 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); 1631 if (!pdesc) 1632 return -ENOMEM; 1633 1634 pctl_desc->pins = pdesc; 1635 1636 bank = 0; 1637 for_each_child_of_node_scoped(np, child) { 1638 if (of_property_read_bool(child, "gpio-controller")) { 1639 const char *bank_name = NULL; 1640 char **pin_names; 1641 1642 ret = st_gpiolib_register_bank(info, bank, child); 1643 if (ret) 1644 return ret; 1645 1646 k = info->banks[bank].range.pin_base; 1647 bank_name = info->banks[bank].range.name; 1648 1649 pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK); 1650 if (IS_ERR(pin_names)) 1651 return PTR_ERR(pin_names); 1652 1653 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { 1654 pdesc->number = k; 1655 pdesc->name = pin_names[j]; 1656 pdesc++; 1657 } 1658 st_parse_syscfgs(info, bank, child); 1659 bank++; 1660 } else { 1661 ret = st_pctl_parse_functions(child, info, 1662 i++, &grp_index); 1663 if (ret) { 1664 dev_err(dev, "No functions found.\n"); 1665 return ret; 1666 } 1667 } 1668 } 1669 1670 return 0; 1671 } 1672 1673 static int st_pctl_probe(struct platform_device *pdev) 1674 { 1675 struct device *dev = &pdev->dev; 1676 struct st_pinctrl *info; 1677 struct pinctrl_desc *pctl_desc; 1678 int ret, i; 1679 1680 if (!dev->of_node) { 1681 dev_err(dev, "device node not found.\n"); 1682 return -EINVAL; 1683 } 1684 1685 pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); 1686 if (!pctl_desc) 1687 return -ENOMEM; 1688 1689 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1690 if (!info) 1691 return -ENOMEM; 1692 1693 info->dev = dev; 1694 platform_set_drvdata(pdev, info); 1695 ret = st_pctl_probe_dt(pdev, pctl_desc, info); 1696 if (ret) 1697 return ret; 1698 1699 pctl_desc->owner = THIS_MODULE; 1700 pctl_desc->pctlops = &st_pctlops; 1701 pctl_desc->pmxops = &st_pmxops; 1702 pctl_desc->confops = &st_confops; 1703 pctl_desc->name = dev_name(dev); 1704 1705 info->pctl = devm_pinctrl_register(dev, pctl_desc, info); 1706 if (IS_ERR(info->pctl)) 1707 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); 1708 1709 for (i = 0; i < info->nbanks; i++) 1710 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); 1711 1712 return 0; 1713 } 1714 1715 static struct platform_driver st_pctl_driver = { 1716 .driver = { 1717 .name = "st-pinctrl", 1718 .of_match_table = st_pctl_of_match, 1719 }, 1720 .probe = st_pctl_probe, 1721 }; 1722 1723 static int __init st_pctl_init(void) 1724 { 1725 return platform_driver_register(&st_pctl_driver); 1726 } 1727 arch_initcall(st_pctl_init); 1728