1 /* 2 * Generic device tree based pinctrl driver for one register per pin 3 * type pinmux controllers 4 * 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12 #include <linux/init.h> 13 #include <linux/module.h> 14 #include <linux/io.h> 15 #include <linux/slab.h> 16 #include <linux/err.h> 17 #include <linux/list.h> 18 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/of_address.h> 22 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 27 #include "core.h" 28 #include "pinconf.h" 29 30 #define DRIVER_NAME "pinctrl-single" 31 #define PCS_MUX_PINS_NAME "pinctrl-single,pins" 32 #define PCS_MUX_BITS_NAME "pinctrl-single,bits" 33 #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1) 34 #define PCS_OFF_DISABLED ~0U 35 36 /** 37 * struct pcs_pingroup - pingroups for a function 38 * @np: pingroup device node pointer 39 * @name: pingroup name 40 * @gpins: array of the pins in the group 41 * @ngpins: number of pins in the group 42 * @node: list node 43 */ 44 struct pcs_pingroup { 45 struct device_node *np; 46 const char *name; 47 int *gpins; 48 int ngpins; 49 struct list_head node; 50 }; 51 52 /** 53 * struct pcs_func_vals - mux function register offset and value pair 54 * @reg: register virtual address 55 * @val: register value 56 */ 57 struct pcs_func_vals { 58 void __iomem *reg; 59 unsigned val; 60 unsigned mask; 61 }; 62 63 /** 64 * struct pcs_conf_vals - pinconf parameter, pinconf register offset 65 * and value, enable, disable, mask 66 * @param: config parameter 67 * @val: user input bits in the pinconf register 68 * @enable: enable bits in the pinconf register 69 * @disable: disable bits in the pinconf register 70 * @mask: mask bits in the register value 71 */ 72 struct pcs_conf_vals { 73 enum pin_config_param param; 74 unsigned val; 75 unsigned enable; 76 unsigned disable; 77 unsigned mask; 78 }; 79 80 /** 81 * struct pcs_conf_type - pinconf property name, pinconf param pair 82 * @name: property name in DTS file 83 * @param: config parameter 84 */ 85 struct pcs_conf_type { 86 const char *name; 87 enum pin_config_param param; 88 }; 89 90 /** 91 * struct pcs_function - pinctrl function 92 * @name: pinctrl function name 93 * @vals: register and vals array 94 * @nvals: number of entries in vals array 95 * @pgnames: array of pingroup names the function uses 96 * @npgnames: number of pingroup names the function uses 97 * @node: list node 98 */ 99 struct pcs_function { 100 const char *name; 101 struct pcs_func_vals *vals; 102 unsigned nvals; 103 const char **pgnames; 104 int npgnames; 105 struct pcs_conf_vals *conf; 106 int nconfs; 107 struct list_head node; 108 }; 109 110 /** 111 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function 112 * @offset: offset base of pins 113 * @npins: number pins with the same mux value of gpio function 114 * @gpiofunc: mux value of gpio function 115 * @node: list node 116 */ 117 struct pcs_gpiofunc_range { 118 unsigned offset; 119 unsigned npins; 120 unsigned gpiofunc; 121 struct list_head node; 122 }; 123 124 /** 125 * struct pcs_data - wrapper for data needed by pinctrl framework 126 * @pa: pindesc array 127 * @cur: index to current element 128 * 129 * REVISIT: We should be able to drop this eventually by adding 130 * support for registering pins individually in the pinctrl 131 * framework for those drivers that don't need a static array. 132 */ 133 struct pcs_data { 134 struct pinctrl_pin_desc *pa; 135 int cur; 136 }; 137 138 /** 139 * struct pcs_name - register name for a pin 140 * @name: name of the pinctrl register 141 * 142 * REVISIT: We may want to make names optional in the pinctrl 143 * framework as some drivers may not care about pin names to 144 * avoid kernel bloat. The pin names can be deciphered by user 145 * space tools using debugfs based on the register address and 146 * SoC packaging information. 147 */ 148 struct pcs_name { 149 char name[PCS_REG_NAME_LEN]; 150 }; 151 152 /** 153 * struct pcs_device - pinctrl device instance 154 * @res: resources 155 * @base: virtual address of the controller 156 * @size: size of the ioremapped area 157 * @dev: device entry 158 * @pctl: pin controller device 159 * @mutex: mutex protecting the lists 160 * @width: bits per mux register 161 * @fmask: function register mask 162 * @fshift: function register shift 163 * @foff: value to turn mux off 164 * @fmax: max number of functions in fmask 165 * @is_pinconf: whether supports pinconf 166 * @names: array of register names for pins 167 * @pins: physical pins on the SoC 168 * @pgtree: pingroup index radix tree 169 * @ftree: function index radix tree 170 * @pingroups: list of pingroups 171 * @functions: list of functions 172 * @gpiofuncs: list of gpio functions 173 * @ngroups: number of pingroups 174 * @nfuncs: number of functions 175 * @desc: pin controller descriptor 176 * @read: register read function to use 177 * @write: register write function to use 178 */ 179 struct pcs_device { 180 struct resource *res; 181 void __iomem *base; 182 unsigned size; 183 struct device *dev; 184 struct pinctrl_dev *pctl; 185 struct mutex mutex; 186 unsigned width; 187 unsigned fmask; 188 unsigned fshift; 189 unsigned foff; 190 unsigned fmax; 191 bool bits_per_mux; 192 bool is_pinconf; 193 struct pcs_name *names; 194 struct pcs_data pins; 195 struct radix_tree_root pgtree; 196 struct radix_tree_root ftree; 197 struct list_head pingroups; 198 struct list_head functions; 199 struct list_head gpiofuncs; 200 unsigned ngroups; 201 unsigned nfuncs; 202 struct pinctrl_desc desc; 203 unsigned (*read)(void __iomem *reg); 204 void (*write)(unsigned val, void __iomem *reg); 205 }; 206 207 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, 208 unsigned long *config); 209 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, 210 unsigned long config); 211 212 static enum pin_config_param pcs_bias[] = { 213 PIN_CONFIG_BIAS_PULL_DOWN, 214 PIN_CONFIG_BIAS_PULL_UP, 215 }; 216 217 /* 218 * REVISIT: Reads and writes could eventually use regmap or something 219 * generic. But at least on omaps, some mux registers are performance 220 * critical as they may need to be remuxed every time before and after 221 * idle. Adding tests for register access width for every read and 222 * write like regmap is doing is not desired, and caching the registers 223 * does not help in this case. 224 */ 225 226 static unsigned __maybe_unused pcs_readb(void __iomem *reg) 227 { 228 return readb(reg); 229 } 230 231 static unsigned __maybe_unused pcs_readw(void __iomem *reg) 232 { 233 return readw(reg); 234 } 235 236 static unsigned __maybe_unused pcs_readl(void __iomem *reg) 237 { 238 return readl(reg); 239 } 240 241 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg) 242 { 243 writeb(val, reg); 244 } 245 246 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg) 247 { 248 writew(val, reg); 249 } 250 251 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg) 252 { 253 writel(val, reg); 254 } 255 256 static int pcs_get_groups_count(struct pinctrl_dev *pctldev) 257 { 258 struct pcs_device *pcs; 259 260 pcs = pinctrl_dev_get_drvdata(pctldev); 261 262 return pcs->ngroups; 263 } 264 265 static const char *pcs_get_group_name(struct pinctrl_dev *pctldev, 266 unsigned gselector) 267 { 268 struct pcs_device *pcs; 269 struct pcs_pingroup *group; 270 271 pcs = pinctrl_dev_get_drvdata(pctldev); 272 group = radix_tree_lookup(&pcs->pgtree, gselector); 273 if (!group) { 274 dev_err(pcs->dev, "%s could not find pingroup%i\n", 275 __func__, gselector); 276 return NULL; 277 } 278 279 return group->name; 280 } 281 282 static int pcs_get_group_pins(struct pinctrl_dev *pctldev, 283 unsigned gselector, 284 const unsigned **pins, 285 unsigned *npins) 286 { 287 struct pcs_device *pcs; 288 struct pcs_pingroup *group; 289 290 pcs = pinctrl_dev_get_drvdata(pctldev); 291 group = radix_tree_lookup(&pcs->pgtree, gselector); 292 if (!group) { 293 dev_err(pcs->dev, "%s could not find pingroup%i\n", 294 __func__, gselector); 295 return -EINVAL; 296 } 297 298 *pins = group->gpins; 299 *npins = group->ngpins; 300 301 return 0; 302 } 303 304 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, 305 struct seq_file *s, 306 unsigned pin) 307 { 308 struct pcs_device *pcs; 309 unsigned val, mux_bytes; 310 311 pcs = pinctrl_dev_get_drvdata(pctldev); 312 313 mux_bytes = pcs->width / BITS_PER_BYTE; 314 val = pcs->read(pcs->base + pin * mux_bytes); 315 316 seq_printf(s, "%08x %s " , val, DRIVER_NAME); 317 } 318 319 static void pcs_dt_free_map(struct pinctrl_dev *pctldev, 320 struct pinctrl_map *map, unsigned num_maps) 321 { 322 struct pcs_device *pcs; 323 324 pcs = pinctrl_dev_get_drvdata(pctldev); 325 devm_kfree(pcs->dev, map); 326 } 327 328 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, 329 struct device_node *np_config, 330 struct pinctrl_map **map, unsigned *num_maps); 331 332 static const struct pinctrl_ops pcs_pinctrl_ops = { 333 .get_groups_count = pcs_get_groups_count, 334 .get_group_name = pcs_get_group_name, 335 .get_group_pins = pcs_get_group_pins, 336 .pin_dbg_show = pcs_pin_dbg_show, 337 .dt_node_to_map = pcs_dt_node_to_map, 338 .dt_free_map = pcs_dt_free_map, 339 }; 340 341 static int pcs_get_functions_count(struct pinctrl_dev *pctldev) 342 { 343 struct pcs_device *pcs; 344 345 pcs = pinctrl_dev_get_drvdata(pctldev); 346 347 return pcs->nfuncs; 348 } 349 350 static const char *pcs_get_function_name(struct pinctrl_dev *pctldev, 351 unsigned fselector) 352 { 353 struct pcs_device *pcs; 354 struct pcs_function *func; 355 356 pcs = pinctrl_dev_get_drvdata(pctldev); 357 func = radix_tree_lookup(&pcs->ftree, fselector); 358 if (!func) { 359 dev_err(pcs->dev, "%s could not find function%i\n", 360 __func__, fselector); 361 return NULL; 362 } 363 364 return func->name; 365 } 366 367 static int pcs_get_function_groups(struct pinctrl_dev *pctldev, 368 unsigned fselector, 369 const char * const **groups, 370 unsigned * const ngroups) 371 { 372 struct pcs_device *pcs; 373 struct pcs_function *func; 374 375 pcs = pinctrl_dev_get_drvdata(pctldev); 376 func = radix_tree_lookup(&pcs->ftree, fselector); 377 if (!func) { 378 dev_err(pcs->dev, "%s could not find function%i\n", 379 __func__, fselector); 380 return -EINVAL; 381 } 382 *groups = func->pgnames; 383 *ngroups = func->npgnames; 384 385 return 0; 386 } 387 388 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin, 389 struct pcs_function **func) 390 { 391 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); 392 struct pin_desc *pdesc = pin_desc_get(pctldev, pin); 393 const struct pinctrl_setting_mux *setting; 394 unsigned fselector; 395 396 /* If pin is not described in DTS & enabled, mux_setting is NULL. */ 397 setting = pdesc->mux_setting; 398 if (!setting) 399 return -ENOTSUPP; 400 fselector = setting->func; 401 *func = radix_tree_lookup(&pcs->ftree, fselector); 402 if (!(*func)) { 403 dev_err(pcs->dev, "%s could not find function%i\n", 404 __func__, fselector); 405 return -ENOTSUPP; 406 } 407 return 0; 408 } 409 410 static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, 411 unsigned group) 412 { 413 struct pcs_device *pcs; 414 struct pcs_function *func; 415 int i; 416 417 pcs = pinctrl_dev_get_drvdata(pctldev); 418 /* If function mask is null, needn't enable it. */ 419 if (!pcs->fmask) 420 return 0; 421 func = radix_tree_lookup(&pcs->ftree, fselector); 422 if (!func) 423 return -EINVAL; 424 425 dev_dbg(pcs->dev, "enabling %s function%i\n", 426 func->name, fselector); 427 428 for (i = 0; i < func->nvals; i++) { 429 struct pcs_func_vals *vals; 430 unsigned val, mask; 431 432 vals = &func->vals[i]; 433 val = pcs->read(vals->reg); 434 if (!vals->mask) 435 mask = pcs->fmask; 436 else 437 mask = pcs->fmask & vals->mask; 438 439 val &= ~mask; 440 val |= (vals->val & mask); 441 pcs->write(val, vals->reg); 442 } 443 444 return 0; 445 } 446 447 static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector, 448 unsigned group) 449 { 450 struct pcs_device *pcs; 451 struct pcs_function *func; 452 int i; 453 454 pcs = pinctrl_dev_get_drvdata(pctldev); 455 /* If function mask is null, needn't disable it. */ 456 if (!pcs->fmask) 457 return; 458 459 func = radix_tree_lookup(&pcs->ftree, fselector); 460 if (!func) { 461 dev_err(pcs->dev, "%s could not find function%i\n", 462 __func__, fselector); 463 return; 464 } 465 466 /* 467 * Ignore disable if function-off is not specified. Some hardware 468 * does not have clearly defined disable function. For pin specific 469 * off modes, you can use alternate named states as described in 470 * pinctrl-bindings.txt. 471 */ 472 if (pcs->foff == PCS_OFF_DISABLED) { 473 dev_dbg(pcs->dev, "ignoring disable for %s function%i\n", 474 func->name, fselector); 475 return; 476 } 477 478 dev_dbg(pcs->dev, "disabling function%i %s\n", 479 fselector, func->name); 480 481 for (i = 0; i < func->nvals; i++) { 482 struct pcs_func_vals *vals; 483 unsigned val; 484 485 vals = &func->vals[i]; 486 val = pcs->read(vals->reg); 487 val &= ~pcs->fmask; 488 val |= pcs->foff << pcs->fshift; 489 pcs->write(val, vals->reg); 490 } 491 } 492 493 static int pcs_request_gpio(struct pinctrl_dev *pctldev, 494 struct pinctrl_gpio_range *range, unsigned pin) 495 { 496 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); 497 struct pcs_gpiofunc_range *frange = NULL; 498 struct list_head *pos, *tmp; 499 int mux_bytes = 0; 500 unsigned data; 501 502 /* If function mask is null, return directly. */ 503 if (!pcs->fmask) 504 return -ENOTSUPP; 505 506 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { 507 frange = list_entry(pos, struct pcs_gpiofunc_range, node); 508 if (pin >= frange->offset + frange->npins 509 || pin < frange->offset) 510 continue; 511 mux_bytes = pcs->width / BITS_PER_BYTE; 512 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask; 513 data |= frange->gpiofunc; 514 pcs->write(data, pcs->base + pin * mux_bytes); 515 break; 516 } 517 return 0; 518 } 519 520 static const struct pinmux_ops pcs_pinmux_ops = { 521 .get_functions_count = pcs_get_functions_count, 522 .get_function_name = pcs_get_function_name, 523 .get_function_groups = pcs_get_function_groups, 524 .enable = pcs_enable, 525 .disable = pcs_disable, 526 .gpio_request_enable = pcs_request_gpio, 527 }; 528 529 /* Clear BIAS value */ 530 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin) 531 { 532 unsigned long config; 533 int i; 534 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { 535 config = pinconf_to_config_packed(pcs_bias[i], 0); 536 pcs_pinconf_set(pctldev, pin, config); 537 } 538 } 539 540 /* 541 * Check whether PIN_CONFIG_BIAS_DISABLE is valid. 542 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid. 543 */ 544 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin) 545 { 546 unsigned long config; 547 int i; 548 549 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { 550 config = pinconf_to_config_packed(pcs_bias[i], 0); 551 if (!pcs_pinconf_get(pctldev, pin, &config)) 552 goto out; 553 } 554 return true; 555 out: 556 return false; 557 } 558 559 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, 560 unsigned pin, unsigned long *config) 561 { 562 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); 563 struct pcs_function *func; 564 enum pin_config_param param; 565 unsigned offset = 0, data = 0, i, j, ret; 566 567 ret = pcs_get_function(pctldev, pin, &func); 568 if (ret) 569 return ret; 570 571 for (i = 0; i < func->nconfs; i++) { 572 param = pinconf_to_config_param(*config); 573 if (param == PIN_CONFIG_BIAS_DISABLE) { 574 if (pcs_pinconf_bias_disable(pctldev, pin)) { 575 *config = 0; 576 return 0; 577 } else { 578 return -ENOTSUPP; 579 } 580 } else if (param != func->conf[i].param) { 581 continue; 582 } 583 584 offset = pin * (pcs->width / BITS_PER_BYTE); 585 data = pcs->read(pcs->base + offset) & func->conf[i].mask; 586 switch (func->conf[i].param) { 587 /* 4 parameters */ 588 case PIN_CONFIG_BIAS_PULL_DOWN: 589 case PIN_CONFIG_BIAS_PULL_UP: 590 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 591 if ((data != func->conf[i].enable) || 592 (data == func->conf[i].disable)) 593 return -ENOTSUPP; 594 *config = 0; 595 break; 596 /* 2 parameters */ 597 case PIN_CONFIG_INPUT_SCHMITT: 598 for (j = 0; j < func->nconfs; j++) { 599 switch (func->conf[j].param) { 600 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 601 if (data != func->conf[j].enable) 602 return -ENOTSUPP; 603 break; 604 default: 605 break; 606 } 607 } 608 *config = data; 609 break; 610 case PIN_CONFIG_DRIVE_STRENGTH: 611 case PIN_CONFIG_SLEW_RATE: 612 default: 613 *config = data; 614 break; 615 } 616 return 0; 617 } 618 return -ENOTSUPP; 619 } 620 621 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, 622 unsigned pin, unsigned long config) 623 { 624 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); 625 struct pcs_function *func; 626 unsigned offset = 0, shift = 0, i, data, ret; 627 u16 arg; 628 629 ret = pcs_get_function(pctldev, pin, &func); 630 if (ret) 631 return ret; 632 633 for (i = 0; i < func->nconfs; i++) { 634 if (pinconf_to_config_param(config) == func->conf[i].param) { 635 offset = pin * (pcs->width / BITS_PER_BYTE); 636 data = pcs->read(pcs->base + offset); 637 arg = pinconf_to_config_argument(config); 638 switch (func->conf[i].param) { 639 /* 2 parameters */ 640 case PIN_CONFIG_INPUT_SCHMITT: 641 case PIN_CONFIG_DRIVE_STRENGTH: 642 case PIN_CONFIG_SLEW_RATE: 643 shift = ffs(func->conf[i].mask) - 1; 644 data &= ~func->conf[i].mask; 645 data |= (arg << shift) & func->conf[i].mask; 646 break; 647 /* 4 parameters */ 648 case PIN_CONFIG_BIAS_DISABLE: 649 pcs_pinconf_clear_bias(pctldev, pin); 650 break; 651 case PIN_CONFIG_BIAS_PULL_DOWN: 652 case PIN_CONFIG_BIAS_PULL_UP: 653 if (arg) 654 pcs_pinconf_clear_bias(pctldev, pin); 655 /* fall through */ 656 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 657 data &= ~func->conf[i].mask; 658 if (arg) 659 data |= func->conf[i].enable; 660 else 661 data |= func->conf[i].disable; 662 break; 663 default: 664 return -ENOTSUPP; 665 } 666 pcs->write(data, pcs->base + offset); 667 return 0; 668 } 669 } 670 return -ENOTSUPP; 671 } 672 673 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, 674 unsigned group, unsigned long *config) 675 { 676 const unsigned *pins; 677 unsigned npins, old = 0; 678 int i, ret; 679 680 ret = pcs_get_group_pins(pctldev, group, &pins, &npins); 681 if (ret) 682 return ret; 683 for (i = 0; i < npins; i++) { 684 if (pcs_pinconf_get(pctldev, pins[i], config)) 685 return -ENOTSUPP; 686 /* configs do not match between two pins */ 687 if (i && (old != *config)) 688 return -ENOTSUPP; 689 old = *config; 690 } 691 return 0; 692 } 693 694 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, 695 unsigned group, unsigned long config) 696 { 697 const unsigned *pins; 698 unsigned npins; 699 int i, ret; 700 701 ret = pcs_get_group_pins(pctldev, group, &pins, &npins); 702 if (ret) 703 return ret; 704 for (i = 0; i < npins; i++) { 705 if (pcs_pinconf_set(pctldev, pins[i], config)) 706 return -ENOTSUPP; 707 } 708 return 0; 709 } 710 711 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev, 712 struct seq_file *s, unsigned pin) 713 { 714 } 715 716 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 717 struct seq_file *s, unsigned selector) 718 { 719 } 720 721 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, 722 struct seq_file *s, 723 unsigned long config) 724 { 725 pinconf_generic_dump_config(pctldev, s, config); 726 } 727 728 static const struct pinconf_ops pcs_pinconf_ops = { 729 .pin_config_get = pcs_pinconf_get, 730 .pin_config_set = pcs_pinconf_set, 731 .pin_config_group_get = pcs_pinconf_group_get, 732 .pin_config_group_set = pcs_pinconf_group_set, 733 .pin_config_dbg_show = pcs_pinconf_dbg_show, 734 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show, 735 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show, 736 .is_generic = true, 737 }; 738 739 /** 740 * pcs_add_pin() - add a pin to the static per controller pin array 741 * @pcs: pcs driver instance 742 * @offset: register offset from base 743 */ 744 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) 745 { 746 struct pinctrl_pin_desc *pin; 747 struct pcs_name *pn; 748 int i; 749 750 i = pcs->pins.cur; 751 if (i >= pcs->desc.npins) { 752 dev_err(pcs->dev, "too many pins, max %i\n", 753 pcs->desc.npins); 754 return -ENOMEM; 755 } 756 757 pin = &pcs->pins.pa[i]; 758 pn = &pcs->names[i]; 759 sprintf(pn->name, "%lx", 760 (unsigned long)pcs->res->start + offset); 761 pin->name = pn->name; 762 pin->number = i; 763 pcs->pins.cur++; 764 765 return i; 766 } 767 768 /** 769 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver 770 * @pcs: pcs driver instance 771 * 772 * In case of errors, resources are freed in pcs_free_resources. 773 * 774 * If your hardware needs holes in the address space, then just set 775 * up multiple driver instances. 776 */ 777 static int pcs_allocate_pin_table(struct pcs_device *pcs) 778 { 779 int mux_bytes, nr_pins, i; 780 781 mux_bytes = pcs->width / BITS_PER_BYTE; 782 nr_pins = pcs->size / mux_bytes; 783 784 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); 785 pcs->pins.pa = devm_kzalloc(pcs->dev, 786 sizeof(*pcs->pins.pa) * nr_pins, 787 GFP_KERNEL); 788 if (!pcs->pins.pa) 789 return -ENOMEM; 790 791 pcs->names = devm_kzalloc(pcs->dev, 792 sizeof(struct pcs_name) * nr_pins, 793 GFP_KERNEL); 794 if (!pcs->names) 795 return -ENOMEM; 796 797 pcs->desc.pins = pcs->pins.pa; 798 pcs->desc.npins = nr_pins; 799 800 for (i = 0; i < pcs->desc.npins; i++) { 801 unsigned offset; 802 int res; 803 804 offset = i * mux_bytes; 805 res = pcs_add_pin(pcs, offset); 806 if (res < 0) { 807 dev_err(pcs->dev, "error adding pins: %i\n", res); 808 return res; 809 } 810 } 811 812 return 0; 813 } 814 815 /** 816 * pcs_add_function() - adds a new function to the function list 817 * @pcs: pcs driver instance 818 * @np: device node of the mux entry 819 * @name: name of the function 820 * @vals: array of mux register value pairs used by the function 821 * @nvals: number of mux register value pairs 822 * @pgnames: array of pingroup names for the function 823 * @npgnames: number of pingroup names 824 */ 825 static struct pcs_function *pcs_add_function(struct pcs_device *pcs, 826 struct device_node *np, 827 const char *name, 828 struct pcs_func_vals *vals, 829 unsigned nvals, 830 const char **pgnames, 831 unsigned npgnames) 832 { 833 struct pcs_function *function; 834 835 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); 836 if (!function) 837 return NULL; 838 839 function->name = name; 840 function->vals = vals; 841 function->nvals = nvals; 842 function->pgnames = pgnames; 843 function->npgnames = npgnames; 844 845 mutex_lock(&pcs->mutex); 846 list_add_tail(&function->node, &pcs->functions); 847 radix_tree_insert(&pcs->ftree, pcs->nfuncs, function); 848 pcs->nfuncs++; 849 mutex_unlock(&pcs->mutex); 850 851 return function; 852 } 853 854 static void pcs_remove_function(struct pcs_device *pcs, 855 struct pcs_function *function) 856 { 857 int i; 858 859 mutex_lock(&pcs->mutex); 860 for (i = 0; i < pcs->nfuncs; i++) { 861 struct pcs_function *found; 862 863 found = radix_tree_lookup(&pcs->ftree, i); 864 if (found == function) 865 radix_tree_delete(&pcs->ftree, i); 866 } 867 list_del(&function->node); 868 mutex_unlock(&pcs->mutex); 869 } 870 871 /** 872 * pcs_add_pingroup() - add a pingroup to the pingroup list 873 * @pcs: pcs driver instance 874 * @np: device node of the mux entry 875 * @name: name of the pingroup 876 * @gpins: array of the pins that belong to the group 877 * @ngpins: number of pins in the group 878 */ 879 static int pcs_add_pingroup(struct pcs_device *pcs, 880 struct device_node *np, 881 const char *name, 882 int *gpins, 883 int ngpins) 884 { 885 struct pcs_pingroup *pingroup; 886 887 pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL); 888 if (!pingroup) 889 return -ENOMEM; 890 891 pingroup->name = name; 892 pingroup->np = np; 893 pingroup->gpins = gpins; 894 pingroup->ngpins = ngpins; 895 896 mutex_lock(&pcs->mutex); 897 list_add_tail(&pingroup->node, &pcs->pingroups); 898 radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup); 899 pcs->ngroups++; 900 mutex_unlock(&pcs->mutex); 901 902 return 0; 903 } 904 905 /** 906 * pcs_get_pin_by_offset() - get a pin index based on the register offset 907 * @pcs: pcs driver instance 908 * @offset: register offset from the base 909 * 910 * Note that this is OK as long as the pins are in a static array. 911 */ 912 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) 913 { 914 unsigned index; 915 916 if (offset >= pcs->size) { 917 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", 918 offset, pcs->size); 919 return -EINVAL; 920 } 921 922 index = offset / (pcs->width / BITS_PER_BYTE); 923 924 return index; 925 } 926 927 /* 928 * check whether data matches enable bits or disable bits 929 * Return value: 1 for matching enable bits, 0 for matching disable bits, 930 * and negative value for matching failure. 931 */ 932 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable) 933 { 934 int ret = -EINVAL; 935 936 if (data == enable) 937 ret = 1; 938 else if (data == disable) 939 ret = 0; 940 return ret; 941 } 942 943 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param, 944 unsigned value, unsigned enable, unsigned disable, 945 unsigned mask) 946 { 947 (*conf)->param = param; 948 (*conf)->val = value; 949 (*conf)->enable = enable; 950 (*conf)->disable = disable; 951 (*conf)->mask = mask; 952 (*conf)++; 953 } 954 955 static void add_setting(unsigned long **setting, enum pin_config_param param, 956 unsigned arg) 957 { 958 **setting = pinconf_to_config_packed(param, arg); 959 (*setting)++; 960 } 961 962 /* add pinconf setting with 2 parameters */ 963 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np, 964 const char *name, enum pin_config_param param, 965 struct pcs_conf_vals **conf, unsigned long **settings) 966 { 967 unsigned value[2], shift; 968 int ret; 969 970 ret = of_property_read_u32_array(np, name, value, 2); 971 if (ret) 972 return; 973 /* set value & mask */ 974 value[0] &= value[1]; 975 shift = ffs(value[1]) - 1; 976 /* skip enable & disable */ 977 add_config(conf, param, value[0], 0, 0, value[1]); 978 add_setting(settings, param, value[0] >> shift); 979 } 980 981 /* add pinconf setting with 4 parameters */ 982 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np, 983 const char *name, enum pin_config_param param, 984 struct pcs_conf_vals **conf, unsigned long **settings) 985 { 986 unsigned value[4]; 987 int ret; 988 989 /* value to set, enable, disable, mask */ 990 ret = of_property_read_u32_array(np, name, value, 4); 991 if (ret) 992 return; 993 if (!value[3]) { 994 dev_err(pcs->dev, "mask field of the property can't be 0\n"); 995 return; 996 } 997 value[0] &= value[3]; 998 value[1] &= value[3]; 999 value[2] &= value[3]; 1000 ret = pcs_config_match(value[0], value[1], value[2]); 1001 if (ret < 0) 1002 dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); 1003 add_config(conf, param, value[0], value[1], value[2], value[3]); 1004 add_setting(settings, param, ret); 1005 } 1006 1007 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, 1008 struct pcs_function *func, 1009 struct pinctrl_map **map) 1010 1011 { 1012 struct pinctrl_map *m = *map; 1013 int i = 0, nconfs = 0; 1014 unsigned long *settings = NULL, *s = NULL; 1015 struct pcs_conf_vals *conf = NULL; 1016 struct pcs_conf_type prop2[] = { 1017 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, 1018 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, 1019 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, 1020 }; 1021 struct pcs_conf_type prop4[] = { 1022 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, 1023 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, 1024 { "pinctrl-single,input-schmitt-enable", 1025 PIN_CONFIG_INPUT_SCHMITT_ENABLE, }, 1026 }; 1027 1028 /* If pinconf isn't supported, don't parse properties in below. */ 1029 if (!pcs->is_pinconf) 1030 return 0; 1031 1032 /* cacluate how much properties are supported in current node */ 1033 for (i = 0; i < ARRAY_SIZE(prop2); i++) { 1034 if (of_find_property(np, prop2[i].name, NULL)) 1035 nconfs++; 1036 } 1037 for (i = 0; i < ARRAY_SIZE(prop4); i++) { 1038 if (of_find_property(np, prop4[i].name, NULL)) 1039 nconfs++; 1040 } 1041 if (!nconfs) 1042 return 0; 1043 1044 func->conf = devm_kzalloc(pcs->dev, 1045 sizeof(struct pcs_conf_vals) * nconfs, 1046 GFP_KERNEL); 1047 if (!func->conf) 1048 return -ENOMEM; 1049 func->nconfs = nconfs; 1050 conf = &(func->conf[0]); 1051 m++; 1052 settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs, 1053 GFP_KERNEL); 1054 if (!settings) 1055 return -ENOMEM; 1056 s = &settings[0]; 1057 1058 for (i = 0; i < ARRAY_SIZE(prop2); i++) 1059 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param, 1060 &conf, &s); 1061 for (i = 0; i < ARRAY_SIZE(prop4); i++) 1062 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param, 1063 &conf, &s); 1064 m->type = PIN_MAP_TYPE_CONFIGS_GROUP; 1065 m->data.configs.group_or_pin = np->name; 1066 m->data.configs.configs = settings; 1067 m->data.configs.num_configs = nconfs; 1068 return 0; 1069 } 1070 1071 static void pcs_free_pingroups(struct pcs_device *pcs); 1072 1073 /** 1074 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry 1075 * @pcs: pinctrl driver instance 1076 * @np: device node of the mux entry 1077 * @map: map entry 1078 * @num_maps: number of map 1079 * @pgnames: pingroup names 1080 * 1081 * Note that this binding currently supports only sets of one register + value. 1082 * 1083 * Also note that this driver tries to avoid understanding pin and function 1084 * names because of the extra bloat they would cause especially in the case of 1085 * a large number of pins. This driver just sets what is specified for the board 1086 * in the .dts file. Further user space debugging tools can be developed to 1087 * decipher the pin and function names using debugfs. 1088 * 1089 * If you are concerned about the boot time, set up the static pins in 1090 * the bootloader, and only set up selected pins as device tree entries. 1091 */ 1092 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, 1093 struct device_node *np, 1094 struct pinctrl_map **map, 1095 unsigned *num_maps, 1096 const char **pgnames) 1097 { 1098 struct pcs_func_vals *vals; 1099 const __be32 *mux; 1100 int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM; 1101 struct pcs_function *function; 1102 1103 if (pcs->bits_per_mux) { 1104 params = 3; 1105 mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); 1106 } else { 1107 params = 2; 1108 mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); 1109 } 1110 1111 if (!mux) { 1112 dev_err(pcs->dev, "no valid property for %s\n", np->name); 1113 return -EINVAL; 1114 } 1115 1116 if (size < (sizeof(*mux) * params)) { 1117 dev_err(pcs->dev, "bad data for %s\n", np->name); 1118 return -EINVAL; 1119 } 1120 1121 size /= sizeof(*mux); /* Number of elements in array */ 1122 rows = size / params; 1123 1124 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); 1125 if (!vals) 1126 return -ENOMEM; 1127 1128 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL); 1129 if (!pins) 1130 goto free_vals; 1131 1132 while (index < size) { 1133 unsigned offset, val; 1134 int pin; 1135 1136 offset = be32_to_cpup(mux + index++); 1137 val = be32_to_cpup(mux + index++); 1138 vals[found].reg = pcs->base + offset; 1139 vals[found].val = val; 1140 if (params == 3) { 1141 val = be32_to_cpup(mux + index++); 1142 vals[found].mask = val; 1143 } 1144 1145 pin = pcs_get_pin_by_offset(pcs, offset); 1146 if (pin < 0) { 1147 dev_err(pcs->dev, 1148 "could not add functions for %s %ux\n", 1149 np->name, offset); 1150 break; 1151 } 1152 pins[found++] = pin; 1153 } 1154 1155 pgnames[0] = np->name; 1156 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); 1157 if (!function) 1158 goto free_pins; 1159 1160 res = pcs_add_pingroup(pcs, np, np->name, pins, found); 1161 if (res < 0) 1162 goto free_function; 1163 1164 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; 1165 (*map)->data.mux.group = np->name; 1166 (*map)->data.mux.function = np->name; 1167 1168 if (pcs->is_pinconf) { 1169 if (pcs_parse_pinconf(pcs, np, function, map)) 1170 goto free_pingroups; 1171 *num_maps = 2; 1172 } else { 1173 *num_maps = 1; 1174 } 1175 return 0; 1176 1177 free_pingroups: 1178 pcs_free_pingroups(pcs); 1179 *num_maps = 1; 1180 free_function: 1181 pcs_remove_function(pcs, function); 1182 1183 free_pins: 1184 devm_kfree(pcs->dev, pins); 1185 1186 free_vals: 1187 devm_kfree(pcs->dev, vals); 1188 1189 return res; 1190 } 1191 /** 1192 * pcs_dt_node_to_map() - allocates and parses pinctrl maps 1193 * @pctldev: pinctrl instance 1194 * @np_config: device tree pinmux entry 1195 * @map: array of map entries 1196 * @num_maps: number of maps 1197 */ 1198 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, 1199 struct device_node *np_config, 1200 struct pinctrl_map **map, unsigned *num_maps) 1201 { 1202 struct pcs_device *pcs; 1203 const char **pgnames; 1204 int ret; 1205 1206 pcs = pinctrl_dev_get_drvdata(pctldev); 1207 1208 /* create 2 maps. One is for pinmux, and the other is for pinconf. */ 1209 *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL); 1210 if (!*map) 1211 return -ENOMEM; 1212 1213 *num_maps = 0; 1214 1215 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); 1216 if (!pgnames) { 1217 ret = -ENOMEM; 1218 goto free_map; 1219 } 1220 1221 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps, 1222 pgnames); 1223 if (ret < 0) { 1224 dev_err(pcs->dev, "no pins entries for %s\n", 1225 np_config->name); 1226 goto free_pgnames; 1227 } 1228 1229 return 0; 1230 1231 free_pgnames: 1232 devm_kfree(pcs->dev, pgnames); 1233 free_map: 1234 devm_kfree(pcs->dev, *map); 1235 1236 return ret; 1237 } 1238 1239 /** 1240 * pcs_free_funcs() - free memory used by functions 1241 * @pcs: pcs driver instance 1242 */ 1243 static void pcs_free_funcs(struct pcs_device *pcs) 1244 { 1245 struct list_head *pos, *tmp; 1246 int i; 1247 1248 mutex_lock(&pcs->mutex); 1249 for (i = 0; i < pcs->nfuncs; i++) { 1250 struct pcs_function *func; 1251 1252 func = radix_tree_lookup(&pcs->ftree, i); 1253 if (!func) 1254 continue; 1255 radix_tree_delete(&pcs->ftree, i); 1256 } 1257 list_for_each_safe(pos, tmp, &pcs->functions) { 1258 struct pcs_function *function; 1259 1260 function = list_entry(pos, struct pcs_function, node); 1261 list_del(&function->node); 1262 } 1263 mutex_unlock(&pcs->mutex); 1264 } 1265 1266 /** 1267 * pcs_free_pingroups() - free memory used by pingroups 1268 * @pcs: pcs driver instance 1269 */ 1270 static void pcs_free_pingroups(struct pcs_device *pcs) 1271 { 1272 struct list_head *pos, *tmp; 1273 int i; 1274 1275 mutex_lock(&pcs->mutex); 1276 for (i = 0; i < pcs->ngroups; i++) { 1277 struct pcs_pingroup *pingroup; 1278 1279 pingroup = radix_tree_lookup(&pcs->pgtree, i); 1280 if (!pingroup) 1281 continue; 1282 radix_tree_delete(&pcs->pgtree, i); 1283 } 1284 list_for_each_safe(pos, tmp, &pcs->pingroups) { 1285 struct pcs_pingroup *pingroup; 1286 1287 pingroup = list_entry(pos, struct pcs_pingroup, node); 1288 list_del(&pingroup->node); 1289 } 1290 mutex_unlock(&pcs->mutex); 1291 } 1292 1293 /** 1294 * pcs_free_resources() - free memory used by this driver 1295 * @pcs: pcs driver instance 1296 */ 1297 static void pcs_free_resources(struct pcs_device *pcs) 1298 { 1299 if (pcs->pctl) 1300 pinctrl_unregister(pcs->pctl); 1301 1302 pcs_free_funcs(pcs); 1303 pcs_free_pingroups(pcs); 1304 } 1305 1306 #define PCS_GET_PROP_U32(name, reg, err) \ 1307 do { \ 1308 ret = of_property_read_u32(np, name, reg); \ 1309 if (ret) { \ 1310 dev_err(pcs->dev, err); \ 1311 return ret; \ 1312 } \ 1313 } while (0); 1314 1315 static struct of_device_id pcs_of_match[]; 1316 1317 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) 1318 { 1319 const char *propname = "pinctrl-single,gpio-range"; 1320 const char *cellname = "#pinctrl-single,gpio-range-cells"; 1321 struct of_phandle_args gpiospec; 1322 struct pcs_gpiofunc_range *range; 1323 int ret, i; 1324 1325 for (i = 0; ; i++) { 1326 ret = of_parse_phandle_with_args(node, propname, cellname, 1327 i, &gpiospec); 1328 /* Do not treat it as error. Only treat it as end condition. */ 1329 if (ret) { 1330 ret = 0; 1331 break; 1332 } 1333 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); 1334 if (!range) { 1335 ret = -ENOMEM; 1336 break; 1337 } 1338 range->offset = gpiospec.args[0]; 1339 range->npins = gpiospec.args[1]; 1340 range->gpiofunc = gpiospec.args[2]; 1341 mutex_lock(&pcs->mutex); 1342 list_add_tail(&range->node, &pcs->gpiofuncs); 1343 mutex_unlock(&pcs->mutex); 1344 } 1345 return ret; 1346 } 1347 1348 static int pcs_probe(struct platform_device *pdev) 1349 { 1350 struct device_node *np = pdev->dev.of_node; 1351 const struct of_device_id *match; 1352 struct resource *res; 1353 struct pcs_device *pcs; 1354 int ret; 1355 1356 match = of_match_device(pcs_of_match, &pdev->dev); 1357 if (!match) 1358 return -EINVAL; 1359 1360 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); 1361 if (!pcs) { 1362 dev_err(&pdev->dev, "could not allocate\n"); 1363 return -ENOMEM; 1364 } 1365 pcs->dev = &pdev->dev; 1366 mutex_init(&pcs->mutex); 1367 INIT_LIST_HEAD(&pcs->pingroups); 1368 INIT_LIST_HEAD(&pcs->functions); 1369 INIT_LIST_HEAD(&pcs->gpiofuncs); 1370 pcs->is_pinconf = match->data; 1371 1372 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, 1373 "register width not specified\n"); 1374 1375 ret = of_property_read_u32(np, "pinctrl-single,function-mask", 1376 &pcs->fmask); 1377 if (!ret) { 1378 pcs->fshift = ffs(pcs->fmask) - 1; 1379 pcs->fmax = pcs->fmask >> pcs->fshift; 1380 } else { 1381 /* If mask property doesn't exist, function mux is invalid. */ 1382 pcs->fmask = 0; 1383 pcs->fshift = 0; 1384 pcs->fmax = 0; 1385 } 1386 1387 ret = of_property_read_u32(np, "pinctrl-single,function-off", 1388 &pcs->foff); 1389 if (ret) 1390 pcs->foff = PCS_OFF_DISABLED; 1391 1392 pcs->bits_per_mux = of_property_read_bool(np, 1393 "pinctrl-single,bit-per-mux"); 1394 1395 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1396 if (!res) { 1397 dev_err(pcs->dev, "could not get resource\n"); 1398 return -ENODEV; 1399 } 1400 1401 pcs->res = devm_request_mem_region(pcs->dev, res->start, 1402 resource_size(res), DRIVER_NAME); 1403 if (!pcs->res) { 1404 dev_err(pcs->dev, "could not get mem_region\n"); 1405 return -EBUSY; 1406 } 1407 1408 pcs->size = resource_size(pcs->res); 1409 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); 1410 if (!pcs->base) { 1411 dev_err(pcs->dev, "could not ioremap\n"); 1412 return -ENODEV; 1413 } 1414 1415 INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL); 1416 INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL); 1417 platform_set_drvdata(pdev, pcs); 1418 1419 switch (pcs->width) { 1420 case 8: 1421 pcs->read = pcs_readb; 1422 pcs->write = pcs_writeb; 1423 break; 1424 case 16: 1425 pcs->read = pcs_readw; 1426 pcs->write = pcs_writew; 1427 break; 1428 case 32: 1429 pcs->read = pcs_readl; 1430 pcs->write = pcs_writel; 1431 break; 1432 default: 1433 break; 1434 } 1435 1436 pcs->desc.name = DRIVER_NAME; 1437 pcs->desc.pctlops = &pcs_pinctrl_ops; 1438 pcs->desc.pmxops = &pcs_pinmux_ops; 1439 if (pcs->is_pinconf) 1440 pcs->desc.confops = &pcs_pinconf_ops; 1441 pcs->desc.owner = THIS_MODULE; 1442 1443 ret = pcs_allocate_pin_table(pcs); 1444 if (ret < 0) 1445 goto free; 1446 1447 pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs); 1448 if (!pcs->pctl) { 1449 dev_err(pcs->dev, "could not register single pinctrl driver\n"); 1450 ret = -EINVAL; 1451 goto free; 1452 } 1453 1454 ret = pcs_add_gpio_func(np, pcs); 1455 if (ret < 0) 1456 goto free; 1457 1458 dev_info(pcs->dev, "%i pins at pa %p size %u\n", 1459 pcs->desc.npins, pcs->base, pcs->size); 1460 1461 return 0; 1462 1463 free: 1464 pcs_free_resources(pcs); 1465 1466 return ret; 1467 } 1468 1469 static int pcs_remove(struct platform_device *pdev) 1470 { 1471 struct pcs_device *pcs = platform_get_drvdata(pdev); 1472 1473 if (!pcs) 1474 return 0; 1475 1476 pcs_free_resources(pcs); 1477 1478 return 0; 1479 } 1480 1481 static struct of_device_id pcs_of_match[] = { 1482 { .compatible = "pinctrl-single", .data = (void *)false }, 1483 { .compatible = "pinconf-single", .data = (void *)true }, 1484 { }, 1485 }; 1486 MODULE_DEVICE_TABLE(of, pcs_of_match); 1487 1488 static struct platform_driver pcs_driver = { 1489 .probe = pcs_probe, 1490 .remove = pcs_remove, 1491 .driver = { 1492 .owner = THIS_MODULE, 1493 .name = DRIVER_NAME, 1494 .of_match_table = pcs_of_match, 1495 }, 1496 }; 1497 1498 module_platform_driver(pcs_driver); 1499 1500 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); 1501 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver"); 1502 MODULE_LICENSE("GPL v2"); 1503