1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd. 4 * 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * https://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18 #ifndef _PINCTRL_ROCKCHIP_H 19 #define _PINCTRL_ROCKCHIP_H 20 21 #define RK_GPIO0_A0 0 22 #define RK_GPIO0_A1 1 23 #define RK_GPIO0_A2 2 24 #define RK_GPIO0_A3 3 25 #define RK_GPIO0_A4 4 26 #define RK_GPIO0_A5 5 27 #define RK_GPIO0_A6 6 28 #define RK_GPIO0_A7 7 29 #define RK_GPIO0_B0 8 30 #define RK_GPIO0_B1 9 31 #define RK_GPIO0_B2 10 32 #define RK_GPIO0_B3 11 33 #define RK_GPIO0_B4 12 34 #define RK_GPIO0_B5 13 35 #define RK_GPIO0_B6 14 36 #define RK_GPIO0_B7 15 37 #define RK_GPIO0_C0 16 38 #define RK_GPIO0_C1 17 39 #define RK_GPIO0_C2 18 40 #define RK_GPIO0_C3 19 41 #define RK_GPIO0_C4 20 42 #define RK_GPIO0_C5 21 43 #define RK_GPIO0_C6 22 44 #define RK_GPIO0_C7 23 45 #define RK_GPIO0_D0 24 46 #define RK_GPIO0_D1 25 47 #define RK_GPIO0_D2 26 48 #define RK_GPIO0_D3 27 49 #define RK_GPIO0_D4 28 50 #define RK_GPIO0_D5 29 51 #define RK_GPIO0_D6 30 52 #define RK_GPIO0_D7 31 53 54 #define RK_GPIO1_A0 32 55 #define RK_GPIO1_A1 33 56 #define RK_GPIO1_A2 34 57 #define RK_GPIO1_A3 35 58 #define RK_GPIO1_A4 36 59 #define RK_GPIO1_A5 37 60 #define RK_GPIO1_A6 38 61 #define RK_GPIO1_A7 39 62 #define RK_GPIO1_B0 40 63 #define RK_GPIO1_B1 41 64 #define RK_GPIO1_B2 42 65 #define RK_GPIO1_B3 43 66 #define RK_GPIO1_B4 44 67 #define RK_GPIO1_B5 45 68 #define RK_GPIO1_B6 46 69 #define RK_GPIO1_B7 47 70 #define RK_GPIO1_C0 48 71 #define RK_GPIO1_C1 49 72 #define RK_GPIO1_C2 50 73 #define RK_GPIO1_C3 51 74 #define RK_GPIO1_C4 52 75 #define RK_GPIO1_C5 53 76 #define RK_GPIO1_C6 54 77 #define RK_GPIO1_C7 55 78 #define RK_GPIO1_D0 56 79 #define RK_GPIO1_D1 57 80 #define RK_GPIO1_D2 58 81 #define RK_GPIO1_D3 59 82 #define RK_GPIO1_D4 60 83 #define RK_GPIO1_D5 61 84 #define RK_GPIO1_D6 62 85 #define RK_GPIO1_D7 63 86 87 #define RK_GPIO2_A0 64 88 #define RK_GPIO2_A1 65 89 #define RK_GPIO2_A2 66 90 #define RK_GPIO2_A3 67 91 #define RK_GPIO2_A4 68 92 #define RK_GPIO2_A5 69 93 #define RK_GPIO2_A6 70 94 #define RK_GPIO2_A7 71 95 #define RK_GPIO2_B0 72 96 #define RK_GPIO2_B1 73 97 #define RK_GPIO2_B2 74 98 #define RK_GPIO2_B3 75 99 #define RK_GPIO2_B4 76 100 #define RK_GPIO2_B5 77 101 #define RK_GPIO2_B6 78 102 #define RK_GPIO2_B7 79 103 #define RK_GPIO2_C0 80 104 #define RK_GPIO2_C1 81 105 #define RK_GPIO2_C2 82 106 #define RK_GPIO2_C3 83 107 #define RK_GPIO2_C4 84 108 #define RK_GPIO2_C5 85 109 #define RK_GPIO2_C6 86 110 #define RK_GPIO2_C7 87 111 #define RK_GPIO2_D0 88 112 #define RK_GPIO2_D1 89 113 #define RK_GPIO2_D2 90 114 #define RK_GPIO2_D3 91 115 #define RK_GPIO2_D4 92 116 #define RK_GPIO2_D5 93 117 #define RK_GPIO2_D6 94 118 #define RK_GPIO2_D7 95 119 120 #define RK_GPIO3_A0 96 121 #define RK_GPIO3_A1 97 122 #define RK_GPIO3_A2 98 123 #define RK_GPIO3_A3 99 124 #define RK_GPIO3_A4 100 125 #define RK_GPIO3_A5 101 126 #define RK_GPIO3_A6 102 127 #define RK_GPIO3_A7 103 128 #define RK_GPIO3_B0 104 129 #define RK_GPIO3_B1 105 130 #define RK_GPIO3_B2 106 131 #define RK_GPIO3_B3 107 132 #define RK_GPIO3_B4 108 133 #define RK_GPIO3_B5 109 134 #define RK_GPIO3_B6 110 135 #define RK_GPIO3_B7 111 136 #define RK_GPIO3_C0 112 137 #define RK_GPIO3_C1 113 138 #define RK_GPIO3_C2 114 139 #define RK_GPIO3_C3 115 140 #define RK_GPIO3_C4 116 141 #define RK_GPIO3_C5 117 142 #define RK_GPIO3_C6 118 143 #define RK_GPIO3_C7 119 144 #define RK_GPIO3_D0 120 145 #define RK_GPIO3_D1 121 146 #define RK_GPIO3_D2 122 147 #define RK_GPIO3_D3 123 148 #define RK_GPIO3_D4 124 149 #define RK_GPIO3_D5 125 150 #define RK_GPIO3_D6 126 151 #define RK_GPIO3_D7 127 152 153 #define RK_GPIO4_A0 128 154 #define RK_GPIO4_A1 129 155 #define RK_GPIO4_A2 130 156 #define RK_GPIO4_A3 131 157 #define RK_GPIO4_A4 132 158 #define RK_GPIO4_A5 133 159 #define RK_GPIO4_A6 134 160 #define RK_GPIO4_A7 135 161 #define RK_GPIO4_B0 136 162 #define RK_GPIO4_B1 137 163 #define RK_GPIO4_B2 138 164 #define RK_GPIO4_B3 139 165 #define RK_GPIO4_B4 140 166 #define RK_GPIO4_B5 141 167 #define RK_GPIO4_B6 142 168 #define RK_GPIO4_B7 143 169 #define RK_GPIO4_C0 144 170 #define RK_GPIO4_C1 145 171 #define RK_GPIO4_C2 146 172 #define RK_GPIO4_C3 147 173 #define RK_GPIO4_C4 148 174 #define RK_GPIO4_C5 149 175 #define RK_GPIO4_C6 150 176 #define RK_GPIO4_C7 151 177 #define RK_GPIO4_D0 152 178 #define RK_GPIO4_D1 153 179 #define RK_GPIO4_D2 154 180 #define RK_GPIO4_D3 155 181 #define RK_GPIO4_D4 156 182 #define RK_GPIO4_D5 157 183 #define RK_GPIO4_D6 158 184 #define RK_GPIO4_D7 159 185 186 enum rockchip_pinctrl_type { 187 PX30, 188 RV1103B, 189 RV1108, 190 RV1126, 191 RK2928, 192 RK3066B, 193 RK3128, 194 RK3188, 195 RK3288, 196 RK3308, 197 RK3328, 198 RK3368, 199 RK3399, 200 RK3506, 201 RK3528, 202 RK3562, 203 RK3568, 204 RK3576, 205 RK3588, 206 }; 207 208 /** 209 * struct rockchip_gpio_regs 210 * @port_dr: data register 211 * @port_ddr: data direction register 212 * @int_en: interrupt enable 213 * @int_mask: interrupt mask 214 * @int_type: interrupt trigger type, such as high, low, edge trriger type. 215 * @int_polarity: interrupt polarity enable register 216 * @int_bothedge: interrupt bothedge enable register 217 * @int_status: interrupt status register 218 * @int_rawstatus: int_status = int_rawstatus & int_mask 219 * @debounce: enable debounce for interrupt signal 220 * @dbclk_div_en: enable divider for debounce clock 221 * @dbclk_div_con: setting for divider of debounce clock 222 * @port_eoi: end of interrupt of the port 223 * @ext_port: port data from external 224 * @version_id: controller version register 225 */ 226 struct rockchip_gpio_regs { 227 u32 port_dr; 228 u32 port_ddr; 229 u32 int_en; 230 u32 int_mask; 231 u32 int_type; 232 u32 int_polarity; 233 u32 int_bothedge; 234 u32 int_status; 235 u32 int_rawstatus; 236 u32 debounce; 237 u32 dbclk_div_en; 238 u32 dbclk_div_con; 239 u32 port_eoi; 240 u32 ext_port; 241 u32 version_id; 242 }; 243 244 /** 245 * struct rockchip_iomux 246 * @type: iomux variant using IOMUX_* constants 247 * @offset: if initialized to -1 it will be autocalculated, by specifying 248 * an initial offset value the relevant source offset can be reset 249 * to a new value for autocalculating the following iomux registers. 250 */ 251 struct rockchip_iomux { 252 int type; 253 int offset; 254 }; 255 256 /* 257 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 258 */ 259 enum rockchip_pin_drv_type { 260 DRV_TYPE_IO_DEFAULT = 0, 261 DRV_TYPE_IO_1V8_OR_3V0, 262 DRV_TYPE_IO_1V8_ONLY, 263 DRV_TYPE_IO_1V8_3V0_AUTO, 264 DRV_TYPE_IO_3V3_ONLY, 265 DRV_TYPE_IO_LEVEL_2_BIT, 266 DRV_TYPE_IO_LEVEL_8_BIT, 267 DRV_TYPE_MAX 268 }; 269 270 /* 271 * enum type index corresponding to rockchip_pull_list arrays index. 272 */ 273 enum rockchip_pin_pull_type { 274 PULL_TYPE_IO_DEFAULT = 0, 275 PULL_TYPE_IO_1V8_ONLY, 276 PULL_TYPE_MAX 277 }; 278 279 /** 280 * struct rockchip_drv 281 * @drv_type: drive strength variant using rockchip_perpin_drv_type 282 * @offset: if initialized to -1 it will be autocalculated, by specifying 283 * an initial offset value the relevant source offset can be reset 284 * to a new value for autocalculating the following drive strength 285 * registers. if used chips own cal_drv func instead to calculate 286 * registers offset, the variant could be ignored. 287 */ 288 struct rockchip_drv { 289 enum rockchip_pin_drv_type drv_type; 290 int offset; 291 }; 292 293 /** 294 * struct rockchip_pin_bank 295 * @dev: the pinctrl device bind to the bank 296 * @reg_base: register base of the gpio bank 297 * @regmap_pull: optional separate register for additional pull settings 298 * @clk: clock of the gpio bank 299 * @db_clk: clock of the gpio debounce 300 * @irq: interrupt of the gpio bank 301 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 302 * @pin_base: first pin number 303 * @nr_pins: number of pins in this bank 304 * @name: name of the bank 305 * @bank_num: number of the bank, to account for holes 306 * @iomux: array describing the 4 iomux sources of the bank 307 * @drv: array describing the 4 drive strength sources of the bank 308 * @pull_type: array describing the 4 pull type sources of the bank 309 * @valid: is all necessary information present 310 * @of_node: dt node of this bank 311 * @drvdata: common pinctrl basedata 312 * @domain: irqdomain of the gpio bank 313 * @gpio_chip: gpiolib chip 314 * @grange: gpio range 315 * @slock: spinlock for the gpio bank 316 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode 317 * @recalced_mask: bit mask to indicate a need to recalulate the mask 318 * @route_mask: bits describing the routing pins of per bank 319 * @deferred_output: gpio output settings to be done after gpio bank probed 320 * @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl 321 */ 322 struct rockchip_pin_bank { 323 struct device *dev; 324 void __iomem *reg_base; 325 struct regmap *regmap_pull; 326 struct clk *clk; 327 struct clk *db_clk; 328 int irq; 329 u32 saved_masks; 330 u32 pin_base; 331 u8 nr_pins; 332 char *name; 333 u8 bank_num; 334 struct rockchip_iomux iomux[4]; 335 struct rockchip_drv drv[4]; 336 enum rockchip_pin_pull_type pull_type[4]; 337 bool valid; 338 struct device_node *of_node; 339 struct rockchip_pinctrl *drvdata; 340 struct irq_domain *domain; 341 struct gpio_chip gpio_chip; 342 struct pinctrl_gpio_range grange; 343 raw_spinlock_t slock; 344 const struct rockchip_gpio_regs *gpio_regs; 345 u32 gpio_type; 346 u32 toggle_edge_mode; 347 u32 recalced_mask; 348 u32 route_mask; 349 struct list_head deferred_pins; 350 struct mutex deferred_lock; 351 }; 352 353 /** 354 * struct rockchip_mux_recalced_data: represent a pin iomux data. 355 * @num: bank number. 356 * @pin: pin number. 357 * @bit: index at register. 358 * @reg: register offset. 359 * @mask: mask bit 360 */ 361 struct rockchip_mux_recalced_data { 362 u8 num; 363 u8 pin; 364 u32 reg; 365 u8 bit; 366 u8 mask; 367 }; 368 369 enum rockchip_mux_route_location { 370 ROCKCHIP_ROUTE_SAME = 0, 371 ROCKCHIP_ROUTE_PMU, 372 ROCKCHIP_ROUTE_GRF, 373 }; 374 375 /** 376 * struct rockchip_mux_recalced_data: represent a pin iomux data. 377 * @bank_num: bank number. 378 * @pin: index at register or used to calc index. 379 * @func: the min pin. 380 * @route_location: the mux route location (same, pmu, grf). 381 * @route_offset: the max pin. 382 * @route_val: the register offset. 383 */ 384 struct rockchip_mux_route_data { 385 u8 bank_num; 386 u8 pin; 387 u8 func; 388 enum rockchip_mux_route_location route_location; 389 u32 route_offset; 390 u32 route_val; 391 }; 392 393 struct rockchip_pin_ctrl { 394 struct rockchip_pin_bank *pin_banks; 395 u32 nr_banks; 396 u32 nr_pins; 397 char *label; 398 enum rockchip_pinctrl_type type; 399 int grf_mux_offset; 400 int pmu_mux_offset; 401 int grf_drv_offset; 402 int pmu_drv_offset; 403 struct rockchip_mux_recalced_data *iomux_recalced; 404 u32 niomux_recalced; 405 struct rockchip_mux_route_data *iomux_routes; 406 u32 niomux_routes; 407 408 int (*pull_calc_reg)(struct rockchip_pin_bank *bank, 409 int pin_num, struct regmap **regmap, 410 int *reg, u8 *bit); 411 int (*drv_calc_reg)(struct rockchip_pin_bank *bank, 412 int pin_num, struct regmap **regmap, 413 int *reg, u8 *bit); 414 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 415 int pin_num, struct regmap **regmap, 416 int *reg, u8 *bit); 417 }; 418 419 struct rockchip_pin_config { 420 unsigned int func; 421 unsigned long *configs; 422 unsigned int nconfigs; 423 }; 424 425 enum pin_config_param; 426 427 struct rockchip_pin_deferred { 428 struct list_head head; 429 unsigned int pin; 430 enum pin_config_param param; 431 u32 arg; 432 }; 433 434 /** 435 * struct rockchip_pin_group: represent group of pins of a pinmux function. 436 * @name: name of the pin group, used to lookup the group. 437 * @pins: the pins included in this group. 438 * @npins: number of pins included in this group. 439 * @data: local pin configuration 440 */ 441 struct rockchip_pin_group { 442 const char *name; 443 unsigned int npins; 444 unsigned int *pins; 445 struct rockchip_pin_config *data; 446 }; 447 448 /** 449 * struct rockchip_pmx_func: represent a pin function. 450 * @name: name of the pin function, used to lookup the function. 451 * @groups: one or more names of pin groups that provide this function. 452 * @ngroups: number of groups included in @groups. 453 */ 454 struct rockchip_pmx_func { 455 const char *name; 456 const char **groups; 457 u8 ngroups; 458 }; 459 460 struct rockchip_pinctrl { 461 struct regmap *regmap_base; 462 int reg_size; 463 struct regmap *regmap_pull; 464 struct regmap *regmap_pmu; 465 struct regmap *regmap_ioc1; 466 struct device *dev; 467 struct rockchip_pin_ctrl *ctrl; 468 struct pinctrl_desc pctl; 469 struct pinctrl_dev *pctl_dev; 470 struct rockchip_pin_group *groups; 471 unsigned int ngroups; 472 struct rockchip_pmx_func *functions; 473 unsigned int nfunctions; 474 }; 475 476 #endif 477