1 /* 2 * Pinctrl driver for Rockchip SoCs 3 * 4 * Copyright (c) 2013 MundoReader S.L. 5 * Author: Heiko Stuebner <heiko@sntech.de> 6 * 7 * With some ideas taken from pinctrl-samsung: 8 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 9 * http://www.samsung.com 10 * Copyright (c) 2012 Linaro Ltd 11 * http://www.linaro.org 12 * 13 * and pinctrl-at91: 14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as published 18 * by the Free Software Foundation. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/platform_device.h> 28 #include <linux/io.h> 29 #include <linux/bitops.h> 30 #include <linux/gpio.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/pinctrl/machine.h> 34 #include <linux/pinctrl/pinconf.h> 35 #include <linux/pinctrl/pinctrl.h> 36 #include <linux/pinctrl/pinmux.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/irqchip/chained_irq.h> 39 #include <linux/clk.h> 40 #include <linux/regmap.h> 41 #include <linux/mfd/syscon.h> 42 #include <dt-bindings/pinctrl/rockchip.h> 43 44 #include "core.h" 45 #include "pinconf.h" 46 47 /* GPIO control registers */ 48 #define GPIO_SWPORT_DR 0x00 49 #define GPIO_SWPORT_DDR 0x04 50 #define GPIO_INTEN 0x30 51 #define GPIO_INTMASK 0x34 52 #define GPIO_INTTYPE_LEVEL 0x38 53 #define GPIO_INT_POLARITY 0x3c 54 #define GPIO_INT_STATUS 0x40 55 #define GPIO_INT_RAWSTATUS 0x44 56 #define GPIO_DEBOUNCE 0x48 57 #define GPIO_PORTS_EOI 0x4c 58 #define GPIO_EXT_PORT 0x50 59 #define GPIO_LS_SYNC 0x60 60 61 enum rockchip_pinctrl_type { 62 RK2928, 63 RK3066B, 64 RK3188, 65 RK3288, 66 RK3368, 67 }; 68 69 /** 70 * Encode variants of iomux registers into a type variable 71 */ 72 #define IOMUX_GPIO_ONLY BIT(0) 73 #define IOMUX_WIDTH_4BIT BIT(1) 74 #define IOMUX_SOURCE_PMU BIT(2) 75 #define IOMUX_UNROUTED BIT(3) 76 77 /** 78 * @type: iomux variant using IOMUX_* constants 79 * @offset: if initialized to -1 it will be autocalculated, by specifying 80 * an initial offset value the relevant source offset can be reset 81 * to a new value for autocalculating the following iomux registers. 82 */ 83 struct rockchip_iomux { 84 int type; 85 int offset; 86 }; 87 88 /** 89 * @reg_base: register base of the gpio bank 90 * @reg_pull: optional separate register for additional pull settings 91 * @clk: clock of the gpio bank 92 * @irq: interrupt of the gpio bank 93 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 94 * @pin_base: first pin number 95 * @nr_pins: number of pins in this bank 96 * @name: name of the bank 97 * @bank_num: number of the bank, to account for holes 98 * @iomux: array describing the 4 iomux sources of the bank 99 * @valid: are all necessary informations present 100 * @of_node: dt node of this bank 101 * @drvdata: common pinctrl basedata 102 * @domain: irqdomain of the gpio bank 103 * @gpio_chip: gpiolib chip 104 * @grange: gpio range 105 * @slock: spinlock for the gpio bank 106 */ 107 struct rockchip_pin_bank { 108 void __iomem *reg_base; 109 struct regmap *regmap_pull; 110 struct clk *clk; 111 int irq; 112 u32 saved_masks; 113 u32 pin_base; 114 u8 nr_pins; 115 char *name; 116 u8 bank_num; 117 struct rockchip_iomux iomux[4]; 118 bool valid; 119 struct device_node *of_node; 120 struct rockchip_pinctrl *drvdata; 121 struct irq_domain *domain; 122 struct gpio_chip gpio_chip; 123 struct pinctrl_gpio_range grange; 124 spinlock_t slock; 125 u32 toggle_edge_mode; 126 }; 127 128 #define PIN_BANK(id, pins, label) \ 129 { \ 130 .bank_num = id, \ 131 .nr_pins = pins, \ 132 .name = label, \ 133 .iomux = { \ 134 { .offset = -1 }, \ 135 { .offset = -1 }, \ 136 { .offset = -1 }, \ 137 { .offset = -1 }, \ 138 }, \ 139 } 140 141 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 142 { \ 143 .bank_num = id, \ 144 .nr_pins = pins, \ 145 .name = label, \ 146 .iomux = { \ 147 { .type = iom0, .offset = -1 }, \ 148 { .type = iom1, .offset = -1 }, \ 149 { .type = iom2, .offset = -1 }, \ 150 { .type = iom3, .offset = -1 }, \ 151 }, \ 152 } 153 154 /** 155 */ 156 struct rockchip_pin_ctrl { 157 struct rockchip_pin_bank *pin_banks; 158 u32 nr_banks; 159 u32 nr_pins; 160 char *label; 161 enum rockchip_pinctrl_type type; 162 int grf_mux_offset; 163 int pmu_mux_offset; 164 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 165 int pin_num, struct regmap **regmap, 166 int *reg, u8 *bit); 167 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 168 int pin_num, struct regmap **regmap, 169 int *reg, u8 *bit); 170 }; 171 172 struct rockchip_pin_config { 173 unsigned int func; 174 unsigned long *configs; 175 unsigned int nconfigs; 176 }; 177 178 /** 179 * struct rockchip_pin_group: represent group of pins of a pinmux function. 180 * @name: name of the pin group, used to lookup the group. 181 * @pins: the pins included in this group. 182 * @npins: number of pins included in this group. 183 * @func: the mux function number to be programmed when selected. 184 * @configs: the config values to be set for each pin 185 * @nconfigs: number of configs for each pin 186 */ 187 struct rockchip_pin_group { 188 const char *name; 189 unsigned int npins; 190 unsigned int *pins; 191 struct rockchip_pin_config *data; 192 }; 193 194 /** 195 * struct rockchip_pmx_func: represent a pin function. 196 * @name: name of the pin function, used to lookup the function. 197 * @groups: one or more names of pin groups that provide this function. 198 * @num_groups: number of groups included in @groups. 199 */ 200 struct rockchip_pmx_func { 201 const char *name; 202 const char **groups; 203 u8 ngroups; 204 }; 205 206 struct rockchip_pinctrl { 207 struct regmap *regmap_base; 208 int reg_size; 209 struct regmap *regmap_pull; 210 struct regmap *regmap_pmu; 211 struct device *dev; 212 struct rockchip_pin_ctrl *ctrl; 213 struct pinctrl_desc pctl; 214 struct pinctrl_dev *pctl_dev; 215 struct rockchip_pin_group *groups; 216 unsigned int ngroups; 217 struct rockchip_pmx_func *functions; 218 unsigned int nfunctions; 219 }; 220 221 static struct regmap_config rockchip_regmap_config = { 222 .reg_bits = 32, 223 .val_bits = 32, 224 .reg_stride = 4, 225 }; 226 227 static const inline struct rockchip_pin_group *pinctrl_name_to_group( 228 const struct rockchip_pinctrl *info, 229 const char *name) 230 { 231 int i; 232 233 for (i = 0; i < info->ngroups; i++) { 234 if (!strcmp(info->groups[i].name, name)) 235 return &info->groups[i]; 236 } 237 238 return NULL; 239 } 240 241 /* 242 * given a pin number that is local to a pin controller, find out the pin bank 243 * and the register base of the pin bank. 244 */ 245 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 246 unsigned pin) 247 { 248 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 249 250 while (pin >= (b->pin_base + b->nr_pins)) 251 b++; 252 253 return b; 254 } 255 256 static struct rockchip_pin_bank *bank_num_to_bank( 257 struct rockchip_pinctrl *info, 258 unsigned num) 259 { 260 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 261 int i; 262 263 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 264 if (b->bank_num == num) 265 return b; 266 } 267 268 return ERR_PTR(-EINVAL); 269 } 270 271 /* 272 * Pinctrl_ops handling 273 */ 274 275 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 276 { 277 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 278 279 return info->ngroups; 280 } 281 282 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 283 unsigned selector) 284 { 285 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 286 287 return info->groups[selector].name; 288 } 289 290 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 291 unsigned selector, const unsigned **pins, 292 unsigned *npins) 293 { 294 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 295 296 if (selector >= info->ngroups) 297 return -EINVAL; 298 299 *pins = info->groups[selector].pins; 300 *npins = info->groups[selector].npins; 301 302 return 0; 303 } 304 305 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 306 struct device_node *np, 307 struct pinctrl_map **map, unsigned *num_maps) 308 { 309 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 310 const struct rockchip_pin_group *grp; 311 struct pinctrl_map *new_map; 312 struct device_node *parent; 313 int map_num = 1; 314 int i; 315 316 /* 317 * first find the group of this node and check if we need to create 318 * config maps for pins 319 */ 320 grp = pinctrl_name_to_group(info, np->name); 321 if (!grp) { 322 dev_err(info->dev, "unable to find group for node %s\n", 323 np->name); 324 return -EINVAL; 325 } 326 327 map_num += grp->npins; 328 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, 329 GFP_KERNEL); 330 if (!new_map) 331 return -ENOMEM; 332 333 *map = new_map; 334 *num_maps = map_num; 335 336 /* create mux map */ 337 parent = of_get_parent(np); 338 if (!parent) { 339 devm_kfree(pctldev->dev, new_map); 340 return -EINVAL; 341 } 342 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 343 new_map[0].data.mux.function = parent->name; 344 new_map[0].data.mux.group = np->name; 345 of_node_put(parent); 346 347 /* create config map */ 348 new_map++; 349 for (i = 0; i < grp->npins; i++) { 350 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 351 new_map[i].data.configs.group_or_pin = 352 pin_get_name(pctldev, grp->pins[i]); 353 new_map[i].data.configs.configs = grp->data[i].configs; 354 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 355 } 356 357 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 358 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 359 360 return 0; 361 } 362 363 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 364 struct pinctrl_map *map, unsigned num_maps) 365 { 366 } 367 368 static const struct pinctrl_ops rockchip_pctrl_ops = { 369 .get_groups_count = rockchip_get_groups_count, 370 .get_group_name = rockchip_get_group_name, 371 .get_group_pins = rockchip_get_group_pins, 372 .dt_node_to_map = rockchip_dt_node_to_map, 373 .dt_free_map = rockchip_dt_free_map, 374 }; 375 376 /* 377 * Hardware access 378 */ 379 380 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 381 { 382 struct rockchip_pinctrl *info = bank->drvdata; 383 int iomux_num = (pin / 8); 384 struct regmap *regmap; 385 unsigned int val; 386 int reg, ret, mask; 387 u8 bit; 388 389 if (iomux_num > 3) 390 return -EINVAL; 391 392 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 393 dev_err(info->dev, "pin %d is unrouted\n", pin); 394 return -EINVAL; 395 } 396 397 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 398 return RK_FUNC_GPIO; 399 400 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 401 ? info->regmap_pmu : info->regmap_base; 402 403 /* get basic quadrupel of mux registers and the correct reg inside */ 404 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; 405 reg = bank->iomux[iomux_num].offset; 406 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { 407 if ((pin % 8) >= 4) 408 reg += 0x4; 409 bit = (pin % 4) * 4; 410 } else { 411 bit = (pin % 8) * 2; 412 } 413 414 ret = regmap_read(regmap, reg, &val); 415 if (ret) 416 return ret; 417 418 return ((val >> bit) & mask); 419 } 420 421 /* 422 * Set a new mux function for a pin. 423 * 424 * The register is divided into the upper and lower 16 bit. When changing 425 * a value, the previous register value is not read and changed. Instead 426 * it seems the changed bits are marked in the upper 16 bit, while the 427 * changed value gets set in the same offset in the lower 16 bit. 428 * All pin settings seem to be 2 bit wide in both the upper and lower 429 * parts. 430 * @bank: pin bank to change 431 * @pin: pin to change 432 * @mux: new mux function to set 433 */ 434 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 435 { 436 struct rockchip_pinctrl *info = bank->drvdata; 437 int iomux_num = (pin / 8); 438 struct regmap *regmap; 439 int reg, ret, mask; 440 unsigned long flags; 441 u8 bit; 442 u32 data, rmask; 443 444 if (iomux_num > 3) 445 return -EINVAL; 446 447 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 448 dev_err(info->dev, "pin %d is unrouted\n", pin); 449 return -EINVAL; 450 } 451 452 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 453 if (mux != RK_FUNC_GPIO) { 454 dev_err(info->dev, 455 "pin %d only supports a gpio mux\n", pin); 456 return -ENOTSUPP; 457 } else { 458 return 0; 459 } 460 } 461 462 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 463 bank->bank_num, pin, mux); 464 465 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 466 ? info->regmap_pmu : info->regmap_base; 467 468 /* get basic quadrupel of mux registers and the correct reg inside */ 469 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; 470 reg = bank->iomux[iomux_num].offset; 471 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { 472 if ((pin % 8) >= 4) 473 reg += 0x4; 474 bit = (pin % 4) * 4; 475 } else { 476 bit = (pin % 8) * 2; 477 } 478 479 spin_lock_irqsave(&bank->slock, flags); 480 481 data = (mask << (bit + 16)); 482 rmask = data | (data >> 16); 483 data |= (mux & mask) << bit; 484 ret = regmap_update_bits(regmap, reg, rmask, data); 485 486 spin_unlock_irqrestore(&bank->slock, flags); 487 488 return ret; 489 } 490 491 #define RK2928_PULL_OFFSET 0x118 492 #define RK2928_PULL_PINS_PER_REG 16 493 #define RK2928_PULL_BANK_STRIDE 8 494 495 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 496 int pin_num, struct regmap **regmap, 497 int *reg, u8 *bit) 498 { 499 struct rockchip_pinctrl *info = bank->drvdata; 500 501 *regmap = info->regmap_base; 502 *reg = RK2928_PULL_OFFSET; 503 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 504 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 505 506 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 507 }; 508 509 #define RK3188_PULL_OFFSET 0x164 510 #define RK3188_PULL_BITS_PER_PIN 2 511 #define RK3188_PULL_PINS_PER_REG 8 512 #define RK3188_PULL_BANK_STRIDE 16 513 #define RK3188_PULL_PMU_OFFSET 0x64 514 515 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 516 int pin_num, struct regmap **regmap, 517 int *reg, u8 *bit) 518 { 519 struct rockchip_pinctrl *info = bank->drvdata; 520 521 /* The first 12 pins of the first bank are located elsewhere */ 522 if (bank->bank_num == 0 && pin_num < 12) { 523 *regmap = info->regmap_pmu ? info->regmap_pmu 524 : bank->regmap_pull; 525 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 526 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 527 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 528 *bit *= RK3188_PULL_BITS_PER_PIN; 529 } else { 530 *regmap = info->regmap_pull ? info->regmap_pull 531 : info->regmap_base; 532 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 533 534 /* correct the offset, as it is the 2nd pull register */ 535 *reg -= 4; 536 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 537 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 538 539 /* 540 * The bits in these registers have an inverse ordering 541 * with the lowest pin being in bits 15:14 and the highest 542 * pin in bits 1:0 543 */ 544 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 545 *bit *= RK3188_PULL_BITS_PER_PIN; 546 } 547 } 548 549 #define RK3288_PULL_OFFSET 0x140 550 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 551 int pin_num, struct regmap **regmap, 552 int *reg, u8 *bit) 553 { 554 struct rockchip_pinctrl *info = bank->drvdata; 555 556 /* The first 24 pins of the first bank are located in PMU */ 557 if (bank->bank_num == 0) { 558 *regmap = info->regmap_pmu; 559 *reg = RK3188_PULL_PMU_OFFSET; 560 561 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 562 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 563 *bit *= RK3188_PULL_BITS_PER_PIN; 564 } else { 565 *regmap = info->regmap_base; 566 *reg = RK3288_PULL_OFFSET; 567 568 /* correct the offset, as we're starting with the 2nd bank */ 569 *reg -= 0x10; 570 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 571 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 572 573 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 574 *bit *= RK3188_PULL_BITS_PER_PIN; 575 } 576 } 577 578 #define RK3288_DRV_PMU_OFFSET 0x70 579 #define RK3288_DRV_GRF_OFFSET 0x1c0 580 #define RK3288_DRV_BITS_PER_PIN 2 581 #define RK3288_DRV_PINS_PER_REG 8 582 #define RK3288_DRV_BANK_STRIDE 16 583 584 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 585 int pin_num, struct regmap **regmap, 586 int *reg, u8 *bit) 587 { 588 struct rockchip_pinctrl *info = bank->drvdata; 589 590 /* The first 24 pins of the first bank are located in PMU */ 591 if (bank->bank_num == 0) { 592 *regmap = info->regmap_pmu; 593 *reg = RK3288_DRV_PMU_OFFSET; 594 595 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 596 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 597 *bit *= RK3288_DRV_BITS_PER_PIN; 598 } else { 599 *regmap = info->regmap_base; 600 *reg = RK3288_DRV_GRF_OFFSET; 601 602 /* correct the offset, as we're starting with the 2nd bank */ 603 *reg -= 0x10; 604 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 605 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 606 607 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 608 *bit *= RK3288_DRV_BITS_PER_PIN; 609 } 610 } 611 612 #define RK3228_PULL_OFFSET 0x100 613 614 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 615 int pin_num, struct regmap **regmap, 616 int *reg, u8 *bit) 617 { 618 struct rockchip_pinctrl *info = bank->drvdata; 619 620 *regmap = info->regmap_base; 621 *reg = RK3228_PULL_OFFSET; 622 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 623 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 624 625 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 626 *bit *= RK3188_PULL_BITS_PER_PIN; 627 } 628 629 #define RK3228_DRV_GRF_OFFSET 0x200 630 631 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 632 int pin_num, struct regmap **regmap, 633 int *reg, u8 *bit) 634 { 635 struct rockchip_pinctrl *info = bank->drvdata; 636 637 *regmap = info->regmap_base; 638 *reg = RK3228_DRV_GRF_OFFSET; 639 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 640 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 641 642 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 643 *bit *= RK3288_DRV_BITS_PER_PIN; 644 } 645 646 #define RK3368_PULL_GRF_OFFSET 0x100 647 #define RK3368_PULL_PMU_OFFSET 0x10 648 649 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 650 int pin_num, struct regmap **regmap, 651 int *reg, u8 *bit) 652 { 653 struct rockchip_pinctrl *info = bank->drvdata; 654 655 /* The first 32 pins of the first bank are located in PMU */ 656 if (bank->bank_num == 0) { 657 *regmap = info->regmap_pmu; 658 *reg = RK3368_PULL_PMU_OFFSET; 659 660 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 661 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 662 *bit *= RK3188_PULL_BITS_PER_PIN; 663 } else { 664 *regmap = info->regmap_base; 665 *reg = RK3368_PULL_GRF_OFFSET; 666 667 /* correct the offset, as we're starting with the 2nd bank */ 668 *reg -= 0x10; 669 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 670 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 671 672 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 673 *bit *= RK3188_PULL_BITS_PER_PIN; 674 } 675 } 676 677 #define RK3368_DRV_PMU_OFFSET 0x20 678 #define RK3368_DRV_GRF_OFFSET 0x200 679 680 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 681 int pin_num, struct regmap **regmap, 682 int *reg, u8 *bit) 683 { 684 struct rockchip_pinctrl *info = bank->drvdata; 685 686 /* The first 32 pins of the first bank are located in PMU */ 687 if (bank->bank_num == 0) { 688 *regmap = info->regmap_pmu; 689 *reg = RK3368_DRV_PMU_OFFSET; 690 691 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 692 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 693 *bit *= RK3288_DRV_BITS_PER_PIN; 694 } else { 695 *regmap = info->regmap_base; 696 *reg = RK3368_DRV_GRF_OFFSET; 697 698 /* correct the offset, as we're starting with the 2nd bank */ 699 *reg -= 0x10; 700 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 701 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 702 703 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 704 *bit *= RK3288_DRV_BITS_PER_PIN; 705 } 706 } 707 708 static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 }; 709 710 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 711 int pin_num) 712 { 713 struct rockchip_pinctrl *info = bank->drvdata; 714 struct rockchip_pin_ctrl *ctrl = info->ctrl; 715 struct regmap *regmap; 716 int reg, ret; 717 u32 data; 718 u8 bit; 719 720 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 721 722 ret = regmap_read(regmap, reg, &data); 723 if (ret) 724 return ret; 725 726 data >>= bit; 727 data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1; 728 729 return rockchip_perpin_drv_list[data]; 730 } 731 732 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 733 int pin_num, int strength) 734 { 735 struct rockchip_pinctrl *info = bank->drvdata; 736 struct rockchip_pin_ctrl *ctrl = info->ctrl; 737 struct regmap *regmap; 738 unsigned long flags; 739 int reg, ret, i; 740 u32 data, rmask; 741 u8 bit; 742 743 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 744 745 ret = -EINVAL; 746 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list); i++) { 747 if (rockchip_perpin_drv_list[i] == strength) { 748 ret = i; 749 break; 750 } 751 } 752 753 if (ret < 0) { 754 dev_err(info->dev, "unsupported driver strength %d\n", 755 strength); 756 return ret; 757 } 758 759 spin_lock_irqsave(&bank->slock, flags); 760 761 /* enable the write to the equivalent lower bits */ 762 data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16); 763 rmask = data | (data >> 16); 764 data |= (ret << bit); 765 766 ret = regmap_update_bits(regmap, reg, rmask, data); 767 spin_unlock_irqrestore(&bank->slock, flags); 768 769 return ret; 770 } 771 772 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 773 { 774 struct rockchip_pinctrl *info = bank->drvdata; 775 struct rockchip_pin_ctrl *ctrl = info->ctrl; 776 struct regmap *regmap; 777 int reg, ret; 778 u8 bit; 779 u32 data; 780 781 /* rk3066b does support any pulls */ 782 if (ctrl->type == RK3066B) 783 return PIN_CONFIG_BIAS_DISABLE; 784 785 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 786 787 ret = regmap_read(regmap, reg, &data); 788 if (ret) 789 return ret; 790 791 switch (ctrl->type) { 792 case RK2928: 793 return !(data & BIT(bit)) 794 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 795 : PIN_CONFIG_BIAS_DISABLE; 796 case RK3188: 797 case RK3288: 798 case RK3368: 799 data >>= bit; 800 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 801 802 switch (data) { 803 case 0: 804 return PIN_CONFIG_BIAS_DISABLE; 805 case 1: 806 return PIN_CONFIG_BIAS_PULL_UP; 807 case 2: 808 return PIN_CONFIG_BIAS_PULL_DOWN; 809 case 3: 810 return PIN_CONFIG_BIAS_BUS_HOLD; 811 } 812 813 dev_err(info->dev, "unknown pull setting\n"); 814 return -EIO; 815 default: 816 dev_err(info->dev, "unsupported pinctrl type\n"); 817 return -EINVAL; 818 }; 819 } 820 821 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 822 int pin_num, int pull) 823 { 824 struct rockchip_pinctrl *info = bank->drvdata; 825 struct rockchip_pin_ctrl *ctrl = info->ctrl; 826 struct regmap *regmap; 827 int reg, ret; 828 unsigned long flags; 829 u8 bit; 830 u32 data, rmask; 831 832 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 833 bank->bank_num, pin_num, pull); 834 835 /* rk3066b does support any pulls */ 836 if (ctrl->type == RK3066B) 837 return pull ? -EINVAL : 0; 838 839 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 840 841 switch (ctrl->type) { 842 case RK2928: 843 spin_lock_irqsave(&bank->slock, flags); 844 845 data = BIT(bit + 16); 846 if (pull == PIN_CONFIG_BIAS_DISABLE) 847 data |= BIT(bit); 848 ret = regmap_write(regmap, reg, data); 849 850 spin_unlock_irqrestore(&bank->slock, flags); 851 break; 852 case RK3188: 853 case RK3288: 854 case RK3368: 855 spin_lock_irqsave(&bank->slock, flags); 856 857 /* enable the write to the equivalent lower bits */ 858 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 859 rmask = data | (data >> 16); 860 861 switch (pull) { 862 case PIN_CONFIG_BIAS_DISABLE: 863 break; 864 case PIN_CONFIG_BIAS_PULL_UP: 865 data |= (1 << bit); 866 break; 867 case PIN_CONFIG_BIAS_PULL_DOWN: 868 data |= (2 << bit); 869 break; 870 case PIN_CONFIG_BIAS_BUS_HOLD: 871 data |= (3 << bit); 872 break; 873 default: 874 spin_unlock_irqrestore(&bank->slock, flags); 875 dev_err(info->dev, "unsupported pull setting %d\n", 876 pull); 877 return -EINVAL; 878 } 879 880 ret = regmap_update_bits(regmap, reg, rmask, data); 881 882 spin_unlock_irqrestore(&bank->slock, flags); 883 break; 884 default: 885 dev_err(info->dev, "unsupported pinctrl type\n"); 886 return -EINVAL; 887 } 888 889 return ret; 890 } 891 892 /* 893 * Pinmux_ops handling 894 */ 895 896 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 897 { 898 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 899 900 return info->nfunctions; 901 } 902 903 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 904 unsigned selector) 905 { 906 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 907 908 return info->functions[selector].name; 909 } 910 911 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 912 unsigned selector, const char * const **groups, 913 unsigned * const num_groups) 914 { 915 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 916 917 *groups = info->functions[selector].groups; 918 *num_groups = info->functions[selector].ngroups; 919 920 return 0; 921 } 922 923 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 924 unsigned group) 925 { 926 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 927 const unsigned int *pins = info->groups[group].pins; 928 const struct rockchip_pin_config *data = info->groups[group].data; 929 struct rockchip_pin_bank *bank; 930 int cnt, ret = 0; 931 932 dev_dbg(info->dev, "enable function %s group %s\n", 933 info->functions[selector].name, info->groups[group].name); 934 935 /* 936 * for each pin in the pin group selected, program the correspoding pin 937 * pin function number in the config register. 938 */ 939 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 940 bank = pin_to_bank(info, pins[cnt]); 941 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 942 data[cnt].func); 943 if (ret) 944 break; 945 } 946 947 if (ret) { 948 /* revert the already done pin settings */ 949 for (cnt--; cnt >= 0; cnt--) 950 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 951 952 return ret; 953 } 954 955 return 0; 956 } 957 958 /* 959 * The calls to gpio_direction_output() and gpio_direction_input() 960 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 961 * function called from the gpiolib interface). 962 */ 963 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, 964 int pin, bool input) 965 { 966 struct rockchip_pin_bank *bank; 967 int ret; 968 unsigned long flags; 969 u32 data; 970 971 bank = gpiochip_get_data(chip); 972 973 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 974 if (ret < 0) 975 return ret; 976 977 clk_enable(bank->clk); 978 spin_lock_irqsave(&bank->slock, flags); 979 980 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 981 /* set bit to 1 for output, 0 for input */ 982 if (!input) 983 data |= BIT(pin); 984 else 985 data &= ~BIT(pin); 986 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 987 988 spin_unlock_irqrestore(&bank->slock, flags); 989 clk_disable(bank->clk); 990 991 return 0; 992 } 993 994 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 995 struct pinctrl_gpio_range *range, 996 unsigned offset, bool input) 997 { 998 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 999 struct gpio_chip *chip; 1000 int pin; 1001 1002 chip = range->gc; 1003 pin = offset - chip->base; 1004 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 1005 offset, range->name, pin, input ? "input" : "output"); 1006 1007 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, 1008 input); 1009 } 1010 1011 static const struct pinmux_ops rockchip_pmx_ops = { 1012 .get_functions_count = rockchip_pmx_get_funcs_count, 1013 .get_function_name = rockchip_pmx_get_func_name, 1014 .get_function_groups = rockchip_pmx_get_groups, 1015 .set_mux = rockchip_pmx_set, 1016 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 1017 }; 1018 1019 /* 1020 * Pinconf_ops handling 1021 */ 1022 1023 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 1024 enum pin_config_param pull) 1025 { 1026 switch (ctrl->type) { 1027 case RK2928: 1028 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 1029 pull == PIN_CONFIG_BIAS_DISABLE); 1030 case RK3066B: 1031 return pull ? false : true; 1032 case RK3188: 1033 case RK3288: 1034 case RK3368: 1035 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 1036 } 1037 1038 return false; 1039 } 1040 1041 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); 1042 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 1043 1044 /* set the pin config settings for a specified pin */ 1045 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1046 unsigned long *configs, unsigned num_configs) 1047 { 1048 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1049 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 1050 enum pin_config_param param; 1051 u16 arg; 1052 int i; 1053 int rc; 1054 1055 for (i = 0; i < num_configs; i++) { 1056 param = pinconf_to_config_param(configs[i]); 1057 arg = pinconf_to_config_argument(configs[i]); 1058 1059 switch (param) { 1060 case PIN_CONFIG_BIAS_DISABLE: 1061 rc = rockchip_set_pull(bank, pin - bank->pin_base, 1062 param); 1063 if (rc) 1064 return rc; 1065 break; 1066 case PIN_CONFIG_BIAS_PULL_UP: 1067 case PIN_CONFIG_BIAS_PULL_DOWN: 1068 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1069 case PIN_CONFIG_BIAS_BUS_HOLD: 1070 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 1071 return -ENOTSUPP; 1072 1073 if (!arg) 1074 return -EINVAL; 1075 1076 rc = rockchip_set_pull(bank, pin - bank->pin_base, 1077 param); 1078 if (rc) 1079 return rc; 1080 break; 1081 case PIN_CONFIG_OUTPUT: 1082 rockchip_gpio_set(&bank->gpio_chip, 1083 pin - bank->pin_base, arg); 1084 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, 1085 pin - bank->pin_base, false); 1086 if (rc) 1087 return rc; 1088 break; 1089 case PIN_CONFIG_DRIVE_STRENGTH: 1090 /* rk3288 is the first with per-pin drive-strength */ 1091 if (!info->ctrl->drv_calc_reg) 1092 return -ENOTSUPP; 1093 1094 rc = rockchip_set_drive_perpin(bank, 1095 pin - bank->pin_base, arg); 1096 if (rc < 0) 1097 return rc; 1098 break; 1099 default: 1100 return -ENOTSUPP; 1101 break; 1102 } 1103 } /* for each config */ 1104 1105 return 0; 1106 } 1107 1108 /* get the pin config settings for a specified pin */ 1109 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 1110 unsigned long *config) 1111 { 1112 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1113 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 1114 enum pin_config_param param = pinconf_to_config_param(*config); 1115 u16 arg; 1116 int rc; 1117 1118 switch (param) { 1119 case PIN_CONFIG_BIAS_DISABLE: 1120 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 1121 return -EINVAL; 1122 1123 arg = 0; 1124 break; 1125 case PIN_CONFIG_BIAS_PULL_UP: 1126 case PIN_CONFIG_BIAS_PULL_DOWN: 1127 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1128 case PIN_CONFIG_BIAS_BUS_HOLD: 1129 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 1130 return -ENOTSUPP; 1131 1132 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 1133 return -EINVAL; 1134 1135 arg = 1; 1136 break; 1137 case PIN_CONFIG_OUTPUT: 1138 rc = rockchip_get_mux(bank, pin - bank->pin_base); 1139 if (rc != RK_FUNC_GPIO) 1140 return -EINVAL; 1141 1142 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 1143 if (rc < 0) 1144 return rc; 1145 1146 arg = rc ? 1 : 0; 1147 break; 1148 case PIN_CONFIG_DRIVE_STRENGTH: 1149 /* rk3288 is the first with per-pin drive-strength */ 1150 if (!info->ctrl->drv_calc_reg) 1151 return -ENOTSUPP; 1152 1153 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 1154 if (rc < 0) 1155 return rc; 1156 1157 arg = rc; 1158 break; 1159 default: 1160 return -ENOTSUPP; 1161 break; 1162 } 1163 1164 *config = pinconf_to_config_packed(param, arg); 1165 1166 return 0; 1167 } 1168 1169 static const struct pinconf_ops rockchip_pinconf_ops = { 1170 .pin_config_get = rockchip_pinconf_get, 1171 .pin_config_set = rockchip_pinconf_set, 1172 .is_generic = true, 1173 }; 1174 1175 static const struct of_device_id rockchip_bank_match[] = { 1176 { .compatible = "rockchip,gpio-bank" }, 1177 { .compatible = "rockchip,rk3188-gpio-bank0" }, 1178 {}, 1179 }; 1180 1181 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 1182 struct device_node *np) 1183 { 1184 struct device_node *child; 1185 1186 for_each_child_of_node(np, child) { 1187 if (of_match_node(rockchip_bank_match, child)) 1188 continue; 1189 1190 info->nfunctions++; 1191 info->ngroups += of_get_child_count(child); 1192 } 1193 } 1194 1195 static int rockchip_pinctrl_parse_groups(struct device_node *np, 1196 struct rockchip_pin_group *grp, 1197 struct rockchip_pinctrl *info, 1198 u32 index) 1199 { 1200 struct rockchip_pin_bank *bank; 1201 int size; 1202 const __be32 *list; 1203 int num; 1204 int i, j; 1205 int ret; 1206 1207 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 1208 1209 /* Initialise group */ 1210 grp->name = np->name; 1211 1212 /* 1213 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 1214 * do sanity check and calculate pins number 1215 */ 1216 list = of_get_property(np, "rockchip,pins", &size); 1217 /* we do not check return since it's safe node passed down */ 1218 size /= sizeof(*list); 1219 if (!size || size % 4) { 1220 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 1221 return -EINVAL; 1222 } 1223 1224 grp->npins = size / 4; 1225 1226 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 1227 GFP_KERNEL); 1228 grp->data = devm_kzalloc(info->dev, grp->npins * 1229 sizeof(struct rockchip_pin_config), 1230 GFP_KERNEL); 1231 if (!grp->pins || !grp->data) 1232 return -ENOMEM; 1233 1234 for (i = 0, j = 0; i < size; i += 4, j++) { 1235 const __be32 *phandle; 1236 struct device_node *np_config; 1237 1238 num = be32_to_cpu(*list++); 1239 bank = bank_num_to_bank(info, num); 1240 if (IS_ERR(bank)) 1241 return PTR_ERR(bank); 1242 1243 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 1244 grp->data[j].func = be32_to_cpu(*list++); 1245 1246 phandle = list++; 1247 if (!phandle) 1248 return -EINVAL; 1249 1250 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 1251 ret = pinconf_generic_parse_dt_config(np_config, NULL, 1252 &grp->data[j].configs, &grp->data[j].nconfigs); 1253 if (ret) 1254 return ret; 1255 } 1256 1257 return 0; 1258 } 1259 1260 static int rockchip_pinctrl_parse_functions(struct device_node *np, 1261 struct rockchip_pinctrl *info, 1262 u32 index) 1263 { 1264 struct device_node *child; 1265 struct rockchip_pmx_func *func; 1266 struct rockchip_pin_group *grp; 1267 int ret; 1268 static u32 grp_index; 1269 u32 i = 0; 1270 1271 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 1272 1273 func = &info->functions[index]; 1274 1275 /* Initialise function */ 1276 func->name = np->name; 1277 func->ngroups = of_get_child_count(np); 1278 if (func->ngroups <= 0) 1279 return 0; 1280 1281 func->groups = devm_kzalloc(info->dev, 1282 func->ngroups * sizeof(char *), GFP_KERNEL); 1283 if (!func->groups) 1284 return -ENOMEM; 1285 1286 for_each_child_of_node(np, child) { 1287 func->groups[i] = child->name; 1288 grp = &info->groups[grp_index++]; 1289 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 1290 if (ret) { 1291 of_node_put(child); 1292 return ret; 1293 } 1294 } 1295 1296 return 0; 1297 } 1298 1299 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 1300 struct rockchip_pinctrl *info) 1301 { 1302 struct device *dev = &pdev->dev; 1303 struct device_node *np = dev->of_node; 1304 struct device_node *child; 1305 int ret; 1306 int i; 1307 1308 rockchip_pinctrl_child_count(info, np); 1309 1310 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1311 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 1312 1313 info->functions = devm_kzalloc(dev, info->nfunctions * 1314 sizeof(struct rockchip_pmx_func), 1315 GFP_KERNEL); 1316 if (!info->functions) { 1317 dev_err(dev, "failed to allocate memory for function list\n"); 1318 return -EINVAL; 1319 } 1320 1321 info->groups = devm_kzalloc(dev, info->ngroups * 1322 sizeof(struct rockchip_pin_group), 1323 GFP_KERNEL); 1324 if (!info->groups) { 1325 dev_err(dev, "failed allocate memory for ping group list\n"); 1326 return -EINVAL; 1327 } 1328 1329 i = 0; 1330 1331 for_each_child_of_node(np, child) { 1332 if (of_match_node(rockchip_bank_match, child)) 1333 continue; 1334 1335 ret = rockchip_pinctrl_parse_functions(child, info, i++); 1336 if (ret) { 1337 dev_err(&pdev->dev, "failed to parse function\n"); 1338 of_node_put(child); 1339 return ret; 1340 } 1341 } 1342 1343 return 0; 1344 } 1345 1346 static int rockchip_pinctrl_register(struct platform_device *pdev, 1347 struct rockchip_pinctrl *info) 1348 { 1349 struct pinctrl_desc *ctrldesc = &info->pctl; 1350 struct pinctrl_pin_desc *pindesc, *pdesc; 1351 struct rockchip_pin_bank *pin_bank; 1352 int pin, bank, ret; 1353 int k; 1354 1355 ctrldesc->name = "rockchip-pinctrl"; 1356 ctrldesc->owner = THIS_MODULE; 1357 ctrldesc->pctlops = &rockchip_pctrl_ops; 1358 ctrldesc->pmxops = &rockchip_pmx_ops; 1359 ctrldesc->confops = &rockchip_pinconf_ops; 1360 1361 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 1362 info->ctrl->nr_pins, GFP_KERNEL); 1363 if (!pindesc) { 1364 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); 1365 return -ENOMEM; 1366 } 1367 ctrldesc->pins = pindesc; 1368 ctrldesc->npins = info->ctrl->nr_pins; 1369 1370 pdesc = pindesc; 1371 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 1372 pin_bank = &info->ctrl->pin_banks[bank]; 1373 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 1374 pdesc->number = k; 1375 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 1376 pin_bank->name, pin); 1377 pdesc++; 1378 } 1379 } 1380 1381 ret = rockchip_pinctrl_parse_dt(pdev, info); 1382 if (ret) 1383 return ret; 1384 1385 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); 1386 if (IS_ERR(info->pctl_dev)) { 1387 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 1388 return PTR_ERR(info->pctl_dev); 1389 } 1390 1391 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 1392 pin_bank = &info->ctrl->pin_banks[bank]; 1393 pin_bank->grange.name = pin_bank->name; 1394 pin_bank->grange.id = bank; 1395 pin_bank->grange.pin_base = pin_bank->pin_base; 1396 pin_bank->grange.base = pin_bank->gpio_chip.base; 1397 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 1398 pin_bank->grange.gc = &pin_bank->gpio_chip; 1399 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 1400 } 1401 1402 return 0; 1403 } 1404 1405 /* 1406 * GPIO handling 1407 */ 1408 1409 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 1410 { 1411 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 1412 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 1413 unsigned long flags; 1414 u32 data; 1415 1416 clk_enable(bank->clk); 1417 spin_lock_irqsave(&bank->slock, flags); 1418 1419 data = readl(reg); 1420 data &= ~BIT(offset); 1421 if (value) 1422 data |= BIT(offset); 1423 writel(data, reg); 1424 1425 spin_unlock_irqrestore(&bank->slock, flags); 1426 clk_disable(bank->clk); 1427 } 1428 1429 /* 1430 * Returns the level of the pin for input direction and setting of the DR 1431 * register for output gpios. 1432 */ 1433 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 1434 { 1435 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 1436 u32 data; 1437 1438 clk_enable(bank->clk); 1439 data = readl(bank->reg_base + GPIO_EXT_PORT); 1440 clk_disable(bank->clk); 1441 data >>= offset; 1442 data &= 1; 1443 return data; 1444 } 1445 1446 /* 1447 * gpiolib gpio_direction_input callback function. The setting of the pin 1448 * mux function as 'gpio input' will be handled by the pinctrl susbsystem 1449 * interface. 1450 */ 1451 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 1452 { 1453 return pinctrl_gpio_direction_input(gc->base + offset); 1454 } 1455 1456 /* 1457 * gpiolib gpio_direction_output callback function. The setting of the pin 1458 * mux function as 'gpio output' will be handled by the pinctrl susbsystem 1459 * interface. 1460 */ 1461 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 1462 unsigned offset, int value) 1463 { 1464 rockchip_gpio_set(gc, offset, value); 1465 return pinctrl_gpio_direction_output(gc->base + offset); 1466 } 1467 1468 /* 1469 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 1470 * and a virtual IRQ, if not already present. 1471 */ 1472 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 1473 { 1474 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 1475 unsigned int virq; 1476 1477 if (!bank->domain) 1478 return -ENXIO; 1479 1480 virq = irq_create_mapping(bank->domain, offset); 1481 1482 return (virq) ? : -ENXIO; 1483 } 1484 1485 static const struct gpio_chip rockchip_gpiolib_chip = { 1486 .request = gpiochip_generic_request, 1487 .free = gpiochip_generic_free, 1488 .set = rockchip_gpio_set, 1489 .get = rockchip_gpio_get, 1490 .direction_input = rockchip_gpio_direction_input, 1491 .direction_output = rockchip_gpio_direction_output, 1492 .to_irq = rockchip_gpio_to_irq, 1493 .owner = THIS_MODULE, 1494 }; 1495 1496 /* 1497 * Interrupt handling 1498 */ 1499 1500 static void rockchip_irq_demux(struct irq_desc *desc) 1501 { 1502 struct irq_chip *chip = irq_desc_get_chip(desc); 1503 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 1504 u32 pend; 1505 1506 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 1507 1508 chained_irq_enter(chip, desc); 1509 1510 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 1511 1512 while (pend) { 1513 unsigned int irq, virq; 1514 1515 irq = __ffs(pend); 1516 pend &= ~BIT(irq); 1517 virq = irq_linear_revmap(bank->domain, irq); 1518 1519 if (!virq) { 1520 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 1521 continue; 1522 } 1523 1524 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 1525 1526 /* 1527 * Triggering IRQ on both rising and falling edge 1528 * needs manual intervention. 1529 */ 1530 if (bank->toggle_edge_mode & BIT(irq)) { 1531 u32 data, data_old, polarity; 1532 unsigned long flags; 1533 1534 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 1535 do { 1536 spin_lock_irqsave(&bank->slock, flags); 1537 1538 polarity = readl_relaxed(bank->reg_base + 1539 GPIO_INT_POLARITY); 1540 if (data & BIT(irq)) 1541 polarity &= ~BIT(irq); 1542 else 1543 polarity |= BIT(irq); 1544 writel(polarity, 1545 bank->reg_base + GPIO_INT_POLARITY); 1546 1547 spin_unlock_irqrestore(&bank->slock, flags); 1548 1549 data_old = data; 1550 data = readl_relaxed(bank->reg_base + 1551 GPIO_EXT_PORT); 1552 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 1553 } 1554 1555 generic_handle_irq(virq); 1556 } 1557 1558 chained_irq_exit(chip, desc); 1559 } 1560 1561 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 1562 { 1563 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1564 struct rockchip_pin_bank *bank = gc->private; 1565 u32 mask = BIT(d->hwirq); 1566 u32 polarity; 1567 u32 level; 1568 u32 data; 1569 unsigned long flags; 1570 int ret; 1571 1572 /* make sure the pin is configured as gpio input */ 1573 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 1574 if (ret < 0) 1575 return ret; 1576 1577 clk_enable(bank->clk); 1578 spin_lock_irqsave(&bank->slock, flags); 1579 1580 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 1581 data &= ~mask; 1582 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 1583 1584 spin_unlock_irqrestore(&bank->slock, flags); 1585 1586 if (type & IRQ_TYPE_EDGE_BOTH) 1587 irq_set_handler_locked(d, handle_edge_irq); 1588 else 1589 irq_set_handler_locked(d, handle_level_irq); 1590 1591 spin_lock_irqsave(&bank->slock, flags); 1592 irq_gc_lock(gc); 1593 1594 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 1595 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 1596 1597 switch (type) { 1598 case IRQ_TYPE_EDGE_BOTH: 1599 bank->toggle_edge_mode |= mask; 1600 level |= mask; 1601 1602 /* 1603 * Determine gpio state. If 1 next interrupt should be falling 1604 * otherwise rising. 1605 */ 1606 data = readl(bank->reg_base + GPIO_EXT_PORT); 1607 if (data & mask) 1608 polarity &= ~mask; 1609 else 1610 polarity |= mask; 1611 break; 1612 case IRQ_TYPE_EDGE_RISING: 1613 bank->toggle_edge_mode &= ~mask; 1614 level |= mask; 1615 polarity |= mask; 1616 break; 1617 case IRQ_TYPE_EDGE_FALLING: 1618 bank->toggle_edge_mode &= ~mask; 1619 level |= mask; 1620 polarity &= ~mask; 1621 break; 1622 case IRQ_TYPE_LEVEL_HIGH: 1623 bank->toggle_edge_mode &= ~mask; 1624 level &= ~mask; 1625 polarity |= mask; 1626 break; 1627 case IRQ_TYPE_LEVEL_LOW: 1628 bank->toggle_edge_mode &= ~mask; 1629 level &= ~mask; 1630 polarity &= ~mask; 1631 break; 1632 default: 1633 irq_gc_unlock(gc); 1634 spin_unlock_irqrestore(&bank->slock, flags); 1635 clk_disable(bank->clk); 1636 return -EINVAL; 1637 } 1638 1639 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 1640 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 1641 1642 irq_gc_unlock(gc); 1643 spin_unlock_irqrestore(&bank->slock, flags); 1644 clk_disable(bank->clk); 1645 1646 return 0; 1647 } 1648 1649 static void rockchip_irq_suspend(struct irq_data *d) 1650 { 1651 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1652 struct rockchip_pin_bank *bank = gc->private; 1653 1654 clk_enable(bank->clk); 1655 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 1656 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 1657 clk_disable(bank->clk); 1658 } 1659 1660 static void rockchip_irq_resume(struct irq_data *d) 1661 { 1662 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1663 struct rockchip_pin_bank *bank = gc->private; 1664 1665 clk_enable(bank->clk); 1666 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 1667 clk_disable(bank->clk); 1668 } 1669 1670 static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d) 1671 { 1672 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1673 struct rockchip_pin_bank *bank = gc->private; 1674 1675 clk_enable(bank->clk); 1676 irq_gc_mask_clr_bit(d); 1677 } 1678 1679 void rockchip_irq_gc_mask_set_bit(struct irq_data *d) 1680 { 1681 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1682 struct rockchip_pin_bank *bank = gc->private; 1683 1684 irq_gc_mask_set_bit(d); 1685 clk_disable(bank->clk); 1686 } 1687 1688 static int rockchip_interrupts_register(struct platform_device *pdev, 1689 struct rockchip_pinctrl *info) 1690 { 1691 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1692 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1693 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 1694 struct irq_chip_generic *gc; 1695 int ret; 1696 int i, j; 1697 1698 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1699 if (!bank->valid) { 1700 dev_warn(&pdev->dev, "bank %s is not valid\n", 1701 bank->name); 1702 continue; 1703 } 1704 1705 ret = clk_enable(bank->clk); 1706 if (ret) { 1707 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", 1708 bank->name); 1709 continue; 1710 } 1711 1712 bank->domain = irq_domain_add_linear(bank->of_node, 32, 1713 &irq_generic_chip_ops, NULL); 1714 if (!bank->domain) { 1715 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 1716 bank->name); 1717 clk_disable(bank->clk); 1718 continue; 1719 } 1720 1721 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 1722 "rockchip_gpio_irq", handle_level_irq, 1723 clr, 0, IRQ_GC_INIT_MASK_CACHE); 1724 if (ret) { 1725 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 1726 bank->name); 1727 irq_domain_remove(bank->domain); 1728 clk_disable(bank->clk); 1729 continue; 1730 } 1731 1732 /* 1733 * Linux assumes that all interrupts start out disabled/masked. 1734 * Our driver only uses the concept of masked and always keeps 1735 * things enabled, so for us that's all masked and all enabled. 1736 */ 1737 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); 1738 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); 1739 1740 gc = irq_get_domain_generic_chip(bank->domain, 0); 1741 gc->reg_base = bank->reg_base; 1742 gc->private = bank; 1743 gc->chip_types[0].regs.mask = GPIO_INTMASK; 1744 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 1745 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 1746 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit; 1747 gc->chip_types[0].chip.irq_unmask = 1748 rockchip_irq_gc_mask_clr_bit; 1749 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 1750 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 1751 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 1752 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 1753 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 1754 1755 irq_set_chained_handler_and_data(bank->irq, 1756 rockchip_irq_demux, bank); 1757 1758 /* map the gpio irqs here, when the clock is still running */ 1759 for (j = 0 ; j < 32 ; j++) 1760 irq_create_mapping(bank->domain, j); 1761 1762 clk_disable(bank->clk); 1763 } 1764 1765 return 0; 1766 } 1767 1768 static int rockchip_gpiolib_register(struct platform_device *pdev, 1769 struct rockchip_pinctrl *info) 1770 { 1771 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1772 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1773 struct gpio_chip *gc; 1774 int ret; 1775 int i; 1776 1777 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1778 if (!bank->valid) { 1779 dev_warn(&pdev->dev, "bank %s is not valid\n", 1780 bank->name); 1781 continue; 1782 } 1783 1784 bank->gpio_chip = rockchip_gpiolib_chip; 1785 1786 gc = &bank->gpio_chip; 1787 gc->base = bank->pin_base; 1788 gc->ngpio = bank->nr_pins; 1789 gc->parent = &pdev->dev; 1790 gc->of_node = bank->of_node; 1791 gc->label = bank->name; 1792 1793 ret = gpiochip_add_data(gc, bank); 1794 if (ret) { 1795 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 1796 gc->label, ret); 1797 goto fail; 1798 } 1799 } 1800 1801 rockchip_interrupts_register(pdev, info); 1802 1803 return 0; 1804 1805 fail: 1806 for (--i, --bank; i >= 0; --i, --bank) { 1807 if (!bank->valid) 1808 continue; 1809 gpiochip_remove(&bank->gpio_chip); 1810 } 1811 return ret; 1812 } 1813 1814 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 1815 struct rockchip_pinctrl *info) 1816 { 1817 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1818 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1819 int i; 1820 1821 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1822 if (!bank->valid) 1823 continue; 1824 gpiochip_remove(&bank->gpio_chip); 1825 } 1826 1827 return 0; 1828 } 1829 1830 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 1831 struct rockchip_pinctrl *info) 1832 { 1833 struct resource res; 1834 void __iomem *base; 1835 1836 if (of_address_to_resource(bank->of_node, 0, &res)) { 1837 dev_err(info->dev, "cannot find IO resource for bank\n"); 1838 return -ENOENT; 1839 } 1840 1841 bank->reg_base = devm_ioremap_resource(info->dev, &res); 1842 if (IS_ERR(bank->reg_base)) 1843 return PTR_ERR(bank->reg_base); 1844 1845 /* 1846 * special case, where parts of the pull setting-registers are 1847 * part of the PMU register space 1848 */ 1849 if (of_device_is_compatible(bank->of_node, 1850 "rockchip,rk3188-gpio-bank0")) { 1851 struct device_node *node; 1852 1853 node = of_parse_phandle(bank->of_node->parent, 1854 "rockchip,pmu", 0); 1855 if (!node) { 1856 if (of_address_to_resource(bank->of_node, 1, &res)) { 1857 dev_err(info->dev, "cannot find IO resource for bank\n"); 1858 return -ENOENT; 1859 } 1860 1861 base = devm_ioremap_resource(info->dev, &res); 1862 if (IS_ERR(base)) 1863 return PTR_ERR(base); 1864 rockchip_regmap_config.max_register = 1865 resource_size(&res) - 4; 1866 rockchip_regmap_config.name = 1867 "rockchip,rk3188-gpio-bank0-pull"; 1868 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 1869 base, 1870 &rockchip_regmap_config); 1871 } 1872 } 1873 1874 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 1875 1876 bank->clk = of_clk_get(bank->of_node, 0); 1877 if (IS_ERR(bank->clk)) 1878 return PTR_ERR(bank->clk); 1879 1880 return clk_prepare(bank->clk); 1881 } 1882 1883 static const struct of_device_id rockchip_pinctrl_dt_match[]; 1884 1885 /* retrieve the soc specific data */ 1886 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 1887 struct rockchip_pinctrl *d, 1888 struct platform_device *pdev) 1889 { 1890 const struct of_device_id *match; 1891 struct device_node *node = pdev->dev.of_node; 1892 struct device_node *np; 1893 struct rockchip_pin_ctrl *ctrl; 1894 struct rockchip_pin_bank *bank; 1895 int grf_offs, pmu_offs, i, j; 1896 1897 match = of_match_node(rockchip_pinctrl_dt_match, node); 1898 ctrl = (struct rockchip_pin_ctrl *)match->data; 1899 1900 for_each_child_of_node(node, np) { 1901 if (!of_find_property(np, "gpio-controller", NULL)) 1902 continue; 1903 1904 bank = ctrl->pin_banks; 1905 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1906 if (!strcmp(bank->name, np->name)) { 1907 bank->of_node = np; 1908 1909 if (!rockchip_get_bank_data(bank, d)) 1910 bank->valid = true; 1911 1912 break; 1913 } 1914 } 1915 } 1916 1917 grf_offs = ctrl->grf_mux_offset; 1918 pmu_offs = ctrl->pmu_mux_offset; 1919 bank = ctrl->pin_banks; 1920 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1921 int bank_pins = 0; 1922 1923 spin_lock_init(&bank->slock); 1924 bank->drvdata = d; 1925 bank->pin_base = ctrl->nr_pins; 1926 ctrl->nr_pins += bank->nr_pins; 1927 1928 /* calculate iomux offsets */ 1929 for (j = 0; j < 4; j++) { 1930 struct rockchip_iomux *iom = &bank->iomux[j]; 1931 int inc; 1932 1933 if (bank_pins >= bank->nr_pins) 1934 break; 1935 1936 /* preset offset value, set new start value */ 1937 if (iom->offset >= 0) { 1938 if (iom->type & IOMUX_SOURCE_PMU) 1939 pmu_offs = iom->offset; 1940 else 1941 grf_offs = iom->offset; 1942 } else { /* set current offset */ 1943 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 1944 pmu_offs : grf_offs; 1945 } 1946 1947 dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n", 1948 i, j, iom->offset); 1949 1950 /* 1951 * Increase offset according to iomux width. 1952 * 4bit iomux'es are spread over two registers. 1953 */ 1954 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4; 1955 if (iom->type & IOMUX_SOURCE_PMU) 1956 pmu_offs += inc; 1957 else 1958 grf_offs += inc; 1959 1960 bank_pins += 8; 1961 } 1962 } 1963 1964 return ctrl; 1965 } 1966 1967 #define RK3288_GRF_GPIO6C_IOMUX 0x64 1968 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 1969 1970 static u32 rk3288_grf_gpio6c_iomux; 1971 1972 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 1973 { 1974 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 1975 int ret = pinctrl_force_sleep(info->pctl_dev); 1976 1977 if (ret) 1978 return ret; 1979 1980 /* 1981 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 1982 * the setting here, and restore it at resume. 1983 */ 1984 if (info->ctrl->type == RK3288) { 1985 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 1986 &rk3288_grf_gpio6c_iomux); 1987 if (ret) { 1988 pinctrl_force_default(info->pctl_dev); 1989 return ret; 1990 } 1991 } 1992 1993 return 0; 1994 } 1995 1996 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 1997 { 1998 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 1999 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 2000 rk3288_grf_gpio6c_iomux | 2001 GPIO6C6_SEL_WRITE_ENABLE); 2002 2003 if (ret) 2004 return ret; 2005 2006 return pinctrl_force_default(info->pctl_dev); 2007 } 2008 2009 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 2010 rockchip_pinctrl_resume); 2011 2012 static int rockchip_pinctrl_probe(struct platform_device *pdev) 2013 { 2014 struct rockchip_pinctrl *info; 2015 struct device *dev = &pdev->dev; 2016 struct rockchip_pin_ctrl *ctrl; 2017 struct device_node *np = pdev->dev.of_node, *node; 2018 struct resource *res; 2019 void __iomem *base; 2020 int ret; 2021 2022 if (!dev->of_node) { 2023 dev_err(dev, "device tree node not found\n"); 2024 return -ENODEV; 2025 } 2026 2027 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); 2028 if (!info) 2029 return -ENOMEM; 2030 2031 info->dev = dev; 2032 2033 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 2034 if (!ctrl) { 2035 dev_err(dev, "driver data not available\n"); 2036 return -EINVAL; 2037 } 2038 info->ctrl = ctrl; 2039 2040 node = of_parse_phandle(np, "rockchip,grf", 0); 2041 if (node) { 2042 info->regmap_base = syscon_node_to_regmap(node); 2043 if (IS_ERR(info->regmap_base)) 2044 return PTR_ERR(info->regmap_base); 2045 } else { 2046 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2047 base = devm_ioremap_resource(&pdev->dev, res); 2048 if (IS_ERR(base)) 2049 return PTR_ERR(base); 2050 2051 rockchip_regmap_config.max_register = resource_size(res) - 4; 2052 rockchip_regmap_config.name = "rockchip,pinctrl"; 2053 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 2054 &rockchip_regmap_config); 2055 2056 /* to check for the old dt-bindings */ 2057 info->reg_size = resource_size(res); 2058 2059 /* Honor the old binding, with pull registers as 2nd resource */ 2060 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 2061 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2062 base = devm_ioremap_resource(&pdev->dev, res); 2063 if (IS_ERR(base)) 2064 return PTR_ERR(base); 2065 2066 rockchip_regmap_config.max_register = 2067 resource_size(res) - 4; 2068 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 2069 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 2070 base, 2071 &rockchip_regmap_config); 2072 } 2073 } 2074 2075 /* try to find the optional reference to the pmu syscon */ 2076 node = of_parse_phandle(np, "rockchip,pmu", 0); 2077 if (node) { 2078 info->regmap_pmu = syscon_node_to_regmap(node); 2079 if (IS_ERR(info->regmap_pmu)) 2080 return PTR_ERR(info->regmap_pmu); 2081 } 2082 2083 ret = rockchip_gpiolib_register(pdev, info); 2084 if (ret) 2085 return ret; 2086 2087 ret = rockchip_pinctrl_register(pdev, info); 2088 if (ret) { 2089 rockchip_gpiolib_unregister(pdev, info); 2090 return ret; 2091 } 2092 2093 platform_set_drvdata(pdev, info); 2094 2095 return 0; 2096 } 2097 2098 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2099 PIN_BANK(0, 32, "gpio0"), 2100 PIN_BANK(1, 32, "gpio1"), 2101 PIN_BANK(2, 32, "gpio2"), 2102 PIN_BANK(3, 32, "gpio3"), 2103 }; 2104 2105 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2106 .pin_banks = rk2928_pin_banks, 2107 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2108 .label = "RK2928-GPIO", 2109 .type = RK2928, 2110 .grf_mux_offset = 0xa8, 2111 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2112 }; 2113 2114 static struct rockchip_pin_bank rk3036_pin_banks[] = { 2115 PIN_BANK(0, 32, "gpio0"), 2116 PIN_BANK(1, 32, "gpio1"), 2117 PIN_BANK(2, 32, "gpio2"), 2118 }; 2119 2120 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 2121 .pin_banks = rk3036_pin_banks, 2122 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 2123 .label = "RK3036-GPIO", 2124 .type = RK2928, 2125 .grf_mux_offset = 0xa8, 2126 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2127 }; 2128 2129 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2130 PIN_BANK(0, 32, "gpio0"), 2131 PIN_BANK(1, 32, "gpio1"), 2132 PIN_BANK(2, 32, "gpio2"), 2133 PIN_BANK(3, 32, "gpio3"), 2134 PIN_BANK(4, 32, "gpio4"), 2135 PIN_BANK(6, 16, "gpio6"), 2136 }; 2137 2138 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 2139 .pin_banks = rk3066a_pin_banks, 2140 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 2141 .label = "RK3066a-GPIO", 2142 .type = RK2928, 2143 .grf_mux_offset = 0xa8, 2144 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2145 }; 2146 2147 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 2148 PIN_BANK(0, 32, "gpio0"), 2149 PIN_BANK(1, 32, "gpio1"), 2150 PIN_BANK(2, 32, "gpio2"), 2151 PIN_BANK(3, 32, "gpio3"), 2152 }; 2153 2154 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 2155 .pin_banks = rk3066b_pin_banks, 2156 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 2157 .label = "RK3066b-GPIO", 2158 .type = RK3066B, 2159 .grf_mux_offset = 0x60, 2160 }; 2161 2162 static struct rockchip_pin_bank rk3188_pin_banks[] = { 2163 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 2164 PIN_BANK(1, 32, "gpio1"), 2165 PIN_BANK(2, 32, "gpio2"), 2166 PIN_BANK(3, 32, "gpio3"), 2167 }; 2168 2169 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 2170 .pin_banks = rk3188_pin_banks, 2171 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 2172 .label = "RK3188-GPIO", 2173 .type = RK3188, 2174 .grf_mux_offset = 0x60, 2175 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 2176 }; 2177 2178 static struct rockchip_pin_bank rk3228_pin_banks[] = { 2179 PIN_BANK(0, 32, "gpio0"), 2180 PIN_BANK(1, 32, "gpio1"), 2181 PIN_BANK(2, 32, "gpio2"), 2182 PIN_BANK(3, 32, "gpio3"), 2183 }; 2184 2185 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 2186 .pin_banks = rk3228_pin_banks, 2187 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 2188 .label = "RK3228-GPIO", 2189 .type = RK3288, 2190 .grf_mux_offset = 0x0, 2191 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2192 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2193 }; 2194 2195 static struct rockchip_pin_bank rk3288_pin_banks[] = { 2196 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 2197 IOMUX_SOURCE_PMU, 2198 IOMUX_SOURCE_PMU, 2199 IOMUX_UNROUTED 2200 ), 2201 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 2202 IOMUX_UNROUTED, 2203 IOMUX_UNROUTED, 2204 0 2205 ), 2206 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 2207 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 2208 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 2209 IOMUX_WIDTH_4BIT, 2210 0, 2211 0 2212 ), 2213 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 2214 0, 2215 0, 2216 IOMUX_UNROUTED 2217 ), 2218 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 2219 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 2220 0, 2221 IOMUX_WIDTH_4BIT, 2222 IOMUX_UNROUTED 2223 ), 2224 PIN_BANK(8, 16, "gpio8"), 2225 }; 2226 2227 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 2228 .pin_banks = rk3288_pin_banks, 2229 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 2230 .label = "RK3288-GPIO", 2231 .type = RK3288, 2232 .grf_mux_offset = 0x0, 2233 .pmu_mux_offset = 0x84, 2234 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 2235 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 2236 }; 2237 2238 static struct rockchip_pin_bank rk3368_pin_banks[] = { 2239 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2240 IOMUX_SOURCE_PMU, 2241 IOMUX_SOURCE_PMU, 2242 IOMUX_SOURCE_PMU 2243 ), 2244 PIN_BANK(1, 32, "gpio1"), 2245 PIN_BANK(2, 32, "gpio2"), 2246 PIN_BANK(3, 32, "gpio3"), 2247 }; 2248 2249 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 2250 .pin_banks = rk3368_pin_banks, 2251 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 2252 .label = "RK3368-GPIO", 2253 .type = RK3368, 2254 .grf_mux_offset = 0x0, 2255 .pmu_mux_offset = 0x0, 2256 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 2257 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 2258 }; 2259 2260 2261 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 2262 { .compatible = "rockchip,rk2928-pinctrl", 2263 .data = (void *)&rk2928_pin_ctrl }, 2264 { .compatible = "rockchip,rk3036-pinctrl", 2265 .data = (void *)&rk3036_pin_ctrl }, 2266 { .compatible = "rockchip,rk3066a-pinctrl", 2267 .data = (void *)&rk3066a_pin_ctrl }, 2268 { .compatible = "rockchip,rk3066b-pinctrl", 2269 .data = (void *)&rk3066b_pin_ctrl }, 2270 { .compatible = "rockchip,rk3188-pinctrl", 2271 .data = (void *)&rk3188_pin_ctrl }, 2272 { .compatible = "rockchip,rk3228-pinctrl", 2273 .data = (void *)&rk3228_pin_ctrl }, 2274 { .compatible = "rockchip,rk3288-pinctrl", 2275 .data = (void *)&rk3288_pin_ctrl }, 2276 { .compatible = "rockchip,rk3368-pinctrl", 2277 .data = (void *)&rk3368_pin_ctrl }, 2278 {}, 2279 }; 2280 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 2281 2282 static struct platform_driver rockchip_pinctrl_driver = { 2283 .probe = rockchip_pinctrl_probe, 2284 .driver = { 2285 .name = "rockchip-pinctrl", 2286 .pm = &rockchip_pinctrl_dev_pm_ops, 2287 .of_match_table = rockchip_pinctrl_dt_match, 2288 }, 2289 }; 2290 2291 static int __init rockchip_pinctrl_drv_register(void) 2292 { 2293 return platform_driver_register(&rockchip_pinctrl_driver); 2294 } 2295 postcore_initcall(rockchip_pinctrl_drv_register); 2296 2297 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); 2298 MODULE_DESCRIPTION("Rockchip pinctrl driver"); 2299 MODULE_LICENSE("GPL v2"); 2300