1 /* 2 * Pinctrl driver for Rockchip SoCs 3 * 4 * Copyright (c) 2013 MundoReader S.L. 5 * Author: Heiko Stuebner <heiko@sntech.de> 6 * 7 * With some ideas taken from pinctrl-samsung: 8 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 9 * http://www.samsung.com 10 * Copyright (c) 2012 Linaro Ltd 11 * http://www.linaro.org 12 * 13 * and pinctrl-at91: 14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as published 18 * by the Free Software Foundation. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 */ 25 26 #include <linux/init.h> 27 #include <linux/platform_device.h> 28 #include <linux/io.h> 29 #include <linux/bitops.h> 30 #include <linux/gpio.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/pinctrl/machine.h> 34 #include <linux/pinctrl/pinconf.h> 35 #include <linux/pinctrl/pinctrl.h> 36 #include <linux/pinctrl/pinmux.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/irqchip/chained_irq.h> 39 #include <linux/clk.h> 40 #include <linux/regmap.h> 41 #include <linux/mfd/syscon.h> 42 #include <dt-bindings/pinctrl/rockchip.h> 43 44 #include "core.h" 45 #include "pinconf.h" 46 47 /* GPIO control registers */ 48 #define GPIO_SWPORT_DR 0x00 49 #define GPIO_SWPORT_DDR 0x04 50 #define GPIO_INTEN 0x30 51 #define GPIO_INTMASK 0x34 52 #define GPIO_INTTYPE_LEVEL 0x38 53 #define GPIO_INT_POLARITY 0x3c 54 #define GPIO_INT_STATUS 0x40 55 #define GPIO_INT_RAWSTATUS 0x44 56 #define GPIO_DEBOUNCE 0x48 57 #define GPIO_PORTS_EOI 0x4c 58 #define GPIO_EXT_PORT 0x50 59 #define GPIO_LS_SYNC 0x60 60 61 enum rockchip_pinctrl_type { 62 RV1108, 63 RK2928, 64 RK3066B, 65 RK3188, 66 RK3288, 67 RK3368, 68 RK3399, 69 }; 70 71 /** 72 * Encode variants of iomux registers into a type variable 73 */ 74 #define IOMUX_GPIO_ONLY BIT(0) 75 #define IOMUX_WIDTH_4BIT BIT(1) 76 #define IOMUX_SOURCE_PMU BIT(2) 77 #define IOMUX_UNROUTED BIT(3) 78 #define IOMUX_WIDTH_3BIT BIT(4) 79 #define IOMUX_RECALCED BIT(5) 80 81 /** 82 * @type: iomux variant using IOMUX_* constants 83 * @offset: if initialized to -1 it will be autocalculated, by specifying 84 * an initial offset value the relevant source offset can be reset 85 * to a new value for autocalculating the following iomux registers. 86 */ 87 struct rockchip_iomux { 88 int type; 89 int offset; 90 }; 91 92 /** 93 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 94 */ 95 enum rockchip_pin_drv_type { 96 DRV_TYPE_IO_DEFAULT = 0, 97 DRV_TYPE_IO_1V8_OR_3V0, 98 DRV_TYPE_IO_1V8_ONLY, 99 DRV_TYPE_IO_1V8_3V0_AUTO, 100 DRV_TYPE_IO_3V3_ONLY, 101 DRV_TYPE_MAX 102 }; 103 104 /** 105 * enum type index corresponding to rockchip_pull_list arrays index. 106 */ 107 enum rockchip_pin_pull_type { 108 PULL_TYPE_IO_DEFAULT = 0, 109 PULL_TYPE_IO_1V8_ONLY, 110 PULL_TYPE_MAX 111 }; 112 113 /** 114 * @drv_type: drive strength variant using rockchip_perpin_drv_type 115 * @offset: if initialized to -1 it will be autocalculated, by specifying 116 * an initial offset value the relevant source offset can be reset 117 * to a new value for autocalculating the following drive strength 118 * registers. if used chips own cal_drv func instead to calculate 119 * registers offset, the variant could be ignored. 120 */ 121 struct rockchip_drv { 122 enum rockchip_pin_drv_type drv_type; 123 int offset; 124 }; 125 126 /** 127 * @reg_base: register base of the gpio bank 128 * @reg_pull: optional separate register for additional pull settings 129 * @clk: clock of the gpio bank 130 * @irq: interrupt of the gpio bank 131 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 132 * @pin_base: first pin number 133 * @nr_pins: number of pins in this bank 134 * @name: name of the bank 135 * @bank_num: number of the bank, to account for holes 136 * @iomux: array describing the 4 iomux sources of the bank 137 * @drv: array describing the 4 drive strength sources of the bank 138 * @pull_type: array describing the 4 pull type sources of the bank 139 * @valid: are all necessary informations present 140 * @of_node: dt node of this bank 141 * @drvdata: common pinctrl basedata 142 * @domain: irqdomain of the gpio bank 143 * @gpio_chip: gpiolib chip 144 * @grange: gpio range 145 * @slock: spinlock for the gpio bank 146 */ 147 struct rockchip_pin_bank { 148 void __iomem *reg_base; 149 struct regmap *regmap_pull; 150 struct clk *clk; 151 int irq; 152 u32 saved_masks; 153 u32 pin_base; 154 u8 nr_pins; 155 char *name; 156 u8 bank_num; 157 struct rockchip_iomux iomux[4]; 158 struct rockchip_drv drv[4]; 159 enum rockchip_pin_pull_type pull_type[4]; 160 bool valid; 161 struct device_node *of_node; 162 struct rockchip_pinctrl *drvdata; 163 struct irq_domain *domain; 164 struct gpio_chip gpio_chip; 165 struct pinctrl_gpio_range grange; 166 raw_spinlock_t slock; 167 u32 toggle_edge_mode; 168 }; 169 170 #define PIN_BANK(id, pins, label) \ 171 { \ 172 .bank_num = id, \ 173 .nr_pins = pins, \ 174 .name = label, \ 175 .iomux = { \ 176 { .offset = -1 }, \ 177 { .offset = -1 }, \ 178 { .offset = -1 }, \ 179 { .offset = -1 }, \ 180 }, \ 181 } 182 183 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 184 { \ 185 .bank_num = id, \ 186 .nr_pins = pins, \ 187 .name = label, \ 188 .iomux = { \ 189 { .type = iom0, .offset = -1 }, \ 190 { .type = iom1, .offset = -1 }, \ 191 { .type = iom2, .offset = -1 }, \ 192 { .type = iom3, .offset = -1 }, \ 193 }, \ 194 } 195 196 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 197 { \ 198 .bank_num = id, \ 199 .nr_pins = pins, \ 200 .name = label, \ 201 .iomux = { \ 202 { .offset = -1 }, \ 203 { .offset = -1 }, \ 204 { .offset = -1 }, \ 205 { .offset = -1 }, \ 206 }, \ 207 .drv = { \ 208 { .drv_type = type0, .offset = -1 }, \ 209 { .drv_type = type1, .offset = -1 }, \ 210 { .drv_type = type2, .offset = -1 }, \ 211 { .drv_type = type3, .offset = -1 }, \ 212 }, \ 213 } 214 215 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 216 drv2, drv3, pull0, pull1, \ 217 pull2, pull3) \ 218 { \ 219 .bank_num = id, \ 220 .nr_pins = pins, \ 221 .name = label, \ 222 .iomux = { \ 223 { .offset = -1 }, \ 224 { .offset = -1 }, \ 225 { .offset = -1 }, \ 226 { .offset = -1 }, \ 227 }, \ 228 .drv = { \ 229 { .drv_type = drv0, .offset = -1 }, \ 230 { .drv_type = drv1, .offset = -1 }, \ 231 { .drv_type = drv2, .offset = -1 }, \ 232 { .drv_type = drv3, .offset = -1 }, \ 233 }, \ 234 .pull_type[0] = pull0, \ 235 .pull_type[1] = pull1, \ 236 .pull_type[2] = pull2, \ 237 .pull_type[3] = pull3, \ 238 } 239 240 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 241 iom2, iom3, drv0, drv1, drv2, \ 242 drv3, offset0, offset1, \ 243 offset2, offset3) \ 244 { \ 245 .bank_num = id, \ 246 .nr_pins = pins, \ 247 .name = label, \ 248 .iomux = { \ 249 { .type = iom0, .offset = -1 }, \ 250 { .type = iom1, .offset = -1 }, \ 251 { .type = iom2, .offset = -1 }, \ 252 { .type = iom3, .offset = -1 }, \ 253 }, \ 254 .drv = { \ 255 { .drv_type = drv0, .offset = offset0 }, \ 256 { .drv_type = drv1, .offset = offset1 }, \ 257 { .drv_type = drv2, .offset = offset2 }, \ 258 { .drv_type = drv3, .offset = offset3 }, \ 259 }, \ 260 } 261 262 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 263 label, iom0, iom1, iom2, \ 264 iom3, drv0, drv1, drv2, \ 265 drv3, offset0, offset1, \ 266 offset2, offset3, pull0, \ 267 pull1, pull2, pull3) \ 268 { \ 269 .bank_num = id, \ 270 .nr_pins = pins, \ 271 .name = label, \ 272 .iomux = { \ 273 { .type = iom0, .offset = -1 }, \ 274 { .type = iom1, .offset = -1 }, \ 275 { .type = iom2, .offset = -1 }, \ 276 { .type = iom3, .offset = -1 }, \ 277 }, \ 278 .drv = { \ 279 { .drv_type = drv0, .offset = offset0 }, \ 280 { .drv_type = drv1, .offset = offset1 }, \ 281 { .drv_type = drv2, .offset = offset2 }, \ 282 { .drv_type = drv3, .offset = offset3 }, \ 283 }, \ 284 .pull_type[0] = pull0, \ 285 .pull_type[1] = pull1, \ 286 .pull_type[2] = pull2, \ 287 .pull_type[3] = pull3, \ 288 } 289 290 /** 291 */ 292 struct rockchip_pin_ctrl { 293 struct rockchip_pin_bank *pin_banks; 294 u32 nr_banks; 295 u32 nr_pins; 296 char *label; 297 enum rockchip_pinctrl_type type; 298 int grf_mux_offset; 299 int pmu_mux_offset; 300 int grf_drv_offset; 301 int pmu_drv_offset; 302 303 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 304 int pin_num, struct regmap **regmap, 305 int *reg, u8 *bit); 306 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 307 int pin_num, struct regmap **regmap, 308 int *reg, u8 *bit); 309 void (*iomux_recalc)(u8 bank_num, int pin, int *reg, 310 u8 *bit, int *mask); 311 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 312 int pin_num, struct regmap **regmap, 313 int *reg, u8 *bit); 314 }; 315 316 struct rockchip_pin_config { 317 unsigned int func; 318 unsigned long *configs; 319 unsigned int nconfigs; 320 }; 321 322 /** 323 * struct rockchip_pin_group: represent group of pins of a pinmux function. 324 * @name: name of the pin group, used to lookup the group. 325 * @pins: the pins included in this group. 326 * @npins: number of pins included in this group. 327 * @func: the mux function number to be programmed when selected. 328 * @configs: the config values to be set for each pin 329 * @nconfigs: number of configs for each pin 330 */ 331 struct rockchip_pin_group { 332 const char *name; 333 unsigned int npins; 334 unsigned int *pins; 335 struct rockchip_pin_config *data; 336 }; 337 338 /** 339 * struct rockchip_pmx_func: represent a pin function. 340 * @name: name of the pin function, used to lookup the function. 341 * @groups: one or more names of pin groups that provide this function. 342 * @num_groups: number of groups included in @groups. 343 */ 344 struct rockchip_pmx_func { 345 const char *name; 346 const char **groups; 347 u8 ngroups; 348 }; 349 350 struct rockchip_pinctrl { 351 struct regmap *regmap_base; 352 int reg_size; 353 struct regmap *regmap_pull; 354 struct regmap *regmap_pmu; 355 struct device *dev; 356 struct rockchip_pin_ctrl *ctrl; 357 struct pinctrl_desc pctl; 358 struct pinctrl_dev *pctl_dev; 359 struct rockchip_pin_group *groups; 360 unsigned int ngroups; 361 struct rockchip_pmx_func *functions; 362 unsigned int nfunctions; 363 }; 364 365 /** 366 * struct rockchip_mux_recalced_data: represent a pin iomux data. 367 * @num: bank number. 368 * @pin: pin number. 369 * @bit: index at register. 370 * @reg: register offset. 371 * @mask: mask bit 372 */ 373 struct rockchip_mux_recalced_data { 374 u8 num; 375 u8 pin; 376 u8 reg; 377 u8 bit; 378 u8 mask; 379 }; 380 381 static struct regmap_config rockchip_regmap_config = { 382 .reg_bits = 32, 383 .val_bits = 32, 384 .reg_stride = 4, 385 }; 386 387 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 388 const struct rockchip_pinctrl *info, 389 const char *name) 390 { 391 int i; 392 393 for (i = 0; i < info->ngroups; i++) { 394 if (!strcmp(info->groups[i].name, name)) 395 return &info->groups[i]; 396 } 397 398 return NULL; 399 } 400 401 /* 402 * given a pin number that is local to a pin controller, find out the pin bank 403 * and the register base of the pin bank. 404 */ 405 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 406 unsigned pin) 407 { 408 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 409 410 while (pin >= (b->pin_base + b->nr_pins)) 411 b++; 412 413 return b; 414 } 415 416 static struct rockchip_pin_bank *bank_num_to_bank( 417 struct rockchip_pinctrl *info, 418 unsigned num) 419 { 420 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 421 int i; 422 423 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 424 if (b->bank_num == num) 425 return b; 426 } 427 428 return ERR_PTR(-EINVAL); 429 } 430 431 /* 432 * Pinctrl_ops handling 433 */ 434 435 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 436 { 437 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 438 439 return info->ngroups; 440 } 441 442 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 443 unsigned selector) 444 { 445 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 446 447 return info->groups[selector].name; 448 } 449 450 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 451 unsigned selector, const unsigned **pins, 452 unsigned *npins) 453 { 454 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 455 456 if (selector >= info->ngroups) 457 return -EINVAL; 458 459 *pins = info->groups[selector].pins; 460 *npins = info->groups[selector].npins; 461 462 return 0; 463 } 464 465 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 466 struct device_node *np, 467 struct pinctrl_map **map, unsigned *num_maps) 468 { 469 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 470 const struct rockchip_pin_group *grp; 471 struct pinctrl_map *new_map; 472 struct device_node *parent; 473 int map_num = 1; 474 int i; 475 476 /* 477 * first find the group of this node and check if we need to create 478 * config maps for pins 479 */ 480 grp = pinctrl_name_to_group(info, np->name); 481 if (!grp) { 482 dev_err(info->dev, "unable to find group for node %s\n", 483 np->name); 484 return -EINVAL; 485 } 486 487 map_num += grp->npins; 488 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, 489 GFP_KERNEL); 490 if (!new_map) 491 return -ENOMEM; 492 493 *map = new_map; 494 *num_maps = map_num; 495 496 /* create mux map */ 497 parent = of_get_parent(np); 498 if (!parent) { 499 devm_kfree(pctldev->dev, new_map); 500 return -EINVAL; 501 } 502 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 503 new_map[0].data.mux.function = parent->name; 504 new_map[0].data.mux.group = np->name; 505 of_node_put(parent); 506 507 /* create config map */ 508 new_map++; 509 for (i = 0; i < grp->npins; i++) { 510 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 511 new_map[i].data.configs.group_or_pin = 512 pin_get_name(pctldev, grp->pins[i]); 513 new_map[i].data.configs.configs = grp->data[i].configs; 514 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 515 } 516 517 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 518 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 519 520 return 0; 521 } 522 523 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 524 struct pinctrl_map *map, unsigned num_maps) 525 { 526 } 527 528 static const struct pinctrl_ops rockchip_pctrl_ops = { 529 .get_groups_count = rockchip_get_groups_count, 530 .get_group_name = rockchip_get_group_name, 531 .get_group_pins = rockchip_get_group_pins, 532 .dt_node_to_map = rockchip_dt_node_to_map, 533 .dt_free_map = rockchip_dt_free_map, 534 }; 535 536 /* 537 * Hardware access 538 */ 539 540 static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 541 { 542 .num = 2, 543 .pin = 12, 544 .reg = 0x24, 545 .bit = 8, 546 .mask = 0x3 547 }, { 548 .num = 2, 549 .pin = 15, 550 .reg = 0x28, 551 .bit = 0, 552 .mask = 0x7 553 }, { 554 .num = 2, 555 .pin = 23, 556 .reg = 0x30, 557 .bit = 14, 558 .mask = 0x3 559 }, 560 }; 561 562 static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg, 563 u8 *bit, int *mask) 564 { 565 const struct rockchip_mux_recalced_data *data = NULL; 566 int i; 567 568 for (i = 0; i < ARRAY_SIZE(rk3328_mux_recalced_data); i++) 569 if (rk3328_mux_recalced_data[i].num == bank_num && 570 rk3328_mux_recalced_data[i].pin == pin) { 571 data = &rk3328_mux_recalced_data[i]; 572 break; 573 } 574 575 if (!data) 576 return; 577 578 *reg = data->reg; 579 *mask = data->mask; 580 *bit = data->bit; 581 } 582 583 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 584 { 585 struct rockchip_pinctrl *info = bank->drvdata; 586 struct rockchip_pin_ctrl *ctrl = info->ctrl; 587 int iomux_num = (pin / 8); 588 struct regmap *regmap; 589 unsigned int val; 590 int reg, ret, mask, mux_type; 591 u8 bit; 592 593 if (iomux_num > 3) 594 return -EINVAL; 595 596 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 597 dev_err(info->dev, "pin %d is unrouted\n", pin); 598 return -EINVAL; 599 } 600 601 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 602 return RK_FUNC_GPIO; 603 604 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 605 ? info->regmap_pmu : info->regmap_base; 606 607 /* get basic quadrupel of mux registers and the correct reg inside */ 608 mux_type = bank->iomux[iomux_num].type; 609 reg = bank->iomux[iomux_num].offset; 610 if (mux_type & IOMUX_WIDTH_4BIT) { 611 if ((pin % 8) >= 4) 612 reg += 0x4; 613 bit = (pin % 4) * 4; 614 mask = 0xf; 615 } else if (mux_type & IOMUX_WIDTH_3BIT) { 616 if ((pin % 8) >= 5) 617 reg += 0x4; 618 bit = (pin % 8 % 5) * 3; 619 mask = 0x7; 620 } else { 621 bit = (pin % 8) * 2; 622 mask = 0x3; 623 } 624 625 if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED)) 626 ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask); 627 628 ret = regmap_read(regmap, reg, &val); 629 if (ret) 630 return ret; 631 632 return ((val >> bit) & mask); 633 } 634 635 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 636 int pin, int mux) 637 { 638 struct rockchip_pinctrl *info = bank->drvdata; 639 int iomux_num = (pin / 8); 640 641 if (iomux_num > 3) 642 return -EINVAL; 643 644 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 645 dev_err(info->dev, "pin %d is unrouted\n", pin); 646 return -EINVAL; 647 } 648 649 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 650 if (mux != RK_FUNC_GPIO) { 651 dev_err(info->dev, 652 "pin %d only supports a gpio mux\n", pin); 653 return -ENOTSUPP; 654 } 655 } 656 657 return 0; 658 } 659 660 /* 661 * Set a new mux function for a pin. 662 * 663 * The register is divided into the upper and lower 16 bit. When changing 664 * a value, the previous register value is not read and changed. Instead 665 * it seems the changed bits are marked in the upper 16 bit, while the 666 * changed value gets set in the same offset in the lower 16 bit. 667 * All pin settings seem to be 2 bit wide in both the upper and lower 668 * parts. 669 * @bank: pin bank to change 670 * @pin: pin to change 671 * @mux: new mux function to set 672 */ 673 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 674 { 675 struct rockchip_pinctrl *info = bank->drvdata; 676 struct rockchip_pin_ctrl *ctrl = info->ctrl; 677 int iomux_num = (pin / 8); 678 struct regmap *regmap; 679 int reg, ret, mask, mux_type; 680 u8 bit; 681 u32 data, rmask; 682 683 ret = rockchip_verify_mux(bank, pin, mux); 684 if (ret < 0) 685 return ret; 686 687 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 688 return 0; 689 690 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 691 bank->bank_num, pin, mux); 692 693 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 694 ? info->regmap_pmu : info->regmap_base; 695 696 /* get basic quadrupel of mux registers and the correct reg inside */ 697 mux_type = bank->iomux[iomux_num].type; 698 reg = bank->iomux[iomux_num].offset; 699 if (mux_type & IOMUX_WIDTH_4BIT) { 700 if ((pin % 8) >= 4) 701 reg += 0x4; 702 bit = (pin % 4) * 4; 703 mask = 0xf; 704 } else if (mux_type & IOMUX_WIDTH_3BIT) { 705 if ((pin % 8) >= 5) 706 reg += 0x4; 707 bit = (pin % 8 % 5) * 3; 708 mask = 0x7; 709 } else { 710 bit = (pin % 8) * 2; 711 mask = 0x3; 712 } 713 714 if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED)) 715 ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask); 716 717 data = (mask << (bit + 16)); 718 rmask = data | (data >> 16); 719 data |= (mux & mask) << bit; 720 ret = regmap_update_bits(regmap, reg, rmask, data); 721 722 return ret; 723 } 724 725 #define RV1108_PULL_PMU_OFFSET 0x10 726 #define RV1108_PULL_OFFSET 0x110 727 #define RV1108_PULL_PINS_PER_REG 8 728 #define RV1108_PULL_BITS_PER_PIN 2 729 #define RV1108_PULL_BANK_STRIDE 16 730 731 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 732 int pin_num, struct regmap **regmap, 733 int *reg, u8 *bit) 734 { 735 struct rockchip_pinctrl *info = bank->drvdata; 736 737 /* The first 24 pins of the first bank are located in PMU */ 738 if (bank->bank_num == 0) { 739 *regmap = info->regmap_pmu; 740 *reg = RV1108_PULL_PMU_OFFSET; 741 } else { 742 *reg = RV1108_PULL_OFFSET; 743 *regmap = info->regmap_base; 744 /* correct the offset, as we're starting with the 2nd bank */ 745 *reg -= 0x10; 746 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 747 } 748 749 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 750 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 751 *bit *= RV1108_PULL_BITS_PER_PIN; 752 } 753 754 #define RV1108_DRV_PMU_OFFSET 0x20 755 #define RV1108_DRV_GRF_OFFSET 0x210 756 #define RV1108_DRV_BITS_PER_PIN 2 757 #define RV1108_DRV_PINS_PER_REG 8 758 #define RV1108_DRV_BANK_STRIDE 16 759 760 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 761 int pin_num, struct regmap **regmap, 762 int *reg, u8 *bit) 763 { 764 struct rockchip_pinctrl *info = bank->drvdata; 765 766 /* The first 24 pins of the first bank are located in PMU */ 767 if (bank->bank_num == 0) { 768 *regmap = info->regmap_pmu; 769 *reg = RV1108_DRV_PMU_OFFSET; 770 } else { 771 *regmap = info->regmap_base; 772 *reg = RV1108_DRV_GRF_OFFSET; 773 774 /* correct the offset, as we're starting with the 2nd bank */ 775 *reg -= 0x10; 776 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 777 } 778 779 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 780 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 781 *bit *= RV1108_DRV_BITS_PER_PIN; 782 } 783 784 #define RK2928_PULL_OFFSET 0x118 785 #define RK2928_PULL_PINS_PER_REG 16 786 #define RK2928_PULL_BANK_STRIDE 8 787 788 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 789 int pin_num, struct regmap **regmap, 790 int *reg, u8 *bit) 791 { 792 struct rockchip_pinctrl *info = bank->drvdata; 793 794 *regmap = info->regmap_base; 795 *reg = RK2928_PULL_OFFSET; 796 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 797 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 798 799 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 800 }; 801 802 #define RK3188_PULL_OFFSET 0x164 803 #define RK3188_PULL_BITS_PER_PIN 2 804 #define RK3188_PULL_PINS_PER_REG 8 805 #define RK3188_PULL_BANK_STRIDE 16 806 #define RK3188_PULL_PMU_OFFSET 0x64 807 808 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 809 int pin_num, struct regmap **regmap, 810 int *reg, u8 *bit) 811 { 812 struct rockchip_pinctrl *info = bank->drvdata; 813 814 /* The first 12 pins of the first bank are located elsewhere */ 815 if (bank->bank_num == 0 && pin_num < 12) { 816 *regmap = info->regmap_pmu ? info->regmap_pmu 817 : bank->regmap_pull; 818 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 819 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 820 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 821 *bit *= RK3188_PULL_BITS_PER_PIN; 822 } else { 823 *regmap = info->regmap_pull ? info->regmap_pull 824 : info->regmap_base; 825 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 826 827 /* correct the offset, as it is the 2nd pull register */ 828 *reg -= 4; 829 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 830 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 831 832 /* 833 * The bits in these registers have an inverse ordering 834 * with the lowest pin being in bits 15:14 and the highest 835 * pin in bits 1:0 836 */ 837 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 838 *bit *= RK3188_PULL_BITS_PER_PIN; 839 } 840 } 841 842 #define RK3288_PULL_OFFSET 0x140 843 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 844 int pin_num, struct regmap **regmap, 845 int *reg, u8 *bit) 846 { 847 struct rockchip_pinctrl *info = bank->drvdata; 848 849 /* The first 24 pins of the first bank are located in PMU */ 850 if (bank->bank_num == 0) { 851 *regmap = info->regmap_pmu; 852 *reg = RK3188_PULL_PMU_OFFSET; 853 854 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 855 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 856 *bit *= RK3188_PULL_BITS_PER_PIN; 857 } else { 858 *regmap = info->regmap_base; 859 *reg = RK3288_PULL_OFFSET; 860 861 /* correct the offset, as we're starting with the 2nd bank */ 862 *reg -= 0x10; 863 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 864 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 865 866 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 867 *bit *= RK3188_PULL_BITS_PER_PIN; 868 } 869 } 870 871 #define RK3288_DRV_PMU_OFFSET 0x70 872 #define RK3288_DRV_GRF_OFFSET 0x1c0 873 #define RK3288_DRV_BITS_PER_PIN 2 874 #define RK3288_DRV_PINS_PER_REG 8 875 #define RK3288_DRV_BANK_STRIDE 16 876 877 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 878 int pin_num, struct regmap **regmap, 879 int *reg, u8 *bit) 880 { 881 struct rockchip_pinctrl *info = bank->drvdata; 882 883 /* The first 24 pins of the first bank are located in PMU */ 884 if (bank->bank_num == 0) { 885 *regmap = info->regmap_pmu; 886 *reg = RK3288_DRV_PMU_OFFSET; 887 888 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 889 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 890 *bit *= RK3288_DRV_BITS_PER_PIN; 891 } else { 892 *regmap = info->regmap_base; 893 *reg = RK3288_DRV_GRF_OFFSET; 894 895 /* correct the offset, as we're starting with the 2nd bank */ 896 *reg -= 0x10; 897 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 898 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 899 900 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 901 *bit *= RK3288_DRV_BITS_PER_PIN; 902 } 903 } 904 905 #define RK3228_PULL_OFFSET 0x100 906 907 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 908 int pin_num, struct regmap **regmap, 909 int *reg, u8 *bit) 910 { 911 struct rockchip_pinctrl *info = bank->drvdata; 912 913 *regmap = info->regmap_base; 914 *reg = RK3228_PULL_OFFSET; 915 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 916 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 917 918 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 919 *bit *= RK3188_PULL_BITS_PER_PIN; 920 } 921 922 #define RK3228_DRV_GRF_OFFSET 0x200 923 924 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 925 int pin_num, struct regmap **regmap, 926 int *reg, u8 *bit) 927 { 928 struct rockchip_pinctrl *info = bank->drvdata; 929 930 *regmap = info->regmap_base; 931 *reg = RK3228_DRV_GRF_OFFSET; 932 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 933 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 934 935 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 936 *bit *= RK3288_DRV_BITS_PER_PIN; 937 } 938 939 #define RK3368_PULL_GRF_OFFSET 0x100 940 #define RK3368_PULL_PMU_OFFSET 0x10 941 942 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 943 int pin_num, struct regmap **regmap, 944 int *reg, u8 *bit) 945 { 946 struct rockchip_pinctrl *info = bank->drvdata; 947 948 /* The first 32 pins of the first bank are located in PMU */ 949 if (bank->bank_num == 0) { 950 *regmap = info->regmap_pmu; 951 *reg = RK3368_PULL_PMU_OFFSET; 952 953 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 954 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 955 *bit *= RK3188_PULL_BITS_PER_PIN; 956 } else { 957 *regmap = info->regmap_base; 958 *reg = RK3368_PULL_GRF_OFFSET; 959 960 /* correct the offset, as we're starting with the 2nd bank */ 961 *reg -= 0x10; 962 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 963 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 964 965 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 966 *bit *= RK3188_PULL_BITS_PER_PIN; 967 } 968 } 969 970 #define RK3368_DRV_PMU_OFFSET 0x20 971 #define RK3368_DRV_GRF_OFFSET 0x200 972 973 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 974 int pin_num, struct regmap **regmap, 975 int *reg, u8 *bit) 976 { 977 struct rockchip_pinctrl *info = bank->drvdata; 978 979 /* The first 32 pins of the first bank are located in PMU */ 980 if (bank->bank_num == 0) { 981 *regmap = info->regmap_pmu; 982 *reg = RK3368_DRV_PMU_OFFSET; 983 984 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 985 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 986 *bit *= RK3288_DRV_BITS_PER_PIN; 987 } else { 988 *regmap = info->regmap_base; 989 *reg = RK3368_DRV_GRF_OFFSET; 990 991 /* correct the offset, as we're starting with the 2nd bank */ 992 *reg -= 0x10; 993 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 994 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 995 996 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 997 *bit *= RK3288_DRV_BITS_PER_PIN; 998 } 999 } 1000 1001 #define RK3399_PULL_GRF_OFFSET 0xe040 1002 #define RK3399_PULL_PMU_OFFSET 0x40 1003 #define RK3399_DRV_3BITS_PER_PIN 3 1004 1005 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1006 int pin_num, struct regmap **regmap, 1007 int *reg, u8 *bit) 1008 { 1009 struct rockchip_pinctrl *info = bank->drvdata; 1010 1011 /* The bank0:16 and bank1:32 pins are located in PMU */ 1012 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1013 *regmap = info->regmap_pmu; 1014 *reg = RK3399_PULL_PMU_OFFSET; 1015 1016 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1017 1018 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1019 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1020 *bit *= RK3188_PULL_BITS_PER_PIN; 1021 } else { 1022 *regmap = info->regmap_base; 1023 *reg = RK3399_PULL_GRF_OFFSET; 1024 1025 /* correct the offset, as we're starting with the 3rd bank */ 1026 *reg -= 0x20; 1027 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1028 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1029 1030 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1031 *bit *= RK3188_PULL_BITS_PER_PIN; 1032 } 1033 } 1034 1035 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1036 int pin_num, struct regmap **regmap, 1037 int *reg, u8 *bit) 1038 { 1039 struct rockchip_pinctrl *info = bank->drvdata; 1040 int drv_num = (pin_num / 8); 1041 1042 /* The bank0:16 and bank1:32 pins are located in PMU */ 1043 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1044 *regmap = info->regmap_pmu; 1045 else 1046 *regmap = info->regmap_base; 1047 1048 *reg = bank->drv[drv_num].offset; 1049 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1050 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1051 *bit = (pin_num % 8) * 3; 1052 else 1053 *bit = (pin_num % 8) * 2; 1054 } 1055 1056 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1057 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1058 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1059 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1060 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1061 { 4, 7, 10, 13, 16, 19, 22, 26 } 1062 }; 1063 1064 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 1065 int pin_num) 1066 { 1067 struct rockchip_pinctrl *info = bank->drvdata; 1068 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1069 struct regmap *regmap; 1070 int reg, ret; 1071 u32 data, temp, rmask_bits; 1072 u8 bit; 1073 int drv_type = bank->drv[pin_num / 8].drv_type; 1074 1075 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1076 1077 switch (drv_type) { 1078 case DRV_TYPE_IO_1V8_3V0_AUTO: 1079 case DRV_TYPE_IO_3V3_ONLY: 1080 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1081 switch (bit) { 1082 case 0 ... 12: 1083 /* regular case, nothing to do */ 1084 break; 1085 case 15: 1086 /* 1087 * drive-strength offset is special, as it is 1088 * spread over 2 registers 1089 */ 1090 ret = regmap_read(regmap, reg, &data); 1091 if (ret) 1092 return ret; 1093 1094 ret = regmap_read(regmap, reg + 0x4, &temp); 1095 if (ret) 1096 return ret; 1097 1098 /* 1099 * the bit data[15] contains bit 0 of the value 1100 * while temp[1:0] contains bits 2 and 1 1101 */ 1102 data >>= 15; 1103 temp &= 0x3; 1104 temp <<= 1; 1105 data |= temp; 1106 1107 return rockchip_perpin_drv_list[drv_type][data]; 1108 case 18 ... 21: 1109 /* setting fully enclosed in the second register */ 1110 reg += 4; 1111 bit -= 16; 1112 break; 1113 default: 1114 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1115 bit, drv_type); 1116 return -EINVAL; 1117 } 1118 1119 break; 1120 case DRV_TYPE_IO_DEFAULT: 1121 case DRV_TYPE_IO_1V8_OR_3V0: 1122 case DRV_TYPE_IO_1V8_ONLY: 1123 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1124 break; 1125 default: 1126 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1127 drv_type); 1128 return -EINVAL; 1129 } 1130 1131 ret = regmap_read(regmap, reg, &data); 1132 if (ret) 1133 return ret; 1134 1135 data >>= bit; 1136 data &= (1 << rmask_bits) - 1; 1137 1138 return rockchip_perpin_drv_list[drv_type][data]; 1139 } 1140 1141 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1142 int pin_num, int strength) 1143 { 1144 struct rockchip_pinctrl *info = bank->drvdata; 1145 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1146 struct regmap *regmap; 1147 int reg, ret, i; 1148 u32 data, rmask, rmask_bits, temp; 1149 u8 bit; 1150 int drv_type = bank->drv[pin_num / 8].drv_type; 1151 1152 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", 1153 bank->bank_num, pin_num, strength); 1154 1155 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1156 1157 ret = -EINVAL; 1158 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1159 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1160 ret = i; 1161 break; 1162 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1163 ret = rockchip_perpin_drv_list[drv_type][i]; 1164 break; 1165 } 1166 } 1167 1168 if (ret < 0) { 1169 dev_err(info->dev, "unsupported driver strength %d\n", 1170 strength); 1171 return ret; 1172 } 1173 1174 switch (drv_type) { 1175 case DRV_TYPE_IO_1V8_3V0_AUTO: 1176 case DRV_TYPE_IO_3V3_ONLY: 1177 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1178 switch (bit) { 1179 case 0 ... 12: 1180 /* regular case, nothing to do */ 1181 break; 1182 case 15: 1183 /* 1184 * drive-strength offset is special, as it is spread 1185 * over 2 registers, the bit data[15] contains bit 0 1186 * of the value while temp[1:0] contains bits 2 and 1 1187 */ 1188 data = (ret & 0x1) << 15; 1189 temp = (ret >> 0x1) & 0x3; 1190 1191 rmask = BIT(15) | BIT(31); 1192 data |= BIT(31); 1193 ret = regmap_update_bits(regmap, reg, rmask, data); 1194 if (ret) 1195 return ret; 1196 1197 rmask = 0x3 | (0x3 << 16); 1198 temp |= (0x3 << 16); 1199 reg += 0x4; 1200 ret = regmap_update_bits(regmap, reg, rmask, temp); 1201 1202 return ret; 1203 case 18 ... 21: 1204 /* setting fully enclosed in the second register */ 1205 reg += 4; 1206 bit -= 16; 1207 break; 1208 default: 1209 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 1210 bit, drv_type); 1211 return -EINVAL; 1212 } 1213 break; 1214 case DRV_TYPE_IO_DEFAULT: 1215 case DRV_TYPE_IO_1V8_OR_3V0: 1216 case DRV_TYPE_IO_1V8_ONLY: 1217 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1218 break; 1219 default: 1220 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 1221 drv_type); 1222 return -EINVAL; 1223 } 1224 1225 /* enable the write to the equivalent lower bits */ 1226 data = ((1 << rmask_bits) - 1) << (bit + 16); 1227 rmask = data | (data >> 16); 1228 data |= (ret << bit); 1229 1230 ret = regmap_update_bits(regmap, reg, rmask, data); 1231 1232 return ret; 1233 } 1234 1235 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1236 { 1237 PIN_CONFIG_BIAS_DISABLE, 1238 PIN_CONFIG_BIAS_PULL_UP, 1239 PIN_CONFIG_BIAS_PULL_DOWN, 1240 PIN_CONFIG_BIAS_BUS_HOLD 1241 }, 1242 { 1243 PIN_CONFIG_BIAS_DISABLE, 1244 PIN_CONFIG_BIAS_PULL_DOWN, 1245 PIN_CONFIG_BIAS_DISABLE, 1246 PIN_CONFIG_BIAS_PULL_UP 1247 }, 1248 }; 1249 1250 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 1251 { 1252 struct rockchip_pinctrl *info = bank->drvdata; 1253 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1254 struct regmap *regmap; 1255 int reg, ret, pull_type; 1256 u8 bit; 1257 u32 data; 1258 1259 /* rk3066b does support any pulls */ 1260 if (ctrl->type == RK3066B) 1261 return PIN_CONFIG_BIAS_DISABLE; 1262 1263 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1264 1265 ret = regmap_read(regmap, reg, &data); 1266 if (ret) 1267 return ret; 1268 1269 switch (ctrl->type) { 1270 case RK2928: 1271 return !(data & BIT(bit)) 1272 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 1273 : PIN_CONFIG_BIAS_DISABLE; 1274 case RV1108: 1275 case RK3188: 1276 case RK3288: 1277 case RK3368: 1278 case RK3399: 1279 pull_type = bank->pull_type[pin_num / 8]; 1280 data >>= bit; 1281 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 1282 1283 return rockchip_pull_list[pull_type][data]; 1284 default: 1285 dev_err(info->dev, "unsupported pinctrl type\n"); 1286 return -EINVAL; 1287 }; 1288 } 1289 1290 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 1291 int pin_num, int pull) 1292 { 1293 struct rockchip_pinctrl *info = bank->drvdata; 1294 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1295 struct regmap *regmap; 1296 int reg, ret, i, pull_type; 1297 u8 bit; 1298 u32 data, rmask; 1299 1300 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 1301 bank->bank_num, pin_num, pull); 1302 1303 /* rk3066b does support any pulls */ 1304 if (ctrl->type == RK3066B) 1305 return pull ? -EINVAL : 0; 1306 1307 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1308 1309 switch (ctrl->type) { 1310 case RK2928: 1311 data = BIT(bit + 16); 1312 if (pull == PIN_CONFIG_BIAS_DISABLE) 1313 data |= BIT(bit); 1314 ret = regmap_write(regmap, reg, data); 1315 break; 1316 case RV1108: 1317 case RK3188: 1318 case RK3288: 1319 case RK3368: 1320 case RK3399: 1321 pull_type = bank->pull_type[pin_num / 8]; 1322 ret = -EINVAL; 1323 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 1324 i++) { 1325 if (rockchip_pull_list[pull_type][i] == pull) { 1326 ret = i; 1327 break; 1328 } 1329 } 1330 1331 if (ret < 0) { 1332 dev_err(info->dev, "unsupported pull setting %d\n", 1333 pull); 1334 return ret; 1335 } 1336 1337 /* enable the write to the equivalent lower bits */ 1338 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 1339 rmask = data | (data >> 16); 1340 data |= (ret << bit); 1341 1342 ret = regmap_update_bits(regmap, reg, rmask, data); 1343 break; 1344 default: 1345 dev_err(info->dev, "unsupported pinctrl type\n"); 1346 return -EINVAL; 1347 } 1348 1349 return ret; 1350 } 1351 1352 #define RK3328_SCHMITT_BITS_PER_PIN 1 1353 #define RK3328_SCHMITT_PINS_PER_REG 16 1354 #define RK3328_SCHMITT_BANK_STRIDE 8 1355 #define RK3328_SCHMITT_GRF_OFFSET 0x380 1356 1357 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1358 int pin_num, 1359 struct regmap **regmap, 1360 int *reg, u8 *bit) 1361 { 1362 struct rockchip_pinctrl *info = bank->drvdata; 1363 1364 *regmap = info->regmap_base; 1365 *reg = RK3328_SCHMITT_GRF_OFFSET; 1366 1367 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 1368 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 1369 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 1370 1371 return 0; 1372 } 1373 1374 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 1375 { 1376 struct rockchip_pinctrl *info = bank->drvdata; 1377 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1378 struct regmap *regmap; 1379 int reg, ret; 1380 u8 bit; 1381 u32 data; 1382 1383 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1384 if (ret) 1385 return ret; 1386 1387 ret = regmap_read(regmap, reg, &data); 1388 if (ret) 1389 return ret; 1390 1391 data >>= bit; 1392 return data & 0x1; 1393 } 1394 1395 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 1396 int pin_num, int enable) 1397 { 1398 struct rockchip_pinctrl *info = bank->drvdata; 1399 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1400 struct regmap *regmap; 1401 int reg, ret; 1402 u8 bit; 1403 u32 data, rmask; 1404 1405 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", 1406 bank->bank_num, pin_num, enable); 1407 1408 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1409 if (ret) 1410 return ret; 1411 1412 /* enable the write to the equivalent lower bits */ 1413 data = BIT(bit + 16) | (enable << bit); 1414 rmask = BIT(bit + 16) | BIT(bit); 1415 1416 return regmap_update_bits(regmap, reg, rmask, data); 1417 } 1418 1419 /* 1420 * Pinmux_ops handling 1421 */ 1422 1423 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 1424 { 1425 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1426 1427 return info->nfunctions; 1428 } 1429 1430 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 1431 unsigned selector) 1432 { 1433 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1434 1435 return info->functions[selector].name; 1436 } 1437 1438 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 1439 unsigned selector, const char * const **groups, 1440 unsigned * const num_groups) 1441 { 1442 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1443 1444 *groups = info->functions[selector].groups; 1445 *num_groups = info->functions[selector].ngroups; 1446 1447 return 0; 1448 } 1449 1450 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 1451 unsigned group) 1452 { 1453 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1454 const unsigned int *pins = info->groups[group].pins; 1455 const struct rockchip_pin_config *data = info->groups[group].data; 1456 struct rockchip_pin_bank *bank; 1457 int cnt, ret = 0; 1458 1459 dev_dbg(info->dev, "enable function %s group %s\n", 1460 info->functions[selector].name, info->groups[group].name); 1461 1462 /* 1463 * for each pin in the pin group selected, program the correspoding pin 1464 * pin function number in the config register. 1465 */ 1466 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 1467 bank = pin_to_bank(info, pins[cnt]); 1468 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 1469 data[cnt].func); 1470 if (ret) 1471 break; 1472 } 1473 1474 if (ret) { 1475 /* revert the already done pin settings */ 1476 for (cnt--; cnt >= 0; cnt--) 1477 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 1478 1479 return ret; 1480 } 1481 1482 return 0; 1483 } 1484 1485 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 1486 { 1487 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 1488 u32 data; 1489 1490 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 1491 1492 return !(data & BIT(offset)); 1493 } 1494 1495 /* 1496 * The calls to gpio_direction_output() and gpio_direction_input() 1497 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 1498 * function called from the gpiolib interface). 1499 */ 1500 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, 1501 int pin, bool input) 1502 { 1503 struct rockchip_pin_bank *bank; 1504 int ret; 1505 unsigned long flags; 1506 u32 data; 1507 1508 bank = gpiochip_get_data(chip); 1509 1510 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 1511 if (ret < 0) 1512 return ret; 1513 1514 clk_enable(bank->clk); 1515 raw_spin_lock_irqsave(&bank->slock, flags); 1516 1517 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 1518 /* set bit to 1 for output, 0 for input */ 1519 if (!input) 1520 data |= BIT(pin); 1521 else 1522 data &= ~BIT(pin); 1523 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 1524 1525 raw_spin_unlock_irqrestore(&bank->slock, flags); 1526 clk_disable(bank->clk); 1527 1528 return 0; 1529 } 1530 1531 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 1532 struct pinctrl_gpio_range *range, 1533 unsigned offset, bool input) 1534 { 1535 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1536 struct gpio_chip *chip; 1537 int pin; 1538 1539 chip = range->gc; 1540 pin = offset - chip->base; 1541 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 1542 offset, range->name, pin, input ? "input" : "output"); 1543 1544 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, 1545 input); 1546 } 1547 1548 static const struct pinmux_ops rockchip_pmx_ops = { 1549 .get_functions_count = rockchip_pmx_get_funcs_count, 1550 .get_function_name = rockchip_pmx_get_func_name, 1551 .get_function_groups = rockchip_pmx_get_groups, 1552 .set_mux = rockchip_pmx_set, 1553 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 1554 }; 1555 1556 /* 1557 * Pinconf_ops handling 1558 */ 1559 1560 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 1561 enum pin_config_param pull) 1562 { 1563 switch (ctrl->type) { 1564 case RK2928: 1565 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 1566 pull == PIN_CONFIG_BIAS_DISABLE); 1567 case RK3066B: 1568 return pull ? false : true; 1569 case RV1108: 1570 case RK3188: 1571 case RK3288: 1572 case RK3368: 1573 case RK3399: 1574 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 1575 } 1576 1577 return false; 1578 } 1579 1580 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); 1581 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 1582 1583 /* set the pin config settings for a specified pin */ 1584 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1585 unsigned long *configs, unsigned num_configs) 1586 { 1587 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1588 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 1589 enum pin_config_param param; 1590 u32 arg; 1591 int i; 1592 int rc; 1593 1594 for (i = 0; i < num_configs; i++) { 1595 param = pinconf_to_config_param(configs[i]); 1596 arg = pinconf_to_config_argument(configs[i]); 1597 1598 switch (param) { 1599 case PIN_CONFIG_BIAS_DISABLE: 1600 rc = rockchip_set_pull(bank, pin - bank->pin_base, 1601 param); 1602 if (rc) 1603 return rc; 1604 break; 1605 case PIN_CONFIG_BIAS_PULL_UP: 1606 case PIN_CONFIG_BIAS_PULL_DOWN: 1607 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1608 case PIN_CONFIG_BIAS_BUS_HOLD: 1609 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 1610 return -ENOTSUPP; 1611 1612 if (!arg) 1613 return -EINVAL; 1614 1615 rc = rockchip_set_pull(bank, pin - bank->pin_base, 1616 param); 1617 if (rc) 1618 return rc; 1619 break; 1620 case PIN_CONFIG_OUTPUT: 1621 rockchip_gpio_set(&bank->gpio_chip, 1622 pin - bank->pin_base, arg); 1623 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, 1624 pin - bank->pin_base, false); 1625 if (rc) 1626 return rc; 1627 break; 1628 case PIN_CONFIG_DRIVE_STRENGTH: 1629 /* rk3288 is the first with per-pin drive-strength */ 1630 if (!info->ctrl->drv_calc_reg) 1631 return -ENOTSUPP; 1632 1633 rc = rockchip_set_drive_perpin(bank, 1634 pin - bank->pin_base, arg); 1635 if (rc < 0) 1636 return rc; 1637 break; 1638 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1639 if (!info->ctrl->schmitt_calc_reg) 1640 return -ENOTSUPP; 1641 1642 rc = rockchip_set_schmitt(bank, 1643 pin - bank->pin_base, arg); 1644 if (rc < 0) 1645 return rc; 1646 break; 1647 default: 1648 return -ENOTSUPP; 1649 break; 1650 } 1651 } /* for each config */ 1652 1653 return 0; 1654 } 1655 1656 /* get the pin config settings for a specified pin */ 1657 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 1658 unsigned long *config) 1659 { 1660 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1661 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 1662 enum pin_config_param param = pinconf_to_config_param(*config); 1663 u16 arg; 1664 int rc; 1665 1666 switch (param) { 1667 case PIN_CONFIG_BIAS_DISABLE: 1668 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 1669 return -EINVAL; 1670 1671 arg = 0; 1672 break; 1673 case PIN_CONFIG_BIAS_PULL_UP: 1674 case PIN_CONFIG_BIAS_PULL_DOWN: 1675 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1676 case PIN_CONFIG_BIAS_BUS_HOLD: 1677 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 1678 return -ENOTSUPP; 1679 1680 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 1681 return -EINVAL; 1682 1683 arg = 1; 1684 break; 1685 case PIN_CONFIG_OUTPUT: 1686 rc = rockchip_get_mux(bank, pin - bank->pin_base); 1687 if (rc != RK_FUNC_GPIO) 1688 return -EINVAL; 1689 1690 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 1691 if (rc < 0) 1692 return rc; 1693 1694 arg = rc ? 1 : 0; 1695 break; 1696 case PIN_CONFIG_DRIVE_STRENGTH: 1697 /* rk3288 is the first with per-pin drive-strength */ 1698 if (!info->ctrl->drv_calc_reg) 1699 return -ENOTSUPP; 1700 1701 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 1702 if (rc < 0) 1703 return rc; 1704 1705 arg = rc; 1706 break; 1707 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1708 if (!info->ctrl->schmitt_calc_reg) 1709 return -ENOTSUPP; 1710 1711 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 1712 if (rc < 0) 1713 return rc; 1714 1715 arg = rc; 1716 break; 1717 default: 1718 return -ENOTSUPP; 1719 break; 1720 } 1721 1722 *config = pinconf_to_config_packed(param, arg); 1723 1724 return 0; 1725 } 1726 1727 static const struct pinconf_ops rockchip_pinconf_ops = { 1728 .pin_config_get = rockchip_pinconf_get, 1729 .pin_config_set = rockchip_pinconf_set, 1730 .is_generic = true, 1731 }; 1732 1733 static const struct of_device_id rockchip_bank_match[] = { 1734 { .compatible = "rockchip,gpio-bank" }, 1735 { .compatible = "rockchip,rk3188-gpio-bank0" }, 1736 {}, 1737 }; 1738 1739 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 1740 struct device_node *np) 1741 { 1742 struct device_node *child; 1743 1744 for_each_child_of_node(np, child) { 1745 if (of_match_node(rockchip_bank_match, child)) 1746 continue; 1747 1748 info->nfunctions++; 1749 info->ngroups += of_get_child_count(child); 1750 } 1751 } 1752 1753 static int rockchip_pinctrl_parse_groups(struct device_node *np, 1754 struct rockchip_pin_group *grp, 1755 struct rockchip_pinctrl *info, 1756 u32 index) 1757 { 1758 struct rockchip_pin_bank *bank; 1759 int size; 1760 const __be32 *list; 1761 int num; 1762 int i, j; 1763 int ret; 1764 1765 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 1766 1767 /* Initialise group */ 1768 grp->name = np->name; 1769 1770 /* 1771 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 1772 * do sanity check and calculate pins number 1773 */ 1774 list = of_get_property(np, "rockchip,pins", &size); 1775 /* we do not check return since it's safe node passed down */ 1776 size /= sizeof(*list); 1777 if (!size || size % 4) { 1778 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 1779 return -EINVAL; 1780 } 1781 1782 grp->npins = size / 4; 1783 1784 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 1785 GFP_KERNEL); 1786 grp->data = devm_kzalloc(info->dev, grp->npins * 1787 sizeof(struct rockchip_pin_config), 1788 GFP_KERNEL); 1789 if (!grp->pins || !grp->data) 1790 return -ENOMEM; 1791 1792 for (i = 0, j = 0; i < size; i += 4, j++) { 1793 const __be32 *phandle; 1794 struct device_node *np_config; 1795 1796 num = be32_to_cpu(*list++); 1797 bank = bank_num_to_bank(info, num); 1798 if (IS_ERR(bank)) 1799 return PTR_ERR(bank); 1800 1801 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 1802 grp->data[j].func = be32_to_cpu(*list++); 1803 1804 phandle = list++; 1805 if (!phandle) 1806 return -EINVAL; 1807 1808 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 1809 ret = pinconf_generic_parse_dt_config(np_config, NULL, 1810 &grp->data[j].configs, &grp->data[j].nconfigs); 1811 if (ret) 1812 return ret; 1813 } 1814 1815 return 0; 1816 } 1817 1818 static int rockchip_pinctrl_parse_functions(struct device_node *np, 1819 struct rockchip_pinctrl *info, 1820 u32 index) 1821 { 1822 struct device_node *child; 1823 struct rockchip_pmx_func *func; 1824 struct rockchip_pin_group *grp; 1825 int ret; 1826 static u32 grp_index; 1827 u32 i = 0; 1828 1829 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 1830 1831 func = &info->functions[index]; 1832 1833 /* Initialise function */ 1834 func->name = np->name; 1835 func->ngroups = of_get_child_count(np); 1836 if (func->ngroups <= 0) 1837 return 0; 1838 1839 func->groups = devm_kzalloc(info->dev, 1840 func->ngroups * sizeof(char *), GFP_KERNEL); 1841 if (!func->groups) 1842 return -ENOMEM; 1843 1844 for_each_child_of_node(np, child) { 1845 func->groups[i] = child->name; 1846 grp = &info->groups[grp_index++]; 1847 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 1848 if (ret) { 1849 of_node_put(child); 1850 return ret; 1851 } 1852 } 1853 1854 return 0; 1855 } 1856 1857 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 1858 struct rockchip_pinctrl *info) 1859 { 1860 struct device *dev = &pdev->dev; 1861 struct device_node *np = dev->of_node; 1862 struct device_node *child; 1863 int ret; 1864 int i; 1865 1866 rockchip_pinctrl_child_count(info, np); 1867 1868 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 1869 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 1870 1871 info->functions = devm_kzalloc(dev, info->nfunctions * 1872 sizeof(struct rockchip_pmx_func), 1873 GFP_KERNEL); 1874 if (!info->functions) { 1875 dev_err(dev, "failed to allocate memory for function list\n"); 1876 return -EINVAL; 1877 } 1878 1879 info->groups = devm_kzalloc(dev, info->ngroups * 1880 sizeof(struct rockchip_pin_group), 1881 GFP_KERNEL); 1882 if (!info->groups) { 1883 dev_err(dev, "failed allocate memory for ping group list\n"); 1884 return -EINVAL; 1885 } 1886 1887 i = 0; 1888 1889 for_each_child_of_node(np, child) { 1890 if (of_match_node(rockchip_bank_match, child)) 1891 continue; 1892 1893 ret = rockchip_pinctrl_parse_functions(child, info, i++); 1894 if (ret) { 1895 dev_err(&pdev->dev, "failed to parse function\n"); 1896 of_node_put(child); 1897 return ret; 1898 } 1899 } 1900 1901 return 0; 1902 } 1903 1904 static int rockchip_pinctrl_register(struct platform_device *pdev, 1905 struct rockchip_pinctrl *info) 1906 { 1907 struct pinctrl_desc *ctrldesc = &info->pctl; 1908 struct pinctrl_pin_desc *pindesc, *pdesc; 1909 struct rockchip_pin_bank *pin_bank; 1910 int pin, bank, ret; 1911 int k; 1912 1913 ctrldesc->name = "rockchip-pinctrl"; 1914 ctrldesc->owner = THIS_MODULE; 1915 ctrldesc->pctlops = &rockchip_pctrl_ops; 1916 ctrldesc->pmxops = &rockchip_pmx_ops; 1917 ctrldesc->confops = &rockchip_pinconf_ops; 1918 1919 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 1920 info->ctrl->nr_pins, GFP_KERNEL); 1921 if (!pindesc) { 1922 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); 1923 return -ENOMEM; 1924 } 1925 ctrldesc->pins = pindesc; 1926 ctrldesc->npins = info->ctrl->nr_pins; 1927 1928 pdesc = pindesc; 1929 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 1930 pin_bank = &info->ctrl->pin_banks[bank]; 1931 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 1932 pdesc->number = k; 1933 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 1934 pin_bank->name, pin); 1935 pdesc++; 1936 } 1937 } 1938 1939 ret = rockchip_pinctrl_parse_dt(pdev, info); 1940 if (ret) 1941 return ret; 1942 1943 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); 1944 if (IS_ERR(info->pctl_dev)) { 1945 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 1946 return PTR_ERR(info->pctl_dev); 1947 } 1948 1949 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 1950 pin_bank = &info->ctrl->pin_banks[bank]; 1951 pin_bank->grange.name = pin_bank->name; 1952 pin_bank->grange.id = bank; 1953 pin_bank->grange.pin_base = pin_bank->pin_base; 1954 pin_bank->grange.base = pin_bank->gpio_chip.base; 1955 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 1956 pin_bank->grange.gc = &pin_bank->gpio_chip; 1957 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 1958 } 1959 1960 return 0; 1961 } 1962 1963 /* 1964 * GPIO handling 1965 */ 1966 1967 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 1968 { 1969 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 1970 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 1971 unsigned long flags; 1972 u32 data; 1973 1974 clk_enable(bank->clk); 1975 raw_spin_lock_irqsave(&bank->slock, flags); 1976 1977 data = readl(reg); 1978 data &= ~BIT(offset); 1979 if (value) 1980 data |= BIT(offset); 1981 writel(data, reg); 1982 1983 raw_spin_unlock_irqrestore(&bank->slock, flags); 1984 clk_disable(bank->clk); 1985 } 1986 1987 /* 1988 * Returns the level of the pin for input direction and setting of the DR 1989 * register for output gpios. 1990 */ 1991 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 1992 { 1993 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 1994 u32 data; 1995 1996 clk_enable(bank->clk); 1997 data = readl(bank->reg_base + GPIO_EXT_PORT); 1998 clk_disable(bank->clk); 1999 data >>= offset; 2000 data &= 1; 2001 return data; 2002 } 2003 2004 /* 2005 * gpiolib gpio_direction_input callback function. The setting of the pin 2006 * mux function as 'gpio input' will be handled by the pinctrl susbsystem 2007 * interface. 2008 */ 2009 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 2010 { 2011 return pinctrl_gpio_direction_input(gc->base + offset); 2012 } 2013 2014 /* 2015 * gpiolib gpio_direction_output callback function. The setting of the pin 2016 * mux function as 'gpio output' will be handled by the pinctrl susbsystem 2017 * interface. 2018 */ 2019 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 2020 unsigned offset, int value) 2021 { 2022 rockchip_gpio_set(gc, offset, value); 2023 return pinctrl_gpio_direction_output(gc->base + offset); 2024 } 2025 2026 /* 2027 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 2028 * and a virtual IRQ, if not already present. 2029 */ 2030 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 2031 { 2032 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 2033 unsigned int virq; 2034 2035 if (!bank->domain) 2036 return -ENXIO; 2037 2038 virq = irq_create_mapping(bank->domain, offset); 2039 2040 return (virq) ? : -ENXIO; 2041 } 2042 2043 static const struct gpio_chip rockchip_gpiolib_chip = { 2044 .request = gpiochip_generic_request, 2045 .free = gpiochip_generic_free, 2046 .set = rockchip_gpio_set, 2047 .get = rockchip_gpio_get, 2048 .get_direction = rockchip_gpio_get_direction, 2049 .direction_input = rockchip_gpio_direction_input, 2050 .direction_output = rockchip_gpio_direction_output, 2051 .to_irq = rockchip_gpio_to_irq, 2052 .owner = THIS_MODULE, 2053 }; 2054 2055 /* 2056 * Interrupt handling 2057 */ 2058 2059 static void rockchip_irq_demux(struct irq_desc *desc) 2060 { 2061 struct irq_chip *chip = irq_desc_get_chip(desc); 2062 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 2063 u32 pend; 2064 2065 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 2066 2067 chained_irq_enter(chip, desc); 2068 2069 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 2070 2071 while (pend) { 2072 unsigned int irq, virq; 2073 2074 irq = __ffs(pend); 2075 pend &= ~BIT(irq); 2076 virq = irq_linear_revmap(bank->domain, irq); 2077 2078 if (!virq) { 2079 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 2080 continue; 2081 } 2082 2083 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 2084 2085 /* 2086 * Triggering IRQ on both rising and falling edge 2087 * needs manual intervention. 2088 */ 2089 if (bank->toggle_edge_mode & BIT(irq)) { 2090 u32 data, data_old, polarity; 2091 unsigned long flags; 2092 2093 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 2094 do { 2095 raw_spin_lock_irqsave(&bank->slock, flags); 2096 2097 polarity = readl_relaxed(bank->reg_base + 2098 GPIO_INT_POLARITY); 2099 if (data & BIT(irq)) 2100 polarity &= ~BIT(irq); 2101 else 2102 polarity |= BIT(irq); 2103 writel(polarity, 2104 bank->reg_base + GPIO_INT_POLARITY); 2105 2106 raw_spin_unlock_irqrestore(&bank->slock, flags); 2107 2108 data_old = data; 2109 data = readl_relaxed(bank->reg_base + 2110 GPIO_EXT_PORT); 2111 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 2112 } 2113 2114 generic_handle_irq(virq); 2115 } 2116 2117 chained_irq_exit(chip, desc); 2118 } 2119 2120 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 2121 { 2122 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2123 struct rockchip_pin_bank *bank = gc->private; 2124 u32 mask = BIT(d->hwirq); 2125 u32 polarity; 2126 u32 level; 2127 u32 data; 2128 unsigned long flags; 2129 int ret; 2130 2131 /* make sure the pin is configured as gpio input */ 2132 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 2133 if (ret < 0) 2134 return ret; 2135 2136 clk_enable(bank->clk); 2137 raw_spin_lock_irqsave(&bank->slock, flags); 2138 2139 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2140 data &= ~mask; 2141 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 2142 2143 raw_spin_unlock_irqrestore(&bank->slock, flags); 2144 2145 if (type & IRQ_TYPE_EDGE_BOTH) 2146 irq_set_handler_locked(d, handle_edge_irq); 2147 else 2148 irq_set_handler_locked(d, handle_level_irq); 2149 2150 raw_spin_lock_irqsave(&bank->slock, flags); 2151 irq_gc_lock(gc); 2152 2153 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 2154 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 2155 2156 switch (type) { 2157 case IRQ_TYPE_EDGE_BOTH: 2158 bank->toggle_edge_mode |= mask; 2159 level |= mask; 2160 2161 /* 2162 * Determine gpio state. If 1 next interrupt should be falling 2163 * otherwise rising. 2164 */ 2165 data = readl(bank->reg_base + GPIO_EXT_PORT); 2166 if (data & mask) 2167 polarity &= ~mask; 2168 else 2169 polarity |= mask; 2170 break; 2171 case IRQ_TYPE_EDGE_RISING: 2172 bank->toggle_edge_mode &= ~mask; 2173 level |= mask; 2174 polarity |= mask; 2175 break; 2176 case IRQ_TYPE_EDGE_FALLING: 2177 bank->toggle_edge_mode &= ~mask; 2178 level |= mask; 2179 polarity &= ~mask; 2180 break; 2181 case IRQ_TYPE_LEVEL_HIGH: 2182 bank->toggle_edge_mode &= ~mask; 2183 level &= ~mask; 2184 polarity |= mask; 2185 break; 2186 case IRQ_TYPE_LEVEL_LOW: 2187 bank->toggle_edge_mode &= ~mask; 2188 level &= ~mask; 2189 polarity &= ~mask; 2190 break; 2191 default: 2192 irq_gc_unlock(gc); 2193 raw_spin_unlock_irqrestore(&bank->slock, flags); 2194 clk_disable(bank->clk); 2195 return -EINVAL; 2196 } 2197 2198 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 2199 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 2200 2201 irq_gc_unlock(gc); 2202 raw_spin_unlock_irqrestore(&bank->slock, flags); 2203 clk_disable(bank->clk); 2204 2205 return 0; 2206 } 2207 2208 static void rockchip_irq_suspend(struct irq_data *d) 2209 { 2210 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2211 struct rockchip_pin_bank *bank = gc->private; 2212 2213 clk_enable(bank->clk); 2214 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 2215 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 2216 clk_disable(bank->clk); 2217 } 2218 2219 static void rockchip_irq_resume(struct irq_data *d) 2220 { 2221 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2222 struct rockchip_pin_bank *bank = gc->private; 2223 2224 clk_enable(bank->clk); 2225 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 2226 clk_disable(bank->clk); 2227 } 2228 2229 static void rockchip_irq_enable(struct irq_data *d) 2230 { 2231 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2232 struct rockchip_pin_bank *bank = gc->private; 2233 2234 clk_enable(bank->clk); 2235 irq_gc_mask_clr_bit(d); 2236 } 2237 2238 static void rockchip_irq_disable(struct irq_data *d) 2239 { 2240 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 2241 struct rockchip_pin_bank *bank = gc->private; 2242 2243 irq_gc_mask_set_bit(d); 2244 clk_disable(bank->clk); 2245 } 2246 2247 static int rockchip_interrupts_register(struct platform_device *pdev, 2248 struct rockchip_pinctrl *info) 2249 { 2250 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2251 struct rockchip_pin_bank *bank = ctrl->pin_banks; 2252 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 2253 struct irq_chip_generic *gc; 2254 int ret; 2255 int i, j; 2256 2257 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2258 if (!bank->valid) { 2259 dev_warn(&pdev->dev, "bank %s is not valid\n", 2260 bank->name); 2261 continue; 2262 } 2263 2264 ret = clk_enable(bank->clk); 2265 if (ret) { 2266 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", 2267 bank->name); 2268 continue; 2269 } 2270 2271 bank->domain = irq_domain_add_linear(bank->of_node, 32, 2272 &irq_generic_chip_ops, NULL); 2273 if (!bank->domain) { 2274 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 2275 bank->name); 2276 clk_disable(bank->clk); 2277 continue; 2278 } 2279 2280 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 2281 "rockchip_gpio_irq", handle_level_irq, 2282 clr, 0, IRQ_GC_INIT_MASK_CACHE); 2283 if (ret) { 2284 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 2285 bank->name); 2286 irq_domain_remove(bank->domain); 2287 clk_disable(bank->clk); 2288 continue; 2289 } 2290 2291 /* 2292 * Linux assumes that all interrupts start out disabled/masked. 2293 * Our driver only uses the concept of masked and always keeps 2294 * things enabled, so for us that's all masked and all enabled. 2295 */ 2296 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); 2297 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); 2298 2299 gc = irq_get_domain_generic_chip(bank->domain, 0); 2300 gc->reg_base = bank->reg_base; 2301 gc->private = bank; 2302 gc->chip_types[0].regs.mask = GPIO_INTMASK; 2303 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 2304 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 2305 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 2306 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 2307 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 2308 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 2309 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 2310 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 2311 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 2312 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 2313 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 2314 2315 irq_set_chained_handler_and_data(bank->irq, 2316 rockchip_irq_demux, bank); 2317 2318 /* map the gpio irqs here, when the clock is still running */ 2319 for (j = 0 ; j < 32 ; j++) 2320 irq_create_mapping(bank->domain, j); 2321 2322 clk_disable(bank->clk); 2323 } 2324 2325 return 0; 2326 } 2327 2328 static int rockchip_gpiolib_register(struct platform_device *pdev, 2329 struct rockchip_pinctrl *info) 2330 { 2331 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2332 struct rockchip_pin_bank *bank = ctrl->pin_banks; 2333 struct gpio_chip *gc; 2334 int ret; 2335 int i; 2336 2337 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2338 if (!bank->valid) { 2339 dev_warn(&pdev->dev, "bank %s is not valid\n", 2340 bank->name); 2341 continue; 2342 } 2343 2344 bank->gpio_chip = rockchip_gpiolib_chip; 2345 2346 gc = &bank->gpio_chip; 2347 gc->base = bank->pin_base; 2348 gc->ngpio = bank->nr_pins; 2349 gc->parent = &pdev->dev; 2350 gc->of_node = bank->of_node; 2351 gc->label = bank->name; 2352 2353 ret = gpiochip_add_data(gc, bank); 2354 if (ret) { 2355 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 2356 gc->label, ret); 2357 goto fail; 2358 } 2359 } 2360 2361 rockchip_interrupts_register(pdev, info); 2362 2363 return 0; 2364 2365 fail: 2366 for (--i, --bank; i >= 0; --i, --bank) { 2367 if (!bank->valid) 2368 continue; 2369 gpiochip_remove(&bank->gpio_chip); 2370 } 2371 return ret; 2372 } 2373 2374 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 2375 struct rockchip_pinctrl *info) 2376 { 2377 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2378 struct rockchip_pin_bank *bank = ctrl->pin_banks; 2379 int i; 2380 2381 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2382 if (!bank->valid) 2383 continue; 2384 gpiochip_remove(&bank->gpio_chip); 2385 } 2386 2387 return 0; 2388 } 2389 2390 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 2391 struct rockchip_pinctrl *info) 2392 { 2393 struct resource res; 2394 void __iomem *base; 2395 2396 if (of_address_to_resource(bank->of_node, 0, &res)) { 2397 dev_err(info->dev, "cannot find IO resource for bank\n"); 2398 return -ENOENT; 2399 } 2400 2401 bank->reg_base = devm_ioremap_resource(info->dev, &res); 2402 if (IS_ERR(bank->reg_base)) 2403 return PTR_ERR(bank->reg_base); 2404 2405 /* 2406 * special case, where parts of the pull setting-registers are 2407 * part of the PMU register space 2408 */ 2409 if (of_device_is_compatible(bank->of_node, 2410 "rockchip,rk3188-gpio-bank0")) { 2411 struct device_node *node; 2412 2413 node = of_parse_phandle(bank->of_node->parent, 2414 "rockchip,pmu", 0); 2415 if (!node) { 2416 if (of_address_to_resource(bank->of_node, 1, &res)) { 2417 dev_err(info->dev, "cannot find IO resource for bank\n"); 2418 return -ENOENT; 2419 } 2420 2421 base = devm_ioremap_resource(info->dev, &res); 2422 if (IS_ERR(base)) 2423 return PTR_ERR(base); 2424 rockchip_regmap_config.max_register = 2425 resource_size(&res) - 4; 2426 rockchip_regmap_config.name = 2427 "rockchip,rk3188-gpio-bank0-pull"; 2428 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 2429 base, 2430 &rockchip_regmap_config); 2431 } 2432 } 2433 2434 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 2435 2436 bank->clk = of_clk_get(bank->of_node, 0); 2437 if (IS_ERR(bank->clk)) 2438 return PTR_ERR(bank->clk); 2439 2440 return clk_prepare(bank->clk); 2441 } 2442 2443 static const struct of_device_id rockchip_pinctrl_dt_match[]; 2444 2445 /* retrieve the soc specific data */ 2446 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 2447 struct rockchip_pinctrl *d, 2448 struct platform_device *pdev) 2449 { 2450 const struct of_device_id *match; 2451 struct device_node *node = pdev->dev.of_node; 2452 struct device_node *np; 2453 struct rockchip_pin_ctrl *ctrl; 2454 struct rockchip_pin_bank *bank; 2455 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2456 2457 match = of_match_node(rockchip_pinctrl_dt_match, node); 2458 ctrl = (struct rockchip_pin_ctrl *)match->data; 2459 2460 for_each_child_of_node(node, np) { 2461 if (!of_find_property(np, "gpio-controller", NULL)) 2462 continue; 2463 2464 bank = ctrl->pin_banks; 2465 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2466 if (!strcmp(bank->name, np->name)) { 2467 bank->of_node = np; 2468 2469 if (!rockchip_get_bank_data(bank, d)) 2470 bank->valid = true; 2471 2472 break; 2473 } 2474 } 2475 } 2476 2477 grf_offs = ctrl->grf_mux_offset; 2478 pmu_offs = ctrl->pmu_mux_offset; 2479 drv_pmu_offs = ctrl->pmu_drv_offset; 2480 drv_grf_offs = ctrl->grf_drv_offset; 2481 bank = ctrl->pin_banks; 2482 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2483 int bank_pins = 0; 2484 2485 raw_spin_lock_init(&bank->slock); 2486 bank->drvdata = d; 2487 bank->pin_base = ctrl->nr_pins; 2488 ctrl->nr_pins += bank->nr_pins; 2489 2490 /* calculate iomux and drv offsets */ 2491 for (j = 0; j < 4; j++) { 2492 struct rockchip_iomux *iom = &bank->iomux[j]; 2493 struct rockchip_drv *drv = &bank->drv[j]; 2494 int inc; 2495 2496 if (bank_pins >= bank->nr_pins) 2497 break; 2498 2499 /* preset iomux offset value, set new start value */ 2500 if (iom->offset >= 0) { 2501 if (iom->type & IOMUX_SOURCE_PMU) 2502 pmu_offs = iom->offset; 2503 else 2504 grf_offs = iom->offset; 2505 } else { /* set current iomux offset */ 2506 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2507 pmu_offs : grf_offs; 2508 } 2509 2510 /* preset drv offset value, set new start value */ 2511 if (drv->offset >= 0) { 2512 if (iom->type & IOMUX_SOURCE_PMU) 2513 drv_pmu_offs = drv->offset; 2514 else 2515 drv_grf_offs = drv->offset; 2516 } else { /* set current drv offset */ 2517 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2518 drv_pmu_offs : drv_grf_offs; 2519 } 2520 2521 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2522 i, j, iom->offset, drv->offset); 2523 2524 /* 2525 * Increase offset according to iomux width. 2526 * 4bit iomux'es are spread over two registers. 2527 */ 2528 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2529 IOMUX_WIDTH_3BIT)) ? 8 : 4; 2530 if (iom->type & IOMUX_SOURCE_PMU) 2531 pmu_offs += inc; 2532 else 2533 grf_offs += inc; 2534 2535 /* 2536 * Increase offset according to drv width. 2537 * 3bit drive-strenth'es are spread over two registers. 2538 */ 2539 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2540 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2541 inc = 8; 2542 else 2543 inc = 4; 2544 2545 if (iom->type & IOMUX_SOURCE_PMU) 2546 drv_pmu_offs += inc; 2547 else 2548 drv_grf_offs += inc; 2549 2550 bank_pins += 8; 2551 } 2552 } 2553 2554 return ctrl; 2555 } 2556 2557 #define RK3288_GRF_GPIO6C_IOMUX 0x64 2558 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 2559 2560 static u32 rk3288_grf_gpio6c_iomux; 2561 2562 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 2563 { 2564 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 2565 int ret = pinctrl_force_sleep(info->pctl_dev); 2566 2567 if (ret) 2568 return ret; 2569 2570 /* 2571 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 2572 * the setting here, and restore it at resume. 2573 */ 2574 if (info->ctrl->type == RK3288) { 2575 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 2576 &rk3288_grf_gpio6c_iomux); 2577 if (ret) { 2578 pinctrl_force_default(info->pctl_dev); 2579 return ret; 2580 } 2581 } 2582 2583 return 0; 2584 } 2585 2586 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 2587 { 2588 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 2589 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 2590 rk3288_grf_gpio6c_iomux | 2591 GPIO6C6_SEL_WRITE_ENABLE); 2592 2593 if (ret) 2594 return ret; 2595 2596 return pinctrl_force_default(info->pctl_dev); 2597 } 2598 2599 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 2600 rockchip_pinctrl_resume); 2601 2602 static int rockchip_pinctrl_probe(struct platform_device *pdev) 2603 { 2604 struct rockchip_pinctrl *info; 2605 struct device *dev = &pdev->dev; 2606 struct rockchip_pin_ctrl *ctrl; 2607 struct device_node *np = pdev->dev.of_node, *node; 2608 struct resource *res; 2609 void __iomem *base; 2610 int ret; 2611 2612 if (!dev->of_node) { 2613 dev_err(dev, "device tree node not found\n"); 2614 return -ENODEV; 2615 } 2616 2617 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); 2618 if (!info) 2619 return -ENOMEM; 2620 2621 info->dev = dev; 2622 2623 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 2624 if (!ctrl) { 2625 dev_err(dev, "driver data not available\n"); 2626 return -EINVAL; 2627 } 2628 info->ctrl = ctrl; 2629 2630 node = of_parse_phandle(np, "rockchip,grf", 0); 2631 if (node) { 2632 info->regmap_base = syscon_node_to_regmap(node); 2633 if (IS_ERR(info->regmap_base)) 2634 return PTR_ERR(info->regmap_base); 2635 } else { 2636 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2637 base = devm_ioremap_resource(&pdev->dev, res); 2638 if (IS_ERR(base)) 2639 return PTR_ERR(base); 2640 2641 rockchip_regmap_config.max_register = resource_size(res) - 4; 2642 rockchip_regmap_config.name = "rockchip,pinctrl"; 2643 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 2644 &rockchip_regmap_config); 2645 2646 /* to check for the old dt-bindings */ 2647 info->reg_size = resource_size(res); 2648 2649 /* Honor the old binding, with pull registers as 2nd resource */ 2650 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 2651 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2652 base = devm_ioremap_resource(&pdev->dev, res); 2653 if (IS_ERR(base)) 2654 return PTR_ERR(base); 2655 2656 rockchip_regmap_config.max_register = 2657 resource_size(res) - 4; 2658 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 2659 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 2660 base, 2661 &rockchip_regmap_config); 2662 } 2663 } 2664 2665 /* try to find the optional reference to the pmu syscon */ 2666 node = of_parse_phandle(np, "rockchip,pmu", 0); 2667 if (node) { 2668 info->regmap_pmu = syscon_node_to_regmap(node); 2669 if (IS_ERR(info->regmap_pmu)) 2670 return PTR_ERR(info->regmap_pmu); 2671 } 2672 2673 ret = rockchip_gpiolib_register(pdev, info); 2674 if (ret) 2675 return ret; 2676 2677 ret = rockchip_pinctrl_register(pdev, info); 2678 if (ret) { 2679 rockchip_gpiolib_unregister(pdev, info); 2680 return ret; 2681 } 2682 2683 platform_set_drvdata(pdev, info); 2684 2685 return 0; 2686 } 2687 2688 static struct rockchip_pin_bank rv1108_pin_banks[] = { 2689 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2690 IOMUX_SOURCE_PMU, 2691 IOMUX_SOURCE_PMU, 2692 IOMUX_SOURCE_PMU), 2693 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2694 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 2695 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 2696 }; 2697 2698 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 2699 .pin_banks = rv1108_pin_banks, 2700 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 2701 .label = "RV1108-GPIO", 2702 .type = RV1108, 2703 .grf_mux_offset = 0x10, 2704 .pmu_mux_offset = 0x0, 2705 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 2706 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 2707 }; 2708 2709 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2710 PIN_BANK(0, 32, "gpio0"), 2711 PIN_BANK(1, 32, "gpio1"), 2712 PIN_BANK(2, 32, "gpio2"), 2713 PIN_BANK(3, 32, "gpio3"), 2714 }; 2715 2716 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2717 .pin_banks = rk2928_pin_banks, 2718 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2719 .label = "RK2928-GPIO", 2720 .type = RK2928, 2721 .grf_mux_offset = 0xa8, 2722 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2723 }; 2724 2725 static struct rockchip_pin_bank rk3036_pin_banks[] = { 2726 PIN_BANK(0, 32, "gpio0"), 2727 PIN_BANK(1, 32, "gpio1"), 2728 PIN_BANK(2, 32, "gpio2"), 2729 }; 2730 2731 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 2732 .pin_banks = rk3036_pin_banks, 2733 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 2734 .label = "RK3036-GPIO", 2735 .type = RK2928, 2736 .grf_mux_offset = 0xa8, 2737 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2738 }; 2739 2740 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2741 PIN_BANK(0, 32, "gpio0"), 2742 PIN_BANK(1, 32, "gpio1"), 2743 PIN_BANK(2, 32, "gpio2"), 2744 PIN_BANK(3, 32, "gpio3"), 2745 PIN_BANK(4, 32, "gpio4"), 2746 PIN_BANK(6, 16, "gpio6"), 2747 }; 2748 2749 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 2750 .pin_banks = rk3066a_pin_banks, 2751 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 2752 .label = "RK3066a-GPIO", 2753 .type = RK2928, 2754 .grf_mux_offset = 0xa8, 2755 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2756 }; 2757 2758 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 2759 PIN_BANK(0, 32, "gpio0"), 2760 PIN_BANK(1, 32, "gpio1"), 2761 PIN_BANK(2, 32, "gpio2"), 2762 PIN_BANK(3, 32, "gpio3"), 2763 }; 2764 2765 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 2766 .pin_banks = rk3066b_pin_banks, 2767 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 2768 .label = "RK3066b-GPIO", 2769 .type = RK3066B, 2770 .grf_mux_offset = 0x60, 2771 }; 2772 2773 static struct rockchip_pin_bank rk3188_pin_banks[] = { 2774 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 2775 PIN_BANK(1, 32, "gpio1"), 2776 PIN_BANK(2, 32, "gpio2"), 2777 PIN_BANK(3, 32, "gpio3"), 2778 }; 2779 2780 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 2781 .pin_banks = rk3188_pin_banks, 2782 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 2783 .label = "RK3188-GPIO", 2784 .type = RK3188, 2785 .grf_mux_offset = 0x60, 2786 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 2787 }; 2788 2789 static struct rockchip_pin_bank rk3228_pin_banks[] = { 2790 PIN_BANK(0, 32, "gpio0"), 2791 PIN_BANK(1, 32, "gpio1"), 2792 PIN_BANK(2, 32, "gpio2"), 2793 PIN_BANK(3, 32, "gpio3"), 2794 }; 2795 2796 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 2797 .pin_banks = rk3228_pin_banks, 2798 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 2799 .label = "RK3228-GPIO", 2800 .type = RK3288, 2801 .grf_mux_offset = 0x0, 2802 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2803 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2804 }; 2805 2806 static struct rockchip_pin_bank rk3288_pin_banks[] = { 2807 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 2808 IOMUX_SOURCE_PMU, 2809 IOMUX_SOURCE_PMU, 2810 IOMUX_UNROUTED 2811 ), 2812 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 2813 IOMUX_UNROUTED, 2814 IOMUX_UNROUTED, 2815 0 2816 ), 2817 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 2818 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 2819 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 2820 IOMUX_WIDTH_4BIT, 2821 0, 2822 0 2823 ), 2824 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 2825 0, 2826 0, 2827 IOMUX_UNROUTED 2828 ), 2829 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 2830 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 2831 0, 2832 IOMUX_WIDTH_4BIT, 2833 IOMUX_UNROUTED 2834 ), 2835 PIN_BANK(8, 16, "gpio8"), 2836 }; 2837 2838 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 2839 .pin_banks = rk3288_pin_banks, 2840 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 2841 .label = "RK3288-GPIO", 2842 .type = RK3288, 2843 .grf_mux_offset = 0x0, 2844 .pmu_mux_offset = 0x84, 2845 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 2846 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 2847 }; 2848 2849 static struct rockchip_pin_bank rk3328_pin_banks[] = { 2850 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 2851 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2852 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 2853 IOMUX_WIDTH_3BIT | IOMUX_RECALCED, 2854 IOMUX_WIDTH_3BIT | IOMUX_RECALCED, 2855 0), 2856 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 2857 IOMUX_WIDTH_3BIT, 2858 IOMUX_WIDTH_3BIT | IOMUX_RECALCED, 2859 0, 2860 0), 2861 }; 2862 2863 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 2864 .pin_banks = rk3328_pin_banks, 2865 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 2866 .label = "RK3328-GPIO", 2867 .type = RK3288, 2868 .grf_mux_offset = 0x0, 2869 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2870 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2871 .iomux_recalc = rk3328_recalc_mux, 2872 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 2873 }; 2874 2875 static struct rockchip_pin_bank rk3368_pin_banks[] = { 2876 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2877 IOMUX_SOURCE_PMU, 2878 IOMUX_SOURCE_PMU, 2879 IOMUX_SOURCE_PMU 2880 ), 2881 PIN_BANK(1, 32, "gpio1"), 2882 PIN_BANK(2, 32, "gpio2"), 2883 PIN_BANK(3, 32, "gpio3"), 2884 }; 2885 2886 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 2887 .pin_banks = rk3368_pin_banks, 2888 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 2889 .label = "RK3368-GPIO", 2890 .type = RK3368, 2891 .grf_mux_offset = 0x0, 2892 .pmu_mux_offset = 0x0, 2893 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 2894 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 2895 }; 2896 2897 static struct rockchip_pin_bank rk3399_pin_banks[] = { 2898 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 2899 IOMUX_SOURCE_PMU, 2900 IOMUX_SOURCE_PMU, 2901 IOMUX_SOURCE_PMU, 2902 IOMUX_SOURCE_PMU, 2903 DRV_TYPE_IO_1V8_ONLY, 2904 DRV_TYPE_IO_1V8_ONLY, 2905 DRV_TYPE_IO_DEFAULT, 2906 DRV_TYPE_IO_DEFAULT, 2907 0x0, 2908 0x8, 2909 -1, 2910 -1, 2911 PULL_TYPE_IO_1V8_ONLY, 2912 PULL_TYPE_IO_1V8_ONLY, 2913 PULL_TYPE_IO_DEFAULT, 2914 PULL_TYPE_IO_DEFAULT 2915 ), 2916 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 2917 IOMUX_SOURCE_PMU, 2918 IOMUX_SOURCE_PMU, 2919 IOMUX_SOURCE_PMU, 2920 DRV_TYPE_IO_1V8_OR_3V0, 2921 DRV_TYPE_IO_1V8_OR_3V0, 2922 DRV_TYPE_IO_1V8_OR_3V0, 2923 DRV_TYPE_IO_1V8_OR_3V0, 2924 0x20, 2925 0x28, 2926 0x30, 2927 0x38 2928 ), 2929 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 2930 DRV_TYPE_IO_1V8_OR_3V0, 2931 DRV_TYPE_IO_1V8_ONLY, 2932 DRV_TYPE_IO_1V8_ONLY, 2933 PULL_TYPE_IO_DEFAULT, 2934 PULL_TYPE_IO_DEFAULT, 2935 PULL_TYPE_IO_1V8_ONLY, 2936 PULL_TYPE_IO_1V8_ONLY 2937 ), 2938 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 2939 DRV_TYPE_IO_3V3_ONLY, 2940 DRV_TYPE_IO_3V3_ONLY, 2941 DRV_TYPE_IO_1V8_OR_3V0 2942 ), 2943 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 2944 DRV_TYPE_IO_1V8_3V0_AUTO, 2945 DRV_TYPE_IO_1V8_OR_3V0, 2946 DRV_TYPE_IO_1V8_OR_3V0 2947 ), 2948 }; 2949 2950 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 2951 .pin_banks = rk3399_pin_banks, 2952 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 2953 .label = "RK3399-GPIO", 2954 .type = RK3399, 2955 .grf_mux_offset = 0xe000, 2956 .pmu_mux_offset = 0x0, 2957 .grf_drv_offset = 0xe100, 2958 .pmu_drv_offset = 0x80, 2959 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 2960 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 2961 }; 2962 2963 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 2964 { .compatible = "rockchip,rv1108-pinctrl", 2965 .data = (void *)&rv1108_pin_ctrl }, 2966 { .compatible = "rockchip,rk2928-pinctrl", 2967 .data = (void *)&rk2928_pin_ctrl }, 2968 { .compatible = "rockchip,rk3036-pinctrl", 2969 .data = (void *)&rk3036_pin_ctrl }, 2970 { .compatible = "rockchip,rk3066a-pinctrl", 2971 .data = (void *)&rk3066a_pin_ctrl }, 2972 { .compatible = "rockchip,rk3066b-pinctrl", 2973 .data = (void *)&rk3066b_pin_ctrl }, 2974 { .compatible = "rockchip,rk3188-pinctrl", 2975 .data = (void *)&rk3188_pin_ctrl }, 2976 { .compatible = "rockchip,rk3228-pinctrl", 2977 .data = (void *)&rk3228_pin_ctrl }, 2978 { .compatible = "rockchip,rk3288-pinctrl", 2979 .data = (void *)&rk3288_pin_ctrl }, 2980 { .compatible = "rockchip,rk3328-pinctrl", 2981 .data = (void *)&rk3328_pin_ctrl }, 2982 { .compatible = "rockchip,rk3368-pinctrl", 2983 .data = (void *)&rk3368_pin_ctrl }, 2984 { .compatible = "rockchip,rk3399-pinctrl", 2985 .data = (void *)&rk3399_pin_ctrl }, 2986 {}, 2987 }; 2988 2989 static struct platform_driver rockchip_pinctrl_driver = { 2990 .probe = rockchip_pinctrl_probe, 2991 .driver = { 2992 .name = "rockchip-pinctrl", 2993 .pm = &rockchip_pinctrl_dev_pm_ops, 2994 .of_match_table = rockchip_pinctrl_dt_match, 2995 }, 2996 }; 2997 2998 static int __init rockchip_pinctrl_drv_register(void) 2999 { 3000 return platform_driver_register(&rockchip_pinctrl_driver); 3001 } 3002 postcore_initcall(rockchip_pinctrl_drv_register); 3003