1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Pinctrl driver for Rockchip SoCs 4 * 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * https://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/io.h> 22 #include <linux/bitops.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/of.h> 25 #include <linux/of_platform.h> 26 #include <linux/pinctrl/machine.h> 27 #include <linux/pinctrl/pinconf.h> 28 #include <linux/pinctrl/pinctrl.h> 29 #include <linux/pinctrl/pinmux.h> 30 #include <linux/pinctrl/pinconf-generic.h> 31 #include <linux/irqchip/chained_irq.h> 32 #include <linux/clk.h> 33 #include <linux/regmap.h> 34 #include <linux/mfd/syscon.h> 35 #include <linux/string_helpers.h> 36 37 #include <dt-bindings/pinctrl/rockchip.h> 38 39 #include "core.h" 40 #include "pinconf.h" 41 #include "pinctrl-rockchip.h" 42 43 /* 44 * Generate a bitmask for setting a value (v) with a write mask bit in hiword 45 * register 31:16 area. 46 */ 47 #define WRITE_MASK_VAL(h, l, v) \ 48 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 49 50 /* 51 * Encode variants of iomux registers into a type variable 52 */ 53 #define IOMUX_GPIO_ONLY BIT(0) 54 #define IOMUX_WIDTH_4BIT BIT(1) 55 #define IOMUX_SOURCE_PMU BIT(2) 56 #define IOMUX_UNROUTED BIT(3) 57 #define IOMUX_WIDTH_3BIT BIT(4) 58 #define IOMUX_WIDTH_2BIT BIT(5) 59 #define IOMUX_L_SOURCE_PMU BIT(6) 60 61 #define PIN_BANK(id, pins, label) \ 62 { \ 63 .bank_num = id, \ 64 .nr_pins = pins, \ 65 .name = label, \ 66 .iomux = { \ 67 { .offset = -1 }, \ 68 { .offset = -1 }, \ 69 { .offset = -1 }, \ 70 { .offset = -1 }, \ 71 }, \ 72 } 73 74 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 75 { \ 76 .bank_num = id, \ 77 .nr_pins = pins, \ 78 .name = label, \ 79 .iomux = { \ 80 { .type = iom0, .offset = -1 }, \ 81 { .type = iom1, .offset = -1 }, \ 82 { .type = iom2, .offset = -1 }, \ 83 { .type = iom3, .offset = -1 }, \ 84 }, \ 85 } 86 87 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 88 { \ 89 .bank_num = id, \ 90 .nr_pins = pins, \ 91 .name = label, \ 92 .iomux = { \ 93 { .offset = -1 }, \ 94 { .offset = -1 }, \ 95 { .offset = -1 }, \ 96 { .offset = -1 }, \ 97 }, \ 98 .drv = { \ 99 { .drv_type = type0, .offset = -1 }, \ 100 { .drv_type = type1, .offset = -1 }, \ 101 { .drv_type = type2, .offset = -1 }, \ 102 { .drv_type = type3, .offset = -1 }, \ 103 }, \ 104 } 105 106 #define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \ 107 iom2, iom3, pull0, pull1, \ 108 pull2, pull3) \ 109 { \ 110 .bank_num = id, \ 111 .nr_pins = pins, \ 112 .name = label, \ 113 .iomux = { \ 114 { .type = iom0, .offset = -1 }, \ 115 { .type = iom1, .offset = -1 }, \ 116 { .type = iom2, .offset = -1 }, \ 117 { .type = iom3, .offset = -1 }, \ 118 }, \ 119 .pull_type[0] = pull0, \ 120 .pull_type[1] = pull1, \ 121 .pull_type[2] = pull2, \ 122 .pull_type[3] = pull3, \ 123 } 124 125 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 126 drv2, drv3, pull0, pull1, \ 127 pull2, pull3) \ 128 { \ 129 .bank_num = id, \ 130 .nr_pins = pins, \ 131 .name = label, \ 132 .iomux = { \ 133 { .offset = -1 }, \ 134 { .offset = -1 }, \ 135 { .offset = -1 }, \ 136 { .offset = -1 }, \ 137 }, \ 138 .drv = { \ 139 { .drv_type = drv0, .offset = -1 }, \ 140 { .drv_type = drv1, .offset = -1 }, \ 141 { .drv_type = drv2, .offset = -1 }, \ 142 { .drv_type = drv3, .offset = -1 }, \ 143 }, \ 144 .pull_type[0] = pull0, \ 145 .pull_type[1] = pull1, \ 146 .pull_type[2] = pull2, \ 147 .pull_type[3] = pull3, \ 148 } 149 150 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \ 151 iom3, offset0, offset1, offset2, \ 152 offset3) \ 153 { \ 154 .bank_num = id, \ 155 .nr_pins = pins, \ 156 .name = label, \ 157 .iomux = { \ 158 { .type = iom0, .offset = offset0 }, \ 159 { .type = iom1, .offset = offset1 }, \ 160 { .type = iom2, .offset = offset2 }, \ 161 { .type = iom3, .offset = offset3 }, \ 162 }, \ 163 } 164 165 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 166 iom2, iom3, drv0, drv1, drv2, \ 167 drv3, offset0, offset1, \ 168 offset2, offset3) \ 169 { \ 170 .bank_num = id, \ 171 .nr_pins = pins, \ 172 .name = label, \ 173 .iomux = { \ 174 { .type = iom0, .offset = -1 }, \ 175 { .type = iom1, .offset = -1 }, \ 176 { .type = iom2, .offset = -1 }, \ 177 { .type = iom3, .offset = -1 }, \ 178 }, \ 179 .drv = { \ 180 { .drv_type = drv0, .offset = offset0 }, \ 181 { .drv_type = drv1, .offset = offset1 }, \ 182 { .drv_type = drv2, .offset = offset2 }, \ 183 { .drv_type = drv3, .offset = offset3 }, \ 184 }, \ 185 } 186 187 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 188 label, iom0, iom1, iom2, \ 189 iom3, drv0, drv1, drv2, \ 190 drv3, offset0, offset1, \ 191 offset2, offset3, pull0, \ 192 pull1, pull2, pull3) \ 193 { \ 194 .bank_num = id, \ 195 .nr_pins = pins, \ 196 .name = label, \ 197 .iomux = { \ 198 { .type = iom0, .offset = -1 }, \ 199 { .type = iom1, .offset = -1 }, \ 200 { .type = iom2, .offset = -1 }, \ 201 { .type = iom3, .offset = -1 }, \ 202 }, \ 203 .drv = { \ 204 { .drv_type = drv0, .offset = offset0 }, \ 205 { .drv_type = drv1, .offset = offset1 }, \ 206 { .drv_type = drv2, .offset = offset2 }, \ 207 { .drv_type = drv3, .offset = offset3 }, \ 208 }, \ 209 .pull_type[0] = pull0, \ 210 .pull_type[1] = pull1, \ 211 .pull_type[2] = pull2, \ 212 .pull_type[3] = pull3, \ 213 } 214 215 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 216 { \ 217 .bank_num = ID, \ 218 .pin = PIN, \ 219 .func = FUNC, \ 220 .route_offset = REG, \ 221 .route_val = VAL, \ 222 .route_location = FLAG, \ 223 } 224 225 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \ 226 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME) 227 228 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \ 229 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF) 230 231 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ 232 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) 233 234 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \ 235 PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P) 236 237 static struct regmap_config rockchip_regmap_config = { 238 .reg_bits = 32, 239 .val_bits = 32, 240 .reg_stride = 4, 241 }; 242 243 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 244 const struct rockchip_pinctrl *info, 245 const char *name) 246 { 247 int i; 248 249 for (i = 0; i < info->ngroups; i++) { 250 if (!strcmp(info->groups[i].name, name)) 251 return &info->groups[i]; 252 } 253 254 return NULL; 255 } 256 257 /* 258 * given a pin number that is local to a pin controller, find out the pin bank 259 * and the register base of the pin bank. 260 */ 261 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 262 unsigned pin) 263 { 264 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 265 266 while (pin >= (b->pin_base + b->nr_pins)) 267 b++; 268 269 return b; 270 } 271 272 static struct rockchip_pin_bank *bank_num_to_bank( 273 struct rockchip_pinctrl *info, 274 unsigned num) 275 { 276 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 277 int i; 278 279 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 280 if (b->bank_num == num) 281 return b; 282 } 283 284 return ERR_PTR(-EINVAL); 285 } 286 287 /* 288 * Pinctrl_ops handling 289 */ 290 291 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 292 { 293 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 294 295 return info->ngroups; 296 } 297 298 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 299 unsigned selector) 300 { 301 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 302 303 return info->groups[selector].name; 304 } 305 306 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 307 unsigned selector, const unsigned **pins, 308 unsigned *npins) 309 { 310 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 311 312 if (selector >= info->ngroups) 313 return -EINVAL; 314 315 *pins = info->groups[selector].pins; 316 *npins = info->groups[selector].npins; 317 318 return 0; 319 } 320 321 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 322 struct device_node *np, 323 struct pinctrl_map **map, unsigned *num_maps) 324 { 325 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 326 const struct rockchip_pin_group *grp; 327 struct device *dev = info->dev; 328 struct pinctrl_map *new_map; 329 struct device_node *parent; 330 int map_num = 1; 331 int i; 332 333 /* 334 * first find the group of this node and check if we need to create 335 * config maps for pins 336 */ 337 grp = pinctrl_name_to_group(info, np->name); 338 if (!grp) { 339 dev_err(dev, "unable to find group for node %pOFn\n", np); 340 return -EINVAL; 341 } 342 343 map_num += grp->npins; 344 345 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); 346 if (!new_map) 347 return -ENOMEM; 348 349 *map = new_map; 350 *num_maps = map_num; 351 352 /* create mux map */ 353 parent = of_get_parent(np); 354 if (!parent) { 355 kfree(new_map); 356 return -EINVAL; 357 } 358 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 359 new_map[0].data.mux.function = parent->name; 360 new_map[0].data.mux.group = np->name; 361 of_node_put(parent); 362 363 /* create config map */ 364 new_map++; 365 for (i = 0; i < grp->npins; i++) { 366 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 367 new_map[i].data.configs.group_or_pin = 368 pin_get_name(pctldev, grp->pins[i]); 369 new_map[i].data.configs.configs = grp->data[i].configs; 370 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 371 } 372 373 dev_dbg(dev, "maps: function %s group %s num %d\n", 374 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 375 376 return 0; 377 } 378 379 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 380 struct pinctrl_map *map, unsigned num_maps) 381 { 382 kfree(map); 383 } 384 385 static const struct pinctrl_ops rockchip_pctrl_ops = { 386 .get_groups_count = rockchip_get_groups_count, 387 .get_group_name = rockchip_get_group_name, 388 .get_group_pins = rockchip_get_group_pins, 389 .dt_node_to_map = rockchip_dt_node_to_map, 390 .dt_free_map = rockchip_dt_free_map, 391 }; 392 393 /* 394 * Hardware access 395 */ 396 397 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 398 { 399 .num = 1, 400 .pin = 0, 401 .reg = 0x418, 402 .bit = 0, 403 .mask = 0x3 404 }, { 405 .num = 1, 406 .pin = 1, 407 .reg = 0x418, 408 .bit = 2, 409 .mask = 0x3 410 }, { 411 .num = 1, 412 .pin = 2, 413 .reg = 0x418, 414 .bit = 4, 415 .mask = 0x3 416 }, { 417 .num = 1, 418 .pin = 3, 419 .reg = 0x418, 420 .bit = 6, 421 .mask = 0x3 422 }, { 423 .num = 1, 424 .pin = 4, 425 .reg = 0x418, 426 .bit = 8, 427 .mask = 0x3 428 }, { 429 .num = 1, 430 .pin = 5, 431 .reg = 0x418, 432 .bit = 10, 433 .mask = 0x3 434 }, { 435 .num = 1, 436 .pin = 6, 437 .reg = 0x418, 438 .bit = 12, 439 .mask = 0x3 440 }, { 441 .num = 1, 442 .pin = 7, 443 .reg = 0x418, 444 .bit = 14, 445 .mask = 0x3 446 }, { 447 .num = 1, 448 .pin = 8, 449 .reg = 0x41c, 450 .bit = 0, 451 .mask = 0x3 452 }, { 453 .num = 1, 454 .pin = 9, 455 .reg = 0x41c, 456 .bit = 2, 457 .mask = 0x3 458 }, 459 }; 460 461 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { 462 { 463 .num = 0, 464 .pin = 20, 465 .reg = 0x10000, 466 .bit = 0, 467 .mask = 0xf 468 }, 469 { 470 .num = 0, 471 .pin = 21, 472 .reg = 0x10000, 473 .bit = 4, 474 .mask = 0xf 475 }, 476 { 477 .num = 0, 478 .pin = 22, 479 .reg = 0x10000, 480 .bit = 8, 481 .mask = 0xf 482 }, 483 { 484 .num = 0, 485 .pin = 23, 486 .reg = 0x10000, 487 .bit = 12, 488 .mask = 0xf 489 }, 490 }; 491 492 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 493 { 494 .num = 2, 495 .pin = 20, 496 .reg = 0xe8, 497 .bit = 0, 498 .mask = 0x7 499 }, { 500 .num = 2, 501 .pin = 21, 502 .reg = 0xe8, 503 .bit = 4, 504 .mask = 0x7 505 }, { 506 .num = 2, 507 .pin = 22, 508 .reg = 0xe8, 509 .bit = 8, 510 .mask = 0x7 511 }, { 512 .num = 2, 513 .pin = 23, 514 .reg = 0xe8, 515 .bit = 12, 516 .mask = 0x7 517 }, { 518 .num = 2, 519 .pin = 24, 520 .reg = 0xd4, 521 .bit = 12, 522 .mask = 0x7 523 }, 524 }; 525 526 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 527 { 528 /* gpio1b6_sel */ 529 .num = 1, 530 .pin = 14, 531 .reg = 0x28, 532 .bit = 12, 533 .mask = 0xf 534 }, { 535 /* gpio1b7_sel */ 536 .num = 1, 537 .pin = 15, 538 .reg = 0x2c, 539 .bit = 0, 540 .mask = 0x3 541 }, { 542 /* gpio1c2_sel */ 543 .num = 1, 544 .pin = 18, 545 .reg = 0x30, 546 .bit = 4, 547 .mask = 0xf 548 }, { 549 /* gpio1c3_sel */ 550 .num = 1, 551 .pin = 19, 552 .reg = 0x30, 553 .bit = 8, 554 .mask = 0xf 555 }, { 556 /* gpio1c4_sel */ 557 .num = 1, 558 .pin = 20, 559 .reg = 0x30, 560 .bit = 12, 561 .mask = 0xf 562 }, { 563 /* gpio1c5_sel */ 564 .num = 1, 565 .pin = 21, 566 .reg = 0x34, 567 .bit = 0, 568 .mask = 0xf 569 }, { 570 /* gpio1c6_sel */ 571 .num = 1, 572 .pin = 22, 573 .reg = 0x34, 574 .bit = 4, 575 .mask = 0xf 576 }, { 577 /* gpio1c7_sel */ 578 .num = 1, 579 .pin = 23, 580 .reg = 0x34, 581 .bit = 8, 582 .mask = 0xf 583 }, { 584 /* gpio2a2_sel */ 585 .num = 2, 586 .pin = 2, 587 .reg = 0x40, 588 .bit = 4, 589 .mask = 0x3 590 }, { 591 /* gpio2a3_sel */ 592 .num = 2, 593 .pin = 3, 594 .reg = 0x40, 595 .bit = 6, 596 .mask = 0x3 597 }, { 598 /* gpio2c0_sel */ 599 .num = 2, 600 .pin = 16, 601 .reg = 0x50, 602 .bit = 0, 603 .mask = 0x3 604 }, { 605 /* gpio3b2_sel */ 606 .num = 3, 607 .pin = 10, 608 .reg = 0x68, 609 .bit = 4, 610 .mask = 0x3 611 }, { 612 /* gpio3b3_sel */ 613 .num = 3, 614 .pin = 11, 615 .reg = 0x68, 616 .bit = 6, 617 .mask = 0x3 618 }, { 619 /* gpio3b4_sel */ 620 .num = 3, 621 .pin = 12, 622 .reg = 0x68, 623 .bit = 8, 624 .mask = 0xf 625 }, { 626 /* gpio3b5_sel */ 627 .num = 3, 628 .pin = 13, 629 .reg = 0x68, 630 .bit = 12, 631 .mask = 0xf 632 }, 633 }; 634 635 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 636 { 637 .num = 2, 638 .pin = 12, 639 .reg = 0x24, 640 .bit = 8, 641 .mask = 0x3 642 }, { 643 .num = 2, 644 .pin = 15, 645 .reg = 0x28, 646 .bit = 0, 647 .mask = 0x7 648 }, { 649 .num = 2, 650 .pin = 23, 651 .reg = 0x30, 652 .bit = 14, 653 .mask = 0x3 654 }, 655 }; 656 657 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 658 int *reg, u8 *bit, int *mask) 659 { 660 struct rockchip_pinctrl *info = bank->drvdata; 661 struct rockchip_pin_ctrl *ctrl = info->ctrl; 662 struct rockchip_mux_recalced_data *data; 663 int i; 664 665 for (i = 0; i < ctrl->niomux_recalced; i++) { 666 data = &ctrl->iomux_recalced[i]; 667 if (data->num == bank->bank_num && 668 data->pin == pin) 669 break; 670 } 671 672 if (i >= ctrl->niomux_recalced) 673 return; 674 675 *reg = data->reg; 676 *mask = data->mask; 677 *bit = data->bit; 678 } 679 680 static struct rockchip_mux_route_data px30_mux_route_data[] = { 681 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */ 682 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */ 683 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */ 684 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */ 685 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */ 686 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */ 687 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */ 688 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */ 689 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */ 690 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */ 691 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */ 692 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */ 693 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */ 694 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */ 695 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */ 696 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */ 697 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */ 698 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */ 699 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */ 700 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */ 701 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */ 702 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */ 703 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */ 704 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */ 705 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */ 706 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */ 707 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */ 708 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */ 709 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */ 710 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */ 711 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */ 712 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */ 713 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */ 714 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */ 715 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */ 716 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */ 717 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */ 718 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */ 719 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */ 720 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */ 721 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */ 722 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */ 723 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */ 724 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */ 725 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */ 726 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */ 727 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */ 728 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */ 729 }; 730 731 static struct rockchip_mux_route_data rv1126_mux_route_data[] = { 732 RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ 733 RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ 734 735 RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */ 736 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */ 737 RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */ 738 739 RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ 740 RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ 741 742 RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ 743 RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ 744 745 RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ 746 RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ 747 748 RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */ 749 RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */ 750 RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */ 751 752 RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ 753 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ 754 755 RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */ 756 RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */ 757 RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */ 758 759 RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */ 760 RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */ 761 RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */ 762 763 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ 764 RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ 765 766 RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ 767 RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ 768 769 RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */ 770 RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */ 771 772 RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */ 773 RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */ 774 775 RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */ 776 RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */ 777 778 RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ 779 RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ 780 781 RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ 782 RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ 783 784 RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */ 785 RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */ 786 RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */ 787 788 RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */ 789 RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */ 790 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */ 791 792 RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */ 793 RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */ 794 RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */ 795 796 RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */ 797 RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */ 798 799 RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */ 800 RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */ 801 802 RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */ 803 RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */ 804 805 RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ 806 RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ 807 808 RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */ 809 RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */ 810 811 RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */ 812 RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */ 813 814 RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */ 815 RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */ 816 817 RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ 818 RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ 819 820 RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */ 821 RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */ 822 RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */ 823 824 RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ 825 RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ 826 }; 827 828 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 829 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ 830 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ 831 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ 832 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */ 833 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */ 834 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */ 835 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ 836 }; 837 838 static struct rockchip_mux_route_data rk3188_mux_route_data[] = { 839 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ 840 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ 841 }; 842 843 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 844 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ 845 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ 846 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ 847 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */ 848 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */ 849 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */ 850 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */ 851 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */ 852 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */ 853 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */ 854 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */ 855 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */ 856 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */ 857 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */ 858 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */ 859 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */ 860 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */ 861 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ 862 }; 863 864 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 865 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ 866 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ 867 }; 868 869 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 870 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ 871 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ 872 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ 873 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */ 874 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) | BIT(4)), /* i2c3_sdam1 */ 875 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ 876 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ 877 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ 878 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ 879 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ 880 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ 881 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ 882 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ 883 }; 884 885 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 886 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ 887 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ 888 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ 889 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */ 890 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */ 891 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */ 892 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */ 893 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */ 894 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */ 895 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */ 896 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */ 897 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ 898 }; 899 900 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 901 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ 902 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ 903 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ 904 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */ 905 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ 906 }; 907 908 static struct rockchip_mux_route_data rk3568_mux_route_data[] = { 909 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ 910 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ 911 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ 912 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */ 913 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */ 914 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */ 915 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */ 916 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */ 917 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */ 918 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */ 919 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */ 920 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */ 921 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */ 922 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */ 923 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */ 924 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */ 925 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */ 926 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */ 927 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */ 928 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */ 929 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */ 930 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */ 931 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */ 932 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */ 933 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */ 934 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */ 935 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */ 936 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */ 937 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */ 938 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */ 939 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */ 940 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */ 941 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */ 942 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */ 943 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */ 944 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */ 945 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */ 946 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */ 947 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */ 948 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */ 949 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */ 950 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */ 951 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */ 952 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */ 953 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */ 954 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */ 955 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */ 956 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */ 957 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */ 958 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */ 959 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */ 960 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */ 961 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */ 962 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */ 963 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */ 964 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */ 965 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */ 966 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */ 967 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */ 968 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */ 969 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */ 970 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */ 971 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */ 972 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */ 973 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */ 974 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */ 975 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */ 976 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */ 977 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */ 978 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */ 979 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */ 980 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */ 981 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */ 982 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */ 983 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */ 984 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */ 985 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */ 986 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */ 987 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */ 988 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 989 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 990 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 991 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 992 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */ 993 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */ 994 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */ 995 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */ 996 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */ 997 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */ 998 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */ 999 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */ 1000 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */ 1001 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */ 1002 }; 1003 1004 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1005 int mux, u32 *loc, u32 *reg, u32 *value) 1006 { 1007 struct rockchip_pinctrl *info = bank->drvdata; 1008 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1009 struct rockchip_mux_route_data *data; 1010 int i; 1011 1012 for (i = 0; i < ctrl->niomux_routes; i++) { 1013 data = &ctrl->iomux_routes[i]; 1014 if ((data->bank_num == bank->bank_num) && 1015 (data->pin == pin) && (data->func == mux)) 1016 break; 1017 } 1018 1019 if (i >= ctrl->niomux_routes) 1020 return false; 1021 1022 *loc = data->route_location; 1023 *reg = data->route_offset; 1024 *value = data->route_val; 1025 1026 return true; 1027 } 1028 1029 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1030 { 1031 struct rockchip_pinctrl *info = bank->drvdata; 1032 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1033 int iomux_num = (pin / 8); 1034 struct regmap *regmap; 1035 unsigned int val; 1036 int reg, ret, mask, mux_type; 1037 u8 bit; 1038 1039 if (iomux_num > 3) 1040 return -EINVAL; 1041 1042 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1043 dev_err(info->dev, "pin %d is unrouted\n", pin); 1044 return -EINVAL; 1045 } 1046 1047 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1048 return RK_FUNC_GPIO; 1049 1050 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1051 regmap = info->regmap_pmu; 1052 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1053 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; 1054 else 1055 regmap = info->regmap_base; 1056 1057 /* get basic quadrupel of mux registers and the correct reg inside */ 1058 mux_type = bank->iomux[iomux_num].type; 1059 reg = bank->iomux[iomux_num].offset; 1060 if (mux_type & IOMUX_WIDTH_4BIT) { 1061 if ((pin % 8) >= 4) 1062 reg += 0x4; 1063 bit = (pin % 4) * 4; 1064 mask = 0xf; 1065 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1066 if ((pin % 8) >= 5) 1067 reg += 0x4; 1068 bit = (pin % 8 % 5) * 3; 1069 mask = 0x7; 1070 } else { 1071 bit = (pin % 8) * 2; 1072 mask = 0x3; 1073 } 1074 1075 if (bank->recalced_mask & BIT(pin)) 1076 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1077 1078 if (ctrl->type == RK3588) { 1079 if (bank->bank_num == 0) { 1080 if ((pin >= RK_PB4) && (pin <= RK_PD7)) { 1081 u32 reg0 = 0; 1082 1083 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1084 ret = regmap_read(regmap, reg0, &val); 1085 if (ret) 1086 return ret; 1087 1088 if (!(val & BIT(8))) 1089 return ((val >> bit) & mask); 1090 1091 reg = reg + 0x8000; /* BUS_IOC_BASE */ 1092 regmap = info->regmap_base; 1093 } 1094 } else if (bank->bank_num > 0) { 1095 reg += 0x8000; /* BUS_IOC_BASE */ 1096 } 1097 } 1098 1099 ret = regmap_read(regmap, reg, &val); 1100 if (ret) 1101 return ret; 1102 1103 return ((val >> bit) & mask); 1104 } 1105 1106 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1107 int pin, int mux) 1108 { 1109 struct rockchip_pinctrl *info = bank->drvdata; 1110 struct device *dev = info->dev; 1111 int iomux_num = (pin / 8); 1112 1113 if (iomux_num > 3) 1114 return -EINVAL; 1115 1116 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1117 dev_err(dev, "pin %d is unrouted\n", pin); 1118 return -EINVAL; 1119 } 1120 1121 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1122 if (mux != RK_FUNC_GPIO) { 1123 dev_err(dev, "pin %d only supports a gpio mux\n", pin); 1124 return -ENOTSUPP; 1125 } 1126 } 1127 1128 return 0; 1129 } 1130 1131 /* 1132 * Set a new mux function for a pin. 1133 * 1134 * The register is divided into the upper and lower 16 bit. When changing 1135 * a value, the previous register value is not read and changed. Instead 1136 * it seems the changed bits are marked in the upper 16 bit, while the 1137 * changed value gets set in the same offset in the lower 16 bit. 1138 * All pin settings seem to be 2 bit wide in both the upper and lower 1139 * parts. 1140 * @bank: pin bank to change 1141 * @pin: pin to change 1142 * @mux: new mux function to set 1143 */ 1144 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1145 { 1146 struct rockchip_pinctrl *info = bank->drvdata; 1147 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1148 struct device *dev = info->dev; 1149 int iomux_num = (pin / 8); 1150 struct regmap *regmap; 1151 int reg, ret, mask, mux_type; 1152 u8 bit; 1153 u32 data, rmask, route_location, route_reg, route_val; 1154 1155 ret = rockchip_verify_mux(bank, pin, mux); 1156 if (ret < 0) 1157 return ret; 1158 1159 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1160 return 0; 1161 1162 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1163 1164 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1165 regmap = info->regmap_pmu; 1166 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1167 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; 1168 else 1169 regmap = info->regmap_base; 1170 1171 /* get basic quadrupel of mux registers and the correct reg inside */ 1172 mux_type = bank->iomux[iomux_num].type; 1173 reg = bank->iomux[iomux_num].offset; 1174 if (mux_type & IOMUX_WIDTH_4BIT) { 1175 if ((pin % 8) >= 4) 1176 reg += 0x4; 1177 bit = (pin % 4) * 4; 1178 mask = 0xf; 1179 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1180 if ((pin % 8) >= 5) 1181 reg += 0x4; 1182 bit = (pin % 8 % 5) * 3; 1183 mask = 0x7; 1184 } else { 1185 bit = (pin % 8) * 2; 1186 mask = 0x3; 1187 } 1188 1189 if (bank->recalced_mask & BIT(pin)) 1190 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1191 1192 if (ctrl->type == RK3588) { 1193 if (bank->bank_num == 0) { 1194 if ((pin >= RK_PB4) && (pin <= RK_PD7)) { 1195 if (mux < 8) { 1196 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1197 data = (mask << (bit + 16)); 1198 rmask = data | (data >> 16); 1199 data |= (mux & mask) << bit; 1200 ret = regmap_update_bits(regmap, reg, rmask, data); 1201 } else { 1202 u32 reg0 = 0; 1203 1204 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1205 data = (mask << (bit + 16)); 1206 rmask = data | (data >> 16); 1207 data |= 8 << bit; 1208 ret = regmap_update_bits(regmap, reg0, rmask, data); 1209 1210 reg0 = reg + 0x8000; /* BUS_IOC_BASE */ 1211 data = (mask << (bit + 16)); 1212 rmask = data | (data >> 16); 1213 data |= mux << bit; 1214 regmap = info->regmap_base; 1215 ret |= regmap_update_bits(regmap, reg0, rmask, data); 1216 } 1217 } else { 1218 data = (mask << (bit + 16)); 1219 rmask = data | (data >> 16); 1220 data |= (mux & mask) << bit; 1221 ret = regmap_update_bits(regmap, reg, rmask, data); 1222 } 1223 return ret; 1224 } else if (bank->bank_num > 0) { 1225 reg += 0x8000; /* BUS_IOC_BASE */ 1226 } 1227 } 1228 1229 if (mux > mask) 1230 return -EINVAL; 1231 1232 if (bank->route_mask & BIT(pin)) { 1233 if (rockchip_get_mux_route(bank, pin, mux, &route_location, 1234 &route_reg, &route_val)) { 1235 struct regmap *route_regmap = regmap; 1236 1237 /* handle special locations */ 1238 switch (route_location) { 1239 case ROCKCHIP_ROUTE_PMU: 1240 route_regmap = info->regmap_pmu; 1241 break; 1242 case ROCKCHIP_ROUTE_GRF: 1243 route_regmap = info->regmap_base; 1244 break; 1245 } 1246 1247 ret = regmap_write(route_regmap, route_reg, route_val); 1248 if (ret) 1249 return ret; 1250 } 1251 } 1252 1253 data = (mask << (bit + 16)); 1254 rmask = data | (data >> 16); 1255 data |= (mux & mask) << bit; 1256 ret = regmap_update_bits(regmap, reg, rmask, data); 1257 1258 return ret; 1259 } 1260 1261 #define PX30_PULL_PMU_OFFSET 0x10 1262 #define PX30_PULL_GRF_OFFSET 0x60 1263 #define PX30_PULL_BITS_PER_PIN 2 1264 #define PX30_PULL_PINS_PER_REG 8 1265 #define PX30_PULL_BANK_STRIDE 16 1266 1267 static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1268 int pin_num, struct regmap **regmap, 1269 int *reg, u8 *bit) 1270 { 1271 struct rockchip_pinctrl *info = bank->drvdata; 1272 1273 /* The first 32 pins of the first bank are located in PMU */ 1274 if (bank->bank_num == 0) { 1275 *regmap = info->regmap_pmu; 1276 *reg = PX30_PULL_PMU_OFFSET; 1277 } else { 1278 *regmap = info->regmap_base; 1279 *reg = PX30_PULL_GRF_OFFSET; 1280 1281 /* correct the offset, as we're starting with the 2nd bank */ 1282 *reg -= 0x10; 1283 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1284 } 1285 1286 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1287 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1288 *bit *= PX30_PULL_BITS_PER_PIN; 1289 1290 return 0; 1291 } 1292 1293 #define PX30_DRV_PMU_OFFSET 0x20 1294 #define PX30_DRV_GRF_OFFSET 0xf0 1295 #define PX30_DRV_BITS_PER_PIN 2 1296 #define PX30_DRV_PINS_PER_REG 8 1297 #define PX30_DRV_BANK_STRIDE 16 1298 1299 static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1300 int pin_num, struct regmap **regmap, 1301 int *reg, u8 *bit) 1302 { 1303 struct rockchip_pinctrl *info = bank->drvdata; 1304 1305 /* The first 32 pins of the first bank are located in PMU */ 1306 if (bank->bank_num == 0) { 1307 *regmap = info->regmap_pmu; 1308 *reg = PX30_DRV_PMU_OFFSET; 1309 } else { 1310 *regmap = info->regmap_base; 1311 *reg = PX30_DRV_GRF_OFFSET; 1312 1313 /* correct the offset, as we're starting with the 2nd bank */ 1314 *reg -= 0x10; 1315 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1316 } 1317 1318 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1319 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1320 *bit *= PX30_DRV_BITS_PER_PIN; 1321 1322 return 0; 1323 } 1324 1325 #define PX30_SCHMITT_PMU_OFFSET 0x38 1326 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1327 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1328 #define PX30_SCHMITT_BANK_STRIDE 16 1329 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1330 1331 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1332 int pin_num, 1333 struct regmap **regmap, 1334 int *reg, u8 *bit) 1335 { 1336 struct rockchip_pinctrl *info = bank->drvdata; 1337 int pins_per_reg; 1338 1339 if (bank->bank_num == 0) { 1340 *regmap = info->regmap_pmu; 1341 *reg = PX30_SCHMITT_PMU_OFFSET; 1342 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1343 } else { 1344 *regmap = info->regmap_base; 1345 *reg = PX30_SCHMITT_GRF_OFFSET; 1346 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1347 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1348 } 1349 1350 *reg += ((pin_num / pins_per_reg) * 4); 1351 *bit = pin_num % pins_per_reg; 1352 1353 return 0; 1354 } 1355 1356 #define RV1108_PULL_PMU_OFFSET 0x10 1357 #define RV1108_PULL_OFFSET 0x110 1358 #define RV1108_PULL_PINS_PER_REG 8 1359 #define RV1108_PULL_BITS_PER_PIN 2 1360 #define RV1108_PULL_BANK_STRIDE 16 1361 1362 static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1363 int pin_num, struct regmap **regmap, 1364 int *reg, u8 *bit) 1365 { 1366 struct rockchip_pinctrl *info = bank->drvdata; 1367 1368 /* The first 24 pins of the first bank are located in PMU */ 1369 if (bank->bank_num == 0) { 1370 *regmap = info->regmap_pmu; 1371 *reg = RV1108_PULL_PMU_OFFSET; 1372 } else { 1373 *reg = RV1108_PULL_OFFSET; 1374 *regmap = info->regmap_base; 1375 /* correct the offset, as we're starting with the 2nd bank */ 1376 *reg -= 0x10; 1377 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1378 } 1379 1380 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1381 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1382 *bit *= RV1108_PULL_BITS_PER_PIN; 1383 1384 return 0; 1385 } 1386 1387 #define RV1108_DRV_PMU_OFFSET 0x20 1388 #define RV1108_DRV_GRF_OFFSET 0x210 1389 #define RV1108_DRV_BITS_PER_PIN 2 1390 #define RV1108_DRV_PINS_PER_REG 8 1391 #define RV1108_DRV_BANK_STRIDE 16 1392 1393 static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1394 int pin_num, struct regmap **regmap, 1395 int *reg, u8 *bit) 1396 { 1397 struct rockchip_pinctrl *info = bank->drvdata; 1398 1399 /* The first 24 pins of the first bank are located in PMU */ 1400 if (bank->bank_num == 0) { 1401 *regmap = info->regmap_pmu; 1402 *reg = RV1108_DRV_PMU_OFFSET; 1403 } else { 1404 *regmap = info->regmap_base; 1405 *reg = RV1108_DRV_GRF_OFFSET; 1406 1407 /* correct the offset, as we're starting with the 2nd bank */ 1408 *reg -= 0x10; 1409 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1410 } 1411 1412 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1413 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1414 *bit *= RV1108_DRV_BITS_PER_PIN; 1415 1416 return 0; 1417 } 1418 1419 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1420 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1421 #define RV1108_SCHMITT_BANK_STRIDE 8 1422 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1423 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1424 1425 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1426 int pin_num, 1427 struct regmap **regmap, 1428 int *reg, u8 *bit) 1429 { 1430 struct rockchip_pinctrl *info = bank->drvdata; 1431 int pins_per_reg; 1432 1433 if (bank->bank_num == 0) { 1434 *regmap = info->regmap_pmu; 1435 *reg = RV1108_SCHMITT_PMU_OFFSET; 1436 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1437 } else { 1438 *regmap = info->regmap_base; 1439 *reg = RV1108_SCHMITT_GRF_OFFSET; 1440 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1441 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1442 } 1443 *reg += ((pin_num / pins_per_reg) * 4); 1444 *bit = pin_num % pins_per_reg; 1445 1446 return 0; 1447 } 1448 1449 #define RV1126_PULL_PMU_OFFSET 0x40 1450 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 1451 #define RV1126_PULL_PINS_PER_REG 8 1452 #define RV1126_PULL_BITS_PER_PIN 2 1453 #define RV1126_PULL_BANK_STRIDE 16 1454 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ 1455 1456 static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1457 int pin_num, struct regmap **regmap, 1458 int *reg, u8 *bit) 1459 { 1460 struct rockchip_pinctrl *info = bank->drvdata; 1461 1462 /* The first 24 pins of the first bank are located in PMU */ 1463 if (bank->bank_num == 0) { 1464 if (RV1126_GPIO_C4_D7(pin_num)) { 1465 *regmap = info->regmap_base; 1466 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1467 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); 1468 *bit = pin_num % RV1126_PULL_PINS_PER_REG; 1469 *bit *= RV1126_PULL_BITS_PER_PIN; 1470 return 0; 1471 } 1472 *regmap = info->regmap_pmu; 1473 *reg = RV1126_PULL_PMU_OFFSET; 1474 } else { 1475 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1476 *regmap = info->regmap_base; 1477 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; 1478 } 1479 1480 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); 1481 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); 1482 *bit *= RV1126_PULL_BITS_PER_PIN; 1483 1484 return 0; 1485 } 1486 1487 #define RV1126_DRV_PMU_OFFSET 0x20 1488 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 1489 #define RV1126_DRV_BITS_PER_PIN 4 1490 #define RV1126_DRV_PINS_PER_REG 4 1491 #define RV1126_DRV_BANK_STRIDE 32 1492 1493 static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1494 int pin_num, struct regmap **regmap, 1495 int *reg, u8 *bit) 1496 { 1497 struct rockchip_pinctrl *info = bank->drvdata; 1498 1499 /* The first 24 pins of the first bank are located in PMU */ 1500 if (bank->bank_num == 0) { 1501 if (RV1126_GPIO_C4_D7(pin_num)) { 1502 *regmap = info->regmap_base; 1503 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1504 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); 1505 *reg -= 0x4; 1506 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1507 *bit *= RV1126_DRV_BITS_PER_PIN; 1508 return 0; 1509 } 1510 *regmap = info->regmap_pmu; 1511 *reg = RV1126_DRV_PMU_OFFSET; 1512 } else { 1513 *regmap = info->regmap_base; 1514 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1515 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; 1516 } 1517 1518 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); 1519 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1520 *bit *= RV1126_DRV_BITS_PER_PIN; 1521 1522 return 0; 1523 } 1524 1525 #define RV1126_SCHMITT_PMU_OFFSET 0x60 1526 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 1527 #define RV1126_SCHMITT_BANK_STRIDE 16 1528 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8 1529 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8 1530 1531 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1532 int pin_num, 1533 struct regmap **regmap, 1534 int *reg, u8 *bit) 1535 { 1536 struct rockchip_pinctrl *info = bank->drvdata; 1537 int pins_per_reg; 1538 1539 if (bank->bank_num == 0) { 1540 if (RV1126_GPIO_C4_D7(pin_num)) { 1541 *regmap = info->regmap_base; 1542 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1543 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); 1544 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; 1545 return 0; 1546 } 1547 *regmap = info->regmap_pmu; 1548 *reg = RV1126_SCHMITT_PMU_OFFSET; 1549 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; 1550 } else { 1551 *regmap = info->regmap_base; 1552 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1553 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; 1554 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; 1555 } 1556 *reg += ((pin_num / pins_per_reg) * 4); 1557 *bit = pin_num % pins_per_reg; 1558 1559 return 0; 1560 } 1561 1562 #define RK3308_SCHMITT_PINS_PER_REG 8 1563 #define RK3308_SCHMITT_BANK_STRIDE 16 1564 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1565 1566 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1567 int pin_num, struct regmap **regmap, 1568 int *reg, u8 *bit) 1569 { 1570 struct rockchip_pinctrl *info = bank->drvdata; 1571 1572 *regmap = info->regmap_base; 1573 *reg = RK3308_SCHMITT_GRF_OFFSET; 1574 1575 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1576 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1577 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1578 1579 return 0; 1580 } 1581 1582 #define RK2928_PULL_OFFSET 0x118 1583 #define RK2928_PULL_PINS_PER_REG 16 1584 #define RK2928_PULL_BANK_STRIDE 8 1585 1586 static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1587 int pin_num, struct regmap **regmap, 1588 int *reg, u8 *bit) 1589 { 1590 struct rockchip_pinctrl *info = bank->drvdata; 1591 1592 *regmap = info->regmap_base; 1593 *reg = RK2928_PULL_OFFSET; 1594 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1595 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1596 1597 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1598 1599 return 0; 1600 }; 1601 1602 #define RK3128_PULL_OFFSET 0x118 1603 1604 static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1605 int pin_num, struct regmap **regmap, 1606 int *reg, u8 *bit) 1607 { 1608 struct rockchip_pinctrl *info = bank->drvdata; 1609 1610 *regmap = info->regmap_base; 1611 *reg = RK3128_PULL_OFFSET; 1612 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1613 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1614 1615 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1616 1617 return 0; 1618 } 1619 1620 #define RK3188_PULL_OFFSET 0x164 1621 #define RK3188_PULL_BITS_PER_PIN 2 1622 #define RK3188_PULL_PINS_PER_REG 8 1623 #define RK3188_PULL_BANK_STRIDE 16 1624 #define RK3188_PULL_PMU_OFFSET 0x64 1625 1626 static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1627 int pin_num, struct regmap **regmap, 1628 int *reg, u8 *bit) 1629 { 1630 struct rockchip_pinctrl *info = bank->drvdata; 1631 1632 /* The first 12 pins of the first bank are located elsewhere */ 1633 if (bank->bank_num == 0 && pin_num < 12) { 1634 *regmap = info->regmap_pmu ? info->regmap_pmu 1635 : bank->regmap_pull; 1636 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1637 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1638 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1639 *bit *= RK3188_PULL_BITS_PER_PIN; 1640 } else { 1641 *regmap = info->regmap_pull ? info->regmap_pull 1642 : info->regmap_base; 1643 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1644 1645 /* correct the offset, as it is the 2nd pull register */ 1646 *reg -= 4; 1647 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1648 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1649 1650 /* 1651 * The bits in these registers have an inverse ordering 1652 * with the lowest pin being in bits 15:14 and the highest 1653 * pin in bits 1:0 1654 */ 1655 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1656 *bit *= RK3188_PULL_BITS_PER_PIN; 1657 } 1658 1659 return 0; 1660 } 1661 1662 #define RK3288_PULL_OFFSET 0x140 1663 static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1664 int pin_num, struct regmap **regmap, 1665 int *reg, u8 *bit) 1666 { 1667 struct rockchip_pinctrl *info = bank->drvdata; 1668 1669 /* The first 24 pins of the first bank are located in PMU */ 1670 if (bank->bank_num == 0) { 1671 *regmap = info->regmap_pmu; 1672 *reg = RK3188_PULL_PMU_OFFSET; 1673 1674 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1675 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1676 *bit *= RK3188_PULL_BITS_PER_PIN; 1677 } else { 1678 *regmap = info->regmap_base; 1679 *reg = RK3288_PULL_OFFSET; 1680 1681 /* correct the offset, as we're starting with the 2nd bank */ 1682 *reg -= 0x10; 1683 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1684 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1685 1686 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1687 *bit *= RK3188_PULL_BITS_PER_PIN; 1688 } 1689 1690 return 0; 1691 } 1692 1693 #define RK3288_DRV_PMU_OFFSET 0x70 1694 #define RK3288_DRV_GRF_OFFSET 0x1c0 1695 #define RK3288_DRV_BITS_PER_PIN 2 1696 #define RK3288_DRV_PINS_PER_REG 8 1697 #define RK3288_DRV_BANK_STRIDE 16 1698 1699 static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1700 int pin_num, struct regmap **regmap, 1701 int *reg, u8 *bit) 1702 { 1703 struct rockchip_pinctrl *info = bank->drvdata; 1704 1705 /* The first 24 pins of the first bank are located in PMU */ 1706 if (bank->bank_num == 0) { 1707 *regmap = info->regmap_pmu; 1708 *reg = RK3288_DRV_PMU_OFFSET; 1709 1710 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1711 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1712 *bit *= RK3288_DRV_BITS_PER_PIN; 1713 } else { 1714 *regmap = info->regmap_base; 1715 *reg = RK3288_DRV_GRF_OFFSET; 1716 1717 /* correct the offset, as we're starting with the 2nd bank */ 1718 *reg -= 0x10; 1719 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1720 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1721 1722 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1723 *bit *= RK3288_DRV_BITS_PER_PIN; 1724 } 1725 1726 return 0; 1727 } 1728 1729 #define RK3228_PULL_OFFSET 0x100 1730 1731 static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1732 int pin_num, struct regmap **regmap, 1733 int *reg, u8 *bit) 1734 { 1735 struct rockchip_pinctrl *info = bank->drvdata; 1736 1737 *regmap = info->regmap_base; 1738 *reg = RK3228_PULL_OFFSET; 1739 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1740 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1741 1742 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1743 *bit *= RK3188_PULL_BITS_PER_PIN; 1744 1745 return 0; 1746 } 1747 1748 #define RK3228_DRV_GRF_OFFSET 0x200 1749 1750 static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1751 int pin_num, struct regmap **regmap, 1752 int *reg, u8 *bit) 1753 { 1754 struct rockchip_pinctrl *info = bank->drvdata; 1755 1756 *regmap = info->regmap_base; 1757 *reg = RK3228_DRV_GRF_OFFSET; 1758 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1759 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1760 1761 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1762 *bit *= RK3288_DRV_BITS_PER_PIN; 1763 1764 return 0; 1765 } 1766 1767 #define RK3308_PULL_OFFSET 0xa0 1768 1769 static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1770 int pin_num, struct regmap **regmap, 1771 int *reg, u8 *bit) 1772 { 1773 struct rockchip_pinctrl *info = bank->drvdata; 1774 1775 *regmap = info->regmap_base; 1776 *reg = RK3308_PULL_OFFSET; 1777 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1778 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1779 1780 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1781 *bit *= RK3188_PULL_BITS_PER_PIN; 1782 1783 return 0; 1784 } 1785 1786 #define RK3308_DRV_GRF_OFFSET 0x100 1787 1788 static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1789 int pin_num, struct regmap **regmap, 1790 int *reg, u8 *bit) 1791 { 1792 struct rockchip_pinctrl *info = bank->drvdata; 1793 1794 *regmap = info->regmap_base; 1795 *reg = RK3308_DRV_GRF_OFFSET; 1796 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1797 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1798 1799 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1800 *bit *= RK3288_DRV_BITS_PER_PIN; 1801 1802 return 0; 1803 } 1804 1805 #define RK3368_PULL_GRF_OFFSET 0x100 1806 #define RK3368_PULL_PMU_OFFSET 0x10 1807 1808 static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1809 int pin_num, struct regmap **regmap, 1810 int *reg, u8 *bit) 1811 { 1812 struct rockchip_pinctrl *info = bank->drvdata; 1813 1814 /* The first 32 pins of the first bank are located in PMU */ 1815 if (bank->bank_num == 0) { 1816 *regmap = info->regmap_pmu; 1817 *reg = RK3368_PULL_PMU_OFFSET; 1818 1819 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1820 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1821 *bit *= RK3188_PULL_BITS_PER_PIN; 1822 } else { 1823 *regmap = info->regmap_base; 1824 *reg = RK3368_PULL_GRF_OFFSET; 1825 1826 /* correct the offset, as we're starting with the 2nd bank */ 1827 *reg -= 0x10; 1828 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1829 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1830 1831 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1832 *bit *= RK3188_PULL_BITS_PER_PIN; 1833 } 1834 1835 return 0; 1836 } 1837 1838 #define RK3368_DRV_PMU_OFFSET 0x20 1839 #define RK3368_DRV_GRF_OFFSET 0x200 1840 1841 static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1842 int pin_num, struct regmap **regmap, 1843 int *reg, u8 *bit) 1844 { 1845 struct rockchip_pinctrl *info = bank->drvdata; 1846 1847 /* The first 32 pins of the first bank are located in PMU */ 1848 if (bank->bank_num == 0) { 1849 *regmap = info->regmap_pmu; 1850 *reg = RK3368_DRV_PMU_OFFSET; 1851 1852 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1853 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1854 *bit *= RK3288_DRV_BITS_PER_PIN; 1855 } else { 1856 *regmap = info->regmap_base; 1857 *reg = RK3368_DRV_GRF_OFFSET; 1858 1859 /* correct the offset, as we're starting with the 2nd bank */ 1860 *reg -= 0x10; 1861 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1862 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1863 1864 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1865 *bit *= RK3288_DRV_BITS_PER_PIN; 1866 } 1867 1868 return 0; 1869 } 1870 1871 #define RK3399_PULL_GRF_OFFSET 0xe040 1872 #define RK3399_PULL_PMU_OFFSET 0x40 1873 #define RK3399_DRV_3BITS_PER_PIN 3 1874 1875 static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1876 int pin_num, struct regmap **regmap, 1877 int *reg, u8 *bit) 1878 { 1879 struct rockchip_pinctrl *info = bank->drvdata; 1880 1881 /* The bank0:16 and bank1:32 pins are located in PMU */ 1882 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1883 *regmap = info->regmap_pmu; 1884 *reg = RK3399_PULL_PMU_OFFSET; 1885 1886 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1887 1888 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1889 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1890 *bit *= RK3188_PULL_BITS_PER_PIN; 1891 } else { 1892 *regmap = info->regmap_base; 1893 *reg = RK3399_PULL_GRF_OFFSET; 1894 1895 /* correct the offset, as we're starting with the 3rd bank */ 1896 *reg -= 0x20; 1897 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1898 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1899 1900 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1901 *bit *= RK3188_PULL_BITS_PER_PIN; 1902 } 1903 1904 return 0; 1905 } 1906 1907 static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1908 int pin_num, struct regmap **regmap, 1909 int *reg, u8 *bit) 1910 { 1911 struct rockchip_pinctrl *info = bank->drvdata; 1912 int drv_num = (pin_num / 8); 1913 1914 /* The bank0:16 and bank1:32 pins are located in PMU */ 1915 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1916 *regmap = info->regmap_pmu; 1917 else 1918 *regmap = info->regmap_base; 1919 1920 *reg = bank->drv[drv_num].offset; 1921 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1922 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1923 *bit = (pin_num % 8) * 3; 1924 else 1925 *bit = (pin_num % 8) * 2; 1926 1927 return 0; 1928 } 1929 1930 #define RK3568_PULL_PMU_OFFSET 0x20 1931 #define RK3568_PULL_GRF_OFFSET 0x80 1932 #define RK3568_PULL_BITS_PER_PIN 2 1933 #define RK3568_PULL_PINS_PER_REG 8 1934 #define RK3568_PULL_BANK_STRIDE 0x10 1935 1936 static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1937 int pin_num, struct regmap **regmap, 1938 int *reg, u8 *bit) 1939 { 1940 struct rockchip_pinctrl *info = bank->drvdata; 1941 1942 if (bank->bank_num == 0) { 1943 *regmap = info->regmap_pmu; 1944 *reg = RK3568_PULL_PMU_OFFSET; 1945 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; 1946 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 1947 1948 *bit = pin_num % RK3568_PULL_PINS_PER_REG; 1949 *bit *= RK3568_PULL_BITS_PER_PIN; 1950 } else { 1951 *regmap = info->regmap_base; 1952 *reg = RK3568_PULL_GRF_OFFSET; 1953 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; 1954 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 1955 1956 *bit = (pin_num % RK3568_PULL_PINS_PER_REG); 1957 *bit *= RK3568_PULL_BITS_PER_PIN; 1958 } 1959 1960 return 0; 1961 } 1962 1963 #define RK3568_DRV_PMU_OFFSET 0x70 1964 #define RK3568_DRV_GRF_OFFSET 0x200 1965 #define RK3568_DRV_BITS_PER_PIN 8 1966 #define RK3568_DRV_PINS_PER_REG 2 1967 #define RK3568_DRV_BANK_STRIDE 0x40 1968 1969 static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1970 int pin_num, struct regmap **regmap, 1971 int *reg, u8 *bit) 1972 { 1973 struct rockchip_pinctrl *info = bank->drvdata; 1974 1975 /* The first 32 pins of the first bank are located in PMU */ 1976 if (bank->bank_num == 0) { 1977 *regmap = info->regmap_pmu; 1978 *reg = RK3568_DRV_PMU_OFFSET; 1979 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 1980 1981 *bit = pin_num % RK3568_DRV_PINS_PER_REG; 1982 *bit *= RK3568_DRV_BITS_PER_PIN; 1983 } else { 1984 *regmap = info->regmap_base; 1985 *reg = RK3568_DRV_GRF_OFFSET; 1986 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; 1987 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 1988 1989 *bit = (pin_num % RK3568_DRV_PINS_PER_REG); 1990 *bit *= RK3568_DRV_BITS_PER_PIN; 1991 } 1992 1993 return 0; 1994 } 1995 1996 #define RK3588_PMU1_IOC_REG (0x0000) 1997 #define RK3588_PMU2_IOC_REG (0x4000) 1998 #define RK3588_BUS_IOC_REG (0x8000) 1999 #define RK3588_VCCIO1_4_IOC_REG (0x9000) 2000 #define RK3588_VCCIO3_5_IOC_REG (0xA000) 2001 #define RK3588_VCCIO2_IOC_REG (0xB000) 2002 #define RK3588_VCCIO6_IOC_REG (0xC000) 2003 #define RK3588_EMMC_IOC_REG (0xD000) 2004 2005 static const u32 rk3588_ds_regs[][2] = { 2006 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010}, 2007 {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014}, 2008 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018}, 2009 {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014}, 2010 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018}, 2011 {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C}, 2012 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020}, 2013 {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024}, 2014 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020}, 2015 {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024}, 2016 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028}, 2017 {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C}, 2018 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030}, 2019 {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034}, 2020 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038}, 2021 {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C}, 2022 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040}, 2023 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044}, 2024 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048}, 2025 {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C}, 2026 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050}, 2027 {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054}, 2028 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058}, 2029 {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C}, 2030 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060}, 2031 {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064}, 2032 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068}, 2033 {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C}, 2034 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070}, 2035 {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074}, 2036 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078}, 2037 {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C}, 2038 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080}, 2039 {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084}, 2040 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088}, 2041 {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C}, 2042 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090}, 2043 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090}, 2044 {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094}, 2045 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098}, 2046 {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C}, 2047 }; 2048 2049 static const u32 rk3588_p_regs[][2] = { 2050 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020}, 2051 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024}, 2052 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028}, 2053 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C}, 2054 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030}, 2055 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110}, 2056 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114}, 2057 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118}, 2058 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C}, 2059 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120}, 2060 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120}, 2061 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124}, 2062 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128}, 2063 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C}, 2064 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130}, 2065 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134}, 2066 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138}, 2067 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C}, 2068 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140}, 2069 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144}, 2070 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148}, 2071 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148}, 2072 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C}, 2073 }; 2074 2075 static const u32 rk3588_smt_regs[][2] = { 2076 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030}, 2077 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034}, 2078 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040}, 2079 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044}, 2080 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048}, 2081 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210}, 2082 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214}, 2083 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218}, 2084 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C}, 2085 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220}, 2086 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220}, 2087 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224}, 2088 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228}, 2089 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C}, 2090 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230}, 2091 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234}, 2092 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238}, 2093 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C}, 2094 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240}, 2095 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244}, 2096 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248}, 2097 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248}, 2098 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C}, 2099 }; 2100 2101 #define RK3588_PULL_BITS_PER_PIN 2 2102 #define RK3588_PULL_PINS_PER_REG 8 2103 2104 static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2105 int pin_num, struct regmap **regmap, 2106 int *reg, u8 *bit) 2107 { 2108 struct rockchip_pinctrl *info = bank->drvdata; 2109 u8 bank_num = bank->bank_num; 2110 u32 pin = bank_num * 32 + pin_num; 2111 int i; 2112 2113 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) { 2114 if (pin >= rk3588_p_regs[i][0]) { 2115 *reg = rk3588_p_regs[i][1]; 2116 *regmap = info->regmap_base; 2117 *bit = pin_num % RK3588_PULL_PINS_PER_REG; 2118 *bit *= RK3588_PULL_BITS_PER_PIN; 2119 return 0; 2120 } 2121 } 2122 2123 return -EINVAL; 2124 } 2125 2126 #define RK3588_DRV_BITS_PER_PIN 4 2127 #define RK3588_DRV_PINS_PER_REG 4 2128 2129 static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2130 int pin_num, struct regmap **regmap, 2131 int *reg, u8 *bit) 2132 { 2133 struct rockchip_pinctrl *info = bank->drvdata; 2134 u8 bank_num = bank->bank_num; 2135 u32 pin = bank_num * 32 + pin_num; 2136 int i; 2137 2138 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) { 2139 if (pin >= rk3588_ds_regs[i][0]) { 2140 *reg = rk3588_ds_regs[i][1]; 2141 *regmap = info->regmap_base; 2142 *bit = pin_num % RK3588_DRV_PINS_PER_REG; 2143 *bit *= RK3588_DRV_BITS_PER_PIN; 2144 return 0; 2145 } 2146 } 2147 2148 return -EINVAL; 2149 } 2150 2151 #define RK3588_SMT_BITS_PER_PIN 1 2152 #define RK3588_SMT_PINS_PER_REG 8 2153 2154 static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2155 int pin_num, 2156 struct regmap **regmap, 2157 int *reg, u8 *bit) 2158 { 2159 struct rockchip_pinctrl *info = bank->drvdata; 2160 u8 bank_num = bank->bank_num; 2161 u32 pin = bank_num * 32 + pin_num; 2162 int i; 2163 2164 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) { 2165 if (pin >= rk3588_smt_regs[i][0]) { 2166 *reg = rk3588_smt_regs[i][1]; 2167 *regmap = info->regmap_base; 2168 *bit = pin_num % RK3588_SMT_PINS_PER_REG; 2169 *bit *= RK3588_SMT_BITS_PER_PIN; 2170 return 0; 2171 } 2172 } 2173 2174 return -EINVAL; 2175 } 2176 2177 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2178 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2179 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2180 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2181 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2182 { 4, 7, 10, 13, 16, 19, 22, 26 } 2183 }; 2184 2185 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 2186 int pin_num) 2187 { 2188 struct rockchip_pinctrl *info = bank->drvdata; 2189 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2190 struct device *dev = info->dev; 2191 struct regmap *regmap; 2192 int reg, ret; 2193 u32 data, temp, rmask_bits; 2194 u8 bit; 2195 int drv_type = bank->drv[pin_num / 8].drv_type; 2196 2197 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2198 if (ret) 2199 return ret; 2200 2201 switch (drv_type) { 2202 case DRV_TYPE_IO_1V8_3V0_AUTO: 2203 case DRV_TYPE_IO_3V3_ONLY: 2204 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2205 switch (bit) { 2206 case 0 ... 12: 2207 /* regular case, nothing to do */ 2208 break; 2209 case 15: 2210 /* 2211 * drive-strength offset is special, as it is 2212 * spread over 2 registers 2213 */ 2214 ret = regmap_read(regmap, reg, &data); 2215 if (ret) 2216 return ret; 2217 2218 ret = regmap_read(regmap, reg + 0x4, &temp); 2219 if (ret) 2220 return ret; 2221 2222 /* 2223 * the bit data[15] contains bit 0 of the value 2224 * while temp[1:0] contains bits 2 and 1 2225 */ 2226 data >>= 15; 2227 temp &= 0x3; 2228 temp <<= 1; 2229 data |= temp; 2230 2231 return rockchip_perpin_drv_list[drv_type][data]; 2232 case 18 ... 21: 2233 /* setting fully enclosed in the second register */ 2234 reg += 4; 2235 bit -= 16; 2236 break; 2237 default: 2238 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 2239 bit, drv_type); 2240 return -EINVAL; 2241 } 2242 2243 break; 2244 case DRV_TYPE_IO_DEFAULT: 2245 case DRV_TYPE_IO_1V8_OR_3V0: 2246 case DRV_TYPE_IO_1V8_ONLY: 2247 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2248 break; 2249 default: 2250 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 2251 return -EINVAL; 2252 } 2253 2254 ret = regmap_read(regmap, reg, &data); 2255 if (ret) 2256 return ret; 2257 2258 data >>= bit; 2259 data &= (1 << rmask_bits) - 1; 2260 2261 return rockchip_perpin_drv_list[drv_type][data]; 2262 } 2263 2264 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2265 int pin_num, int strength) 2266 { 2267 struct rockchip_pinctrl *info = bank->drvdata; 2268 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2269 struct device *dev = info->dev; 2270 struct regmap *regmap; 2271 int reg, ret, i; 2272 u32 data, rmask, rmask_bits, temp; 2273 u8 bit; 2274 int drv_type = bank->drv[pin_num / 8].drv_type; 2275 2276 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n", 2277 bank->bank_num, pin_num, strength); 2278 2279 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2280 if (ret) 2281 return ret; 2282 if (ctrl->type == RK3588) { 2283 rmask_bits = RK3588_DRV_BITS_PER_PIN; 2284 ret = strength; 2285 goto config; 2286 } else if (ctrl->type == RK3568) { 2287 rmask_bits = RK3568_DRV_BITS_PER_PIN; 2288 ret = (1 << (strength + 1)) - 1; 2289 goto config; 2290 } 2291 2292 if (ctrl->type == RV1126) { 2293 rmask_bits = RV1126_DRV_BITS_PER_PIN; 2294 ret = strength; 2295 goto config; 2296 } 2297 2298 ret = -EINVAL; 2299 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2300 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2301 ret = i; 2302 break; 2303 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2304 ret = rockchip_perpin_drv_list[drv_type][i]; 2305 break; 2306 } 2307 } 2308 2309 if (ret < 0) { 2310 dev_err(dev, "unsupported driver strength %d\n", strength); 2311 return ret; 2312 } 2313 2314 switch (drv_type) { 2315 case DRV_TYPE_IO_1V8_3V0_AUTO: 2316 case DRV_TYPE_IO_3V3_ONLY: 2317 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2318 switch (bit) { 2319 case 0 ... 12: 2320 /* regular case, nothing to do */ 2321 break; 2322 case 15: 2323 /* 2324 * drive-strength offset is special, as it is spread 2325 * over 2 registers, the bit data[15] contains bit 0 2326 * of the value while temp[1:0] contains bits 2 and 1 2327 */ 2328 data = (ret & 0x1) << 15; 2329 temp = (ret >> 0x1) & 0x3; 2330 2331 rmask = BIT(15) | BIT(31); 2332 data |= BIT(31); 2333 ret = regmap_update_bits(regmap, reg, rmask, data); 2334 if (ret) 2335 return ret; 2336 2337 rmask = 0x3 | (0x3 << 16); 2338 temp |= (0x3 << 16); 2339 reg += 0x4; 2340 ret = regmap_update_bits(regmap, reg, rmask, temp); 2341 2342 return ret; 2343 case 18 ... 21: 2344 /* setting fully enclosed in the second register */ 2345 reg += 4; 2346 bit -= 16; 2347 break; 2348 default: 2349 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 2350 bit, drv_type); 2351 return -EINVAL; 2352 } 2353 break; 2354 case DRV_TYPE_IO_DEFAULT: 2355 case DRV_TYPE_IO_1V8_OR_3V0: 2356 case DRV_TYPE_IO_1V8_ONLY: 2357 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2358 break; 2359 default: 2360 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 2361 return -EINVAL; 2362 } 2363 2364 config: 2365 /* enable the write to the equivalent lower bits */ 2366 data = ((1 << rmask_bits) - 1) << (bit + 16); 2367 rmask = data | (data >> 16); 2368 data |= (ret << bit); 2369 2370 ret = regmap_update_bits(regmap, reg, rmask, data); 2371 2372 return ret; 2373 } 2374 2375 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2376 { 2377 PIN_CONFIG_BIAS_DISABLE, 2378 PIN_CONFIG_BIAS_PULL_UP, 2379 PIN_CONFIG_BIAS_PULL_DOWN, 2380 PIN_CONFIG_BIAS_BUS_HOLD 2381 }, 2382 { 2383 PIN_CONFIG_BIAS_DISABLE, 2384 PIN_CONFIG_BIAS_PULL_DOWN, 2385 PIN_CONFIG_BIAS_DISABLE, 2386 PIN_CONFIG_BIAS_PULL_UP 2387 }, 2388 }; 2389 2390 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 2391 { 2392 struct rockchip_pinctrl *info = bank->drvdata; 2393 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2394 struct device *dev = info->dev; 2395 struct regmap *regmap; 2396 int reg, ret, pull_type; 2397 u8 bit; 2398 u32 data; 2399 2400 /* rk3066b does support any pulls */ 2401 if (ctrl->type == RK3066B) 2402 return PIN_CONFIG_BIAS_DISABLE; 2403 2404 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2405 if (ret) 2406 return ret; 2407 2408 ret = regmap_read(regmap, reg, &data); 2409 if (ret) 2410 return ret; 2411 2412 switch (ctrl->type) { 2413 case RK2928: 2414 case RK3128: 2415 return !(data & BIT(bit)) 2416 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 2417 : PIN_CONFIG_BIAS_DISABLE; 2418 case PX30: 2419 case RV1108: 2420 case RK3188: 2421 case RK3288: 2422 case RK3308: 2423 case RK3368: 2424 case RK3399: 2425 case RK3568: 2426 case RK3588: 2427 pull_type = bank->pull_type[pin_num / 8]; 2428 data >>= bit; 2429 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 2430 /* 2431 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, 2432 * where that pull up value becomes 3. 2433 */ 2434 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 2435 if (data == 3) 2436 data = 1; 2437 } 2438 2439 return rockchip_pull_list[pull_type][data]; 2440 default: 2441 dev_err(dev, "unsupported pinctrl type\n"); 2442 return -EINVAL; 2443 }; 2444 } 2445 2446 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2447 int pin_num, int pull) 2448 { 2449 struct rockchip_pinctrl *info = bank->drvdata; 2450 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2451 struct device *dev = info->dev; 2452 struct regmap *regmap; 2453 int reg, ret, i, pull_type; 2454 u8 bit; 2455 u32 data, rmask; 2456 2457 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); 2458 2459 /* rk3066b does support any pulls */ 2460 if (ctrl->type == RK3066B) 2461 return pull ? -EINVAL : 0; 2462 2463 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2464 if (ret) 2465 return ret; 2466 2467 switch (ctrl->type) { 2468 case RK2928: 2469 case RK3128: 2470 data = BIT(bit + 16); 2471 if (pull == PIN_CONFIG_BIAS_DISABLE) 2472 data |= BIT(bit); 2473 ret = regmap_write(regmap, reg, data); 2474 break; 2475 case PX30: 2476 case RV1108: 2477 case RV1126: 2478 case RK3188: 2479 case RK3288: 2480 case RK3308: 2481 case RK3368: 2482 case RK3399: 2483 case RK3568: 2484 case RK3588: 2485 pull_type = bank->pull_type[pin_num / 8]; 2486 ret = -EINVAL; 2487 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2488 i++) { 2489 if (rockchip_pull_list[pull_type][i] == pull) { 2490 ret = i; 2491 break; 2492 } 2493 } 2494 /* 2495 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, 2496 * where that pull up value becomes 3. 2497 */ 2498 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 2499 if (ret == 1) 2500 ret = 3; 2501 } 2502 2503 if (ret < 0) { 2504 dev_err(dev, "unsupported pull setting %d\n", pull); 2505 return ret; 2506 } 2507 2508 /* enable the write to the equivalent lower bits */ 2509 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2510 rmask = data | (data >> 16); 2511 data |= (ret << bit); 2512 2513 ret = regmap_update_bits(regmap, reg, rmask, data); 2514 break; 2515 default: 2516 dev_err(dev, "unsupported pinctrl type\n"); 2517 return -EINVAL; 2518 } 2519 2520 return ret; 2521 } 2522 2523 #define RK3328_SCHMITT_BITS_PER_PIN 1 2524 #define RK3328_SCHMITT_PINS_PER_REG 16 2525 #define RK3328_SCHMITT_BANK_STRIDE 8 2526 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2527 2528 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2529 int pin_num, 2530 struct regmap **regmap, 2531 int *reg, u8 *bit) 2532 { 2533 struct rockchip_pinctrl *info = bank->drvdata; 2534 2535 *regmap = info->regmap_base; 2536 *reg = RK3328_SCHMITT_GRF_OFFSET; 2537 2538 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2539 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2540 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2541 2542 return 0; 2543 } 2544 2545 #define RK3568_SCHMITT_BITS_PER_PIN 2 2546 #define RK3568_SCHMITT_PINS_PER_REG 8 2547 #define RK3568_SCHMITT_BANK_STRIDE 0x10 2548 #define RK3568_SCHMITT_GRF_OFFSET 0xc0 2549 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 2550 2551 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2552 int pin_num, 2553 struct regmap **regmap, 2554 int *reg, u8 *bit) 2555 { 2556 struct rockchip_pinctrl *info = bank->drvdata; 2557 2558 if (bank->bank_num == 0) { 2559 *regmap = info->regmap_pmu; 2560 *reg = RK3568_SCHMITT_PMUGRF_OFFSET; 2561 } else { 2562 *regmap = info->regmap_base; 2563 *reg = RK3568_SCHMITT_GRF_OFFSET; 2564 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; 2565 } 2566 2567 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); 2568 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; 2569 *bit *= RK3568_SCHMITT_BITS_PER_PIN; 2570 2571 return 0; 2572 } 2573 2574 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 2575 { 2576 struct rockchip_pinctrl *info = bank->drvdata; 2577 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2578 struct regmap *regmap; 2579 int reg, ret; 2580 u8 bit; 2581 u32 data; 2582 2583 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2584 if (ret) 2585 return ret; 2586 2587 ret = regmap_read(regmap, reg, &data); 2588 if (ret) 2589 return ret; 2590 2591 data >>= bit; 2592 switch (ctrl->type) { 2593 case RK3568: 2594 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); 2595 default: 2596 break; 2597 } 2598 2599 return data & 0x1; 2600 } 2601 2602 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2603 int pin_num, int enable) 2604 { 2605 struct rockchip_pinctrl *info = bank->drvdata; 2606 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2607 struct device *dev = info->dev; 2608 struct regmap *regmap; 2609 int reg, ret; 2610 u8 bit; 2611 u32 data, rmask; 2612 2613 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n", 2614 bank->bank_num, pin_num, enable); 2615 2616 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2617 if (ret) 2618 return ret; 2619 2620 /* enable the write to the equivalent lower bits */ 2621 switch (ctrl->type) { 2622 case RK3568: 2623 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); 2624 rmask = data | (data >> 16); 2625 data |= ((enable ? 0x2 : 0x1) << bit); 2626 break; 2627 default: 2628 data = BIT(bit + 16) | (enable << bit); 2629 rmask = BIT(bit + 16) | BIT(bit); 2630 break; 2631 } 2632 2633 return regmap_update_bits(regmap, reg, rmask, data); 2634 } 2635 2636 /* 2637 * Pinmux_ops handling 2638 */ 2639 2640 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2641 { 2642 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2643 2644 return info->nfunctions; 2645 } 2646 2647 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 2648 unsigned selector) 2649 { 2650 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2651 2652 return info->functions[selector].name; 2653 } 2654 2655 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 2656 unsigned selector, const char * const **groups, 2657 unsigned * const num_groups) 2658 { 2659 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2660 2661 *groups = info->functions[selector].groups; 2662 *num_groups = info->functions[selector].ngroups; 2663 2664 return 0; 2665 } 2666 2667 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 2668 unsigned group) 2669 { 2670 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2671 const unsigned int *pins = info->groups[group].pins; 2672 const struct rockchip_pin_config *data = info->groups[group].data; 2673 struct device *dev = info->dev; 2674 struct rockchip_pin_bank *bank; 2675 int cnt, ret = 0; 2676 2677 dev_dbg(dev, "enable function %s group %s\n", 2678 info->functions[selector].name, info->groups[group].name); 2679 2680 /* 2681 * for each pin in the pin group selected, program the corresponding 2682 * pin function number in the config register. 2683 */ 2684 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 2685 bank = pin_to_bank(info, pins[cnt]); 2686 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 2687 data[cnt].func); 2688 if (ret) 2689 break; 2690 } 2691 2692 if (ret) { 2693 /* revert the already done pin settings */ 2694 for (cnt--; cnt >= 0; cnt--) 2695 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 2696 2697 return ret; 2698 } 2699 2700 return 0; 2701 } 2702 2703 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 2704 struct pinctrl_gpio_range *range, 2705 unsigned offset, 2706 bool input) 2707 { 2708 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2709 struct rockchip_pin_bank *bank; 2710 2711 bank = pin_to_bank(info, offset); 2712 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO); 2713 } 2714 2715 static const struct pinmux_ops rockchip_pmx_ops = { 2716 .get_functions_count = rockchip_pmx_get_funcs_count, 2717 .get_function_name = rockchip_pmx_get_func_name, 2718 .get_function_groups = rockchip_pmx_get_groups, 2719 .set_mux = rockchip_pmx_set, 2720 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 2721 }; 2722 2723 /* 2724 * Pinconf_ops handling 2725 */ 2726 2727 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2728 enum pin_config_param pull) 2729 { 2730 switch (ctrl->type) { 2731 case RK2928: 2732 case RK3128: 2733 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2734 pull == PIN_CONFIG_BIAS_DISABLE); 2735 case RK3066B: 2736 return pull ? false : true; 2737 case PX30: 2738 case RV1108: 2739 case RV1126: 2740 case RK3188: 2741 case RK3288: 2742 case RK3308: 2743 case RK3368: 2744 case RK3399: 2745 case RK3568: 2746 case RK3588: 2747 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2748 } 2749 2750 return false; 2751 } 2752 2753 static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank, 2754 unsigned int pin, u32 param, u32 arg) 2755 { 2756 struct rockchip_pin_deferred *cfg; 2757 2758 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); 2759 if (!cfg) 2760 return -ENOMEM; 2761 2762 cfg->pin = pin; 2763 cfg->param = param; 2764 cfg->arg = arg; 2765 2766 list_add_tail(&cfg->head, &bank->deferred_pins); 2767 2768 return 0; 2769 } 2770 2771 /* set the pin config settings for a specified pin */ 2772 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2773 unsigned long *configs, unsigned num_configs) 2774 { 2775 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2776 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2777 struct gpio_chip *gpio = &bank->gpio_chip; 2778 enum pin_config_param param; 2779 u32 arg; 2780 int i; 2781 int rc; 2782 2783 for (i = 0; i < num_configs; i++) { 2784 param = pinconf_to_config_param(configs[i]); 2785 arg = pinconf_to_config_argument(configs[i]); 2786 2787 if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) { 2788 /* 2789 * Check for gpio driver not being probed yet. 2790 * The lock makes sure that either gpio-probe has completed 2791 * or the gpio driver hasn't probed yet. 2792 */ 2793 mutex_lock(&bank->deferred_lock); 2794 if (!gpio || !gpio->direction_output) { 2795 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param, 2796 arg); 2797 mutex_unlock(&bank->deferred_lock); 2798 if (rc) 2799 return rc; 2800 2801 break; 2802 } 2803 mutex_unlock(&bank->deferred_lock); 2804 } 2805 2806 switch (param) { 2807 case PIN_CONFIG_BIAS_DISABLE: 2808 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2809 param); 2810 if (rc) 2811 return rc; 2812 break; 2813 case PIN_CONFIG_BIAS_PULL_UP: 2814 case PIN_CONFIG_BIAS_PULL_DOWN: 2815 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2816 case PIN_CONFIG_BIAS_BUS_HOLD: 2817 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2818 return -ENOTSUPP; 2819 2820 if (!arg) 2821 return -EINVAL; 2822 2823 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2824 param); 2825 if (rc) 2826 return rc; 2827 break; 2828 case PIN_CONFIG_OUTPUT: 2829 rc = rockchip_set_mux(bank, pin - bank->pin_base, 2830 RK_FUNC_GPIO); 2831 if (rc != RK_FUNC_GPIO) 2832 return -EINVAL; 2833 2834 rc = gpio->direction_output(gpio, pin - bank->pin_base, 2835 arg); 2836 if (rc) 2837 return rc; 2838 break; 2839 case PIN_CONFIG_INPUT_ENABLE: 2840 rc = rockchip_set_mux(bank, pin - bank->pin_base, 2841 RK_FUNC_GPIO); 2842 if (rc != RK_FUNC_GPIO) 2843 return -EINVAL; 2844 2845 rc = gpio->direction_input(gpio, pin - bank->pin_base); 2846 if (rc) 2847 return rc; 2848 break; 2849 case PIN_CONFIG_DRIVE_STRENGTH: 2850 /* rk3288 is the first with per-pin drive-strength */ 2851 if (!info->ctrl->drv_calc_reg) 2852 return -ENOTSUPP; 2853 2854 rc = rockchip_set_drive_perpin(bank, 2855 pin - bank->pin_base, arg); 2856 if (rc < 0) 2857 return rc; 2858 break; 2859 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2860 if (!info->ctrl->schmitt_calc_reg) 2861 return -ENOTSUPP; 2862 2863 rc = rockchip_set_schmitt(bank, 2864 pin - bank->pin_base, arg); 2865 if (rc < 0) 2866 return rc; 2867 break; 2868 default: 2869 return -ENOTSUPP; 2870 break; 2871 } 2872 } /* for each config */ 2873 2874 return 0; 2875 } 2876 2877 /* get the pin config settings for a specified pin */ 2878 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2879 unsigned long *config) 2880 { 2881 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2882 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2883 struct gpio_chip *gpio = &bank->gpio_chip; 2884 enum pin_config_param param = pinconf_to_config_param(*config); 2885 u16 arg; 2886 int rc; 2887 2888 switch (param) { 2889 case PIN_CONFIG_BIAS_DISABLE: 2890 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2891 return -EINVAL; 2892 2893 arg = 0; 2894 break; 2895 case PIN_CONFIG_BIAS_PULL_UP: 2896 case PIN_CONFIG_BIAS_PULL_DOWN: 2897 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2898 case PIN_CONFIG_BIAS_BUS_HOLD: 2899 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2900 return -ENOTSUPP; 2901 2902 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2903 return -EINVAL; 2904 2905 arg = 1; 2906 break; 2907 case PIN_CONFIG_OUTPUT: 2908 rc = rockchip_get_mux(bank, pin - bank->pin_base); 2909 if (rc != RK_FUNC_GPIO) 2910 return -EINVAL; 2911 2912 if (!gpio || !gpio->get) { 2913 arg = 0; 2914 break; 2915 } 2916 2917 rc = gpio->get(gpio, pin - bank->pin_base); 2918 if (rc < 0) 2919 return rc; 2920 2921 arg = rc ? 1 : 0; 2922 break; 2923 case PIN_CONFIG_DRIVE_STRENGTH: 2924 /* rk3288 is the first with per-pin drive-strength */ 2925 if (!info->ctrl->drv_calc_reg) 2926 return -ENOTSUPP; 2927 2928 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 2929 if (rc < 0) 2930 return rc; 2931 2932 arg = rc; 2933 break; 2934 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2935 if (!info->ctrl->schmitt_calc_reg) 2936 return -ENOTSUPP; 2937 2938 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 2939 if (rc < 0) 2940 return rc; 2941 2942 arg = rc; 2943 break; 2944 default: 2945 return -ENOTSUPP; 2946 break; 2947 } 2948 2949 *config = pinconf_to_config_packed(param, arg); 2950 2951 return 0; 2952 } 2953 2954 static const struct pinconf_ops rockchip_pinconf_ops = { 2955 .pin_config_get = rockchip_pinconf_get, 2956 .pin_config_set = rockchip_pinconf_set, 2957 .is_generic = true, 2958 }; 2959 2960 static const struct of_device_id rockchip_bank_match[] = { 2961 { .compatible = "rockchip,gpio-bank" }, 2962 { .compatible = "rockchip,rk3188-gpio-bank0" }, 2963 {}, 2964 }; 2965 2966 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 2967 struct device_node *np) 2968 { 2969 struct device_node *child; 2970 2971 for_each_child_of_node(np, child) { 2972 if (of_match_node(rockchip_bank_match, child)) 2973 continue; 2974 2975 info->nfunctions++; 2976 info->ngroups += of_get_child_count(child); 2977 } 2978 } 2979 2980 static int rockchip_pinctrl_parse_groups(struct device_node *np, 2981 struct rockchip_pin_group *grp, 2982 struct rockchip_pinctrl *info, 2983 u32 index) 2984 { 2985 struct device *dev = info->dev; 2986 struct rockchip_pin_bank *bank; 2987 int size; 2988 const __be32 *list; 2989 int num; 2990 int i, j; 2991 int ret; 2992 2993 dev_dbg(dev, "group(%d): %pOFn\n", index, np); 2994 2995 /* Initialise group */ 2996 grp->name = np->name; 2997 2998 /* 2999 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 3000 * do sanity check and calculate pins number 3001 */ 3002 list = of_get_property(np, "rockchip,pins", &size); 3003 /* we do not check return since it's safe node passed down */ 3004 size /= sizeof(*list); 3005 if (!size || size % 4) 3006 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n"); 3007 3008 grp->npins = size / 4; 3009 3010 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); 3011 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL); 3012 if (!grp->pins || !grp->data) 3013 return -ENOMEM; 3014 3015 for (i = 0, j = 0; i < size; i += 4, j++) { 3016 const __be32 *phandle; 3017 struct device_node *np_config; 3018 3019 num = be32_to_cpu(*list++); 3020 bank = bank_num_to_bank(info, num); 3021 if (IS_ERR(bank)) 3022 return PTR_ERR(bank); 3023 3024 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 3025 grp->data[j].func = be32_to_cpu(*list++); 3026 3027 phandle = list++; 3028 if (!phandle) 3029 return -EINVAL; 3030 3031 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 3032 ret = pinconf_generic_parse_dt_config(np_config, NULL, 3033 &grp->data[j].configs, &grp->data[j].nconfigs); 3034 of_node_put(np_config); 3035 if (ret) 3036 return ret; 3037 } 3038 3039 return 0; 3040 } 3041 3042 static int rockchip_pinctrl_parse_functions(struct device_node *np, 3043 struct rockchip_pinctrl *info, 3044 u32 index) 3045 { 3046 struct device *dev = info->dev; 3047 struct rockchip_pmx_func *func; 3048 struct rockchip_pin_group *grp; 3049 int ret; 3050 static u32 grp_index; 3051 u32 i = 0; 3052 3053 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np); 3054 3055 func = &info->functions[index]; 3056 3057 /* Initialise function */ 3058 func->name = np->name; 3059 func->ngroups = of_get_child_count(np); 3060 if (func->ngroups <= 0) 3061 return 0; 3062 3063 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 3064 if (!func->groups) 3065 return -ENOMEM; 3066 3067 for_each_child_of_node_scoped(np, child) { 3068 func->groups[i] = child->name; 3069 grp = &info->groups[grp_index++]; 3070 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 3071 if (ret) 3072 return ret; 3073 } 3074 3075 return 0; 3076 } 3077 3078 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 3079 struct rockchip_pinctrl *info) 3080 { 3081 struct device *dev = &pdev->dev; 3082 struct device_node *np = dev->of_node; 3083 int ret; 3084 int i; 3085 3086 rockchip_pinctrl_child_count(info, np); 3087 3088 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); 3089 dev_dbg(dev, "ngroups = %d\n", info->ngroups); 3090 3091 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 3092 if (!info->functions) 3093 return -ENOMEM; 3094 3095 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 3096 if (!info->groups) 3097 return -ENOMEM; 3098 3099 i = 0; 3100 3101 for_each_child_of_node_scoped(np, child) { 3102 if (of_match_node(rockchip_bank_match, child)) 3103 continue; 3104 3105 ret = rockchip_pinctrl_parse_functions(child, info, i++); 3106 if (ret) { 3107 dev_err(dev, "failed to parse function\n"); 3108 return ret; 3109 } 3110 } 3111 3112 return 0; 3113 } 3114 3115 static int rockchip_pinctrl_register(struct platform_device *pdev, 3116 struct rockchip_pinctrl *info) 3117 { 3118 struct pinctrl_desc *ctrldesc = &info->pctl; 3119 struct pinctrl_pin_desc *pindesc, *pdesc; 3120 struct rockchip_pin_bank *pin_bank; 3121 struct device *dev = &pdev->dev; 3122 char **pin_names; 3123 int pin, bank, ret; 3124 int k; 3125 3126 ctrldesc->name = "rockchip-pinctrl"; 3127 ctrldesc->owner = THIS_MODULE; 3128 ctrldesc->pctlops = &rockchip_pctrl_ops; 3129 ctrldesc->pmxops = &rockchip_pmx_ops; 3130 ctrldesc->confops = &rockchip_pinconf_ops; 3131 3132 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL); 3133 if (!pindesc) 3134 return -ENOMEM; 3135 3136 ctrldesc->pins = pindesc; 3137 ctrldesc->npins = info->ctrl->nr_pins; 3138 3139 pdesc = pindesc; 3140 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { 3141 pin_bank = &info->ctrl->pin_banks[bank]; 3142 3143 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins); 3144 if (IS_ERR(pin_names)) 3145 return PTR_ERR(pin_names); 3146 3147 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 3148 pdesc->number = k; 3149 pdesc->name = pin_names[pin]; 3150 pdesc++; 3151 } 3152 3153 INIT_LIST_HEAD(&pin_bank->deferred_pins); 3154 mutex_init(&pin_bank->deferred_lock); 3155 } 3156 3157 ret = rockchip_pinctrl_parse_dt(pdev, info); 3158 if (ret) 3159 return ret; 3160 3161 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); 3162 if (IS_ERR(info->pctl_dev)) 3163 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); 3164 3165 return 0; 3166 } 3167 3168 static const struct of_device_id rockchip_pinctrl_dt_match[]; 3169 3170 /* retrieve the soc specific data */ 3171 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 3172 struct rockchip_pinctrl *d, 3173 struct platform_device *pdev) 3174 { 3175 struct device *dev = &pdev->dev; 3176 struct device_node *node = dev->of_node; 3177 const struct of_device_id *match; 3178 struct rockchip_pin_ctrl *ctrl; 3179 struct rockchip_pin_bank *bank; 3180 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 3181 3182 match = of_match_node(rockchip_pinctrl_dt_match, node); 3183 ctrl = (struct rockchip_pin_ctrl *)match->data; 3184 3185 grf_offs = ctrl->grf_mux_offset; 3186 pmu_offs = ctrl->pmu_mux_offset; 3187 drv_pmu_offs = ctrl->pmu_drv_offset; 3188 drv_grf_offs = ctrl->grf_drv_offset; 3189 bank = ctrl->pin_banks; 3190 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3191 int bank_pins = 0; 3192 3193 raw_spin_lock_init(&bank->slock); 3194 bank->drvdata = d; 3195 bank->pin_base = ctrl->nr_pins; 3196 ctrl->nr_pins += bank->nr_pins; 3197 3198 /* calculate iomux and drv offsets */ 3199 for (j = 0; j < 4; j++) { 3200 struct rockchip_iomux *iom = &bank->iomux[j]; 3201 struct rockchip_drv *drv = &bank->drv[j]; 3202 int inc; 3203 3204 if (bank_pins >= bank->nr_pins) 3205 break; 3206 3207 /* preset iomux offset value, set new start value */ 3208 if (iom->offset >= 0) { 3209 if ((iom->type & IOMUX_SOURCE_PMU) || 3210 (iom->type & IOMUX_L_SOURCE_PMU)) 3211 pmu_offs = iom->offset; 3212 else 3213 grf_offs = iom->offset; 3214 } else { /* set current iomux offset */ 3215 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || 3216 (iom->type & IOMUX_L_SOURCE_PMU)) ? 3217 pmu_offs : grf_offs; 3218 } 3219 3220 /* preset drv offset value, set new start value */ 3221 if (drv->offset >= 0) { 3222 if (iom->type & IOMUX_SOURCE_PMU) 3223 drv_pmu_offs = drv->offset; 3224 else 3225 drv_grf_offs = drv->offset; 3226 } else { /* set current drv offset */ 3227 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3228 drv_pmu_offs : drv_grf_offs; 3229 } 3230 3231 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3232 i, j, iom->offset, drv->offset); 3233 3234 /* 3235 * Increase offset according to iomux width. 3236 * 4bit iomux'es are spread over two registers. 3237 */ 3238 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3239 IOMUX_WIDTH_3BIT | 3240 IOMUX_WIDTH_2BIT)) ? 8 : 4; 3241 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 3242 pmu_offs += inc; 3243 else 3244 grf_offs += inc; 3245 3246 /* 3247 * Increase offset according to drv width. 3248 * 3bit drive-strenth'es are spread over two registers. 3249 */ 3250 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3251 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3252 inc = 8; 3253 else 3254 inc = 4; 3255 3256 if (iom->type & IOMUX_SOURCE_PMU) 3257 drv_pmu_offs += inc; 3258 else 3259 drv_grf_offs += inc; 3260 3261 bank_pins += 8; 3262 } 3263 3264 /* calculate the per-bank recalced_mask */ 3265 for (j = 0; j < ctrl->niomux_recalced; j++) { 3266 int pin = 0; 3267 3268 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3269 pin = ctrl->iomux_recalced[j].pin; 3270 bank->recalced_mask |= BIT(pin); 3271 } 3272 } 3273 3274 /* calculate the per-bank route_mask */ 3275 for (j = 0; j < ctrl->niomux_routes; j++) { 3276 int pin = 0; 3277 3278 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3279 pin = ctrl->iomux_routes[j].pin; 3280 bank->route_mask |= BIT(pin); 3281 } 3282 } 3283 } 3284 3285 return ctrl; 3286 } 3287 3288 #define RK3288_GRF_GPIO6C_IOMUX 0x64 3289 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 3290 3291 static u32 rk3288_grf_gpio6c_iomux; 3292 3293 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 3294 { 3295 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3296 int ret = pinctrl_force_sleep(info->pctl_dev); 3297 3298 if (ret) 3299 return ret; 3300 3301 /* 3302 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 3303 * the setting here, and restore it at resume. 3304 */ 3305 if (info->ctrl->type == RK3288) { 3306 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3307 &rk3288_grf_gpio6c_iomux); 3308 if (ret) { 3309 pinctrl_force_default(info->pctl_dev); 3310 return ret; 3311 } 3312 } 3313 3314 return 0; 3315 } 3316 3317 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 3318 { 3319 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3320 int ret; 3321 3322 if (info->ctrl->type == RK3288) { 3323 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3324 rk3288_grf_gpio6c_iomux | 3325 GPIO6C6_SEL_WRITE_ENABLE); 3326 if (ret) 3327 return ret; 3328 } 3329 3330 return pinctrl_force_default(info->pctl_dev); 3331 } 3332 3333 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 3334 rockchip_pinctrl_resume); 3335 3336 static int rockchip_pinctrl_probe(struct platform_device *pdev) 3337 { 3338 struct rockchip_pinctrl *info; 3339 struct device *dev = &pdev->dev; 3340 struct device_node *np = dev->of_node, *node; 3341 struct rockchip_pin_ctrl *ctrl; 3342 struct resource *res; 3343 void __iomem *base; 3344 int ret; 3345 3346 if (!dev->of_node) 3347 return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); 3348 3349 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 3350 if (!info) 3351 return -ENOMEM; 3352 3353 info->dev = dev; 3354 3355 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 3356 if (!ctrl) 3357 return dev_err_probe(dev, -EINVAL, "driver data not available\n"); 3358 info->ctrl = ctrl; 3359 3360 node = of_parse_phandle(np, "rockchip,grf", 0); 3361 if (node) { 3362 info->regmap_base = syscon_node_to_regmap(node); 3363 of_node_put(node); 3364 if (IS_ERR(info->regmap_base)) 3365 return PTR_ERR(info->regmap_base); 3366 } else { 3367 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 3368 if (IS_ERR(base)) 3369 return PTR_ERR(base); 3370 3371 rockchip_regmap_config.max_register = resource_size(res) - 4; 3372 rockchip_regmap_config.name = "rockchip,pinctrl"; 3373 info->regmap_base = 3374 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 3375 3376 /* to check for the old dt-bindings */ 3377 info->reg_size = resource_size(res); 3378 3379 /* Honor the old binding, with pull registers as 2nd resource */ 3380 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 3381 base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); 3382 if (IS_ERR(base)) 3383 return PTR_ERR(base); 3384 3385 rockchip_regmap_config.max_register = resource_size(res) - 4; 3386 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 3387 info->regmap_pull = 3388 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 3389 } 3390 } 3391 3392 /* try to find the optional reference to the pmu syscon */ 3393 node = of_parse_phandle(np, "rockchip,pmu", 0); 3394 if (node) { 3395 info->regmap_pmu = syscon_node_to_regmap(node); 3396 of_node_put(node); 3397 if (IS_ERR(info->regmap_pmu)) 3398 return PTR_ERR(info->regmap_pmu); 3399 } 3400 3401 ret = rockchip_pinctrl_register(pdev, info); 3402 if (ret) 3403 return ret; 3404 3405 platform_set_drvdata(pdev, info); 3406 3407 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 3408 if (ret) 3409 return dev_err_probe(dev, ret, "failed to register gpio device\n"); 3410 3411 return 0; 3412 } 3413 3414 static void rockchip_pinctrl_remove(struct platform_device *pdev) 3415 { 3416 struct rockchip_pinctrl *info = platform_get_drvdata(pdev); 3417 struct rockchip_pin_bank *bank; 3418 struct rockchip_pin_deferred *cfg; 3419 int i; 3420 3421 of_platform_depopulate(&pdev->dev); 3422 3423 for (i = 0; i < info->ctrl->nr_banks; i++) { 3424 bank = &info->ctrl->pin_banks[i]; 3425 3426 mutex_lock(&bank->deferred_lock); 3427 while (!list_empty(&bank->deferred_pins)) { 3428 cfg = list_first_entry(&bank->deferred_pins, 3429 struct rockchip_pin_deferred, head); 3430 list_del(&cfg->head); 3431 kfree(cfg); 3432 } 3433 mutex_unlock(&bank->deferred_lock); 3434 } 3435 } 3436 3437 static struct rockchip_pin_bank px30_pin_banks[] = { 3438 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3439 IOMUX_SOURCE_PMU, 3440 IOMUX_SOURCE_PMU, 3441 IOMUX_SOURCE_PMU 3442 ), 3443 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3444 IOMUX_WIDTH_4BIT, 3445 IOMUX_WIDTH_4BIT, 3446 IOMUX_WIDTH_4BIT 3447 ), 3448 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3449 IOMUX_WIDTH_4BIT, 3450 IOMUX_WIDTH_4BIT, 3451 IOMUX_WIDTH_4BIT 3452 ), 3453 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3454 IOMUX_WIDTH_4BIT, 3455 IOMUX_WIDTH_4BIT, 3456 IOMUX_WIDTH_4BIT 3457 ), 3458 }; 3459 3460 static struct rockchip_pin_ctrl px30_pin_ctrl = { 3461 .pin_banks = px30_pin_banks, 3462 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3463 .label = "PX30-GPIO", 3464 .type = PX30, 3465 .grf_mux_offset = 0x0, 3466 .pmu_mux_offset = 0x0, 3467 .iomux_routes = px30_mux_route_data, 3468 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3469 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3470 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3471 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3472 }; 3473 3474 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3475 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3476 IOMUX_SOURCE_PMU, 3477 IOMUX_SOURCE_PMU, 3478 IOMUX_SOURCE_PMU), 3479 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3480 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3481 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3482 }; 3483 3484 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3485 .pin_banks = rv1108_pin_banks, 3486 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3487 .label = "RV1108-GPIO", 3488 .type = RV1108, 3489 .grf_mux_offset = 0x10, 3490 .pmu_mux_offset = 0x0, 3491 .iomux_recalced = rv1108_mux_recalced_data, 3492 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3493 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3494 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3495 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3496 }; 3497 3498 static struct rockchip_pin_bank rv1126_pin_banks[] = { 3499 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3500 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3501 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3502 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, 3503 IOMUX_WIDTH_4BIT), 3504 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 3505 IOMUX_WIDTH_4BIT, 3506 IOMUX_WIDTH_4BIT, 3507 IOMUX_WIDTH_4BIT, 3508 IOMUX_WIDTH_4BIT, 3509 0x10010, 0x10018, 0x10020, 0x10028), 3510 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3511 IOMUX_WIDTH_4BIT, 3512 IOMUX_WIDTH_4BIT, 3513 IOMUX_WIDTH_4BIT, 3514 IOMUX_WIDTH_4BIT), 3515 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3516 IOMUX_WIDTH_4BIT, 3517 IOMUX_WIDTH_4BIT, 3518 IOMUX_WIDTH_4BIT, 3519 IOMUX_WIDTH_4BIT), 3520 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", 3521 IOMUX_WIDTH_4BIT, 0, 0, 0), 3522 }; 3523 3524 static struct rockchip_pin_ctrl rv1126_pin_ctrl = { 3525 .pin_banks = rv1126_pin_banks, 3526 .nr_banks = ARRAY_SIZE(rv1126_pin_banks), 3527 .label = "RV1126-GPIO", 3528 .type = RV1126, 3529 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ 3530 .pmu_mux_offset = 0x0, 3531 .iomux_routes = rv1126_mux_route_data, 3532 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data), 3533 .iomux_recalced = rv1126_mux_recalced_data, 3534 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), 3535 .pull_calc_reg = rv1126_calc_pull_reg_and_bit, 3536 .drv_calc_reg = rv1126_calc_drv_reg_and_bit, 3537 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit, 3538 }; 3539 3540 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3541 PIN_BANK(0, 32, "gpio0"), 3542 PIN_BANK(1, 32, "gpio1"), 3543 PIN_BANK(2, 32, "gpio2"), 3544 PIN_BANK(3, 32, "gpio3"), 3545 }; 3546 3547 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3548 .pin_banks = rk2928_pin_banks, 3549 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3550 .label = "RK2928-GPIO", 3551 .type = RK2928, 3552 .grf_mux_offset = 0xa8, 3553 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3554 }; 3555 3556 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3557 PIN_BANK(0, 32, "gpio0"), 3558 PIN_BANK(1, 32, "gpio1"), 3559 PIN_BANK(2, 32, "gpio2"), 3560 }; 3561 3562 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3563 .pin_banks = rk3036_pin_banks, 3564 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3565 .label = "RK3036-GPIO", 3566 .type = RK2928, 3567 .grf_mux_offset = 0xa8, 3568 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3569 }; 3570 3571 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3572 PIN_BANK(0, 32, "gpio0"), 3573 PIN_BANK(1, 32, "gpio1"), 3574 PIN_BANK(2, 32, "gpio2"), 3575 PIN_BANK(3, 32, "gpio3"), 3576 PIN_BANK(4, 32, "gpio4"), 3577 PIN_BANK(6, 16, "gpio6"), 3578 }; 3579 3580 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3581 .pin_banks = rk3066a_pin_banks, 3582 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3583 .label = "RK3066a-GPIO", 3584 .type = RK2928, 3585 .grf_mux_offset = 0xa8, 3586 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3587 }; 3588 3589 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3590 PIN_BANK(0, 32, "gpio0"), 3591 PIN_BANK(1, 32, "gpio1"), 3592 PIN_BANK(2, 32, "gpio2"), 3593 PIN_BANK(3, 32, "gpio3"), 3594 }; 3595 3596 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3597 .pin_banks = rk3066b_pin_banks, 3598 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3599 .label = "RK3066b-GPIO", 3600 .type = RK3066B, 3601 .grf_mux_offset = 0x60, 3602 }; 3603 3604 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3605 PIN_BANK(0, 32, "gpio0"), 3606 PIN_BANK(1, 32, "gpio1"), 3607 PIN_BANK(2, 32, "gpio2"), 3608 PIN_BANK(3, 32, "gpio3"), 3609 }; 3610 3611 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3612 .pin_banks = rk3128_pin_banks, 3613 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3614 .label = "RK3128-GPIO", 3615 .type = RK3128, 3616 .grf_mux_offset = 0xa8, 3617 .iomux_recalced = rk3128_mux_recalced_data, 3618 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3619 .iomux_routes = rk3128_mux_route_data, 3620 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3621 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3622 }; 3623 3624 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3625 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3626 PIN_BANK(1, 32, "gpio1"), 3627 PIN_BANK(2, 32, "gpio2"), 3628 PIN_BANK(3, 32, "gpio3"), 3629 }; 3630 3631 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3632 .pin_banks = rk3188_pin_banks, 3633 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3634 .label = "RK3188-GPIO", 3635 .type = RK3188, 3636 .grf_mux_offset = 0x60, 3637 .iomux_routes = rk3188_mux_route_data, 3638 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), 3639 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3640 }; 3641 3642 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3643 PIN_BANK(0, 32, "gpio0"), 3644 PIN_BANK(1, 32, "gpio1"), 3645 PIN_BANK(2, 32, "gpio2"), 3646 PIN_BANK(3, 32, "gpio3"), 3647 }; 3648 3649 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3650 .pin_banks = rk3228_pin_banks, 3651 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3652 .label = "RK3228-GPIO", 3653 .type = RK3288, 3654 .grf_mux_offset = 0x0, 3655 .iomux_routes = rk3228_mux_route_data, 3656 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3657 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3658 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3659 }; 3660 3661 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3662 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 3663 IOMUX_SOURCE_PMU, 3664 IOMUX_SOURCE_PMU, 3665 IOMUX_UNROUTED 3666 ), 3667 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3668 IOMUX_UNROUTED, 3669 IOMUX_UNROUTED, 3670 0 3671 ), 3672 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3673 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3674 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3675 IOMUX_WIDTH_4BIT, 3676 0, 3677 0 3678 ), 3679 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3680 0, 3681 0, 3682 IOMUX_UNROUTED 3683 ), 3684 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3685 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3686 0, 3687 IOMUX_WIDTH_4BIT, 3688 IOMUX_UNROUTED 3689 ), 3690 PIN_BANK(8, 16, "gpio8"), 3691 }; 3692 3693 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3694 .pin_banks = rk3288_pin_banks, 3695 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3696 .label = "RK3288-GPIO", 3697 .type = RK3288, 3698 .grf_mux_offset = 0x0, 3699 .pmu_mux_offset = 0x84, 3700 .iomux_routes = rk3288_mux_route_data, 3701 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3702 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3703 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3704 }; 3705 3706 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3707 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, 3708 IOMUX_WIDTH_2BIT, 3709 IOMUX_WIDTH_2BIT, 3710 IOMUX_WIDTH_2BIT), 3711 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, 3712 IOMUX_WIDTH_2BIT, 3713 IOMUX_WIDTH_2BIT, 3714 IOMUX_WIDTH_2BIT), 3715 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, 3716 IOMUX_WIDTH_2BIT, 3717 IOMUX_WIDTH_2BIT, 3718 IOMUX_WIDTH_2BIT), 3719 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, 3720 IOMUX_WIDTH_2BIT, 3721 IOMUX_WIDTH_2BIT, 3722 IOMUX_WIDTH_2BIT), 3723 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, 3724 IOMUX_WIDTH_2BIT, 3725 IOMUX_WIDTH_2BIT, 3726 IOMUX_WIDTH_2BIT), 3727 }; 3728 3729 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3730 .pin_banks = rk3308_pin_banks, 3731 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3732 .label = "RK3308-GPIO", 3733 .type = RK3308, 3734 .grf_mux_offset = 0x0, 3735 .iomux_recalced = rk3308_mux_recalced_data, 3736 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3737 .iomux_routes = rk3308_mux_route_data, 3738 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3739 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3740 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3741 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3742 }; 3743 3744 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3745 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3746 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3747 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3748 IOMUX_WIDTH_3BIT, 3749 IOMUX_WIDTH_3BIT, 3750 0), 3751 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3752 IOMUX_WIDTH_3BIT, 3753 IOMUX_WIDTH_3BIT, 3754 0, 3755 0), 3756 }; 3757 3758 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3759 .pin_banks = rk3328_pin_banks, 3760 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3761 .label = "RK3328-GPIO", 3762 .type = RK3288, 3763 .grf_mux_offset = 0x0, 3764 .iomux_recalced = rk3328_mux_recalced_data, 3765 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3766 .iomux_routes = rk3328_mux_route_data, 3767 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3768 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3769 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3770 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3771 }; 3772 3773 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3774 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3775 IOMUX_SOURCE_PMU, 3776 IOMUX_SOURCE_PMU, 3777 IOMUX_SOURCE_PMU 3778 ), 3779 PIN_BANK(1, 32, "gpio1"), 3780 PIN_BANK(2, 32, "gpio2"), 3781 PIN_BANK(3, 32, "gpio3"), 3782 }; 3783 3784 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3785 .pin_banks = rk3368_pin_banks, 3786 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3787 .label = "RK3368-GPIO", 3788 .type = RK3368, 3789 .grf_mux_offset = 0x0, 3790 .pmu_mux_offset = 0x0, 3791 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3792 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3793 }; 3794 3795 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3796 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3797 IOMUX_SOURCE_PMU, 3798 IOMUX_SOURCE_PMU, 3799 IOMUX_SOURCE_PMU, 3800 IOMUX_SOURCE_PMU, 3801 DRV_TYPE_IO_1V8_ONLY, 3802 DRV_TYPE_IO_1V8_ONLY, 3803 DRV_TYPE_IO_DEFAULT, 3804 DRV_TYPE_IO_DEFAULT, 3805 0x80, 3806 0x88, 3807 -1, 3808 -1, 3809 PULL_TYPE_IO_1V8_ONLY, 3810 PULL_TYPE_IO_1V8_ONLY, 3811 PULL_TYPE_IO_DEFAULT, 3812 PULL_TYPE_IO_DEFAULT 3813 ), 3814 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3815 IOMUX_SOURCE_PMU, 3816 IOMUX_SOURCE_PMU, 3817 IOMUX_SOURCE_PMU, 3818 DRV_TYPE_IO_1V8_OR_3V0, 3819 DRV_TYPE_IO_1V8_OR_3V0, 3820 DRV_TYPE_IO_1V8_OR_3V0, 3821 DRV_TYPE_IO_1V8_OR_3V0, 3822 0xa0, 3823 0xa8, 3824 0xb0, 3825 0xb8 3826 ), 3827 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3828 DRV_TYPE_IO_1V8_OR_3V0, 3829 DRV_TYPE_IO_1V8_ONLY, 3830 DRV_TYPE_IO_1V8_ONLY, 3831 PULL_TYPE_IO_DEFAULT, 3832 PULL_TYPE_IO_DEFAULT, 3833 PULL_TYPE_IO_1V8_ONLY, 3834 PULL_TYPE_IO_1V8_ONLY 3835 ), 3836 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3837 DRV_TYPE_IO_3V3_ONLY, 3838 DRV_TYPE_IO_3V3_ONLY, 3839 DRV_TYPE_IO_1V8_OR_3V0 3840 ), 3841 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3842 DRV_TYPE_IO_1V8_3V0_AUTO, 3843 DRV_TYPE_IO_1V8_OR_3V0, 3844 DRV_TYPE_IO_1V8_OR_3V0 3845 ), 3846 }; 3847 3848 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3849 .pin_banks = rk3399_pin_banks, 3850 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3851 .label = "RK3399-GPIO", 3852 .type = RK3399, 3853 .grf_mux_offset = 0xe000, 3854 .pmu_mux_offset = 0x0, 3855 .grf_drv_offset = 0xe100, 3856 .pmu_drv_offset = 0x80, 3857 .iomux_routes = rk3399_mux_route_data, 3858 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3859 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3860 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3861 }; 3862 3863 static struct rockchip_pin_bank rk3568_pin_banks[] = { 3864 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3865 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3866 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 3867 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), 3868 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3869 IOMUX_WIDTH_4BIT, 3870 IOMUX_WIDTH_4BIT, 3871 IOMUX_WIDTH_4BIT), 3872 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3873 IOMUX_WIDTH_4BIT, 3874 IOMUX_WIDTH_4BIT, 3875 IOMUX_WIDTH_4BIT), 3876 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3877 IOMUX_WIDTH_4BIT, 3878 IOMUX_WIDTH_4BIT, 3879 IOMUX_WIDTH_4BIT), 3880 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3881 IOMUX_WIDTH_4BIT, 3882 IOMUX_WIDTH_4BIT, 3883 IOMUX_WIDTH_4BIT), 3884 }; 3885 3886 static struct rockchip_pin_ctrl rk3568_pin_ctrl = { 3887 .pin_banks = rk3568_pin_banks, 3888 .nr_banks = ARRAY_SIZE(rk3568_pin_banks), 3889 .label = "RK3568-GPIO", 3890 .type = RK3568, 3891 .grf_mux_offset = 0x0, 3892 .pmu_mux_offset = 0x0, 3893 .grf_drv_offset = 0x0200, 3894 .pmu_drv_offset = 0x0070, 3895 .iomux_routes = rk3568_mux_route_data, 3896 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), 3897 .pull_calc_reg = rk3568_calc_pull_reg_and_bit, 3898 .drv_calc_reg = rk3568_calc_drv_reg_and_bit, 3899 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit, 3900 }; 3901 3902 static struct rockchip_pin_bank rk3588_pin_banks[] = { 3903 RK3588_PIN_BANK_FLAGS(0, 32, "gpio0", 3904 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3905 RK3588_PIN_BANK_FLAGS(1, 32, "gpio1", 3906 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3907 RK3588_PIN_BANK_FLAGS(2, 32, "gpio2", 3908 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3909 RK3588_PIN_BANK_FLAGS(3, 32, "gpio3", 3910 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3911 RK3588_PIN_BANK_FLAGS(4, 32, "gpio4", 3912 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 3913 }; 3914 3915 static struct rockchip_pin_ctrl rk3588_pin_ctrl = { 3916 .pin_banks = rk3588_pin_banks, 3917 .nr_banks = ARRAY_SIZE(rk3588_pin_banks), 3918 .label = "RK3588-GPIO", 3919 .type = RK3588, 3920 .pull_calc_reg = rk3588_calc_pull_reg_and_bit, 3921 .drv_calc_reg = rk3588_calc_drv_reg_and_bit, 3922 .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit, 3923 }; 3924 3925 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 3926 { .compatible = "rockchip,px30-pinctrl", 3927 .data = &px30_pin_ctrl }, 3928 { .compatible = "rockchip,rv1108-pinctrl", 3929 .data = &rv1108_pin_ctrl }, 3930 { .compatible = "rockchip,rv1126-pinctrl", 3931 .data = &rv1126_pin_ctrl }, 3932 { .compatible = "rockchip,rk2928-pinctrl", 3933 .data = &rk2928_pin_ctrl }, 3934 { .compatible = "rockchip,rk3036-pinctrl", 3935 .data = &rk3036_pin_ctrl }, 3936 { .compatible = "rockchip,rk3066a-pinctrl", 3937 .data = &rk3066a_pin_ctrl }, 3938 { .compatible = "rockchip,rk3066b-pinctrl", 3939 .data = &rk3066b_pin_ctrl }, 3940 { .compatible = "rockchip,rk3128-pinctrl", 3941 .data = (void *)&rk3128_pin_ctrl }, 3942 { .compatible = "rockchip,rk3188-pinctrl", 3943 .data = &rk3188_pin_ctrl }, 3944 { .compatible = "rockchip,rk3228-pinctrl", 3945 .data = &rk3228_pin_ctrl }, 3946 { .compatible = "rockchip,rk3288-pinctrl", 3947 .data = &rk3288_pin_ctrl }, 3948 { .compatible = "rockchip,rk3308-pinctrl", 3949 .data = &rk3308_pin_ctrl }, 3950 { .compatible = "rockchip,rk3328-pinctrl", 3951 .data = &rk3328_pin_ctrl }, 3952 { .compatible = "rockchip,rk3368-pinctrl", 3953 .data = &rk3368_pin_ctrl }, 3954 { .compatible = "rockchip,rk3399-pinctrl", 3955 .data = &rk3399_pin_ctrl }, 3956 { .compatible = "rockchip,rk3568-pinctrl", 3957 .data = &rk3568_pin_ctrl }, 3958 { .compatible = "rockchip,rk3588-pinctrl", 3959 .data = &rk3588_pin_ctrl }, 3960 {}, 3961 }; 3962 3963 static struct platform_driver rockchip_pinctrl_driver = { 3964 .probe = rockchip_pinctrl_probe, 3965 .remove_new = rockchip_pinctrl_remove, 3966 .driver = { 3967 .name = "rockchip-pinctrl", 3968 .pm = &rockchip_pinctrl_dev_pm_ops, 3969 .of_match_table = rockchip_pinctrl_dt_match, 3970 }, 3971 }; 3972 3973 static int __init rockchip_pinctrl_drv_register(void) 3974 { 3975 return platform_driver_register(&rockchip_pinctrl_driver); 3976 } 3977 postcore_initcall(rockchip_pinctrl_drv_register); 3978 3979 static void __exit rockchip_pinctrl_drv_unregister(void) 3980 { 3981 platform_driver_unregister(&rockchip_pinctrl_driver); 3982 } 3983 module_exit(rockchip_pinctrl_drv_unregister); 3984 3985 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); 3986 MODULE_LICENSE("GPL"); 3987 MODULE_ALIAS("platform:pinctrl-rockchip"); 3988 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 3989