1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Pinctrl driver for Rockchip SoCs 4 * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd. 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * https://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/io.h> 22 #include <linux/bitops.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/of.h> 25 #include <linux/of_platform.h> 26 #include <linux/pinctrl/machine.h> 27 #include <linux/pinctrl/pinconf.h> 28 #include <linux/pinctrl/pinctrl.h> 29 #include <linux/pinctrl/pinmux.h> 30 #include <linux/pinctrl/pinconf-generic.h> 31 #include <linux/irqchip/chained_irq.h> 32 #include <linux/clk.h> 33 #include <linux/regmap.h> 34 #include <linux/mfd/syscon.h> 35 #include <linux/string_helpers.h> 36 37 #include <dt-bindings/pinctrl/rockchip.h> 38 39 #include "core.h" 40 #include "pinconf.h" 41 #include "pinctrl-rockchip.h" 42 43 /* 44 * Generate a bitmask for setting a value (v) with a write mask bit in hiword 45 * register 31:16 area. 46 */ 47 #define WRITE_MASK_VAL(h, l, v) \ 48 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 49 50 /* 51 * Encode variants of iomux registers into a type variable 52 */ 53 #define IOMUX_GPIO_ONLY BIT(0) 54 #define IOMUX_WIDTH_4BIT BIT(1) 55 #define IOMUX_SOURCE_PMU BIT(2) 56 #define IOMUX_UNROUTED BIT(3) 57 #define IOMUX_WIDTH_3BIT BIT(4) 58 #define IOMUX_WIDTH_2BIT BIT(5) 59 #define IOMUX_L_SOURCE_PMU BIT(6) 60 61 #define PIN_BANK(id, pins, label) \ 62 { \ 63 .bank_num = id, \ 64 .nr_pins = pins, \ 65 .name = label, \ 66 .iomux = { \ 67 { .offset = -1 }, \ 68 { .offset = -1 }, \ 69 { .offset = -1 }, \ 70 { .offset = -1 }, \ 71 }, \ 72 } 73 74 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 75 { \ 76 .bank_num = id, \ 77 .nr_pins = pins, \ 78 .name = label, \ 79 .iomux = { \ 80 { .type = iom0, .offset = -1 }, \ 81 { .type = iom1, .offset = -1 }, \ 82 { .type = iom2, .offset = -1 }, \ 83 { .type = iom3, .offset = -1 }, \ 84 }, \ 85 } 86 87 #define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0, \ 88 iom1, iom2, iom3, \ 89 offset0, offset1, \ 90 offset2, offset3, pull0, \ 91 pull1, pull2, pull3) \ 92 { \ 93 .bank_num = id, \ 94 .nr_pins = pins, \ 95 .name = label, \ 96 .iomux = { \ 97 { .type = iom0, .offset = offset0 }, \ 98 { .type = iom1, .offset = offset1 }, \ 99 { .type = iom2, .offset = offset2 }, \ 100 { .type = iom3, .offset = offset3 }, \ 101 }, \ 102 .pull_type[0] = pull0, \ 103 .pull_type[1] = pull1, \ 104 .pull_type[2] = pull2, \ 105 .pull_type[3] = pull3, \ 106 } 107 108 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 109 { \ 110 .bank_num = id, \ 111 .nr_pins = pins, \ 112 .name = label, \ 113 .iomux = { \ 114 { .offset = -1 }, \ 115 { .offset = -1 }, \ 116 { .offset = -1 }, \ 117 { .offset = -1 }, \ 118 }, \ 119 .drv = { \ 120 { .drv_type = type0, .offset = -1 }, \ 121 { .drv_type = type1, .offset = -1 }, \ 122 { .drv_type = type2, .offset = -1 }, \ 123 { .drv_type = type3, .offset = -1 }, \ 124 }, \ 125 } 126 127 #define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \ 128 iom2, iom3, pull0, pull1, \ 129 pull2, pull3) \ 130 { \ 131 .bank_num = id, \ 132 .nr_pins = pins, \ 133 .name = label, \ 134 .iomux = { \ 135 { .type = iom0, .offset = -1 }, \ 136 { .type = iom1, .offset = -1 }, \ 137 { .type = iom2, .offset = -1 }, \ 138 { .type = iom3, .offset = -1 }, \ 139 }, \ 140 .pull_type[0] = pull0, \ 141 .pull_type[1] = pull1, \ 142 .pull_type[2] = pull2, \ 143 .pull_type[3] = pull3, \ 144 } 145 146 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 147 drv2, drv3, pull0, pull1, \ 148 pull2, pull3) \ 149 { \ 150 .bank_num = id, \ 151 .nr_pins = pins, \ 152 .name = label, \ 153 .iomux = { \ 154 { .offset = -1 }, \ 155 { .offset = -1 }, \ 156 { .offset = -1 }, \ 157 { .offset = -1 }, \ 158 }, \ 159 .drv = { \ 160 { .drv_type = drv0, .offset = -1 }, \ 161 { .drv_type = drv1, .offset = -1 }, \ 162 { .drv_type = drv2, .offset = -1 }, \ 163 { .drv_type = drv3, .offset = -1 }, \ 164 }, \ 165 .pull_type[0] = pull0, \ 166 .pull_type[1] = pull1, \ 167 .pull_type[2] = pull2, \ 168 .pull_type[3] = pull3, \ 169 } 170 171 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \ 172 iom3, offset0, offset1, offset2, \ 173 offset3) \ 174 { \ 175 .bank_num = id, \ 176 .nr_pins = pins, \ 177 .name = label, \ 178 .iomux = { \ 179 { .type = iom0, .offset = offset0 }, \ 180 { .type = iom1, .offset = offset1 }, \ 181 { .type = iom2, .offset = offset2 }, \ 182 { .type = iom3, .offset = offset3 }, \ 183 }, \ 184 } 185 186 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 187 iom2, iom3, drv0, drv1, drv2, \ 188 drv3, offset0, offset1, \ 189 offset2, offset3) \ 190 { \ 191 .bank_num = id, \ 192 .nr_pins = pins, \ 193 .name = label, \ 194 .iomux = { \ 195 { .type = iom0, .offset = -1 }, \ 196 { .type = iom1, .offset = -1 }, \ 197 { .type = iom2, .offset = -1 }, \ 198 { .type = iom3, .offset = -1 }, \ 199 }, \ 200 .drv = { \ 201 { .drv_type = drv0, .offset = offset0 }, \ 202 { .drv_type = drv1, .offset = offset1 }, \ 203 { .drv_type = drv2, .offset = offset2 }, \ 204 { .drv_type = drv3, .offset = offset3 }, \ 205 }, \ 206 } 207 208 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 209 label, iom0, iom1, iom2, \ 210 iom3, drv0, drv1, drv2, \ 211 drv3, offset0, offset1, \ 212 offset2, offset3, pull0, \ 213 pull1, pull2, pull3) \ 214 { \ 215 .bank_num = id, \ 216 .nr_pins = pins, \ 217 .name = label, \ 218 .iomux = { \ 219 { .type = iom0, .offset = -1 }, \ 220 { .type = iom1, .offset = -1 }, \ 221 { .type = iom2, .offset = -1 }, \ 222 { .type = iom3, .offset = -1 }, \ 223 }, \ 224 .drv = { \ 225 { .drv_type = drv0, .offset = offset0 }, \ 226 { .drv_type = drv1, .offset = offset1 }, \ 227 { .drv_type = drv2, .offset = offset2 }, \ 228 { .drv_type = drv3, .offset = offset3 }, \ 229 }, \ 230 .pull_type[0] = pull0, \ 231 .pull_type[1] = pull1, \ 232 .pull_type[2] = pull2, \ 233 .pull_type[3] = pull3, \ 234 } 235 236 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 237 { \ 238 .bank_num = ID, \ 239 .pin = PIN, \ 240 .func = FUNC, \ 241 .route_offset = REG, \ 242 .route_val = VAL, \ 243 .route_location = FLAG, \ 244 } 245 246 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \ 247 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME) 248 249 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \ 250 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF) 251 252 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ 253 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) 254 255 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \ 256 PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P) 257 258 static struct regmap_config rockchip_regmap_config = { 259 .reg_bits = 32, 260 .val_bits = 32, 261 .reg_stride = 4, 262 }; 263 264 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 265 const struct rockchip_pinctrl *info, 266 const char *name) 267 { 268 int i; 269 270 for (i = 0; i < info->ngroups; i++) { 271 if (!strcmp(info->groups[i].name, name)) 272 return &info->groups[i]; 273 } 274 275 return NULL; 276 } 277 278 /* 279 * given a pin number that is local to a pin controller, find out the pin bank 280 * and the register base of the pin bank. 281 */ 282 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 283 unsigned pin) 284 { 285 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 286 287 while (pin >= (b->pin_base + b->nr_pins)) 288 b++; 289 290 return b; 291 } 292 293 static struct rockchip_pin_bank *bank_num_to_bank( 294 struct rockchip_pinctrl *info, 295 unsigned num) 296 { 297 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 298 int i; 299 300 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 301 if (b->bank_num == num) 302 return b; 303 } 304 305 return ERR_PTR(-EINVAL); 306 } 307 308 /* 309 * Pinctrl_ops handling 310 */ 311 312 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 313 { 314 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 315 316 return info->ngroups; 317 } 318 319 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 320 unsigned selector) 321 { 322 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 323 324 return info->groups[selector].name; 325 } 326 327 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 328 unsigned selector, const unsigned **pins, 329 unsigned *npins) 330 { 331 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 332 333 if (selector >= info->ngroups) 334 return -EINVAL; 335 336 *pins = info->groups[selector].pins; 337 *npins = info->groups[selector].npins; 338 339 return 0; 340 } 341 342 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 343 struct device_node *np, 344 struct pinctrl_map **map, unsigned *num_maps) 345 { 346 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 347 const struct rockchip_pin_group *grp; 348 struct device *dev = info->dev; 349 struct pinctrl_map *new_map; 350 struct device_node *parent; 351 int map_num = 1; 352 int i; 353 354 /* 355 * first find the group of this node and check if we need to create 356 * config maps for pins 357 */ 358 grp = pinctrl_name_to_group(info, np->name); 359 if (!grp) { 360 dev_err(dev, "unable to find group for node %pOFn\n", np); 361 return -EINVAL; 362 } 363 364 map_num += grp->npins; 365 366 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); 367 if (!new_map) 368 return -ENOMEM; 369 370 *map = new_map; 371 *num_maps = map_num; 372 373 /* create mux map */ 374 parent = of_get_parent(np); 375 if (!parent) { 376 kfree(new_map); 377 return -EINVAL; 378 } 379 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 380 new_map[0].data.mux.function = parent->name; 381 new_map[0].data.mux.group = np->name; 382 of_node_put(parent); 383 384 /* create config map */ 385 new_map++; 386 for (i = 0; i < grp->npins; i++) { 387 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 388 new_map[i].data.configs.group_or_pin = 389 pin_get_name(pctldev, grp->pins[i]); 390 new_map[i].data.configs.configs = grp->data[i].configs; 391 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 392 } 393 394 dev_dbg(dev, "maps: function %s group %s num %d\n", 395 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 396 397 return 0; 398 } 399 400 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 401 struct pinctrl_map *map, unsigned num_maps) 402 { 403 kfree(map); 404 } 405 406 static const struct pinctrl_ops rockchip_pctrl_ops = { 407 .get_groups_count = rockchip_get_groups_count, 408 .get_group_name = rockchip_get_group_name, 409 .get_group_pins = rockchip_get_group_pins, 410 .dt_node_to_map = rockchip_dt_node_to_map, 411 .dt_free_map = rockchip_dt_free_map, 412 }; 413 414 /* 415 * Hardware access 416 */ 417 418 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 419 { 420 .num = 1, 421 .pin = 0, 422 .reg = 0x418, 423 .bit = 0, 424 .mask = 0x3 425 }, { 426 .num = 1, 427 .pin = 1, 428 .reg = 0x418, 429 .bit = 2, 430 .mask = 0x3 431 }, { 432 .num = 1, 433 .pin = 2, 434 .reg = 0x418, 435 .bit = 4, 436 .mask = 0x3 437 }, { 438 .num = 1, 439 .pin = 3, 440 .reg = 0x418, 441 .bit = 6, 442 .mask = 0x3 443 }, { 444 .num = 1, 445 .pin = 4, 446 .reg = 0x418, 447 .bit = 8, 448 .mask = 0x3 449 }, { 450 .num = 1, 451 .pin = 5, 452 .reg = 0x418, 453 .bit = 10, 454 .mask = 0x3 455 }, { 456 .num = 1, 457 .pin = 6, 458 .reg = 0x418, 459 .bit = 12, 460 .mask = 0x3 461 }, { 462 .num = 1, 463 .pin = 7, 464 .reg = 0x418, 465 .bit = 14, 466 .mask = 0x3 467 }, { 468 .num = 1, 469 .pin = 8, 470 .reg = 0x41c, 471 .bit = 0, 472 .mask = 0x3 473 }, { 474 .num = 1, 475 .pin = 9, 476 .reg = 0x41c, 477 .bit = 2, 478 .mask = 0x3 479 }, 480 }; 481 482 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { 483 { 484 .num = 0, 485 .pin = 20, 486 .reg = 0x10000, 487 .bit = 0, 488 .mask = 0xf 489 }, 490 { 491 .num = 0, 492 .pin = 21, 493 .reg = 0x10000, 494 .bit = 4, 495 .mask = 0xf 496 }, 497 { 498 .num = 0, 499 .pin = 22, 500 .reg = 0x10000, 501 .bit = 8, 502 .mask = 0xf 503 }, 504 { 505 .num = 0, 506 .pin = 23, 507 .reg = 0x10000, 508 .bit = 12, 509 .mask = 0xf 510 }, 511 }; 512 513 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 514 { 515 .num = 2, 516 .pin = 20, 517 .reg = 0xe8, 518 .bit = 0, 519 .mask = 0x7 520 }, { 521 .num = 2, 522 .pin = 21, 523 .reg = 0xe8, 524 .bit = 4, 525 .mask = 0x7 526 }, { 527 .num = 2, 528 .pin = 22, 529 .reg = 0xe8, 530 .bit = 8, 531 .mask = 0x7 532 }, { 533 .num = 2, 534 .pin = 23, 535 .reg = 0xe8, 536 .bit = 12, 537 .mask = 0x7 538 }, { 539 .num = 2, 540 .pin = 24, 541 .reg = 0xd4, 542 .bit = 12, 543 .mask = 0x7 544 }, 545 }; 546 547 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 548 { 549 /* gpio1b6_sel */ 550 .num = 1, 551 .pin = 14, 552 .reg = 0x28, 553 .bit = 12, 554 .mask = 0xf 555 }, { 556 /* gpio1b7_sel */ 557 .num = 1, 558 .pin = 15, 559 .reg = 0x2c, 560 .bit = 0, 561 .mask = 0x3 562 }, { 563 /* gpio1c2_sel */ 564 .num = 1, 565 .pin = 18, 566 .reg = 0x30, 567 .bit = 4, 568 .mask = 0xf 569 }, { 570 /* gpio1c3_sel */ 571 .num = 1, 572 .pin = 19, 573 .reg = 0x30, 574 .bit = 8, 575 .mask = 0xf 576 }, { 577 /* gpio1c4_sel */ 578 .num = 1, 579 .pin = 20, 580 .reg = 0x30, 581 .bit = 12, 582 .mask = 0xf 583 }, { 584 /* gpio1c5_sel */ 585 .num = 1, 586 .pin = 21, 587 .reg = 0x34, 588 .bit = 0, 589 .mask = 0xf 590 }, { 591 /* gpio1c6_sel */ 592 .num = 1, 593 .pin = 22, 594 .reg = 0x34, 595 .bit = 4, 596 .mask = 0xf 597 }, { 598 /* gpio1c7_sel */ 599 .num = 1, 600 .pin = 23, 601 .reg = 0x34, 602 .bit = 8, 603 .mask = 0xf 604 }, { 605 /* gpio2a2_sel */ 606 .num = 2, 607 .pin = 2, 608 .reg = 0x40, 609 .bit = 4, 610 .mask = 0x3 611 }, { 612 /* gpio2a3_sel */ 613 .num = 2, 614 .pin = 3, 615 .reg = 0x40, 616 .bit = 6, 617 .mask = 0x3 618 }, { 619 /* gpio2c0_sel */ 620 .num = 2, 621 .pin = 16, 622 .reg = 0x50, 623 .bit = 0, 624 .mask = 0x3 625 }, { 626 /* gpio3b2_sel */ 627 .num = 3, 628 .pin = 10, 629 .reg = 0x68, 630 .bit = 4, 631 .mask = 0x3 632 }, { 633 /* gpio3b3_sel */ 634 .num = 3, 635 .pin = 11, 636 .reg = 0x68, 637 .bit = 6, 638 .mask = 0x3 639 }, { 640 /* gpio3b4_sel */ 641 .num = 3, 642 .pin = 12, 643 .reg = 0x68, 644 .bit = 8, 645 .mask = 0xf 646 }, { 647 /* gpio3b5_sel */ 648 .num = 3, 649 .pin = 13, 650 .reg = 0x68, 651 .bit = 12, 652 .mask = 0xf 653 }, 654 }; 655 656 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 657 { 658 /* gpio2_b7_sel */ 659 .num = 2, 660 .pin = 15, 661 .reg = 0x28, 662 .bit = 0, 663 .mask = 0x7 664 }, { 665 /* gpio2_c7_sel */ 666 .num = 2, 667 .pin = 23, 668 .reg = 0x30, 669 .bit = 14, 670 .mask = 0x3 671 }, { 672 /* gpio3_b1_sel */ 673 .num = 3, 674 .pin = 9, 675 .reg = 0x44, 676 .bit = 2, 677 .mask = 0x3 678 }, { 679 /* gpio3_b2_sel */ 680 .num = 3, 681 .pin = 10, 682 .reg = 0x44, 683 .bit = 4, 684 .mask = 0x3 685 }, { 686 /* gpio3_b3_sel */ 687 .num = 3, 688 .pin = 11, 689 .reg = 0x44, 690 .bit = 6, 691 .mask = 0x3 692 }, { 693 /* gpio3_b4_sel */ 694 .num = 3, 695 .pin = 12, 696 .reg = 0x44, 697 .bit = 8, 698 .mask = 0x3 699 }, { 700 /* gpio3_b5_sel */ 701 .num = 3, 702 .pin = 13, 703 .reg = 0x44, 704 .bit = 10, 705 .mask = 0x3 706 }, { 707 /* gpio3_b6_sel */ 708 .num = 3, 709 .pin = 14, 710 .reg = 0x44, 711 .bit = 12, 712 .mask = 0x3 713 }, { 714 /* gpio3_b7_sel */ 715 .num = 3, 716 .pin = 15, 717 .reg = 0x44, 718 .bit = 14, 719 .mask = 0x3 720 }, 721 }; 722 723 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 724 int *reg, u8 *bit, int *mask) 725 { 726 struct rockchip_pinctrl *info = bank->drvdata; 727 struct rockchip_pin_ctrl *ctrl = info->ctrl; 728 struct rockchip_mux_recalced_data *data; 729 int i; 730 731 for (i = 0; i < ctrl->niomux_recalced; i++) { 732 data = &ctrl->iomux_recalced[i]; 733 if (data->num == bank->bank_num && 734 data->pin == pin) 735 break; 736 } 737 738 if (i >= ctrl->niomux_recalced) 739 return; 740 741 *reg = data->reg; 742 *mask = data->mask; 743 *bit = data->bit; 744 } 745 746 static struct rockchip_mux_route_data px30_mux_route_data[] = { 747 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */ 748 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */ 749 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */ 750 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */ 751 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */ 752 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */ 753 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */ 754 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */ 755 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */ 756 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */ 757 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */ 758 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */ 759 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */ 760 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */ 761 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */ 762 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */ 763 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */ 764 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */ 765 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */ 766 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */ 767 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */ 768 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */ 769 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */ 770 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */ 771 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */ 772 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */ 773 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */ 774 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */ 775 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */ 776 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */ 777 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */ 778 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */ 779 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */ 780 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */ 781 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */ 782 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */ 783 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */ 784 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */ 785 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */ 786 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */ 787 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */ 788 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */ 789 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */ 790 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */ 791 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */ 792 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */ 793 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */ 794 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */ 795 }; 796 797 static struct rockchip_mux_route_data rv1126_mux_route_data[] = { 798 RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ 799 RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ 800 801 RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */ 802 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */ 803 RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */ 804 805 RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ 806 RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ 807 808 RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ 809 RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ 810 811 RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ 812 RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ 813 814 RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */ 815 RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */ 816 RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */ 817 818 RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ 819 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ 820 821 RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */ 822 RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */ 823 RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */ 824 825 RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */ 826 RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */ 827 RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */ 828 829 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ 830 RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ 831 832 RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ 833 RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ 834 835 RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */ 836 RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */ 837 838 RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */ 839 RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */ 840 841 RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */ 842 RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */ 843 844 RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ 845 RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ 846 847 RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ 848 RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ 849 850 RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */ 851 RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */ 852 RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */ 853 854 RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */ 855 RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */ 856 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */ 857 858 RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */ 859 RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */ 860 RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */ 861 862 RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */ 863 RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */ 864 865 RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */ 866 RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */ 867 868 RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */ 869 RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */ 870 871 RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ 872 RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ 873 874 RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */ 875 RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */ 876 877 RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */ 878 RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */ 879 880 RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */ 881 RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */ 882 883 RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ 884 RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ 885 886 RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */ 887 RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */ 888 RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */ 889 890 RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ 891 RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ 892 }; 893 894 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 895 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ 896 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ 897 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ 898 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */ 899 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */ 900 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */ 901 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ 902 }; 903 904 static struct rockchip_mux_route_data rk3188_mux_route_data[] = { 905 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ 906 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ 907 }; 908 909 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 910 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ 911 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ 912 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ 913 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */ 914 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */ 915 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */ 916 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */ 917 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */ 918 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */ 919 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */ 920 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */ 921 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */ 922 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */ 923 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */ 924 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */ 925 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */ 926 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */ 927 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ 928 }; 929 930 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 931 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ 932 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ 933 }; 934 935 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 936 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ 937 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ 938 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ 939 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */ 940 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) | BIT(4)), /* i2c3_sdam1 */ 941 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ 942 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ 943 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ 944 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ 945 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ 946 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ 947 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ 948 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ 949 }; 950 951 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 952 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ 953 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ 954 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ 955 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */ 956 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */ 957 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */ 958 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */ 959 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */ 960 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */ 961 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */ 962 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */ 963 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ 964 }; 965 966 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 967 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ 968 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ 969 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ 970 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */ 971 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ 972 }; 973 974 static struct rockchip_mux_route_data rk3568_mux_route_data[] = { 975 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ 976 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ 977 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ 978 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */ 979 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */ 980 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */ 981 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */ 982 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */ 983 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */ 984 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */ 985 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */ 986 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */ 987 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */ 988 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */ 989 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */ 990 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */ 991 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */ 992 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */ 993 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */ 994 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */ 995 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */ 996 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */ 997 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */ 998 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */ 999 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */ 1000 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */ 1001 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */ 1002 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */ 1003 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */ 1004 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */ 1005 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */ 1006 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */ 1007 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */ 1008 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */ 1009 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */ 1010 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */ 1011 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */ 1012 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */ 1013 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */ 1014 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */ 1015 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */ 1016 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */ 1017 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */ 1018 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */ 1019 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */ 1020 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */ 1021 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */ 1022 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */ 1023 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */ 1024 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */ 1025 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */ 1026 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */ 1027 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */ 1028 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */ 1029 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */ 1030 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */ 1031 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */ 1032 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */ 1033 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */ 1034 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */ 1035 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */ 1036 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */ 1037 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */ 1038 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */ 1039 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */ 1040 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */ 1041 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */ 1042 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */ 1043 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */ 1044 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */ 1045 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */ 1046 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */ 1047 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */ 1048 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */ 1049 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */ 1050 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */ 1051 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */ 1052 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */ 1053 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */ 1054 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 1055 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 1056 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 1057 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 1058 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */ 1059 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */ 1060 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */ 1061 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */ 1062 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */ 1063 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */ 1064 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */ 1065 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */ 1066 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */ 1067 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */ 1068 }; 1069 1070 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1071 int mux, u32 *loc, u32 *reg, u32 *value) 1072 { 1073 struct rockchip_pinctrl *info = bank->drvdata; 1074 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1075 struct rockchip_mux_route_data *data; 1076 int i; 1077 1078 for (i = 0; i < ctrl->niomux_routes; i++) { 1079 data = &ctrl->iomux_routes[i]; 1080 if ((data->bank_num == bank->bank_num) && 1081 (data->pin == pin) && (data->func == mux)) 1082 break; 1083 } 1084 1085 if (i >= ctrl->niomux_routes) 1086 return false; 1087 1088 *loc = data->route_location; 1089 *reg = data->route_offset; 1090 *value = data->route_val; 1091 1092 return true; 1093 } 1094 1095 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1096 { 1097 struct rockchip_pinctrl *info = bank->drvdata; 1098 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1099 int iomux_num = (pin / 8); 1100 struct regmap *regmap; 1101 unsigned int val; 1102 int reg, ret, mask, mux_type; 1103 u8 bit; 1104 1105 if (iomux_num > 3) 1106 return -EINVAL; 1107 1108 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1109 dev_err(info->dev, "pin %d is unrouted\n", pin); 1110 return -EINVAL; 1111 } 1112 1113 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1114 return RK_FUNC_GPIO; 1115 1116 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1117 regmap = info->regmap_pmu; 1118 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1119 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; 1120 else 1121 regmap = info->regmap_base; 1122 1123 /* get basic quadrupel of mux registers and the correct reg inside */ 1124 mux_type = bank->iomux[iomux_num].type; 1125 reg = bank->iomux[iomux_num].offset; 1126 if (mux_type & IOMUX_WIDTH_4BIT) { 1127 if ((pin % 8) >= 4) 1128 reg += 0x4; 1129 bit = (pin % 4) * 4; 1130 mask = 0xf; 1131 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1132 if ((pin % 8) >= 5) 1133 reg += 0x4; 1134 bit = (pin % 8 % 5) * 3; 1135 mask = 0x7; 1136 } else { 1137 bit = (pin % 8) * 2; 1138 mask = 0x3; 1139 } 1140 1141 if (bank->recalced_mask & BIT(pin)) 1142 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1143 1144 if (ctrl->type == RK3576) { 1145 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) 1146 reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */ 1147 } 1148 1149 if (ctrl->type == RK3588) { 1150 if (bank->bank_num == 0) { 1151 if ((pin >= RK_PB4) && (pin <= RK_PD7)) { 1152 u32 reg0 = 0; 1153 1154 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1155 ret = regmap_read(regmap, reg0, &val); 1156 if (ret) 1157 return ret; 1158 1159 if (!(val & BIT(8))) 1160 return ((val >> bit) & mask); 1161 1162 reg = reg + 0x8000; /* BUS_IOC_BASE */ 1163 regmap = info->regmap_base; 1164 } 1165 } else if (bank->bank_num > 0) { 1166 reg += 0x8000; /* BUS_IOC_BASE */ 1167 } 1168 } 1169 1170 ret = regmap_read(regmap, reg, &val); 1171 if (ret) 1172 return ret; 1173 1174 return ((val >> bit) & mask); 1175 } 1176 1177 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1178 int pin, int mux) 1179 { 1180 struct rockchip_pinctrl *info = bank->drvdata; 1181 struct device *dev = info->dev; 1182 int iomux_num = (pin / 8); 1183 1184 if (iomux_num > 3) 1185 return -EINVAL; 1186 1187 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1188 dev_err(dev, "pin %d is unrouted\n", pin); 1189 return -EINVAL; 1190 } 1191 1192 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1193 if (mux != RK_FUNC_GPIO) { 1194 dev_err(dev, "pin %d only supports a gpio mux\n", pin); 1195 return -ENOTSUPP; 1196 } 1197 } 1198 1199 return 0; 1200 } 1201 1202 /* 1203 * Set a new mux function for a pin. 1204 * 1205 * The register is divided into the upper and lower 16 bit. When changing 1206 * a value, the previous register value is not read and changed. Instead 1207 * it seems the changed bits are marked in the upper 16 bit, while the 1208 * changed value gets set in the same offset in the lower 16 bit. 1209 * All pin settings seem to be 2 bit wide in both the upper and lower 1210 * parts. 1211 * @bank: pin bank to change 1212 * @pin: pin to change 1213 * @mux: new mux function to set 1214 */ 1215 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1216 { 1217 struct rockchip_pinctrl *info = bank->drvdata; 1218 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1219 struct device *dev = info->dev; 1220 int iomux_num = (pin / 8); 1221 struct regmap *regmap; 1222 int reg, ret, mask, mux_type; 1223 u8 bit; 1224 u32 data, rmask, route_location, route_reg, route_val; 1225 1226 ret = rockchip_verify_mux(bank, pin, mux); 1227 if (ret < 0) 1228 return ret; 1229 1230 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1231 return 0; 1232 1233 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1234 1235 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1236 regmap = info->regmap_pmu; 1237 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1238 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; 1239 else 1240 regmap = info->regmap_base; 1241 1242 /* get basic quadrupel of mux registers and the correct reg inside */ 1243 mux_type = bank->iomux[iomux_num].type; 1244 reg = bank->iomux[iomux_num].offset; 1245 if (mux_type & IOMUX_WIDTH_4BIT) { 1246 if ((pin % 8) >= 4) 1247 reg += 0x4; 1248 bit = (pin % 4) * 4; 1249 mask = 0xf; 1250 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1251 if ((pin % 8) >= 5) 1252 reg += 0x4; 1253 bit = (pin % 8 % 5) * 3; 1254 mask = 0x7; 1255 } else { 1256 bit = (pin % 8) * 2; 1257 mask = 0x3; 1258 } 1259 1260 if (bank->recalced_mask & BIT(pin)) 1261 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1262 1263 if (ctrl->type == RK3576) { 1264 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) 1265 reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */ 1266 } 1267 1268 if (ctrl->type == RK3588) { 1269 if (bank->bank_num == 0) { 1270 if ((pin >= RK_PB4) && (pin <= RK_PD7)) { 1271 if (mux < 8) { 1272 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1273 data = (mask << (bit + 16)); 1274 rmask = data | (data >> 16); 1275 data |= (mux & mask) << bit; 1276 ret = regmap_update_bits(regmap, reg, rmask, data); 1277 } else { 1278 u32 reg0 = 0; 1279 1280 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1281 data = (mask << (bit + 16)); 1282 rmask = data | (data >> 16); 1283 data |= 8 << bit; 1284 ret = regmap_update_bits(regmap, reg0, rmask, data); 1285 1286 reg0 = reg + 0x8000; /* BUS_IOC_BASE */ 1287 data = (mask << (bit + 16)); 1288 rmask = data | (data >> 16); 1289 data |= mux << bit; 1290 regmap = info->regmap_base; 1291 ret |= regmap_update_bits(regmap, reg0, rmask, data); 1292 } 1293 } else { 1294 data = (mask << (bit + 16)); 1295 rmask = data | (data >> 16); 1296 data |= (mux & mask) << bit; 1297 ret = regmap_update_bits(regmap, reg, rmask, data); 1298 } 1299 return ret; 1300 } else if (bank->bank_num > 0) { 1301 reg += 0x8000; /* BUS_IOC_BASE */ 1302 } 1303 } 1304 1305 if (mux > mask) 1306 return -EINVAL; 1307 1308 if (bank->route_mask & BIT(pin)) { 1309 if (rockchip_get_mux_route(bank, pin, mux, &route_location, 1310 &route_reg, &route_val)) { 1311 struct regmap *route_regmap = regmap; 1312 1313 /* handle special locations */ 1314 switch (route_location) { 1315 case ROCKCHIP_ROUTE_PMU: 1316 route_regmap = info->regmap_pmu; 1317 break; 1318 case ROCKCHIP_ROUTE_GRF: 1319 route_regmap = info->regmap_base; 1320 break; 1321 } 1322 1323 ret = regmap_write(route_regmap, route_reg, route_val); 1324 if (ret) 1325 return ret; 1326 } 1327 } 1328 1329 data = (mask << (bit + 16)); 1330 rmask = data | (data >> 16); 1331 data |= (mux & mask) << bit; 1332 ret = regmap_update_bits(regmap, reg, rmask, data); 1333 1334 return ret; 1335 } 1336 1337 #define PX30_PULL_PMU_OFFSET 0x10 1338 #define PX30_PULL_GRF_OFFSET 0x60 1339 #define PX30_PULL_BITS_PER_PIN 2 1340 #define PX30_PULL_PINS_PER_REG 8 1341 #define PX30_PULL_BANK_STRIDE 16 1342 1343 static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1344 int pin_num, struct regmap **regmap, 1345 int *reg, u8 *bit) 1346 { 1347 struct rockchip_pinctrl *info = bank->drvdata; 1348 1349 /* The first 32 pins of the first bank are located in PMU */ 1350 if (bank->bank_num == 0) { 1351 *regmap = info->regmap_pmu; 1352 *reg = PX30_PULL_PMU_OFFSET; 1353 } else { 1354 *regmap = info->regmap_base; 1355 *reg = PX30_PULL_GRF_OFFSET; 1356 1357 /* correct the offset, as we're starting with the 2nd bank */ 1358 *reg -= 0x10; 1359 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1360 } 1361 1362 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1363 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1364 *bit *= PX30_PULL_BITS_PER_PIN; 1365 1366 return 0; 1367 } 1368 1369 #define PX30_DRV_PMU_OFFSET 0x20 1370 #define PX30_DRV_GRF_OFFSET 0xf0 1371 #define PX30_DRV_BITS_PER_PIN 2 1372 #define PX30_DRV_PINS_PER_REG 8 1373 #define PX30_DRV_BANK_STRIDE 16 1374 1375 static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1376 int pin_num, struct regmap **regmap, 1377 int *reg, u8 *bit) 1378 { 1379 struct rockchip_pinctrl *info = bank->drvdata; 1380 1381 /* The first 32 pins of the first bank are located in PMU */ 1382 if (bank->bank_num == 0) { 1383 *regmap = info->regmap_pmu; 1384 *reg = PX30_DRV_PMU_OFFSET; 1385 } else { 1386 *regmap = info->regmap_base; 1387 *reg = PX30_DRV_GRF_OFFSET; 1388 1389 /* correct the offset, as we're starting with the 2nd bank */ 1390 *reg -= 0x10; 1391 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1392 } 1393 1394 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1395 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1396 *bit *= PX30_DRV_BITS_PER_PIN; 1397 1398 return 0; 1399 } 1400 1401 #define PX30_SCHMITT_PMU_OFFSET 0x38 1402 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1403 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1404 #define PX30_SCHMITT_BANK_STRIDE 16 1405 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1406 1407 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1408 int pin_num, 1409 struct regmap **regmap, 1410 int *reg, u8 *bit) 1411 { 1412 struct rockchip_pinctrl *info = bank->drvdata; 1413 int pins_per_reg; 1414 1415 if (bank->bank_num == 0) { 1416 *regmap = info->regmap_pmu; 1417 *reg = PX30_SCHMITT_PMU_OFFSET; 1418 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1419 } else { 1420 *regmap = info->regmap_base; 1421 *reg = PX30_SCHMITT_GRF_OFFSET; 1422 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1423 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1424 } 1425 1426 *reg += ((pin_num / pins_per_reg) * 4); 1427 *bit = pin_num % pins_per_reg; 1428 1429 return 0; 1430 } 1431 1432 #define RV1108_PULL_PMU_OFFSET 0x10 1433 #define RV1108_PULL_OFFSET 0x110 1434 #define RV1108_PULL_PINS_PER_REG 8 1435 #define RV1108_PULL_BITS_PER_PIN 2 1436 #define RV1108_PULL_BANK_STRIDE 16 1437 1438 static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1439 int pin_num, struct regmap **regmap, 1440 int *reg, u8 *bit) 1441 { 1442 struct rockchip_pinctrl *info = bank->drvdata; 1443 1444 /* The first 24 pins of the first bank are located in PMU */ 1445 if (bank->bank_num == 0) { 1446 *regmap = info->regmap_pmu; 1447 *reg = RV1108_PULL_PMU_OFFSET; 1448 } else { 1449 *reg = RV1108_PULL_OFFSET; 1450 *regmap = info->regmap_base; 1451 /* correct the offset, as we're starting with the 2nd bank */ 1452 *reg -= 0x10; 1453 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1454 } 1455 1456 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1457 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1458 *bit *= RV1108_PULL_BITS_PER_PIN; 1459 1460 return 0; 1461 } 1462 1463 #define RV1108_DRV_PMU_OFFSET 0x20 1464 #define RV1108_DRV_GRF_OFFSET 0x210 1465 #define RV1108_DRV_BITS_PER_PIN 2 1466 #define RV1108_DRV_PINS_PER_REG 8 1467 #define RV1108_DRV_BANK_STRIDE 16 1468 1469 static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1470 int pin_num, struct regmap **regmap, 1471 int *reg, u8 *bit) 1472 { 1473 struct rockchip_pinctrl *info = bank->drvdata; 1474 1475 /* The first 24 pins of the first bank are located in PMU */ 1476 if (bank->bank_num == 0) { 1477 *regmap = info->regmap_pmu; 1478 *reg = RV1108_DRV_PMU_OFFSET; 1479 } else { 1480 *regmap = info->regmap_base; 1481 *reg = RV1108_DRV_GRF_OFFSET; 1482 1483 /* correct the offset, as we're starting with the 2nd bank */ 1484 *reg -= 0x10; 1485 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1486 } 1487 1488 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1489 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1490 *bit *= RV1108_DRV_BITS_PER_PIN; 1491 1492 return 0; 1493 } 1494 1495 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1496 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1497 #define RV1108_SCHMITT_BANK_STRIDE 8 1498 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1499 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1500 1501 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1502 int pin_num, 1503 struct regmap **regmap, 1504 int *reg, u8 *bit) 1505 { 1506 struct rockchip_pinctrl *info = bank->drvdata; 1507 int pins_per_reg; 1508 1509 if (bank->bank_num == 0) { 1510 *regmap = info->regmap_pmu; 1511 *reg = RV1108_SCHMITT_PMU_OFFSET; 1512 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1513 } else { 1514 *regmap = info->regmap_base; 1515 *reg = RV1108_SCHMITT_GRF_OFFSET; 1516 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1517 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1518 } 1519 *reg += ((pin_num / pins_per_reg) * 4); 1520 *bit = pin_num % pins_per_reg; 1521 1522 return 0; 1523 } 1524 1525 #define RV1126_PULL_PMU_OFFSET 0x40 1526 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 1527 #define RV1126_PULL_PINS_PER_REG 8 1528 #define RV1126_PULL_BITS_PER_PIN 2 1529 #define RV1126_PULL_BANK_STRIDE 16 1530 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ 1531 1532 static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1533 int pin_num, struct regmap **regmap, 1534 int *reg, u8 *bit) 1535 { 1536 struct rockchip_pinctrl *info = bank->drvdata; 1537 1538 /* The first 24 pins of the first bank are located in PMU */ 1539 if (bank->bank_num == 0) { 1540 if (RV1126_GPIO_C4_D7(pin_num)) { 1541 *regmap = info->regmap_base; 1542 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1543 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); 1544 *bit = pin_num % RV1126_PULL_PINS_PER_REG; 1545 *bit *= RV1126_PULL_BITS_PER_PIN; 1546 return 0; 1547 } 1548 *regmap = info->regmap_pmu; 1549 *reg = RV1126_PULL_PMU_OFFSET; 1550 } else { 1551 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1552 *regmap = info->regmap_base; 1553 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; 1554 } 1555 1556 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); 1557 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); 1558 *bit *= RV1126_PULL_BITS_PER_PIN; 1559 1560 return 0; 1561 } 1562 1563 #define RV1126_DRV_PMU_OFFSET 0x20 1564 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 1565 #define RV1126_DRV_BITS_PER_PIN 4 1566 #define RV1126_DRV_PINS_PER_REG 4 1567 #define RV1126_DRV_BANK_STRIDE 32 1568 1569 static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1570 int pin_num, struct regmap **regmap, 1571 int *reg, u8 *bit) 1572 { 1573 struct rockchip_pinctrl *info = bank->drvdata; 1574 1575 /* The first 24 pins of the first bank are located in PMU */ 1576 if (bank->bank_num == 0) { 1577 if (RV1126_GPIO_C4_D7(pin_num)) { 1578 *regmap = info->regmap_base; 1579 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1580 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); 1581 *reg -= 0x4; 1582 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1583 *bit *= RV1126_DRV_BITS_PER_PIN; 1584 return 0; 1585 } 1586 *regmap = info->regmap_pmu; 1587 *reg = RV1126_DRV_PMU_OFFSET; 1588 } else { 1589 *regmap = info->regmap_base; 1590 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1591 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; 1592 } 1593 1594 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); 1595 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1596 *bit *= RV1126_DRV_BITS_PER_PIN; 1597 1598 return 0; 1599 } 1600 1601 #define RV1126_SCHMITT_PMU_OFFSET 0x60 1602 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 1603 #define RV1126_SCHMITT_BANK_STRIDE 16 1604 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8 1605 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8 1606 1607 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1608 int pin_num, 1609 struct regmap **regmap, 1610 int *reg, u8 *bit) 1611 { 1612 struct rockchip_pinctrl *info = bank->drvdata; 1613 int pins_per_reg; 1614 1615 if (bank->bank_num == 0) { 1616 if (RV1126_GPIO_C4_D7(pin_num)) { 1617 *regmap = info->regmap_base; 1618 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1619 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); 1620 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; 1621 return 0; 1622 } 1623 *regmap = info->regmap_pmu; 1624 *reg = RV1126_SCHMITT_PMU_OFFSET; 1625 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; 1626 } else { 1627 *regmap = info->regmap_base; 1628 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1629 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; 1630 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; 1631 } 1632 *reg += ((pin_num / pins_per_reg) * 4); 1633 *bit = pin_num % pins_per_reg; 1634 1635 return 0; 1636 } 1637 1638 #define RK3308_SCHMITT_PINS_PER_REG 8 1639 #define RK3308_SCHMITT_BANK_STRIDE 16 1640 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1641 1642 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1643 int pin_num, struct regmap **regmap, 1644 int *reg, u8 *bit) 1645 { 1646 struct rockchip_pinctrl *info = bank->drvdata; 1647 1648 *regmap = info->regmap_base; 1649 *reg = RK3308_SCHMITT_GRF_OFFSET; 1650 1651 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1652 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1653 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1654 1655 return 0; 1656 } 1657 1658 #define RK2928_PULL_OFFSET 0x118 1659 #define RK2928_PULL_PINS_PER_REG 16 1660 #define RK2928_PULL_BANK_STRIDE 8 1661 1662 static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1663 int pin_num, struct regmap **regmap, 1664 int *reg, u8 *bit) 1665 { 1666 struct rockchip_pinctrl *info = bank->drvdata; 1667 1668 *regmap = info->regmap_base; 1669 *reg = RK2928_PULL_OFFSET; 1670 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1671 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1672 1673 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1674 1675 return 0; 1676 }; 1677 1678 #define RK3128_PULL_OFFSET 0x118 1679 1680 static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1681 int pin_num, struct regmap **regmap, 1682 int *reg, u8 *bit) 1683 { 1684 struct rockchip_pinctrl *info = bank->drvdata; 1685 1686 *regmap = info->regmap_base; 1687 *reg = RK3128_PULL_OFFSET; 1688 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1689 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1690 1691 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1692 1693 return 0; 1694 } 1695 1696 #define RK3188_PULL_OFFSET 0x164 1697 #define RK3188_PULL_BITS_PER_PIN 2 1698 #define RK3188_PULL_PINS_PER_REG 8 1699 #define RK3188_PULL_BANK_STRIDE 16 1700 #define RK3188_PULL_PMU_OFFSET 0x64 1701 1702 static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1703 int pin_num, struct regmap **regmap, 1704 int *reg, u8 *bit) 1705 { 1706 struct rockchip_pinctrl *info = bank->drvdata; 1707 1708 /* The first 12 pins of the first bank are located elsewhere */ 1709 if (bank->bank_num == 0 && pin_num < 12) { 1710 *regmap = info->regmap_pmu ? info->regmap_pmu 1711 : bank->regmap_pull; 1712 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1713 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1714 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1715 *bit *= RK3188_PULL_BITS_PER_PIN; 1716 } else { 1717 *regmap = info->regmap_pull ? info->regmap_pull 1718 : info->regmap_base; 1719 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1720 1721 /* correct the offset, as it is the 2nd pull register */ 1722 *reg -= 4; 1723 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1724 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1725 1726 /* 1727 * The bits in these registers have an inverse ordering 1728 * with the lowest pin being in bits 15:14 and the highest 1729 * pin in bits 1:0 1730 */ 1731 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1732 *bit *= RK3188_PULL_BITS_PER_PIN; 1733 } 1734 1735 return 0; 1736 } 1737 1738 #define RK3288_PULL_OFFSET 0x140 1739 static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1740 int pin_num, struct regmap **regmap, 1741 int *reg, u8 *bit) 1742 { 1743 struct rockchip_pinctrl *info = bank->drvdata; 1744 1745 /* The first 24 pins of the first bank are located in PMU */ 1746 if (bank->bank_num == 0) { 1747 *regmap = info->regmap_pmu; 1748 *reg = RK3188_PULL_PMU_OFFSET; 1749 1750 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1751 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1752 *bit *= RK3188_PULL_BITS_PER_PIN; 1753 } else { 1754 *regmap = info->regmap_base; 1755 *reg = RK3288_PULL_OFFSET; 1756 1757 /* correct the offset, as we're starting with the 2nd bank */ 1758 *reg -= 0x10; 1759 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1760 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1761 1762 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1763 *bit *= RK3188_PULL_BITS_PER_PIN; 1764 } 1765 1766 return 0; 1767 } 1768 1769 #define RK3288_DRV_PMU_OFFSET 0x70 1770 #define RK3288_DRV_GRF_OFFSET 0x1c0 1771 #define RK3288_DRV_BITS_PER_PIN 2 1772 #define RK3288_DRV_PINS_PER_REG 8 1773 #define RK3288_DRV_BANK_STRIDE 16 1774 1775 static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1776 int pin_num, struct regmap **regmap, 1777 int *reg, u8 *bit) 1778 { 1779 struct rockchip_pinctrl *info = bank->drvdata; 1780 1781 /* The first 24 pins of the first bank are located in PMU */ 1782 if (bank->bank_num == 0) { 1783 *regmap = info->regmap_pmu; 1784 *reg = RK3288_DRV_PMU_OFFSET; 1785 1786 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1787 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1788 *bit *= RK3288_DRV_BITS_PER_PIN; 1789 } else { 1790 *regmap = info->regmap_base; 1791 *reg = RK3288_DRV_GRF_OFFSET; 1792 1793 /* correct the offset, as we're starting with the 2nd bank */ 1794 *reg -= 0x10; 1795 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1796 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1797 1798 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1799 *bit *= RK3288_DRV_BITS_PER_PIN; 1800 } 1801 1802 return 0; 1803 } 1804 1805 #define RK3228_PULL_OFFSET 0x100 1806 1807 static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1808 int pin_num, struct regmap **regmap, 1809 int *reg, u8 *bit) 1810 { 1811 struct rockchip_pinctrl *info = bank->drvdata; 1812 1813 *regmap = info->regmap_base; 1814 *reg = RK3228_PULL_OFFSET; 1815 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1816 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1817 1818 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1819 *bit *= RK3188_PULL_BITS_PER_PIN; 1820 1821 return 0; 1822 } 1823 1824 #define RK3228_DRV_GRF_OFFSET 0x200 1825 1826 static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1827 int pin_num, struct regmap **regmap, 1828 int *reg, u8 *bit) 1829 { 1830 struct rockchip_pinctrl *info = bank->drvdata; 1831 1832 *regmap = info->regmap_base; 1833 *reg = RK3228_DRV_GRF_OFFSET; 1834 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1835 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1836 1837 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1838 *bit *= RK3288_DRV_BITS_PER_PIN; 1839 1840 return 0; 1841 } 1842 1843 #define RK3308_PULL_OFFSET 0xa0 1844 1845 static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1846 int pin_num, struct regmap **regmap, 1847 int *reg, u8 *bit) 1848 { 1849 struct rockchip_pinctrl *info = bank->drvdata; 1850 1851 *regmap = info->regmap_base; 1852 *reg = RK3308_PULL_OFFSET; 1853 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1854 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1855 1856 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1857 *bit *= RK3188_PULL_BITS_PER_PIN; 1858 1859 return 0; 1860 } 1861 1862 #define RK3308_DRV_GRF_OFFSET 0x100 1863 1864 static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1865 int pin_num, struct regmap **regmap, 1866 int *reg, u8 *bit) 1867 { 1868 struct rockchip_pinctrl *info = bank->drvdata; 1869 1870 *regmap = info->regmap_base; 1871 *reg = RK3308_DRV_GRF_OFFSET; 1872 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1873 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1874 1875 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1876 *bit *= RK3288_DRV_BITS_PER_PIN; 1877 1878 return 0; 1879 } 1880 1881 #define RK3368_PULL_GRF_OFFSET 0x100 1882 #define RK3368_PULL_PMU_OFFSET 0x10 1883 1884 static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1885 int pin_num, struct regmap **regmap, 1886 int *reg, u8 *bit) 1887 { 1888 struct rockchip_pinctrl *info = bank->drvdata; 1889 1890 /* The first 32 pins of the first bank are located in PMU */ 1891 if (bank->bank_num == 0) { 1892 *regmap = info->regmap_pmu; 1893 *reg = RK3368_PULL_PMU_OFFSET; 1894 1895 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1896 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1897 *bit *= RK3188_PULL_BITS_PER_PIN; 1898 } else { 1899 *regmap = info->regmap_base; 1900 *reg = RK3368_PULL_GRF_OFFSET; 1901 1902 /* correct the offset, as we're starting with the 2nd bank */ 1903 *reg -= 0x10; 1904 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1905 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1906 1907 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1908 *bit *= RK3188_PULL_BITS_PER_PIN; 1909 } 1910 1911 return 0; 1912 } 1913 1914 #define RK3368_DRV_PMU_OFFSET 0x20 1915 #define RK3368_DRV_GRF_OFFSET 0x200 1916 1917 static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1918 int pin_num, struct regmap **regmap, 1919 int *reg, u8 *bit) 1920 { 1921 struct rockchip_pinctrl *info = bank->drvdata; 1922 1923 /* The first 32 pins of the first bank are located in PMU */ 1924 if (bank->bank_num == 0) { 1925 *regmap = info->regmap_pmu; 1926 *reg = RK3368_DRV_PMU_OFFSET; 1927 1928 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1929 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1930 *bit *= RK3288_DRV_BITS_PER_PIN; 1931 } else { 1932 *regmap = info->regmap_base; 1933 *reg = RK3368_DRV_GRF_OFFSET; 1934 1935 /* correct the offset, as we're starting with the 2nd bank */ 1936 *reg -= 0x10; 1937 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1938 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1939 1940 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1941 *bit *= RK3288_DRV_BITS_PER_PIN; 1942 } 1943 1944 return 0; 1945 } 1946 1947 #define RK3399_PULL_GRF_OFFSET 0xe040 1948 #define RK3399_PULL_PMU_OFFSET 0x40 1949 #define RK3399_DRV_3BITS_PER_PIN 3 1950 1951 static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1952 int pin_num, struct regmap **regmap, 1953 int *reg, u8 *bit) 1954 { 1955 struct rockchip_pinctrl *info = bank->drvdata; 1956 1957 /* The bank0:16 and bank1:32 pins are located in PMU */ 1958 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1959 *regmap = info->regmap_pmu; 1960 *reg = RK3399_PULL_PMU_OFFSET; 1961 1962 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1963 1964 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1965 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1966 *bit *= RK3188_PULL_BITS_PER_PIN; 1967 } else { 1968 *regmap = info->regmap_base; 1969 *reg = RK3399_PULL_GRF_OFFSET; 1970 1971 /* correct the offset, as we're starting with the 3rd bank */ 1972 *reg -= 0x20; 1973 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1974 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1975 1976 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1977 *bit *= RK3188_PULL_BITS_PER_PIN; 1978 } 1979 1980 return 0; 1981 } 1982 1983 static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1984 int pin_num, struct regmap **regmap, 1985 int *reg, u8 *bit) 1986 { 1987 struct rockchip_pinctrl *info = bank->drvdata; 1988 int drv_num = (pin_num / 8); 1989 1990 /* The bank0:16 and bank1:32 pins are located in PMU */ 1991 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1992 *regmap = info->regmap_pmu; 1993 else 1994 *regmap = info->regmap_base; 1995 1996 *reg = bank->drv[drv_num].offset; 1997 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1998 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1999 *bit = (pin_num % 8) * 3; 2000 else 2001 *bit = (pin_num % 8) * 2; 2002 2003 return 0; 2004 } 2005 2006 #define RK3562_DRV_BITS_PER_PIN 8 2007 #define RK3562_DRV_PINS_PER_REG 2 2008 #define RK3562_DRV_GPIO0_OFFSET 0x20070 2009 #define RK3562_DRV_GPIO1_OFFSET 0x200 2010 #define RK3562_DRV_GPIO2_OFFSET 0x240 2011 #define RK3562_DRV_GPIO3_OFFSET 0x10280 2012 #define RK3562_DRV_GPIO4_OFFSET 0x102C0 2013 2014 static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2015 int pin_num, struct regmap **regmap, 2016 int *reg, u8 *bit) 2017 { 2018 struct rockchip_pinctrl *info = bank->drvdata; 2019 2020 *regmap = info->regmap_base; 2021 switch (bank->bank_num) { 2022 case 0: 2023 *reg = RK3562_DRV_GPIO0_OFFSET; 2024 break; 2025 2026 case 1: 2027 *reg = RK3562_DRV_GPIO1_OFFSET; 2028 break; 2029 2030 case 2: 2031 *reg = RK3562_DRV_GPIO2_OFFSET; 2032 break; 2033 2034 case 3: 2035 *reg = RK3562_DRV_GPIO3_OFFSET; 2036 break; 2037 2038 case 4: 2039 *reg = RK3562_DRV_GPIO4_OFFSET; 2040 break; 2041 2042 default: 2043 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2044 break; 2045 } 2046 2047 *reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4); 2048 *bit = pin_num % RK3562_DRV_PINS_PER_REG; 2049 *bit *= RK3562_DRV_BITS_PER_PIN; 2050 2051 return 0; 2052 } 2053 2054 #define RK3562_PULL_BITS_PER_PIN 2 2055 #define RK3562_PULL_PINS_PER_REG 8 2056 #define RK3562_PULL_GPIO0_OFFSET 0x20020 2057 #define RK3562_PULL_GPIO1_OFFSET 0x80 2058 #define RK3562_PULL_GPIO2_OFFSET 0x90 2059 #define RK3562_PULL_GPIO3_OFFSET 0x100A0 2060 #define RK3562_PULL_GPIO4_OFFSET 0x100B0 2061 2062 static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2063 int pin_num, struct regmap **regmap, 2064 int *reg, u8 *bit) 2065 { 2066 struct rockchip_pinctrl *info = bank->drvdata; 2067 2068 *regmap = info->regmap_base; 2069 switch (bank->bank_num) { 2070 case 0: 2071 *reg = RK3562_PULL_GPIO0_OFFSET; 2072 break; 2073 2074 case 1: 2075 *reg = RK3562_PULL_GPIO1_OFFSET; 2076 break; 2077 2078 case 2: 2079 *reg = RK3562_PULL_GPIO2_OFFSET; 2080 break; 2081 2082 case 3: 2083 *reg = RK3562_PULL_GPIO3_OFFSET; 2084 break; 2085 2086 case 4: 2087 *reg = RK3562_PULL_GPIO4_OFFSET; 2088 break; 2089 2090 default: 2091 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2092 break; 2093 } 2094 2095 *reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4); 2096 *bit = pin_num % RK3562_PULL_PINS_PER_REG; 2097 *bit *= RK3562_PULL_BITS_PER_PIN; 2098 2099 return 0; 2100 } 2101 2102 #define RK3562_SMT_BITS_PER_PIN 2 2103 #define RK3562_SMT_PINS_PER_REG 8 2104 #define RK3562_SMT_GPIO0_OFFSET 0x20030 2105 #define RK3562_SMT_GPIO1_OFFSET 0xC0 2106 #define RK3562_SMT_GPIO2_OFFSET 0xD0 2107 #define RK3562_SMT_GPIO3_OFFSET 0x100E0 2108 #define RK3562_SMT_GPIO4_OFFSET 0x100F0 2109 2110 static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2111 int pin_num, 2112 struct regmap **regmap, 2113 int *reg, u8 *bit) 2114 { 2115 struct rockchip_pinctrl *info = bank->drvdata; 2116 2117 *regmap = info->regmap_base; 2118 switch (bank->bank_num) { 2119 case 0: 2120 *reg = RK3562_SMT_GPIO0_OFFSET; 2121 break; 2122 2123 case 1: 2124 *reg = RK3562_SMT_GPIO1_OFFSET; 2125 break; 2126 2127 case 2: 2128 *reg = RK3562_SMT_GPIO2_OFFSET; 2129 break; 2130 2131 case 3: 2132 *reg = RK3562_SMT_GPIO3_OFFSET; 2133 break; 2134 2135 case 4: 2136 *reg = RK3562_SMT_GPIO4_OFFSET; 2137 break; 2138 2139 default: 2140 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2141 break; 2142 } 2143 2144 *reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4); 2145 *bit = pin_num % RK3562_SMT_PINS_PER_REG; 2146 *bit *= RK3562_SMT_BITS_PER_PIN; 2147 2148 return 0; 2149 } 2150 2151 #define RK3568_PULL_PMU_OFFSET 0x20 2152 #define RK3568_PULL_GRF_OFFSET 0x80 2153 #define RK3568_PULL_BITS_PER_PIN 2 2154 #define RK3568_PULL_PINS_PER_REG 8 2155 #define RK3568_PULL_BANK_STRIDE 0x10 2156 2157 static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2158 int pin_num, struct regmap **regmap, 2159 int *reg, u8 *bit) 2160 { 2161 struct rockchip_pinctrl *info = bank->drvdata; 2162 2163 if (bank->bank_num == 0) { 2164 *regmap = info->regmap_pmu; 2165 *reg = RK3568_PULL_PMU_OFFSET; 2166 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; 2167 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 2168 2169 *bit = pin_num % RK3568_PULL_PINS_PER_REG; 2170 *bit *= RK3568_PULL_BITS_PER_PIN; 2171 } else { 2172 *regmap = info->regmap_base; 2173 *reg = RK3568_PULL_GRF_OFFSET; 2174 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; 2175 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 2176 2177 *bit = (pin_num % RK3568_PULL_PINS_PER_REG); 2178 *bit *= RK3568_PULL_BITS_PER_PIN; 2179 } 2180 2181 return 0; 2182 } 2183 2184 #define RK3568_DRV_PMU_OFFSET 0x70 2185 #define RK3568_DRV_GRF_OFFSET 0x200 2186 #define RK3568_DRV_BITS_PER_PIN 8 2187 #define RK3568_DRV_PINS_PER_REG 2 2188 #define RK3568_DRV_BANK_STRIDE 0x40 2189 2190 static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2191 int pin_num, struct regmap **regmap, 2192 int *reg, u8 *bit) 2193 { 2194 struct rockchip_pinctrl *info = bank->drvdata; 2195 2196 /* The first 32 pins of the first bank are located in PMU */ 2197 if (bank->bank_num == 0) { 2198 *regmap = info->regmap_pmu; 2199 *reg = RK3568_DRV_PMU_OFFSET; 2200 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 2201 2202 *bit = pin_num % RK3568_DRV_PINS_PER_REG; 2203 *bit *= RK3568_DRV_BITS_PER_PIN; 2204 } else { 2205 *regmap = info->regmap_base; 2206 *reg = RK3568_DRV_GRF_OFFSET; 2207 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; 2208 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 2209 2210 *bit = (pin_num % RK3568_DRV_PINS_PER_REG); 2211 *bit *= RK3568_DRV_BITS_PER_PIN; 2212 } 2213 2214 return 0; 2215 } 2216 2217 #define RK3576_DRV_BITS_PER_PIN 4 2218 #define RK3576_DRV_PINS_PER_REG 4 2219 #define RK3576_DRV_GPIO0_AL_OFFSET 0x10 2220 #define RK3576_DRV_GPIO0_BH_OFFSET 0x2014 2221 #define RK3576_DRV_GPIO1_OFFSET 0x6020 2222 #define RK3576_DRV_GPIO2_OFFSET 0x6040 2223 #define RK3576_DRV_GPIO3_OFFSET 0x6060 2224 #define RK3576_DRV_GPIO4_AL_OFFSET 0x6080 2225 #define RK3576_DRV_GPIO4_CL_OFFSET 0xA090 2226 #define RK3576_DRV_GPIO4_DL_OFFSET 0xB098 2227 2228 static int rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2229 int pin_num, struct regmap **regmap, 2230 int *reg, u8 *bit) 2231 { 2232 struct rockchip_pinctrl *info = bank->drvdata; 2233 2234 *regmap = info->regmap_base; 2235 2236 if (bank->bank_num == 0 && pin_num < 12) 2237 *reg = RK3576_DRV_GPIO0_AL_OFFSET; 2238 else if (bank->bank_num == 0) 2239 *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc; 2240 else if (bank->bank_num == 1) 2241 *reg = RK3576_DRV_GPIO1_OFFSET; 2242 else if (bank->bank_num == 2) 2243 *reg = RK3576_DRV_GPIO2_OFFSET; 2244 else if (bank->bank_num == 3) 2245 *reg = RK3576_DRV_GPIO3_OFFSET; 2246 else if (bank->bank_num == 4 && pin_num < 16) 2247 *reg = RK3576_DRV_GPIO4_AL_OFFSET; 2248 else if (bank->bank_num == 4 && pin_num < 24) 2249 *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10; 2250 else if (bank->bank_num == 4) 2251 *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18; 2252 else 2253 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2254 2255 *reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4); 2256 *bit = pin_num % RK3576_DRV_PINS_PER_REG; 2257 *bit *= RK3576_DRV_BITS_PER_PIN; 2258 2259 return 0; 2260 } 2261 2262 #define RK3576_PULL_BITS_PER_PIN 2 2263 #define RK3576_PULL_PINS_PER_REG 8 2264 #define RK3576_PULL_GPIO0_AL_OFFSET 0x20 2265 #define RK3576_PULL_GPIO0_BH_OFFSET 0x2028 2266 #define RK3576_PULL_GPIO1_OFFSET 0x6110 2267 #define RK3576_PULL_GPIO2_OFFSET 0x6120 2268 #define RK3576_PULL_GPIO3_OFFSET 0x6130 2269 #define RK3576_PULL_GPIO4_AL_OFFSET 0x6140 2270 #define RK3576_PULL_GPIO4_CL_OFFSET 0xA148 2271 #define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C 2272 2273 static int rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2274 int pin_num, struct regmap **regmap, 2275 int *reg, u8 *bit) 2276 { 2277 struct rockchip_pinctrl *info = bank->drvdata; 2278 2279 *regmap = info->regmap_base; 2280 2281 if (bank->bank_num == 0 && pin_num < 12) 2282 *reg = RK3576_PULL_GPIO0_AL_OFFSET; 2283 else if (bank->bank_num == 0) 2284 *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4; 2285 else if (bank->bank_num == 1) 2286 *reg = RK3576_PULL_GPIO1_OFFSET; 2287 else if (bank->bank_num == 2) 2288 *reg = RK3576_PULL_GPIO2_OFFSET; 2289 else if (bank->bank_num == 3) 2290 *reg = RK3576_PULL_GPIO3_OFFSET; 2291 else if (bank->bank_num == 4 && pin_num < 16) 2292 *reg = RK3576_PULL_GPIO4_AL_OFFSET; 2293 else if (bank->bank_num == 4 && pin_num < 24) 2294 *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8; 2295 else if (bank->bank_num == 4) 2296 *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc; 2297 else 2298 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2299 2300 *reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4); 2301 *bit = pin_num % RK3576_PULL_PINS_PER_REG; 2302 *bit *= RK3576_PULL_BITS_PER_PIN; 2303 2304 return 0; 2305 } 2306 2307 #define RK3576_SMT_BITS_PER_PIN 1 2308 #define RK3576_SMT_PINS_PER_REG 8 2309 #define RK3576_SMT_GPIO0_AL_OFFSET 0x30 2310 #define RK3576_SMT_GPIO0_BH_OFFSET 0x2040 2311 #define RK3576_SMT_GPIO1_OFFSET 0x6210 2312 #define RK3576_SMT_GPIO2_OFFSET 0x6220 2313 #define RK3576_SMT_GPIO3_OFFSET 0x6230 2314 #define RK3576_SMT_GPIO4_AL_OFFSET 0x6240 2315 #define RK3576_SMT_GPIO4_CL_OFFSET 0xA248 2316 #define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C 2317 2318 static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2319 int pin_num, 2320 struct regmap **regmap, 2321 int *reg, u8 *bit) 2322 { 2323 struct rockchip_pinctrl *info = bank->drvdata; 2324 2325 *regmap = info->regmap_base; 2326 2327 if (bank->bank_num == 0 && pin_num < 12) 2328 *reg = RK3576_SMT_GPIO0_AL_OFFSET; 2329 else if (bank->bank_num == 0) 2330 *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4; 2331 else if (bank->bank_num == 1) 2332 *reg = RK3576_SMT_GPIO1_OFFSET; 2333 else if (bank->bank_num == 2) 2334 *reg = RK3576_SMT_GPIO2_OFFSET; 2335 else if (bank->bank_num == 3) 2336 *reg = RK3576_SMT_GPIO3_OFFSET; 2337 else if (bank->bank_num == 4 && pin_num < 16) 2338 *reg = RK3576_SMT_GPIO4_AL_OFFSET; 2339 else if (bank->bank_num == 4 && pin_num < 24) 2340 *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8; 2341 else if (bank->bank_num == 4) 2342 *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc; 2343 else 2344 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2345 2346 *reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4); 2347 *bit = pin_num % RK3576_SMT_PINS_PER_REG; 2348 *bit *= RK3576_SMT_BITS_PER_PIN; 2349 2350 return 0; 2351 } 2352 2353 #define RK3588_PMU1_IOC_REG (0x0000) 2354 #define RK3588_PMU2_IOC_REG (0x4000) 2355 #define RK3588_BUS_IOC_REG (0x8000) 2356 #define RK3588_VCCIO1_4_IOC_REG (0x9000) 2357 #define RK3588_VCCIO3_5_IOC_REG (0xA000) 2358 #define RK3588_VCCIO2_IOC_REG (0xB000) 2359 #define RK3588_VCCIO6_IOC_REG (0xC000) 2360 #define RK3588_EMMC_IOC_REG (0xD000) 2361 2362 static const u32 rk3588_ds_regs[][2] = { 2363 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010}, 2364 {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014}, 2365 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018}, 2366 {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014}, 2367 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018}, 2368 {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C}, 2369 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020}, 2370 {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024}, 2371 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020}, 2372 {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024}, 2373 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028}, 2374 {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C}, 2375 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030}, 2376 {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034}, 2377 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038}, 2378 {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C}, 2379 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040}, 2380 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044}, 2381 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048}, 2382 {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C}, 2383 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050}, 2384 {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054}, 2385 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058}, 2386 {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C}, 2387 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060}, 2388 {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064}, 2389 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068}, 2390 {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C}, 2391 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070}, 2392 {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074}, 2393 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078}, 2394 {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C}, 2395 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080}, 2396 {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084}, 2397 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088}, 2398 {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C}, 2399 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090}, 2400 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090}, 2401 {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094}, 2402 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098}, 2403 {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C}, 2404 }; 2405 2406 static const u32 rk3588_p_regs[][2] = { 2407 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020}, 2408 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024}, 2409 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028}, 2410 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C}, 2411 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030}, 2412 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110}, 2413 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114}, 2414 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118}, 2415 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C}, 2416 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120}, 2417 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120}, 2418 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124}, 2419 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128}, 2420 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C}, 2421 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130}, 2422 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134}, 2423 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138}, 2424 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C}, 2425 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140}, 2426 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144}, 2427 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148}, 2428 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148}, 2429 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C}, 2430 }; 2431 2432 static const u32 rk3588_smt_regs[][2] = { 2433 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030}, 2434 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034}, 2435 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040}, 2436 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044}, 2437 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048}, 2438 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210}, 2439 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214}, 2440 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218}, 2441 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C}, 2442 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220}, 2443 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220}, 2444 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224}, 2445 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228}, 2446 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C}, 2447 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230}, 2448 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234}, 2449 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238}, 2450 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C}, 2451 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240}, 2452 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244}, 2453 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248}, 2454 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248}, 2455 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C}, 2456 }; 2457 2458 #define RK3588_PULL_BITS_PER_PIN 2 2459 #define RK3588_PULL_PINS_PER_REG 8 2460 2461 static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2462 int pin_num, struct regmap **regmap, 2463 int *reg, u8 *bit) 2464 { 2465 struct rockchip_pinctrl *info = bank->drvdata; 2466 u8 bank_num = bank->bank_num; 2467 u32 pin = bank_num * 32 + pin_num; 2468 int i; 2469 2470 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) { 2471 if (pin >= rk3588_p_regs[i][0]) { 2472 *reg = rk3588_p_regs[i][1]; 2473 *regmap = info->regmap_base; 2474 *bit = pin_num % RK3588_PULL_PINS_PER_REG; 2475 *bit *= RK3588_PULL_BITS_PER_PIN; 2476 return 0; 2477 } 2478 } 2479 2480 return -EINVAL; 2481 } 2482 2483 #define RK3588_DRV_BITS_PER_PIN 4 2484 #define RK3588_DRV_PINS_PER_REG 4 2485 2486 static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2487 int pin_num, struct regmap **regmap, 2488 int *reg, u8 *bit) 2489 { 2490 struct rockchip_pinctrl *info = bank->drvdata; 2491 u8 bank_num = bank->bank_num; 2492 u32 pin = bank_num * 32 + pin_num; 2493 int i; 2494 2495 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) { 2496 if (pin >= rk3588_ds_regs[i][0]) { 2497 *reg = rk3588_ds_regs[i][1]; 2498 *regmap = info->regmap_base; 2499 *bit = pin_num % RK3588_DRV_PINS_PER_REG; 2500 *bit *= RK3588_DRV_BITS_PER_PIN; 2501 return 0; 2502 } 2503 } 2504 2505 return -EINVAL; 2506 } 2507 2508 #define RK3588_SMT_BITS_PER_PIN 1 2509 #define RK3588_SMT_PINS_PER_REG 8 2510 2511 static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2512 int pin_num, 2513 struct regmap **regmap, 2514 int *reg, u8 *bit) 2515 { 2516 struct rockchip_pinctrl *info = bank->drvdata; 2517 u8 bank_num = bank->bank_num; 2518 u32 pin = bank_num * 32 + pin_num; 2519 int i; 2520 2521 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) { 2522 if (pin >= rk3588_smt_regs[i][0]) { 2523 *reg = rk3588_smt_regs[i][1]; 2524 *regmap = info->regmap_base; 2525 *bit = pin_num % RK3588_SMT_PINS_PER_REG; 2526 *bit *= RK3588_SMT_BITS_PER_PIN; 2527 return 0; 2528 } 2529 } 2530 2531 return -EINVAL; 2532 } 2533 2534 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2535 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2536 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2537 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2538 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2539 { 4, 7, 10, 13, 16, 19, 22, 26 } 2540 }; 2541 2542 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 2543 int pin_num) 2544 { 2545 struct rockchip_pinctrl *info = bank->drvdata; 2546 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2547 struct device *dev = info->dev; 2548 struct regmap *regmap; 2549 int reg, ret; 2550 u32 data, temp, rmask_bits; 2551 u8 bit; 2552 int drv_type = bank->drv[pin_num / 8].drv_type; 2553 2554 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2555 if (ret) 2556 return ret; 2557 2558 switch (drv_type) { 2559 case DRV_TYPE_IO_1V8_3V0_AUTO: 2560 case DRV_TYPE_IO_3V3_ONLY: 2561 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2562 switch (bit) { 2563 case 0 ... 12: 2564 /* regular case, nothing to do */ 2565 break; 2566 case 15: 2567 /* 2568 * drive-strength offset is special, as it is 2569 * spread over 2 registers 2570 */ 2571 ret = regmap_read(regmap, reg, &data); 2572 if (ret) 2573 return ret; 2574 2575 ret = regmap_read(regmap, reg + 0x4, &temp); 2576 if (ret) 2577 return ret; 2578 2579 /* 2580 * the bit data[15] contains bit 0 of the value 2581 * while temp[1:0] contains bits 2 and 1 2582 */ 2583 data >>= 15; 2584 temp &= 0x3; 2585 temp <<= 1; 2586 data |= temp; 2587 2588 return rockchip_perpin_drv_list[drv_type][data]; 2589 case 18 ... 21: 2590 /* setting fully enclosed in the second register */ 2591 reg += 4; 2592 bit -= 16; 2593 break; 2594 default: 2595 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 2596 bit, drv_type); 2597 return -EINVAL; 2598 } 2599 2600 break; 2601 case DRV_TYPE_IO_DEFAULT: 2602 case DRV_TYPE_IO_1V8_OR_3V0: 2603 case DRV_TYPE_IO_1V8_ONLY: 2604 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2605 break; 2606 default: 2607 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 2608 return -EINVAL; 2609 } 2610 2611 ret = regmap_read(regmap, reg, &data); 2612 if (ret) 2613 return ret; 2614 2615 data >>= bit; 2616 data &= (1 << rmask_bits) - 1; 2617 2618 return rockchip_perpin_drv_list[drv_type][data]; 2619 } 2620 2621 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2622 int pin_num, int strength) 2623 { 2624 struct rockchip_pinctrl *info = bank->drvdata; 2625 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2626 struct device *dev = info->dev; 2627 struct regmap *regmap; 2628 int reg, ret, i; 2629 u32 data, rmask, rmask_bits, temp; 2630 u8 bit; 2631 int drv_type = bank->drv[pin_num / 8].drv_type; 2632 2633 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n", 2634 bank->bank_num, pin_num, strength); 2635 2636 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2637 if (ret) 2638 return ret; 2639 if (ctrl->type == RK3588) { 2640 rmask_bits = RK3588_DRV_BITS_PER_PIN; 2641 ret = strength; 2642 goto config; 2643 } else if (ctrl->type == RK3562 || 2644 ctrl->type == RK3568) { 2645 rmask_bits = RK3568_DRV_BITS_PER_PIN; 2646 ret = (1 << (strength + 1)) - 1; 2647 goto config; 2648 } else if (ctrl->type == RK3576) { 2649 rmask_bits = RK3576_DRV_BITS_PER_PIN; 2650 ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1)); 2651 goto config; 2652 } 2653 2654 if (ctrl->type == RV1126) { 2655 rmask_bits = RV1126_DRV_BITS_PER_PIN; 2656 ret = strength; 2657 goto config; 2658 } 2659 2660 ret = -EINVAL; 2661 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2662 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2663 ret = i; 2664 break; 2665 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2666 ret = rockchip_perpin_drv_list[drv_type][i]; 2667 break; 2668 } 2669 } 2670 2671 if (ret < 0) { 2672 dev_err(dev, "unsupported driver strength %d\n", strength); 2673 return ret; 2674 } 2675 2676 switch (drv_type) { 2677 case DRV_TYPE_IO_1V8_3V0_AUTO: 2678 case DRV_TYPE_IO_3V3_ONLY: 2679 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2680 switch (bit) { 2681 case 0 ... 12: 2682 /* regular case, nothing to do */ 2683 break; 2684 case 15: 2685 /* 2686 * drive-strength offset is special, as it is spread 2687 * over 2 registers, the bit data[15] contains bit 0 2688 * of the value while temp[1:0] contains bits 2 and 1 2689 */ 2690 data = (ret & 0x1) << 15; 2691 temp = (ret >> 0x1) & 0x3; 2692 2693 rmask = BIT(15) | BIT(31); 2694 data |= BIT(31); 2695 ret = regmap_update_bits(regmap, reg, rmask, data); 2696 if (ret) 2697 return ret; 2698 2699 rmask = 0x3 | (0x3 << 16); 2700 temp |= (0x3 << 16); 2701 reg += 0x4; 2702 ret = regmap_update_bits(regmap, reg, rmask, temp); 2703 2704 return ret; 2705 case 18 ... 21: 2706 /* setting fully enclosed in the second register */ 2707 reg += 4; 2708 bit -= 16; 2709 break; 2710 default: 2711 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 2712 bit, drv_type); 2713 return -EINVAL; 2714 } 2715 break; 2716 case DRV_TYPE_IO_DEFAULT: 2717 case DRV_TYPE_IO_1V8_OR_3V0: 2718 case DRV_TYPE_IO_1V8_ONLY: 2719 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2720 break; 2721 default: 2722 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 2723 return -EINVAL; 2724 } 2725 2726 config: 2727 /* enable the write to the equivalent lower bits */ 2728 data = ((1 << rmask_bits) - 1) << (bit + 16); 2729 rmask = data | (data >> 16); 2730 data |= (ret << bit); 2731 2732 ret = regmap_update_bits(regmap, reg, rmask, data); 2733 2734 return ret; 2735 } 2736 2737 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2738 { 2739 PIN_CONFIG_BIAS_DISABLE, 2740 PIN_CONFIG_BIAS_PULL_UP, 2741 PIN_CONFIG_BIAS_PULL_DOWN, 2742 PIN_CONFIG_BIAS_BUS_HOLD 2743 }, 2744 { 2745 PIN_CONFIG_BIAS_DISABLE, 2746 PIN_CONFIG_BIAS_PULL_DOWN, 2747 PIN_CONFIG_BIAS_DISABLE, 2748 PIN_CONFIG_BIAS_PULL_UP 2749 }, 2750 }; 2751 2752 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 2753 { 2754 struct rockchip_pinctrl *info = bank->drvdata; 2755 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2756 struct device *dev = info->dev; 2757 struct regmap *regmap; 2758 int reg, ret, pull_type; 2759 u8 bit; 2760 u32 data; 2761 2762 /* rk3066b does support any pulls */ 2763 if (ctrl->type == RK3066B) 2764 return PIN_CONFIG_BIAS_DISABLE; 2765 2766 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2767 if (ret) 2768 return ret; 2769 2770 ret = regmap_read(regmap, reg, &data); 2771 if (ret) 2772 return ret; 2773 2774 switch (ctrl->type) { 2775 case RK2928: 2776 case RK3128: 2777 return !(data & BIT(bit)) 2778 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 2779 : PIN_CONFIG_BIAS_DISABLE; 2780 case PX30: 2781 case RV1108: 2782 case RK3188: 2783 case RK3288: 2784 case RK3308: 2785 case RK3328: 2786 case RK3368: 2787 case RK3399: 2788 case RK3562: 2789 case RK3568: 2790 case RK3576: 2791 case RK3588: 2792 pull_type = bank->pull_type[pin_num / 8]; 2793 data >>= bit; 2794 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 2795 /* 2796 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, 2797 * where that pull up value becomes 3. 2798 */ 2799 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 2800 if (data == 3) 2801 data = 1; 2802 } 2803 2804 return rockchip_pull_list[pull_type][data]; 2805 default: 2806 dev_err(dev, "unsupported pinctrl type\n"); 2807 return -EINVAL; 2808 }; 2809 } 2810 2811 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2812 int pin_num, int pull) 2813 { 2814 struct rockchip_pinctrl *info = bank->drvdata; 2815 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2816 struct device *dev = info->dev; 2817 struct regmap *regmap; 2818 int reg, ret, i, pull_type; 2819 u8 bit; 2820 u32 data, rmask; 2821 2822 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); 2823 2824 /* rk3066b does support any pulls */ 2825 if (ctrl->type == RK3066B) 2826 return pull ? -EINVAL : 0; 2827 2828 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2829 if (ret) 2830 return ret; 2831 2832 switch (ctrl->type) { 2833 case RK2928: 2834 case RK3128: 2835 data = BIT(bit + 16); 2836 if (pull == PIN_CONFIG_BIAS_DISABLE) 2837 data |= BIT(bit); 2838 ret = regmap_write(regmap, reg, data); 2839 break; 2840 case PX30: 2841 case RV1108: 2842 case RV1126: 2843 case RK3188: 2844 case RK3288: 2845 case RK3308: 2846 case RK3328: 2847 case RK3368: 2848 case RK3399: 2849 case RK3562: 2850 case RK3568: 2851 case RK3576: 2852 case RK3588: 2853 pull_type = bank->pull_type[pin_num / 8]; 2854 ret = -EINVAL; 2855 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2856 i++) { 2857 if (rockchip_pull_list[pull_type][i] == pull) { 2858 ret = i; 2859 break; 2860 } 2861 } 2862 /* 2863 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, 2864 * where that pull up value becomes 3. 2865 */ 2866 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 2867 if (ret == 1) 2868 ret = 3; 2869 } 2870 2871 if (ret < 0) { 2872 dev_err(dev, "unsupported pull setting %d\n", pull); 2873 return ret; 2874 } 2875 2876 /* enable the write to the equivalent lower bits */ 2877 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2878 rmask = data | (data >> 16); 2879 data |= (ret << bit); 2880 2881 ret = regmap_update_bits(regmap, reg, rmask, data); 2882 break; 2883 default: 2884 dev_err(dev, "unsupported pinctrl type\n"); 2885 return -EINVAL; 2886 } 2887 2888 return ret; 2889 } 2890 2891 #define RK3328_SCHMITT_BITS_PER_PIN 1 2892 #define RK3328_SCHMITT_PINS_PER_REG 16 2893 #define RK3328_SCHMITT_BANK_STRIDE 8 2894 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2895 2896 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2897 int pin_num, 2898 struct regmap **regmap, 2899 int *reg, u8 *bit) 2900 { 2901 struct rockchip_pinctrl *info = bank->drvdata; 2902 2903 *regmap = info->regmap_base; 2904 *reg = RK3328_SCHMITT_GRF_OFFSET; 2905 2906 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2907 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2908 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2909 2910 return 0; 2911 } 2912 2913 #define RK3568_SCHMITT_BITS_PER_PIN 2 2914 #define RK3568_SCHMITT_PINS_PER_REG 8 2915 #define RK3568_SCHMITT_BANK_STRIDE 0x10 2916 #define RK3568_SCHMITT_GRF_OFFSET 0xc0 2917 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 2918 2919 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2920 int pin_num, 2921 struct regmap **regmap, 2922 int *reg, u8 *bit) 2923 { 2924 struct rockchip_pinctrl *info = bank->drvdata; 2925 2926 if (bank->bank_num == 0) { 2927 *regmap = info->regmap_pmu; 2928 *reg = RK3568_SCHMITT_PMUGRF_OFFSET; 2929 } else { 2930 *regmap = info->regmap_base; 2931 *reg = RK3568_SCHMITT_GRF_OFFSET; 2932 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; 2933 } 2934 2935 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); 2936 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; 2937 *bit *= RK3568_SCHMITT_BITS_PER_PIN; 2938 2939 return 0; 2940 } 2941 2942 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 2943 { 2944 struct rockchip_pinctrl *info = bank->drvdata; 2945 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2946 struct regmap *regmap; 2947 int reg, ret; 2948 u8 bit; 2949 u32 data; 2950 2951 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2952 if (ret) 2953 return ret; 2954 2955 ret = regmap_read(regmap, reg, &data); 2956 if (ret) 2957 return ret; 2958 2959 data >>= bit; 2960 switch (ctrl->type) { 2961 case RK3562: 2962 case RK3568: 2963 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); 2964 default: 2965 break; 2966 } 2967 2968 return data & 0x1; 2969 } 2970 2971 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2972 int pin_num, int enable) 2973 { 2974 struct rockchip_pinctrl *info = bank->drvdata; 2975 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2976 struct device *dev = info->dev; 2977 struct regmap *regmap; 2978 int reg, ret; 2979 u8 bit; 2980 u32 data, rmask; 2981 2982 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n", 2983 bank->bank_num, pin_num, enable); 2984 2985 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2986 if (ret) 2987 return ret; 2988 2989 /* enable the write to the equivalent lower bits */ 2990 switch (ctrl->type) { 2991 case RK3562: 2992 case RK3568: 2993 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); 2994 rmask = data | (data >> 16); 2995 data |= ((enable ? 0x2 : 0x1) << bit); 2996 break; 2997 default: 2998 data = BIT(bit + 16) | (enable << bit); 2999 rmask = BIT(bit + 16) | BIT(bit); 3000 break; 3001 } 3002 3003 return regmap_update_bits(regmap, reg, rmask, data); 3004 } 3005 3006 /* 3007 * Pinmux_ops handling 3008 */ 3009 3010 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 3011 { 3012 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3013 3014 return info->nfunctions; 3015 } 3016 3017 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 3018 unsigned selector) 3019 { 3020 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3021 3022 return info->functions[selector].name; 3023 } 3024 3025 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 3026 unsigned selector, const char * const **groups, 3027 unsigned * const num_groups) 3028 { 3029 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3030 3031 *groups = info->functions[selector].groups; 3032 *num_groups = info->functions[selector].ngroups; 3033 3034 return 0; 3035 } 3036 3037 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 3038 unsigned group) 3039 { 3040 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3041 const unsigned int *pins = info->groups[group].pins; 3042 const struct rockchip_pin_config *data = info->groups[group].data; 3043 struct device *dev = info->dev; 3044 struct rockchip_pin_bank *bank; 3045 int cnt, ret = 0; 3046 3047 dev_dbg(dev, "enable function %s group %s\n", 3048 info->functions[selector].name, info->groups[group].name); 3049 3050 /* 3051 * for each pin in the pin group selected, program the corresponding 3052 * pin function number in the config register. 3053 */ 3054 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 3055 bank = pin_to_bank(info, pins[cnt]); 3056 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 3057 data[cnt].func); 3058 if (ret) 3059 break; 3060 } 3061 3062 if (ret) { 3063 /* revert the already done pin settings */ 3064 for (cnt--; cnt >= 0; cnt--) { 3065 bank = pin_to_bank(info, pins[cnt]); 3066 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 3067 } 3068 3069 return ret; 3070 } 3071 3072 return 0; 3073 } 3074 3075 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 3076 struct pinctrl_gpio_range *range, 3077 unsigned offset, 3078 bool input) 3079 { 3080 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3081 struct rockchip_pin_bank *bank; 3082 3083 bank = pin_to_bank(info, offset); 3084 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO); 3085 } 3086 3087 static const struct pinmux_ops rockchip_pmx_ops = { 3088 .get_functions_count = rockchip_pmx_get_funcs_count, 3089 .get_function_name = rockchip_pmx_get_func_name, 3090 .get_function_groups = rockchip_pmx_get_groups, 3091 .set_mux = rockchip_pmx_set, 3092 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 3093 }; 3094 3095 /* 3096 * Pinconf_ops handling 3097 */ 3098 3099 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 3100 enum pin_config_param pull) 3101 { 3102 switch (ctrl->type) { 3103 case RK2928: 3104 case RK3128: 3105 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 3106 pull == PIN_CONFIG_BIAS_DISABLE); 3107 case RK3066B: 3108 return pull ? false : true; 3109 case PX30: 3110 case RV1108: 3111 case RV1126: 3112 case RK3188: 3113 case RK3288: 3114 case RK3308: 3115 case RK3328: 3116 case RK3368: 3117 case RK3399: 3118 case RK3562: 3119 case RK3568: 3120 case RK3576: 3121 case RK3588: 3122 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 3123 } 3124 3125 return false; 3126 } 3127 3128 static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank, 3129 unsigned int pin, u32 param, u32 arg) 3130 { 3131 struct rockchip_pin_deferred *cfg; 3132 3133 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); 3134 if (!cfg) 3135 return -ENOMEM; 3136 3137 cfg->pin = pin; 3138 cfg->param = param; 3139 cfg->arg = arg; 3140 3141 list_add_tail(&cfg->head, &bank->deferred_pins); 3142 3143 return 0; 3144 } 3145 3146 /* set the pin config settings for a specified pin */ 3147 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 3148 unsigned long *configs, unsigned num_configs) 3149 { 3150 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3151 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 3152 struct gpio_chip *gpio = &bank->gpio_chip; 3153 enum pin_config_param param; 3154 u32 arg; 3155 int i; 3156 int rc; 3157 3158 for (i = 0; i < num_configs; i++) { 3159 param = pinconf_to_config_param(configs[i]); 3160 arg = pinconf_to_config_argument(configs[i]); 3161 3162 if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) { 3163 /* 3164 * Check for gpio driver not being probed yet. 3165 * The lock makes sure that either gpio-probe has completed 3166 * or the gpio driver hasn't probed yet. 3167 */ 3168 mutex_lock(&bank->deferred_lock); 3169 if (!gpio || !gpio->direction_output) { 3170 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param, 3171 arg); 3172 mutex_unlock(&bank->deferred_lock); 3173 if (rc) 3174 return rc; 3175 3176 break; 3177 } 3178 mutex_unlock(&bank->deferred_lock); 3179 } 3180 3181 switch (param) { 3182 case PIN_CONFIG_BIAS_DISABLE: 3183 rc = rockchip_set_pull(bank, pin - bank->pin_base, 3184 param); 3185 if (rc) 3186 return rc; 3187 break; 3188 case PIN_CONFIG_BIAS_PULL_UP: 3189 case PIN_CONFIG_BIAS_PULL_DOWN: 3190 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 3191 case PIN_CONFIG_BIAS_BUS_HOLD: 3192 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 3193 return -ENOTSUPP; 3194 3195 if (!arg) 3196 return -EINVAL; 3197 3198 rc = rockchip_set_pull(bank, pin - bank->pin_base, 3199 param); 3200 if (rc) 3201 return rc; 3202 break; 3203 case PIN_CONFIG_OUTPUT: 3204 rc = rockchip_set_mux(bank, pin - bank->pin_base, 3205 RK_FUNC_GPIO); 3206 if (rc != RK_FUNC_GPIO) 3207 return -EINVAL; 3208 3209 rc = gpio->direction_output(gpio, pin - bank->pin_base, 3210 arg); 3211 if (rc) 3212 return rc; 3213 break; 3214 case PIN_CONFIG_INPUT_ENABLE: 3215 rc = rockchip_set_mux(bank, pin - bank->pin_base, 3216 RK_FUNC_GPIO); 3217 if (rc != RK_FUNC_GPIO) 3218 return -EINVAL; 3219 3220 rc = gpio->direction_input(gpio, pin - bank->pin_base); 3221 if (rc) 3222 return rc; 3223 break; 3224 case PIN_CONFIG_DRIVE_STRENGTH: 3225 /* rk3288 is the first with per-pin drive-strength */ 3226 if (!info->ctrl->drv_calc_reg) 3227 return -ENOTSUPP; 3228 3229 rc = rockchip_set_drive_perpin(bank, 3230 pin - bank->pin_base, arg); 3231 if (rc < 0) 3232 return rc; 3233 break; 3234 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3235 if (!info->ctrl->schmitt_calc_reg) 3236 return -ENOTSUPP; 3237 3238 rc = rockchip_set_schmitt(bank, 3239 pin - bank->pin_base, arg); 3240 if (rc < 0) 3241 return rc; 3242 break; 3243 default: 3244 return -ENOTSUPP; 3245 break; 3246 } 3247 } /* for each config */ 3248 3249 return 0; 3250 } 3251 3252 /* get the pin config settings for a specified pin */ 3253 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 3254 unsigned long *config) 3255 { 3256 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3257 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 3258 struct gpio_chip *gpio = &bank->gpio_chip; 3259 enum pin_config_param param = pinconf_to_config_param(*config); 3260 u16 arg; 3261 int rc; 3262 3263 switch (param) { 3264 case PIN_CONFIG_BIAS_DISABLE: 3265 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 3266 return -EINVAL; 3267 3268 arg = 0; 3269 break; 3270 case PIN_CONFIG_BIAS_PULL_UP: 3271 case PIN_CONFIG_BIAS_PULL_DOWN: 3272 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 3273 case PIN_CONFIG_BIAS_BUS_HOLD: 3274 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 3275 return -ENOTSUPP; 3276 3277 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 3278 return -EINVAL; 3279 3280 arg = 1; 3281 break; 3282 case PIN_CONFIG_OUTPUT: 3283 rc = rockchip_get_mux(bank, pin - bank->pin_base); 3284 if (rc != RK_FUNC_GPIO) 3285 return -EINVAL; 3286 3287 if (!gpio || !gpio->get) { 3288 arg = 0; 3289 break; 3290 } 3291 3292 rc = gpio->get(gpio, pin - bank->pin_base); 3293 if (rc < 0) 3294 return rc; 3295 3296 arg = rc ? 1 : 0; 3297 break; 3298 case PIN_CONFIG_DRIVE_STRENGTH: 3299 /* rk3288 is the first with per-pin drive-strength */ 3300 if (!info->ctrl->drv_calc_reg) 3301 return -ENOTSUPP; 3302 3303 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 3304 if (rc < 0) 3305 return rc; 3306 3307 arg = rc; 3308 break; 3309 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3310 if (!info->ctrl->schmitt_calc_reg) 3311 return -ENOTSUPP; 3312 3313 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 3314 if (rc < 0) 3315 return rc; 3316 3317 arg = rc; 3318 break; 3319 default: 3320 return -ENOTSUPP; 3321 break; 3322 } 3323 3324 *config = pinconf_to_config_packed(param, arg); 3325 3326 return 0; 3327 } 3328 3329 static const struct pinconf_ops rockchip_pinconf_ops = { 3330 .pin_config_get = rockchip_pinconf_get, 3331 .pin_config_set = rockchip_pinconf_set, 3332 .is_generic = true, 3333 }; 3334 3335 static const struct of_device_id rockchip_bank_match[] = { 3336 { .compatible = "rockchip,gpio-bank" }, 3337 { .compatible = "rockchip,rk3188-gpio-bank0" }, 3338 {}, 3339 }; 3340 3341 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 3342 struct device_node *np) 3343 { 3344 struct device_node *child; 3345 3346 for_each_child_of_node(np, child) { 3347 if (of_match_node(rockchip_bank_match, child)) 3348 continue; 3349 3350 info->nfunctions++; 3351 info->ngroups += of_get_child_count(child); 3352 } 3353 } 3354 3355 static int rockchip_pinctrl_parse_groups(struct device_node *np, 3356 struct rockchip_pin_group *grp, 3357 struct rockchip_pinctrl *info, 3358 u32 index) 3359 { 3360 struct device *dev = info->dev; 3361 struct rockchip_pin_bank *bank; 3362 int size; 3363 const __be32 *list; 3364 int num; 3365 int i, j; 3366 int ret; 3367 3368 dev_dbg(dev, "group(%d): %pOFn\n", index, np); 3369 3370 /* Initialise group */ 3371 grp->name = np->name; 3372 3373 /* 3374 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 3375 * do sanity check and calculate pins number 3376 */ 3377 list = of_get_property(np, "rockchip,pins", &size); 3378 /* we do not check return since it's safe node passed down */ 3379 size /= sizeof(*list); 3380 if (!size || size % 4) 3381 return dev_err_probe(dev, -EINVAL, 3382 "%pOF: rockchip,pins: expected one or more of <bank pin mux CONFIG>, got %d args instead\n", 3383 np, size); 3384 3385 grp->npins = size / 4; 3386 3387 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); 3388 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL); 3389 if (!grp->pins || !grp->data) 3390 return -ENOMEM; 3391 3392 for (i = 0, j = 0; i < size; i += 4, j++) { 3393 const __be32 *phandle; 3394 struct device_node *np_config; 3395 3396 num = be32_to_cpu(*list++); 3397 bank = bank_num_to_bank(info, num); 3398 if (IS_ERR(bank)) 3399 return PTR_ERR(bank); 3400 3401 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 3402 grp->data[j].func = be32_to_cpu(*list++); 3403 3404 phandle = list++; 3405 if (!phandle) 3406 return -EINVAL; 3407 3408 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 3409 ret = pinconf_generic_parse_dt_config(np_config, NULL, 3410 &grp->data[j].configs, &grp->data[j].nconfigs); 3411 of_node_put(np_config); 3412 if (ret) 3413 return ret; 3414 } 3415 3416 return 0; 3417 } 3418 3419 static int rockchip_pinctrl_parse_functions(struct device_node *np, 3420 struct rockchip_pinctrl *info, 3421 u32 index) 3422 { 3423 struct device *dev = info->dev; 3424 struct rockchip_pmx_func *func; 3425 struct rockchip_pin_group *grp; 3426 int ret; 3427 static u32 grp_index; 3428 u32 i = 0; 3429 3430 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np); 3431 3432 func = &info->functions[index]; 3433 3434 /* Initialise function */ 3435 func->name = np->name; 3436 func->ngroups = of_get_child_count(np); 3437 if (func->ngroups <= 0) 3438 return 0; 3439 3440 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 3441 if (!func->groups) 3442 return -ENOMEM; 3443 3444 for_each_child_of_node_scoped(np, child) { 3445 func->groups[i] = child->name; 3446 grp = &info->groups[grp_index++]; 3447 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 3448 if (ret) 3449 return ret; 3450 } 3451 3452 return 0; 3453 } 3454 3455 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 3456 struct rockchip_pinctrl *info) 3457 { 3458 struct device *dev = &pdev->dev; 3459 struct device_node *np = dev->of_node; 3460 int ret; 3461 int i; 3462 3463 rockchip_pinctrl_child_count(info, np); 3464 3465 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); 3466 dev_dbg(dev, "ngroups = %d\n", info->ngroups); 3467 3468 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 3469 if (!info->functions) 3470 return -ENOMEM; 3471 3472 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 3473 if (!info->groups) 3474 return -ENOMEM; 3475 3476 i = 0; 3477 3478 for_each_child_of_node_scoped(np, child) { 3479 if (of_match_node(rockchip_bank_match, child)) 3480 continue; 3481 3482 ret = rockchip_pinctrl_parse_functions(child, info, i++); 3483 if (ret) { 3484 dev_err(dev, "failed to parse function\n"); 3485 return ret; 3486 } 3487 } 3488 3489 return 0; 3490 } 3491 3492 static int rockchip_pinctrl_register(struct platform_device *pdev, 3493 struct rockchip_pinctrl *info) 3494 { 3495 struct pinctrl_desc *ctrldesc = &info->pctl; 3496 struct pinctrl_pin_desc *pindesc, *pdesc; 3497 struct rockchip_pin_bank *pin_bank; 3498 struct device *dev = &pdev->dev; 3499 char **pin_names; 3500 int pin, bank, ret; 3501 int k; 3502 3503 ctrldesc->name = "rockchip-pinctrl"; 3504 ctrldesc->owner = THIS_MODULE; 3505 ctrldesc->pctlops = &rockchip_pctrl_ops; 3506 ctrldesc->pmxops = &rockchip_pmx_ops; 3507 ctrldesc->confops = &rockchip_pinconf_ops; 3508 3509 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL); 3510 if (!pindesc) 3511 return -ENOMEM; 3512 3513 ctrldesc->pins = pindesc; 3514 ctrldesc->npins = info->ctrl->nr_pins; 3515 3516 pdesc = pindesc; 3517 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { 3518 pin_bank = &info->ctrl->pin_banks[bank]; 3519 3520 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins); 3521 if (IS_ERR(pin_names)) 3522 return PTR_ERR(pin_names); 3523 3524 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 3525 pdesc->number = k; 3526 pdesc->name = pin_names[pin]; 3527 pdesc++; 3528 } 3529 3530 INIT_LIST_HEAD(&pin_bank->deferred_pins); 3531 mutex_init(&pin_bank->deferred_lock); 3532 } 3533 3534 ret = rockchip_pinctrl_parse_dt(pdev, info); 3535 if (ret) 3536 return ret; 3537 3538 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); 3539 if (IS_ERR(info->pctl_dev)) 3540 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); 3541 3542 return 0; 3543 } 3544 3545 static const struct of_device_id rockchip_pinctrl_dt_match[]; 3546 3547 /* retrieve the soc specific data */ 3548 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 3549 struct rockchip_pinctrl *d, 3550 struct platform_device *pdev) 3551 { 3552 struct device *dev = &pdev->dev; 3553 struct device_node *node = dev->of_node; 3554 const struct of_device_id *match; 3555 struct rockchip_pin_ctrl *ctrl; 3556 struct rockchip_pin_bank *bank; 3557 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 3558 3559 match = of_match_node(rockchip_pinctrl_dt_match, node); 3560 ctrl = (struct rockchip_pin_ctrl *)match->data; 3561 3562 grf_offs = ctrl->grf_mux_offset; 3563 pmu_offs = ctrl->pmu_mux_offset; 3564 drv_pmu_offs = ctrl->pmu_drv_offset; 3565 drv_grf_offs = ctrl->grf_drv_offset; 3566 bank = ctrl->pin_banks; 3567 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3568 int bank_pins = 0; 3569 3570 raw_spin_lock_init(&bank->slock); 3571 bank->drvdata = d; 3572 bank->pin_base = ctrl->nr_pins; 3573 ctrl->nr_pins += bank->nr_pins; 3574 3575 /* calculate iomux and drv offsets */ 3576 for (j = 0; j < 4; j++) { 3577 struct rockchip_iomux *iom = &bank->iomux[j]; 3578 struct rockchip_drv *drv = &bank->drv[j]; 3579 int inc; 3580 3581 if (bank_pins >= bank->nr_pins) 3582 break; 3583 3584 /* preset iomux offset value, set new start value */ 3585 if (iom->offset >= 0) { 3586 if ((iom->type & IOMUX_SOURCE_PMU) || 3587 (iom->type & IOMUX_L_SOURCE_PMU)) 3588 pmu_offs = iom->offset; 3589 else 3590 grf_offs = iom->offset; 3591 } else { /* set current iomux offset */ 3592 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || 3593 (iom->type & IOMUX_L_SOURCE_PMU)) ? 3594 pmu_offs : grf_offs; 3595 } 3596 3597 /* preset drv offset value, set new start value */ 3598 if (drv->offset >= 0) { 3599 if (iom->type & IOMUX_SOURCE_PMU) 3600 drv_pmu_offs = drv->offset; 3601 else 3602 drv_grf_offs = drv->offset; 3603 } else { /* set current drv offset */ 3604 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3605 drv_pmu_offs : drv_grf_offs; 3606 } 3607 3608 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3609 i, j, iom->offset, drv->offset); 3610 3611 /* 3612 * Increase offset according to iomux width. 3613 * 4bit iomux'es are spread over two registers. 3614 */ 3615 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3616 IOMUX_WIDTH_3BIT | 3617 IOMUX_WIDTH_2BIT)) ? 8 : 4; 3618 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 3619 pmu_offs += inc; 3620 else 3621 grf_offs += inc; 3622 3623 /* 3624 * Increase offset according to drv width. 3625 * 3bit drive-strenth'es are spread over two registers. 3626 */ 3627 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3628 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3629 inc = 8; 3630 else 3631 inc = 4; 3632 3633 if (iom->type & IOMUX_SOURCE_PMU) 3634 drv_pmu_offs += inc; 3635 else 3636 drv_grf_offs += inc; 3637 3638 bank_pins += 8; 3639 } 3640 3641 /* calculate the per-bank recalced_mask */ 3642 for (j = 0; j < ctrl->niomux_recalced; j++) { 3643 int pin = 0; 3644 3645 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3646 pin = ctrl->iomux_recalced[j].pin; 3647 bank->recalced_mask |= BIT(pin); 3648 } 3649 } 3650 3651 /* calculate the per-bank route_mask */ 3652 for (j = 0; j < ctrl->niomux_routes; j++) { 3653 int pin = 0; 3654 3655 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3656 pin = ctrl->iomux_routes[j].pin; 3657 bank->route_mask |= BIT(pin); 3658 } 3659 } 3660 } 3661 3662 return ctrl; 3663 } 3664 3665 #define RK3288_GRF_GPIO6C_IOMUX 0x64 3666 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 3667 3668 static u32 rk3288_grf_gpio6c_iomux; 3669 3670 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 3671 { 3672 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3673 int ret = pinctrl_force_sleep(info->pctl_dev); 3674 3675 if (ret) 3676 return ret; 3677 3678 /* 3679 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 3680 * the setting here, and restore it at resume. 3681 */ 3682 if (info->ctrl->type == RK3288) { 3683 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3684 &rk3288_grf_gpio6c_iomux); 3685 if (ret) { 3686 pinctrl_force_default(info->pctl_dev); 3687 return ret; 3688 } 3689 } 3690 3691 return 0; 3692 } 3693 3694 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 3695 { 3696 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3697 int ret; 3698 3699 if (info->ctrl->type == RK3288) { 3700 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3701 rk3288_grf_gpio6c_iomux | 3702 GPIO6C6_SEL_WRITE_ENABLE); 3703 if (ret) 3704 return ret; 3705 } 3706 3707 return pinctrl_force_default(info->pctl_dev); 3708 } 3709 3710 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 3711 rockchip_pinctrl_resume); 3712 3713 static int rockchip_pinctrl_probe(struct platform_device *pdev) 3714 { 3715 struct rockchip_pinctrl *info; 3716 struct device *dev = &pdev->dev; 3717 struct device_node *np = dev->of_node, *node; 3718 struct rockchip_pin_ctrl *ctrl; 3719 struct resource *res; 3720 void __iomem *base; 3721 int ret; 3722 3723 if (!dev->of_node) 3724 return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); 3725 3726 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 3727 if (!info) 3728 return -ENOMEM; 3729 3730 info->dev = dev; 3731 3732 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 3733 if (!ctrl) 3734 return dev_err_probe(dev, -EINVAL, "driver data not available\n"); 3735 info->ctrl = ctrl; 3736 3737 node = of_parse_phandle(np, "rockchip,grf", 0); 3738 if (node) { 3739 info->regmap_base = syscon_node_to_regmap(node); 3740 of_node_put(node); 3741 if (IS_ERR(info->regmap_base)) 3742 return PTR_ERR(info->regmap_base); 3743 } else { 3744 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 3745 if (IS_ERR(base)) 3746 return PTR_ERR(base); 3747 3748 rockchip_regmap_config.max_register = resource_size(res) - 4; 3749 rockchip_regmap_config.name = "rockchip,pinctrl"; 3750 info->regmap_base = 3751 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 3752 3753 /* to check for the old dt-bindings */ 3754 info->reg_size = resource_size(res); 3755 3756 /* Honor the old binding, with pull registers as 2nd resource */ 3757 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 3758 base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); 3759 if (IS_ERR(base)) 3760 return PTR_ERR(base); 3761 3762 rockchip_regmap_config.max_register = resource_size(res) - 4; 3763 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 3764 info->regmap_pull = 3765 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 3766 } 3767 } 3768 3769 /* try to find the optional reference to the pmu syscon */ 3770 node = of_parse_phandle(np, "rockchip,pmu", 0); 3771 if (node) { 3772 info->regmap_pmu = syscon_node_to_regmap(node); 3773 of_node_put(node); 3774 if (IS_ERR(info->regmap_pmu)) 3775 return PTR_ERR(info->regmap_pmu); 3776 } 3777 3778 ret = rockchip_pinctrl_register(pdev, info); 3779 if (ret) 3780 return ret; 3781 3782 platform_set_drvdata(pdev, info); 3783 3784 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 3785 if (ret) 3786 return dev_err_probe(dev, ret, "failed to register gpio device\n"); 3787 3788 return 0; 3789 } 3790 3791 static void rockchip_pinctrl_remove(struct platform_device *pdev) 3792 { 3793 struct rockchip_pinctrl *info = platform_get_drvdata(pdev); 3794 struct rockchip_pin_bank *bank; 3795 struct rockchip_pin_deferred *cfg; 3796 int i; 3797 3798 of_platform_depopulate(&pdev->dev); 3799 3800 for (i = 0; i < info->ctrl->nr_banks; i++) { 3801 bank = &info->ctrl->pin_banks[i]; 3802 3803 mutex_lock(&bank->deferred_lock); 3804 while (!list_empty(&bank->deferred_pins)) { 3805 cfg = list_first_entry(&bank->deferred_pins, 3806 struct rockchip_pin_deferred, head); 3807 list_del(&cfg->head); 3808 kfree(cfg); 3809 } 3810 mutex_unlock(&bank->deferred_lock); 3811 } 3812 } 3813 3814 static struct rockchip_pin_bank px30_pin_banks[] = { 3815 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3816 IOMUX_SOURCE_PMU, 3817 IOMUX_SOURCE_PMU, 3818 IOMUX_SOURCE_PMU 3819 ), 3820 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3821 IOMUX_WIDTH_4BIT, 3822 IOMUX_WIDTH_4BIT, 3823 IOMUX_WIDTH_4BIT 3824 ), 3825 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3826 IOMUX_WIDTH_4BIT, 3827 IOMUX_WIDTH_4BIT, 3828 IOMUX_WIDTH_4BIT 3829 ), 3830 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3831 IOMUX_WIDTH_4BIT, 3832 IOMUX_WIDTH_4BIT, 3833 IOMUX_WIDTH_4BIT 3834 ), 3835 }; 3836 3837 static struct rockchip_pin_ctrl px30_pin_ctrl = { 3838 .pin_banks = px30_pin_banks, 3839 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3840 .label = "PX30-GPIO", 3841 .type = PX30, 3842 .grf_mux_offset = 0x0, 3843 .pmu_mux_offset = 0x0, 3844 .iomux_routes = px30_mux_route_data, 3845 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3846 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3847 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3848 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3849 }; 3850 3851 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3852 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3853 IOMUX_SOURCE_PMU, 3854 IOMUX_SOURCE_PMU, 3855 IOMUX_SOURCE_PMU), 3856 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3857 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3858 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3859 }; 3860 3861 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3862 .pin_banks = rv1108_pin_banks, 3863 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3864 .label = "RV1108-GPIO", 3865 .type = RV1108, 3866 .grf_mux_offset = 0x10, 3867 .pmu_mux_offset = 0x0, 3868 .iomux_recalced = rv1108_mux_recalced_data, 3869 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3870 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3871 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3872 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3873 }; 3874 3875 static struct rockchip_pin_bank rv1126_pin_banks[] = { 3876 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3877 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3878 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3879 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, 3880 IOMUX_WIDTH_4BIT), 3881 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 3882 IOMUX_WIDTH_4BIT, 3883 IOMUX_WIDTH_4BIT, 3884 IOMUX_WIDTH_4BIT, 3885 IOMUX_WIDTH_4BIT, 3886 0x10010, 0x10018, 0x10020, 0x10028), 3887 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3888 IOMUX_WIDTH_4BIT, 3889 IOMUX_WIDTH_4BIT, 3890 IOMUX_WIDTH_4BIT, 3891 IOMUX_WIDTH_4BIT), 3892 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3893 IOMUX_WIDTH_4BIT, 3894 IOMUX_WIDTH_4BIT, 3895 IOMUX_WIDTH_4BIT, 3896 IOMUX_WIDTH_4BIT), 3897 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", 3898 IOMUX_WIDTH_4BIT, 0, 0, 0), 3899 }; 3900 3901 static struct rockchip_pin_ctrl rv1126_pin_ctrl = { 3902 .pin_banks = rv1126_pin_banks, 3903 .nr_banks = ARRAY_SIZE(rv1126_pin_banks), 3904 .label = "RV1126-GPIO", 3905 .type = RV1126, 3906 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ 3907 .pmu_mux_offset = 0x0, 3908 .iomux_routes = rv1126_mux_route_data, 3909 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data), 3910 .iomux_recalced = rv1126_mux_recalced_data, 3911 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), 3912 .pull_calc_reg = rv1126_calc_pull_reg_and_bit, 3913 .drv_calc_reg = rv1126_calc_drv_reg_and_bit, 3914 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit, 3915 }; 3916 3917 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3918 PIN_BANK(0, 32, "gpio0"), 3919 PIN_BANK(1, 32, "gpio1"), 3920 PIN_BANK(2, 32, "gpio2"), 3921 PIN_BANK(3, 32, "gpio3"), 3922 }; 3923 3924 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3925 .pin_banks = rk2928_pin_banks, 3926 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3927 .label = "RK2928-GPIO", 3928 .type = RK2928, 3929 .grf_mux_offset = 0xa8, 3930 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3931 }; 3932 3933 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3934 PIN_BANK(0, 32, "gpio0"), 3935 PIN_BANK(1, 32, "gpio1"), 3936 PIN_BANK(2, 32, "gpio2"), 3937 }; 3938 3939 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3940 .pin_banks = rk3036_pin_banks, 3941 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3942 .label = "RK3036-GPIO", 3943 .type = RK2928, 3944 .grf_mux_offset = 0xa8, 3945 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3946 }; 3947 3948 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3949 PIN_BANK(0, 32, "gpio0"), 3950 PIN_BANK(1, 32, "gpio1"), 3951 PIN_BANK(2, 32, "gpio2"), 3952 PIN_BANK(3, 32, "gpio3"), 3953 PIN_BANK(4, 32, "gpio4"), 3954 PIN_BANK(6, 16, "gpio6"), 3955 }; 3956 3957 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3958 .pin_banks = rk3066a_pin_banks, 3959 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3960 .label = "RK3066a-GPIO", 3961 .type = RK2928, 3962 .grf_mux_offset = 0xa8, 3963 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3964 }; 3965 3966 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3967 PIN_BANK(0, 32, "gpio0"), 3968 PIN_BANK(1, 32, "gpio1"), 3969 PIN_BANK(2, 32, "gpio2"), 3970 PIN_BANK(3, 32, "gpio3"), 3971 }; 3972 3973 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3974 .pin_banks = rk3066b_pin_banks, 3975 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3976 .label = "RK3066b-GPIO", 3977 .type = RK3066B, 3978 .grf_mux_offset = 0x60, 3979 }; 3980 3981 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3982 PIN_BANK(0, 32, "gpio0"), 3983 PIN_BANK(1, 32, "gpio1"), 3984 PIN_BANK(2, 32, "gpio2"), 3985 PIN_BANK(3, 32, "gpio3"), 3986 }; 3987 3988 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3989 .pin_banks = rk3128_pin_banks, 3990 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3991 .label = "RK3128-GPIO", 3992 .type = RK3128, 3993 .grf_mux_offset = 0xa8, 3994 .iomux_recalced = rk3128_mux_recalced_data, 3995 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3996 .iomux_routes = rk3128_mux_route_data, 3997 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3998 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3999 }; 4000 4001 static struct rockchip_pin_bank rk3188_pin_banks[] = { 4002 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 4003 PIN_BANK(1, 32, "gpio1"), 4004 PIN_BANK(2, 32, "gpio2"), 4005 PIN_BANK(3, 32, "gpio3"), 4006 }; 4007 4008 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 4009 .pin_banks = rk3188_pin_banks, 4010 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 4011 .label = "RK3188-GPIO", 4012 .type = RK3188, 4013 .grf_mux_offset = 0x60, 4014 .iomux_routes = rk3188_mux_route_data, 4015 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), 4016 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 4017 }; 4018 4019 static struct rockchip_pin_bank rk3228_pin_banks[] = { 4020 PIN_BANK(0, 32, "gpio0"), 4021 PIN_BANK(1, 32, "gpio1"), 4022 PIN_BANK(2, 32, "gpio2"), 4023 PIN_BANK(3, 32, "gpio3"), 4024 }; 4025 4026 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 4027 .pin_banks = rk3228_pin_banks, 4028 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 4029 .label = "RK3228-GPIO", 4030 .type = RK3288, 4031 .grf_mux_offset = 0x0, 4032 .iomux_routes = rk3228_mux_route_data, 4033 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 4034 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 4035 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 4036 }; 4037 4038 static struct rockchip_pin_bank rk3288_pin_banks[] = { 4039 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 4040 IOMUX_SOURCE_PMU, 4041 IOMUX_SOURCE_PMU, 4042 IOMUX_UNROUTED 4043 ), 4044 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 4045 IOMUX_UNROUTED, 4046 IOMUX_UNROUTED, 4047 0 4048 ), 4049 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 4050 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 4051 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 4052 IOMUX_WIDTH_4BIT, 4053 0, 4054 0 4055 ), 4056 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 4057 0, 4058 0, 4059 IOMUX_UNROUTED 4060 ), 4061 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 4062 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 4063 0, 4064 IOMUX_WIDTH_4BIT, 4065 IOMUX_UNROUTED 4066 ), 4067 PIN_BANK(8, 16, "gpio8"), 4068 }; 4069 4070 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 4071 .pin_banks = rk3288_pin_banks, 4072 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 4073 .label = "RK3288-GPIO", 4074 .type = RK3288, 4075 .grf_mux_offset = 0x0, 4076 .pmu_mux_offset = 0x84, 4077 .iomux_routes = rk3288_mux_route_data, 4078 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 4079 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 4080 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 4081 }; 4082 4083 static struct rockchip_pin_bank rk3308_pin_banks[] = { 4084 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, 4085 IOMUX_WIDTH_2BIT, 4086 IOMUX_WIDTH_2BIT, 4087 IOMUX_WIDTH_2BIT), 4088 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, 4089 IOMUX_WIDTH_2BIT, 4090 IOMUX_WIDTH_2BIT, 4091 IOMUX_WIDTH_2BIT), 4092 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, 4093 IOMUX_WIDTH_2BIT, 4094 IOMUX_WIDTH_2BIT, 4095 IOMUX_WIDTH_2BIT), 4096 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, 4097 IOMUX_WIDTH_2BIT, 4098 IOMUX_WIDTH_2BIT, 4099 IOMUX_WIDTH_2BIT), 4100 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, 4101 IOMUX_WIDTH_2BIT, 4102 IOMUX_WIDTH_2BIT, 4103 IOMUX_WIDTH_2BIT), 4104 }; 4105 4106 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 4107 .pin_banks = rk3308_pin_banks, 4108 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 4109 .label = "RK3308-GPIO", 4110 .type = RK3308, 4111 .grf_mux_offset = 0x0, 4112 .iomux_recalced = rk3308_mux_recalced_data, 4113 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 4114 .iomux_routes = rk3308_mux_route_data, 4115 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 4116 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 4117 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 4118 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 4119 }; 4120 4121 static struct rockchip_pin_bank rk3328_pin_banks[] = { 4122 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 4123 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 4124 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 4125 IOMUX_WIDTH_2BIT, 4126 IOMUX_WIDTH_3BIT, 4127 0), 4128 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 4129 IOMUX_WIDTH_3BIT, 4130 IOMUX_WIDTH_3BIT, 4131 0, 4132 0), 4133 }; 4134 4135 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 4136 .pin_banks = rk3328_pin_banks, 4137 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 4138 .label = "RK3328-GPIO", 4139 .type = RK3328, 4140 .grf_mux_offset = 0x0, 4141 .iomux_recalced = rk3328_mux_recalced_data, 4142 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 4143 .iomux_routes = rk3328_mux_route_data, 4144 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 4145 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 4146 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 4147 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 4148 }; 4149 4150 static struct rockchip_pin_bank rk3368_pin_banks[] = { 4151 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 4152 IOMUX_SOURCE_PMU, 4153 IOMUX_SOURCE_PMU, 4154 IOMUX_SOURCE_PMU 4155 ), 4156 PIN_BANK(1, 32, "gpio1"), 4157 PIN_BANK(2, 32, "gpio2"), 4158 PIN_BANK(3, 32, "gpio3"), 4159 }; 4160 4161 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 4162 .pin_banks = rk3368_pin_banks, 4163 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 4164 .label = "RK3368-GPIO", 4165 .type = RK3368, 4166 .grf_mux_offset = 0x0, 4167 .pmu_mux_offset = 0x0, 4168 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 4169 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 4170 }; 4171 4172 static struct rockchip_pin_bank rk3399_pin_banks[] = { 4173 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 4174 IOMUX_SOURCE_PMU, 4175 IOMUX_SOURCE_PMU, 4176 IOMUX_SOURCE_PMU, 4177 IOMUX_SOURCE_PMU, 4178 DRV_TYPE_IO_1V8_ONLY, 4179 DRV_TYPE_IO_1V8_ONLY, 4180 DRV_TYPE_IO_DEFAULT, 4181 DRV_TYPE_IO_DEFAULT, 4182 0x80, 4183 0x88, 4184 -1, 4185 -1, 4186 PULL_TYPE_IO_1V8_ONLY, 4187 PULL_TYPE_IO_1V8_ONLY, 4188 PULL_TYPE_IO_DEFAULT, 4189 PULL_TYPE_IO_DEFAULT 4190 ), 4191 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 4192 IOMUX_SOURCE_PMU, 4193 IOMUX_SOURCE_PMU, 4194 IOMUX_SOURCE_PMU, 4195 DRV_TYPE_IO_1V8_OR_3V0, 4196 DRV_TYPE_IO_1V8_OR_3V0, 4197 DRV_TYPE_IO_1V8_OR_3V0, 4198 DRV_TYPE_IO_1V8_OR_3V0, 4199 0xa0, 4200 0xa8, 4201 0xb0, 4202 0xb8 4203 ), 4204 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 4205 DRV_TYPE_IO_1V8_OR_3V0, 4206 DRV_TYPE_IO_1V8_ONLY, 4207 DRV_TYPE_IO_1V8_ONLY, 4208 PULL_TYPE_IO_DEFAULT, 4209 PULL_TYPE_IO_DEFAULT, 4210 PULL_TYPE_IO_1V8_ONLY, 4211 PULL_TYPE_IO_1V8_ONLY 4212 ), 4213 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 4214 DRV_TYPE_IO_3V3_ONLY, 4215 DRV_TYPE_IO_3V3_ONLY, 4216 DRV_TYPE_IO_1V8_OR_3V0 4217 ), 4218 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 4219 DRV_TYPE_IO_1V8_3V0_AUTO, 4220 DRV_TYPE_IO_1V8_OR_3V0, 4221 DRV_TYPE_IO_1V8_OR_3V0 4222 ), 4223 }; 4224 4225 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 4226 .pin_banks = rk3399_pin_banks, 4227 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 4228 .label = "RK3399-GPIO", 4229 .type = RK3399, 4230 .grf_mux_offset = 0xe000, 4231 .pmu_mux_offset = 0x0, 4232 .grf_drv_offset = 0xe100, 4233 .pmu_drv_offset = 0x80, 4234 .iomux_routes = rk3399_mux_route_data, 4235 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 4236 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 4237 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 4238 }; 4239 4240 static struct rockchip_pin_bank rk3562_pin_banks[] = { 4241 PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", 4242 IOMUX_WIDTH_4BIT, 4243 IOMUX_WIDTH_4BIT, 4244 IOMUX_WIDTH_4BIT, 4245 IOMUX_WIDTH_4BIT, 4246 0x20000, 0x20008, 0x20010, 0x20018), 4247 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 4248 IOMUX_WIDTH_4BIT, 4249 IOMUX_WIDTH_4BIT, 4250 IOMUX_WIDTH_4BIT, 4251 IOMUX_WIDTH_4BIT, 4252 0, 0x08, 0x10, 0x18), 4253 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", 4254 IOMUX_WIDTH_4BIT, 4255 IOMUX_WIDTH_4BIT, 4256 IOMUX_WIDTH_4BIT, 4257 IOMUX_WIDTH_4BIT, 4258 0x20, 0, 0, 0), 4259 PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", 4260 IOMUX_WIDTH_4BIT, 4261 IOMUX_WIDTH_4BIT, 4262 IOMUX_WIDTH_4BIT, 4263 IOMUX_WIDTH_4BIT, 4264 0x10040, 0x10048, 0x10050, 0x10058), 4265 PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4", 4266 IOMUX_WIDTH_4BIT, 4267 IOMUX_WIDTH_4BIT, 4268 0, 4269 0, 4270 0x10060, 0x10068, 0, 0), 4271 }; 4272 4273 static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = { 4274 .pin_banks = rk3562_pin_banks, 4275 .nr_banks = ARRAY_SIZE(rk3562_pin_banks), 4276 .label = "RK3562-GPIO", 4277 .type = RK3562, 4278 .pull_calc_reg = rk3562_calc_pull_reg_and_bit, 4279 .drv_calc_reg = rk3562_calc_drv_reg_and_bit, 4280 .schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit, 4281 }; 4282 4283 static struct rockchip_pin_bank rk3568_pin_banks[] = { 4284 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 4285 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 4286 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 4287 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), 4288 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 4289 IOMUX_WIDTH_4BIT, 4290 IOMUX_WIDTH_4BIT, 4291 IOMUX_WIDTH_4BIT), 4292 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 4293 IOMUX_WIDTH_4BIT, 4294 IOMUX_WIDTH_4BIT, 4295 IOMUX_WIDTH_4BIT), 4296 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 4297 IOMUX_WIDTH_4BIT, 4298 IOMUX_WIDTH_4BIT, 4299 IOMUX_WIDTH_4BIT), 4300 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 4301 IOMUX_WIDTH_4BIT, 4302 IOMUX_WIDTH_4BIT, 4303 IOMUX_WIDTH_4BIT), 4304 }; 4305 4306 static struct rockchip_pin_ctrl rk3568_pin_ctrl = { 4307 .pin_banks = rk3568_pin_banks, 4308 .nr_banks = ARRAY_SIZE(rk3568_pin_banks), 4309 .label = "RK3568-GPIO", 4310 .type = RK3568, 4311 .grf_mux_offset = 0x0, 4312 .pmu_mux_offset = 0x0, 4313 .grf_drv_offset = 0x0200, 4314 .pmu_drv_offset = 0x0070, 4315 .iomux_routes = rk3568_mux_route_data, 4316 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), 4317 .pull_calc_reg = rk3568_calc_pull_reg_and_bit, 4318 .drv_calc_reg = rk3568_calc_drv_reg_and_bit, 4319 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit, 4320 }; 4321 4322 #define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3) \ 4323 PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL, \ 4324 IOMUX_WIDTH_4BIT, \ 4325 IOMUX_WIDTH_4BIT, \ 4326 IOMUX_WIDTH_4BIT, \ 4327 IOMUX_WIDTH_4BIT, \ 4328 OFFSET0, OFFSET1, \ 4329 OFFSET2, OFFSET3, \ 4330 PULL_TYPE_IO_1V8_ONLY, \ 4331 PULL_TYPE_IO_1V8_ONLY, \ 4332 PULL_TYPE_IO_1V8_ONLY, \ 4333 PULL_TYPE_IO_1V8_ONLY) 4334 4335 static struct rockchip_pin_bank rk3576_pin_banks[] = { 4336 RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C), 4337 RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038), 4338 RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058), 4339 RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078), 4340 RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398), 4341 }; 4342 4343 static struct rockchip_pin_ctrl rk3576_pin_ctrl __maybe_unused = { 4344 .pin_banks = rk3576_pin_banks, 4345 .nr_banks = ARRAY_SIZE(rk3576_pin_banks), 4346 .label = "RK3576-GPIO", 4347 .type = RK3576, 4348 .pull_calc_reg = rk3576_calc_pull_reg_and_bit, 4349 .drv_calc_reg = rk3576_calc_drv_reg_and_bit, 4350 .schmitt_calc_reg = rk3576_calc_schmitt_reg_and_bit, 4351 }; 4352 4353 static struct rockchip_pin_bank rk3588_pin_banks[] = { 4354 RK3588_PIN_BANK_FLAGS(0, 32, "gpio0", 4355 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 4356 RK3588_PIN_BANK_FLAGS(1, 32, "gpio1", 4357 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 4358 RK3588_PIN_BANK_FLAGS(2, 32, "gpio2", 4359 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 4360 RK3588_PIN_BANK_FLAGS(3, 32, "gpio3", 4361 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 4362 RK3588_PIN_BANK_FLAGS(4, 32, "gpio4", 4363 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 4364 }; 4365 4366 static struct rockchip_pin_ctrl rk3588_pin_ctrl = { 4367 .pin_banks = rk3588_pin_banks, 4368 .nr_banks = ARRAY_SIZE(rk3588_pin_banks), 4369 .label = "RK3588-GPIO", 4370 .type = RK3588, 4371 .pull_calc_reg = rk3588_calc_pull_reg_and_bit, 4372 .drv_calc_reg = rk3588_calc_drv_reg_and_bit, 4373 .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit, 4374 }; 4375 4376 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 4377 { .compatible = "rockchip,px30-pinctrl", 4378 .data = &px30_pin_ctrl }, 4379 { .compatible = "rockchip,rv1108-pinctrl", 4380 .data = &rv1108_pin_ctrl }, 4381 { .compatible = "rockchip,rv1126-pinctrl", 4382 .data = &rv1126_pin_ctrl }, 4383 { .compatible = "rockchip,rk2928-pinctrl", 4384 .data = &rk2928_pin_ctrl }, 4385 { .compatible = "rockchip,rk3036-pinctrl", 4386 .data = &rk3036_pin_ctrl }, 4387 { .compatible = "rockchip,rk3066a-pinctrl", 4388 .data = &rk3066a_pin_ctrl }, 4389 { .compatible = "rockchip,rk3066b-pinctrl", 4390 .data = &rk3066b_pin_ctrl }, 4391 { .compatible = "rockchip,rk3128-pinctrl", 4392 .data = (void *)&rk3128_pin_ctrl }, 4393 { .compatible = "rockchip,rk3188-pinctrl", 4394 .data = &rk3188_pin_ctrl }, 4395 { .compatible = "rockchip,rk3228-pinctrl", 4396 .data = &rk3228_pin_ctrl }, 4397 { .compatible = "rockchip,rk3288-pinctrl", 4398 .data = &rk3288_pin_ctrl }, 4399 { .compatible = "rockchip,rk3308-pinctrl", 4400 .data = &rk3308_pin_ctrl }, 4401 { .compatible = "rockchip,rk3328-pinctrl", 4402 .data = &rk3328_pin_ctrl }, 4403 { .compatible = "rockchip,rk3368-pinctrl", 4404 .data = &rk3368_pin_ctrl }, 4405 { .compatible = "rockchip,rk3399-pinctrl", 4406 .data = &rk3399_pin_ctrl }, 4407 { .compatible = "rockchip,rk3562-pinctrl", 4408 .data = &rk3562_pin_ctrl }, 4409 { .compatible = "rockchip,rk3568-pinctrl", 4410 .data = &rk3568_pin_ctrl }, 4411 { .compatible = "rockchip,rk3576-pinctrl", 4412 .data = &rk3576_pin_ctrl }, 4413 { .compatible = "rockchip,rk3588-pinctrl", 4414 .data = &rk3588_pin_ctrl }, 4415 {}, 4416 }; 4417 4418 static struct platform_driver rockchip_pinctrl_driver = { 4419 .probe = rockchip_pinctrl_probe, 4420 .remove = rockchip_pinctrl_remove, 4421 .driver = { 4422 .name = "rockchip-pinctrl", 4423 .pm = &rockchip_pinctrl_dev_pm_ops, 4424 .of_match_table = rockchip_pinctrl_dt_match, 4425 }, 4426 }; 4427 4428 static int __init rockchip_pinctrl_drv_register(void) 4429 { 4430 return platform_driver_register(&rockchip_pinctrl_driver); 4431 } 4432 postcore_initcall(rockchip_pinctrl_drv_register); 4433 4434 static void __exit rockchip_pinctrl_drv_unregister(void) 4435 { 4436 platform_driver_unregister(&rockchip_pinctrl_driver); 4437 } 4438 module_exit(rockchip_pinctrl_drv_unregister); 4439 4440 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); 4441 MODULE_LICENSE("GPL"); 4442 MODULE_ALIAS("platform:pinctrl-rockchip"); 4443 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 4444