1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi SoCs pinctrl driver 4 * 5 * Author: <alexandre.belloni@free-electrons.com> 6 * License: Dual MIT/GPL 7 * Copyright (c) 2017 Microsemi Corporation 8 */ 9 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/mfd/ocelot.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 #include <linux/slab.h> 19 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 26 #include "core.h" 27 #include "pinconf.h" 28 #include "pinmux.h" 29 30 #define ocelot_clrsetbits(addr, clear, set) \ 31 writel((readl(addr) & ~(clear)) | (set), (addr)) 32 33 enum { 34 PINCONF_BIAS, 35 PINCONF_SCHMITT, 36 PINCONF_DRIVE_STRENGTH, 37 }; 38 39 /* GPIO standard registers */ 40 #define OCELOT_GPIO_OUT_SET 0x0 41 #define OCELOT_GPIO_OUT_CLR 0x4 42 #define OCELOT_GPIO_OUT 0x8 43 #define OCELOT_GPIO_IN 0xc 44 #define OCELOT_GPIO_OE 0x10 45 #define OCELOT_GPIO_INTR 0x14 46 #define OCELOT_GPIO_INTR_ENA 0x18 47 #define OCELOT_GPIO_INTR_IDENT 0x1c 48 #define OCELOT_GPIO_ALT0 0x20 49 #define OCELOT_GPIO_ALT1 0x24 50 #define OCELOT_GPIO_SD_MAP 0x28 51 52 #define OCELOT_FUNC_PER_PIN 4 53 54 enum { 55 FUNC_CAN0_a, 56 FUNC_CAN0_b, 57 FUNC_CAN1, 58 FUNC_CLKMON, 59 FUNC_NONE, 60 FUNC_FAN, 61 FUNC_FC, 62 FUNC_FC0_a, 63 FUNC_FC0_b, 64 FUNC_FC0_c, 65 FUNC_FC1_a, 66 FUNC_FC1_b, 67 FUNC_FC1_c, 68 FUNC_FC2_a, 69 FUNC_FC2_b, 70 FUNC_FC3_a, 71 FUNC_FC3_b, 72 FUNC_FC3_c, 73 FUNC_FC4_a, 74 FUNC_FC4_b, 75 FUNC_FC4_c, 76 FUNC_FC_SHRD, 77 FUNC_FC_SHRD0, 78 FUNC_FC_SHRD1, 79 FUNC_FC_SHRD2, 80 FUNC_FC_SHRD3, 81 FUNC_FC_SHRD4, 82 FUNC_FC_SHRD5, 83 FUNC_FC_SHRD6, 84 FUNC_FC_SHRD7, 85 FUNC_FC_SHRD8, 86 FUNC_FC_SHRD9, 87 FUNC_FC_SHRD10, 88 FUNC_FC_SHRD11, 89 FUNC_FC_SHRD12, 90 FUNC_FC_SHRD13, 91 FUNC_FC_SHRD14, 92 FUNC_FC_SHRD15, 93 FUNC_FC_SHRD16, 94 FUNC_FC_SHRD17, 95 FUNC_FC_SHRD18, 96 FUNC_FC_SHRD19, 97 FUNC_FC_SHRD20, 98 FUNC_FUSA, 99 FUNC_GPIO, 100 FUNC_I2C, 101 FUNC_I2C_Sa, 102 FUNC_IB_TRG_a, 103 FUNC_IB_TRG_b, 104 FUNC_IB_TRG_c, 105 FUNC_IRQ0, 106 FUNC_IRQ_IN_a, 107 FUNC_IRQ_IN_b, 108 FUNC_IRQ_IN_c, 109 FUNC_IRQ0_IN, 110 FUNC_IRQ_OUT_a, 111 FUNC_IRQ_OUT_b, 112 FUNC_IRQ_OUT_c, 113 FUNC_IRQ0_OUT, 114 FUNC_IRQ1, 115 FUNC_IRQ1_IN, 116 FUNC_IRQ1_OUT, 117 FUNC_IRQ2, 118 FUNC_IRQ3, 119 FUNC_IRQ4, 120 FUNC_EXT_IRQ, 121 FUNC_MACLED, 122 FUNC_MIIM, 123 FUNC_MIIM_a, 124 FUNC_MIIM_b, 125 FUNC_MIIM_c, 126 FUNC_MIIM_Sa, 127 FUNC_MIIM_Sb, 128 FUNC_MIIM_IRQ, 129 FUNC_OB_TRG, 130 FUNC_OB_TRG_a, 131 FUNC_OB_TRG_b, 132 FUNC_PHY_LED, 133 FUNC_PHY_DBG, 134 FUNC_PCI_WAKE, 135 FUNC_MD, 136 FUNC_PCIE_PERST, 137 FUNC_PTP0, 138 FUNC_PTP1, 139 FUNC_PTP2, 140 FUNC_PTP3, 141 FUNC_PTPSYNC_0, 142 FUNC_PTPSYNC_1, 143 FUNC_PTPSYNC_2, 144 FUNC_PTPSYNC_3, 145 FUNC_PTPSYNC_4, 146 FUNC_PTPSYNC_5, 147 FUNC_PTPSYNC_6, 148 FUNC_PTPSYNC_7, 149 FUNC_PWM, 150 FUNC_PWM_a, 151 FUNC_PWM_b, 152 FUNC_QSPI1, 153 FUNC_QSPI2, 154 FUNC_R, 155 FUNC_RECO_a, 156 FUNC_RECO_b, 157 FUNC_RECO_CLK, 158 FUNC_SD, 159 FUNC_SFP, 160 FUNC_SFP_SD, 161 FUNC_SG0, 162 FUNC_SG1, 163 FUNC_SG2, 164 FUNC_SPI, 165 FUNC_SGPIO_a, 166 FUNC_SGPIO_b, 167 FUNC_SI, 168 FUNC_SI2, 169 FUNC_SI_Sa, 170 FUNC_SYNCE, 171 FUNC_TACHO, 172 FUNC_TACHO_a, 173 FUNC_TACHO_b, 174 FUNC_TWI, 175 FUNC_TWI2, 176 FUNC_TWI3, 177 FUNC_TWI_SCL_M, 178 FUNC_TWI_SLC_GATE, 179 FUNC_TWI_SLC_GATE_AD, 180 FUNC_UART, 181 FUNC_UART2, 182 FUNC_UART3, 183 FUNC_USB_H_a, 184 FUNC_USB_H_b, 185 FUNC_USB_H_c, 186 FUNC_USB_S_a, 187 FUNC_USB_S_b, 188 FUNC_USB_S_c, 189 FUNC_USB_POWER, 190 FUNC_USB2PHY_RST, 191 FUNC_USB_OVER_DETECT, 192 FUNC_USB_ULPI, 193 FUNC_PLL_STAT, 194 FUNC_EMMC, 195 FUNC_EMMC_SD, 196 FUNC_REF_CLK, 197 FUNC_RCVRD_CLK, 198 FUNC_RGMII, 199 FUNC_MAX 200 }; 201 202 static const char *const ocelot_function_names[] = { 203 [FUNC_CAN0_a] = "can0_a", 204 [FUNC_CAN0_b] = "can0_b", 205 [FUNC_CAN1] = "can1", 206 [FUNC_CLKMON] = "clkmon", 207 [FUNC_NONE] = "none", 208 [FUNC_FAN] = "fan", 209 [FUNC_FC] = "fc", 210 [FUNC_FC0_a] = "fc0_a", 211 [FUNC_FC0_b] = "fc0_b", 212 [FUNC_FC0_c] = "fc0_c", 213 [FUNC_FC1_a] = "fc1_a", 214 [FUNC_FC1_b] = "fc1_b", 215 [FUNC_FC1_c] = "fc1_c", 216 [FUNC_FC2_a] = "fc2_a", 217 [FUNC_FC2_b] = "fc2_b", 218 [FUNC_FC3_a] = "fc3_a", 219 [FUNC_FC3_b] = "fc3_b", 220 [FUNC_FC3_c] = "fc3_c", 221 [FUNC_FC4_a] = "fc4_a", 222 [FUNC_FC4_b] = "fc4_b", 223 [FUNC_FC4_c] = "fc4_c", 224 [FUNC_FC_SHRD] = "fc_shrd", 225 [FUNC_FC_SHRD0] = "fc_shrd0", 226 [FUNC_FC_SHRD1] = "fc_shrd1", 227 [FUNC_FC_SHRD2] = "fc_shrd2", 228 [FUNC_FC_SHRD3] = "fc_shrd3", 229 [FUNC_FC_SHRD4] = "fc_shrd4", 230 [FUNC_FC_SHRD5] = "fc_shrd5", 231 [FUNC_FC_SHRD6] = "fc_shrd6", 232 [FUNC_FC_SHRD7] = "fc_shrd7", 233 [FUNC_FC_SHRD8] = "fc_shrd8", 234 [FUNC_FC_SHRD9] = "fc_shrd9", 235 [FUNC_FC_SHRD10] = "fc_shrd10", 236 [FUNC_FC_SHRD11] = "fc_shrd11", 237 [FUNC_FC_SHRD12] = "fc_shrd12", 238 [FUNC_FC_SHRD13] = "fc_shrd13", 239 [FUNC_FC_SHRD14] = "fc_shrd14", 240 [FUNC_FC_SHRD15] = "fc_shrd15", 241 [FUNC_FC_SHRD16] = "fc_shrd16", 242 [FUNC_FC_SHRD17] = "fc_shrd17", 243 [FUNC_FC_SHRD18] = "fc_shrd18", 244 [FUNC_FC_SHRD19] = "fc_shrd19", 245 [FUNC_FC_SHRD20] = "fc_shrd20", 246 [FUNC_FUSA] = "fusa", 247 [FUNC_GPIO] = "gpio", 248 [FUNC_I2C] = "i2c", 249 [FUNC_I2C_Sa] = "i2c_slave_a", 250 [FUNC_IB_TRG_a] = "ib_trig_a", 251 [FUNC_IB_TRG_b] = "ib_trig_b", 252 [FUNC_IB_TRG_c] = "ib_trig_c", 253 [FUNC_IRQ0] = "irq0", 254 [FUNC_IRQ_IN_a] = "irq_in_a", 255 [FUNC_IRQ_IN_b] = "irq_in_b", 256 [FUNC_IRQ_IN_c] = "irq_in_c", 257 [FUNC_IRQ0_IN] = "irq0_in", 258 [FUNC_IRQ_OUT_a] = "irq_out_a", 259 [FUNC_IRQ_OUT_b] = "irq_out_b", 260 [FUNC_IRQ_OUT_c] = "irq_out_c", 261 [FUNC_IRQ0_OUT] = "irq0_out", 262 [FUNC_IRQ1] = "irq1", 263 [FUNC_IRQ1_IN] = "irq1_in", 264 [FUNC_IRQ1_OUT] = "irq1_out", 265 [FUNC_IRQ2] = "irq2", 266 [FUNC_IRQ3] = "irq3", 267 [FUNC_IRQ4] = "irq4", 268 [FUNC_EXT_IRQ] = "ext_irq", 269 [FUNC_MACLED] = "mac_led", 270 [FUNC_MIIM] = "miim", 271 [FUNC_MIIM_a] = "miim_a", 272 [FUNC_MIIM_b] = "miim_b", 273 [FUNC_MIIM_c] = "miim_c", 274 [FUNC_MIIM_Sa] = "miim_slave_a", 275 [FUNC_MIIM_Sb] = "miim_slave_b", 276 [FUNC_MIIM_IRQ] = "miim_irq", 277 [FUNC_PHY_LED] = "phy_led", 278 [FUNC_PHY_DBG] = "phy_dbg", 279 [FUNC_PCI_WAKE] = "pci_wake", 280 [FUNC_PCIE_PERST] = "pcie_perst", 281 [FUNC_MD] = "md", 282 [FUNC_OB_TRG] = "ob_trig", 283 [FUNC_OB_TRG_a] = "ob_trig_a", 284 [FUNC_OB_TRG_b] = "ob_trig_b", 285 [FUNC_PTP0] = "ptp0", 286 [FUNC_PTP1] = "ptp1", 287 [FUNC_PTP2] = "ptp2", 288 [FUNC_PTP3] = "ptp3", 289 [FUNC_PTPSYNC_0] = "ptpsync_0", 290 [FUNC_PTPSYNC_1] = "ptpsync_1", 291 [FUNC_PTPSYNC_2] = "ptpsync_2", 292 [FUNC_PTPSYNC_3] = "ptpsync_3", 293 [FUNC_PTPSYNC_4] = "ptpsync_4", 294 [FUNC_PTPSYNC_5] = "ptpsync_5", 295 [FUNC_PTPSYNC_6] = "ptpsync_6", 296 [FUNC_PTPSYNC_7] = "ptpsync_7", 297 [FUNC_PWM] = "pwm", 298 [FUNC_PWM_a] = "pwm_a", 299 [FUNC_PWM_b] = "pwm_b", 300 [FUNC_QSPI1] = "qspi1", 301 [FUNC_QSPI2] = "qspi2", 302 [FUNC_R] = "reserved", 303 [FUNC_RECO_a] = "reco_a", 304 [FUNC_RECO_b] = "reco_b", 305 [FUNC_RECO_CLK] = "reco_clk", 306 [FUNC_SD] = "sd", 307 [FUNC_SFP] = "sfp", 308 [FUNC_SFP_SD] = "sfp_sd", 309 [FUNC_SG0] = "sg0", 310 [FUNC_SG1] = "sg1", 311 [FUNC_SG2] = "sg2", 312 [FUNC_SGPIO_a] = "sgpio_a", 313 [FUNC_SGPIO_b] = "sgpio_b", 314 [FUNC_SI] = "si", 315 [FUNC_SI2] = "si2", 316 [FUNC_SI_Sa] = "si_slave_a", 317 [FUNC_SPI] = "spi", 318 [FUNC_SYNCE] = "synce", 319 [FUNC_TACHO] = "tacho", 320 [FUNC_TACHO_a] = "tacho_a", 321 [FUNC_TACHO_b] = "tacho_b", 322 [FUNC_TWI] = "twi", 323 [FUNC_TWI2] = "twi2", 324 [FUNC_TWI3] = "twi3", 325 [FUNC_TWI_SCL_M] = "twi_scl_m", 326 [FUNC_TWI_SLC_GATE] = "twi_slc_gate", 327 [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", 328 [FUNC_USB_H_a] = "usb_host_a", 329 [FUNC_USB_H_b] = "usb_host_b", 330 [FUNC_USB_H_c] = "usb_host_c", 331 [FUNC_USB_S_a] = "usb_slave_a", 332 [FUNC_USB_S_b] = "usb_slave_b", 333 [FUNC_USB_S_c] = "usb_slave_c", 334 [FUNC_USB_POWER] = "usb_power", 335 [FUNC_USB2PHY_RST] = "usb2phy_rst", 336 [FUNC_USB_OVER_DETECT] = "usb_over_detect", 337 [FUNC_USB_ULPI] = "usb_ulpi", 338 [FUNC_UART] = "uart", 339 [FUNC_UART2] = "uart2", 340 [FUNC_UART3] = "uart3", 341 [FUNC_PLL_STAT] = "pll_stat", 342 [FUNC_EMMC] = "emmc", 343 [FUNC_EMMC_SD] = "emmc_sd", 344 [FUNC_REF_CLK] = "ref_clk", 345 [FUNC_RCVRD_CLK] = "rcvrd_clk", 346 [FUNC_RGMII] = "rgmii", 347 }; 348 349 struct ocelot_pmx_func { 350 const char **groups; 351 unsigned int ngroups; 352 }; 353 354 struct ocelot_pin_caps { 355 unsigned int pin; 356 unsigned char functions[OCELOT_FUNC_PER_PIN]; 357 unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 358 }; 359 360 struct ocelot_pincfg_data { 361 u8 pd_bit; 362 u8 pu_bit; 363 u8 drive_bits; 364 u8 schmitt_bit; 365 }; 366 367 struct ocelot_pinctrl { 368 struct device *dev; 369 struct pinctrl_dev *pctl; 370 struct gpio_chip gpio_chip; 371 struct regmap *map; 372 struct regmap *pincfg; 373 struct pinctrl_desc *desc; 374 const struct ocelot_pincfg_data *pincfg_data; 375 struct ocelot_pmx_func func[FUNC_MAX]; 376 u8 stride; 377 u8 altm_stride; 378 struct workqueue_struct *wq; 379 }; 380 381 struct ocelot_match_data { 382 struct pinctrl_desc desc; 383 struct ocelot_pincfg_data pincfg_data; 384 unsigned int n_alt_modes; 385 }; 386 387 struct ocelot_irq_work { 388 struct work_struct irq_work; 389 struct irq_desc *irq_desc; 390 }; 391 392 #define LUTON_P(p, f0, f1) \ 393 static struct ocelot_pin_caps luton_pin_##p = { \ 394 .pin = p, \ 395 .functions = { \ 396 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ 397 }, \ 398 } 399 400 LUTON_P(0, SG0, NONE); 401 LUTON_P(1, SG0, NONE); 402 LUTON_P(2, SG0, NONE); 403 LUTON_P(3, SG0, NONE); 404 LUTON_P(4, TACHO, NONE); 405 LUTON_P(5, TWI, PHY_LED); 406 LUTON_P(6, TWI, PHY_LED); 407 LUTON_P(7, NONE, PHY_LED); 408 LUTON_P(8, EXT_IRQ, PHY_LED); 409 LUTON_P(9, EXT_IRQ, PHY_LED); 410 LUTON_P(10, SFP, PHY_LED); 411 LUTON_P(11, SFP, PHY_LED); 412 LUTON_P(12, SFP, PHY_LED); 413 LUTON_P(13, SFP, PHY_LED); 414 LUTON_P(14, SI, PHY_LED); 415 LUTON_P(15, SI, PHY_LED); 416 LUTON_P(16, SI, PHY_LED); 417 LUTON_P(17, SFP, PHY_LED); 418 LUTON_P(18, SFP, PHY_LED); 419 LUTON_P(19, SFP, PHY_LED); 420 LUTON_P(20, SFP, PHY_LED); 421 LUTON_P(21, SFP, PHY_LED); 422 LUTON_P(22, SFP, PHY_LED); 423 LUTON_P(23, SFP, PHY_LED); 424 LUTON_P(24, SFP, PHY_LED); 425 LUTON_P(25, SFP, PHY_LED); 426 LUTON_P(26, SFP, PHY_LED); 427 LUTON_P(27, SFP, PHY_LED); 428 LUTON_P(28, SFP, PHY_LED); 429 LUTON_P(29, PWM, NONE); 430 LUTON_P(30, UART, NONE); 431 LUTON_P(31, UART, NONE); 432 433 #define LUTON_PIN(n) { \ 434 .number = n, \ 435 .name = "GPIO_"#n, \ 436 .drv_data = &luton_pin_##n \ 437 } 438 439 static const struct pinctrl_pin_desc luton_pins[] = { 440 LUTON_PIN(0), 441 LUTON_PIN(1), 442 LUTON_PIN(2), 443 LUTON_PIN(3), 444 LUTON_PIN(4), 445 LUTON_PIN(5), 446 LUTON_PIN(6), 447 LUTON_PIN(7), 448 LUTON_PIN(8), 449 LUTON_PIN(9), 450 LUTON_PIN(10), 451 LUTON_PIN(11), 452 LUTON_PIN(12), 453 LUTON_PIN(13), 454 LUTON_PIN(14), 455 LUTON_PIN(15), 456 LUTON_PIN(16), 457 LUTON_PIN(17), 458 LUTON_PIN(18), 459 LUTON_PIN(19), 460 LUTON_PIN(20), 461 LUTON_PIN(21), 462 LUTON_PIN(22), 463 LUTON_PIN(23), 464 LUTON_PIN(24), 465 LUTON_PIN(25), 466 LUTON_PIN(26), 467 LUTON_PIN(27), 468 LUTON_PIN(28), 469 LUTON_PIN(29), 470 LUTON_PIN(30), 471 LUTON_PIN(31), 472 }; 473 474 #define SERVAL_P(p, f0, f1, f2) \ 475 static struct ocelot_pin_caps serval_pin_##p = { \ 476 .pin = p, \ 477 .functions = { \ 478 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 479 }, \ 480 } 481 482 SERVAL_P(0, SG0, NONE, NONE); 483 SERVAL_P(1, SG0, NONE, NONE); 484 SERVAL_P(2, SG0, NONE, NONE); 485 SERVAL_P(3, SG0, NONE, NONE); 486 SERVAL_P(4, TACHO, NONE, NONE); 487 SERVAL_P(5, PWM, NONE, NONE); 488 SERVAL_P(6, TWI, NONE, NONE); 489 SERVAL_P(7, TWI, NONE, NONE); 490 SERVAL_P(8, SI, NONE, NONE); 491 SERVAL_P(9, SI, MD, NONE); 492 SERVAL_P(10, SI, MD, NONE); 493 SERVAL_P(11, SFP, MD, TWI_SCL_M); 494 SERVAL_P(12, SFP, MD, TWI_SCL_M); 495 SERVAL_P(13, SFP, UART2, TWI_SCL_M); 496 SERVAL_P(14, SFP, UART2, TWI_SCL_M); 497 SERVAL_P(15, SFP, PTP0, TWI_SCL_M); 498 SERVAL_P(16, SFP, PTP0, TWI_SCL_M); 499 SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); 500 SERVAL_P(18, SFP, NONE, TWI_SCL_M); 501 SERVAL_P(19, SFP, NONE, TWI_SCL_M); 502 SERVAL_P(20, SFP, NONE, TWI_SCL_M); 503 SERVAL_P(21, SFP, NONE, TWI_SCL_M); 504 SERVAL_P(22, NONE, NONE, NONE); 505 SERVAL_P(23, NONE, NONE, NONE); 506 SERVAL_P(24, NONE, NONE, NONE); 507 SERVAL_P(25, NONE, NONE, NONE); 508 SERVAL_P(26, UART, NONE, NONE); 509 SERVAL_P(27, UART, NONE, NONE); 510 SERVAL_P(28, IRQ0, NONE, NONE); 511 SERVAL_P(29, IRQ1, NONE, NONE); 512 SERVAL_P(30, PTP0, NONE, NONE); 513 SERVAL_P(31, PTP0, NONE, NONE); 514 515 #define SERVAL_PIN(n) { \ 516 .number = n, \ 517 .name = "GPIO_"#n, \ 518 .drv_data = &serval_pin_##n \ 519 } 520 521 static const struct pinctrl_pin_desc serval_pins[] = { 522 SERVAL_PIN(0), 523 SERVAL_PIN(1), 524 SERVAL_PIN(2), 525 SERVAL_PIN(3), 526 SERVAL_PIN(4), 527 SERVAL_PIN(5), 528 SERVAL_PIN(6), 529 SERVAL_PIN(7), 530 SERVAL_PIN(8), 531 SERVAL_PIN(9), 532 SERVAL_PIN(10), 533 SERVAL_PIN(11), 534 SERVAL_PIN(12), 535 SERVAL_PIN(13), 536 SERVAL_PIN(14), 537 SERVAL_PIN(15), 538 SERVAL_PIN(16), 539 SERVAL_PIN(17), 540 SERVAL_PIN(18), 541 SERVAL_PIN(19), 542 SERVAL_PIN(20), 543 SERVAL_PIN(21), 544 SERVAL_PIN(22), 545 SERVAL_PIN(23), 546 SERVAL_PIN(24), 547 SERVAL_PIN(25), 548 SERVAL_PIN(26), 549 SERVAL_PIN(27), 550 SERVAL_PIN(28), 551 SERVAL_PIN(29), 552 SERVAL_PIN(30), 553 SERVAL_PIN(31), 554 }; 555 556 #define OCELOT_P(p, f0, f1, f2) \ 557 static struct ocelot_pin_caps ocelot_pin_##p = { \ 558 .pin = p, \ 559 .functions = { \ 560 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 561 }, \ 562 } 563 564 OCELOT_P(0, SG0, NONE, NONE); 565 OCELOT_P(1, SG0, NONE, NONE); 566 OCELOT_P(2, SG0, NONE, NONE); 567 OCELOT_P(3, SG0, NONE, NONE); 568 OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 569 OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 570 OCELOT_P(6, UART, TWI_SCL_M, NONE); 571 OCELOT_P(7, UART, TWI_SCL_M, NONE); 572 OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 573 OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 574 OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 575 OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 576 OCELOT_P(12, UART2, TWI_SCL_M, SFP); 577 OCELOT_P(13, UART2, TWI_SCL_M, SFP); 578 OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 579 OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 580 OCELOT_P(16, TWI, NONE, SI); 581 OCELOT_P(17, TWI, TWI_SCL_M, SI); 582 OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 583 OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 584 OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 585 OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 586 587 #define OCELOT_PIN(n) { \ 588 .number = n, \ 589 .name = "GPIO_"#n, \ 590 .drv_data = &ocelot_pin_##n \ 591 } 592 593 static const struct pinctrl_pin_desc ocelot_pins[] = { 594 OCELOT_PIN(0), 595 OCELOT_PIN(1), 596 OCELOT_PIN(2), 597 OCELOT_PIN(3), 598 OCELOT_PIN(4), 599 OCELOT_PIN(5), 600 OCELOT_PIN(6), 601 OCELOT_PIN(7), 602 OCELOT_PIN(8), 603 OCELOT_PIN(9), 604 OCELOT_PIN(10), 605 OCELOT_PIN(11), 606 OCELOT_PIN(12), 607 OCELOT_PIN(13), 608 OCELOT_PIN(14), 609 OCELOT_PIN(15), 610 OCELOT_PIN(16), 611 OCELOT_PIN(17), 612 OCELOT_PIN(18), 613 OCELOT_PIN(19), 614 OCELOT_PIN(20), 615 OCELOT_PIN(21), 616 }; 617 618 #define JAGUAR2_P(p, f0, f1) \ 619 static struct ocelot_pin_caps jaguar2_pin_##p = { \ 620 .pin = p, \ 621 .functions = { \ 622 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 623 }, \ 624 } 625 626 JAGUAR2_P(0, SG0, NONE); 627 JAGUAR2_P(1, SG0, NONE); 628 JAGUAR2_P(2, SG0, NONE); 629 JAGUAR2_P(3, SG0, NONE); 630 JAGUAR2_P(4, SG1, NONE); 631 JAGUAR2_P(5, SG1, NONE); 632 JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 633 JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 634 JAGUAR2_P(8, PTP0, NONE); 635 JAGUAR2_P(9, PTP1, NONE); 636 JAGUAR2_P(10, UART, NONE); 637 JAGUAR2_P(11, UART, NONE); 638 JAGUAR2_P(12, SG1, NONE); 639 JAGUAR2_P(13, SG1, NONE); 640 JAGUAR2_P(14, TWI, TWI_SCL_M); 641 JAGUAR2_P(15, TWI, NONE); 642 JAGUAR2_P(16, SI, TWI_SCL_M); 643 JAGUAR2_P(17, SI, TWI_SCL_M); 644 JAGUAR2_P(18, SI, TWI_SCL_M); 645 JAGUAR2_P(19, PCI_WAKE, NONE); 646 JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 647 JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 648 JAGUAR2_P(22, TACHO, NONE); 649 JAGUAR2_P(23, PWM, NONE); 650 JAGUAR2_P(24, UART2, NONE); 651 JAGUAR2_P(25, UART2, SI); 652 JAGUAR2_P(26, PTP2, SI); 653 JAGUAR2_P(27, PTP3, SI); 654 JAGUAR2_P(28, TWI2, SI); 655 JAGUAR2_P(29, TWI2, SI); 656 JAGUAR2_P(30, SG2, SI); 657 JAGUAR2_P(31, SG2, SI); 658 JAGUAR2_P(32, SG2, SI); 659 JAGUAR2_P(33, SG2, SI); 660 JAGUAR2_P(34, NONE, TWI_SCL_M); 661 JAGUAR2_P(35, NONE, TWI_SCL_M); 662 JAGUAR2_P(36, NONE, TWI_SCL_M); 663 JAGUAR2_P(37, NONE, TWI_SCL_M); 664 JAGUAR2_P(38, NONE, TWI_SCL_M); 665 JAGUAR2_P(39, NONE, TWI_SCL_M); 666 JAGUAR2_P(40, NONE, TWI_SCL_M); 667 JAGUAR2_P(41, NONE, TWI_SCL_M); 668 JAGUAR2_P(42, NONE, TWI_SCL_M); 669 JAGUAR2_P(43, NONE, TWI_SCL_M); 670 JAGUAR2_P(44, NONE, SFP); 671 JAGUAR2_P(45, NONE, SFP); 672 JAGUAR2_P(46, NONE, SFP); 673 JAGUAR2_P(47, NONE, SFP); 674 JAGUAR2_P(48, SFP, NONE); 675 JAGUAR2_P(49, SFP, SI); 676 JAGUAR2_P(50, SFP, SI); 677 JAGUAR2_P(51, SFP, SI); 678 JAGUAR2_P(52, SFP, NONE); 679 JAGUAR2_P(53, SFP, NONE); 680 JAGUAR2_P(54, SFP, NONE); 681 JAGUAR2_P(55, SFP, NONE); 682 JAGUAR2_P(56, MIIM, SFP); 683 JAGUAR2_P(57, MIIM, SFP); 684 JAGUAR2_P(58, MIIM, SFP); 685 JAGUAR2_P(59, MIIM, SFP); 686 JAGUAR2_P(60, NONE, NONE); 687 JAGUAR2_P(61, NONE, NONE); 688 JAGUAR2_P(62, NONE, NONE); 689 JAGUAR2_P(63, NONE, NONE); 690 691 #define JAGUAR2_PIN(n) { \ 692 .number = n, \ 693 .name = "GPIO_"#n, \ 694 .drv_data = &jaguar2_pin_##n \ 695 } 696 697 static const struct pinctrl_pin_desc jaguar2_pins[] = { 698 JAGUAR2_PIN(0), 699 JAGUAR2_PIN(1), 700 JAGUAR2_PIN(2), 701 JAGUAR2_PIN(3), 702 JAGUAR2_PIN(4), 703 JAGUAR2_PIN(5), 704 JAGUAR2_PIN(6), 705 JAGUAR2_PIN(7), 706 JAGUAR2_PIN(8), 707 JAGUAR2_PIN(9), 708 JAGUAR2_PIN(10), 709 JAGUAR2_PIN(11), 710 JAGUAR2_PIN(12), 711 JAGUAR2_PIN(13), 712 JAGUAR2_PIN(14), 713 JAGUAR2_PIN(15), 714 JAGUAR2_PIN(16), 715 JAGUAR2_PIN(17), 716 JAGUAR2_PIN(18), 717 JAGUAR2_PIN(19), 718 JAGUAR2_PIN(20), 719 JAGUAR2_PIN(21), 720 JAGUAR2_PIN(22), 721 JAGUAR2_PIN(23), 722 JAGUAR2_PIN(24), 723 JAGUAR2_PIN(25), 724 JAGUAR2_PIN(26), 725 JAGUAR2_PIN(27), 726 JAGUAR2_PIN(28), 727 JAGUAR2_PIN(29), 728 JAGUAR2_PIN(30), 729 JAGUAR2_PIN(31), 730 JAGUAR2_PIN(32), 731 JAGUAR2_PIN(33), 732 JAGUAR2_PIN(34), 733 JAGUAR2_PIN(35), 734 JAGUAR2_PIN(36), 735 JAGUAR2_PIN(37), 736 JAGUAR2_PIN(38), 737 JAGUAR2_PIN(39), 738 JAGUAR2_PIN(40), 739 JAGUAR2_PIN(41), 740 JAGUAR2_PIN(42), 741 JAGUAR2_PIN(43), 742 JAGUAR2_PIN(44), 743 JAGUAR2_PIN(45), 744 JAGUAR2_PIN(46), 745 JAGUAR2_PIN(47), 746 JAGUAR2_PIN(48), 747 JAGUAR2_PIN(49), 748 JAGUAR2_PIN(50), 749 JAGUAR2_PIN(51), 750 JAGUAR2_PIN(52), 751 JAGUAR2_PIN(53), 752 JAGUAR2_PIN(54), 753 JAGUAR2_PIN(55), 754 JAGUAR2_PIN(56), 755 JAGUAR2_PIN(57), 756 JAGUAR2_PIN(58), 757 JAGUAR2_PIN(59), 758 JAGUAR2_PIN(60), 759 JAGUAR2_PIN(61), 760 JAGUAR2_PIN(62), 761 JAGUAR2_PIN(63), 762 }; 763 764 #define SERVALT_P(p, f0, f1, f2) \ 765 static struct ocelot_pin_caps servalt_pin_##p = { \ 766 .pin = p, \ 767 .functions = { \ 768 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 769 }, \ 770 } 771 772 SERVALT_P(0, SG0, NONE, NONE); 773 SERVALT_P(1, SG0, NONE, NONE); 774 SERVALT_P(2, SG0, NONE, NONE); 775 SERVALT_P(3, SG0, NONE, NONE); 776 SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 777 SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); 778 SERVALT_P(6, UART, NONE, NONE); 779 SERVALT_P(7, UART, NONE, NONE); 780 SERVALT_P(8, SI, SFP, TWI_SCL_M); 781 SERVALT_P(9, PCI_WAKE, SFP, SI); 782 SERVALT_P(10, PTP0, SFP, TWI_SCL_M); 783 SERVALT_P(11, PTP1, SFP, TWI_SCL_M); 784 SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); 785 SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); 786 SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); 787 SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); 788 SERVALT_P(16, TACHO, SFP, SI); 789 SERVALT_P(17, PWM, NONE, TWI_SCL_M); 790 SERVALT_P(18, PTP2, SFP, SI); 791 SERVALT_P(19, PTP3, SFP, SI); 792 SERVALT_P(20, UART2, SFP, SI); 793 SERVALT_P(21, UART2, NONE, NONE); 794 SERVALT_P(22, MIIM, SFP, TWI2); 795 SERVALT_P(23, MIIM, SFP, TWI2); 796 SERVALT_P(24, TWI, NONE, NONE); 797 SERVALT_P(25, TWI, SFP, TWI_SCL_M); 798 SERVALT_P(26, TWI_SCL_M, SFP, SI); 799 SERVALT_P(27, TWI_SCL_M, SFP, SI); 800 SERVALT_P(28, TWI_SCL_M, SFP, SI); 801 SERVALT_P(29, TWI_SCL_M, NONE, NONE); 802 SERVALT_P(30, TWI_SCL_M, NONE, NONE); 803 SERVALT_P(31, TWI_SCL_M, NONE, NONE); 804 SERVALT_P(32, TWI_SCL_M, NONE, NONE); 805 SERVALT_P(33, RCVRD_CLK, NONE, NONE); 806 SERVALT_P(34, RCVRD_CLK, NONE, NONE); 807 SERVALT_P(35, RCVRD_CLK, NONE, NONE); 808 SERVALT_P(36, RCVRD_CLK, NONE, NONE); 809 810 #define SERVALT_PIN(n) { \ 811 .number = n, \ 812 .name = "GPIO_"#n, \ 813 .drv_data = &servalt_pin_##n \ 814 } 815 816 static const struct pinctrl_pin_desc servalt_pins[] = { 817 SERVALT_PIN(0), 818 SERVALT_PIN(1), 819 SERVALT_PIN(2), 820 SERVALT_PIN(3), 821 SERVALT_PIN(4), 822 SERVALT_PIN(5), 823 SERVALT_PIN(6), 824 SERVALT_PIN(7), 825 SERVALT_PIN(8), 826 SERVALT_PIN(9), 827 SERVALT_PIN(10), 828 SERVALT_PIN(11), 829 SERVALT_PIN(12), 830 SERVALT_PIN(13), 831 SERVALT_PIN(14), 832 SERVALT_PIN(15), 833 SERVALT_PIN(16), 834 SERVALT_PIN(17), 835 SERVALT_PIN(18), 836 SERVALT_PIN(19), 837 SERVALT_PIN(20), 838 SERVALT_PIN(21), 839 SERVALT_PIN(22), 840 SERVALT_PIN(23), 841 SERVALT_PIN(24), 842 SERVALT_PIN(25), 843 SERVALT_PIN(26), 844 SERVALT_PIN(27), 845 SERVALT_PIN(28), 846 SERVALT_PIN(29), 847 SERVALT_PIN(30), 848 SERVALT_PIN(31), 849 SERVALT_PIN(32), 850 SERVALT_PIN(33), 851 SERVALT_PIN(34), 852 SERVALT_PIN(35), 853 SERVALT_PIN(36), 854 }; 855 856 #define SPARX5_P(p, f0, f1, f2) \ 857 static struct ocelot_pin_caps sparx5_pin_##p = { \ 858 .pin = p, \ 859 .functions = { \ 860 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 861 }, \ 862 } 863 864 SPARX5_P(0, SG0, PLL_STAT, NONE); 865 SPARX5_P(1, SG0, NONE, NONE); 866 SPARX5_P(2, SG0, NONE, NONE); 867 SPARX5_P(3, SG0, NONE, NONE); 868 SPARX5_P(4, SG1, NONE, NONE); 869 SPARX5_P(5, SG1, NONE, NONE); 870 SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 871 SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 872 SPARX5_P(8, PTP0, NONE, SFP); 873 SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 874 SPARX5_P(10, UART, NONE, NONE); 875 SPARX5_P(11, UART, NONE, NONE); 876 SPARX5_P(12, SG1, NONE, NONE); 877 SPARX5_P(13, SG1, NONE, NONE); 878 SPARX5_P(14, TWI, TWI_SCL_M, NONE); 879 SPARX5_P(15, TWI, NONE, NONE); 880 SPARX5_P(16, SI, TWI_SCL_M, SFP); 881 SPARX5_P(17, SI, TWI_SCL_M, SFP); 882 SPARX5_P(18, SI, TWI_SCL_M, SFP); 883 SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 884 SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 885 SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 886 SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 887 SPARX5_P(23, PWM, UART3, TWI_SCL_M); 888 SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 889 SPARX5_P(25, PTP3, SI, TWI_SCL_M); 890 SPARX5_P(26, UART2, SI, TWI_SCL_M); 891 SPARX5_P(27, UART2, SI, TWI_SCL_M); 892 SPARX5_P(28, TWI2, SI, SFP); 893 SPARX5_P(29, TWI2, SI, SFP); 894 SPARX5_P(30, SG2, SI, PWM); 895 SPARX5_P(31, SG2, SI, TWI_SCL_M); 896 SPARX5_P(32, SG2, SI, TWI_SCL_M); 897 SPARX5_P(33, SG2, SI, SFP); 898 SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 899 SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 900 SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 901 SPARX5_P(37, SFP, NONE, EMMC); 902 SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 903 SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 904 SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 905 SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 906 SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 907 SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 908 SPARX5_P(44, SI, SFP, EMMC); 909 SPARX5_P(45, SI, SFP, EMMC); 910 SPARX5_P(46, NONE, SFP, EMMC); 911 SPARX5_P(47, NONE, SFP, EMMC); 912 SPARX5_P(48, TWI3, SI, SFP); 913 SPARX5_P(49, TWI3, NONE, SFP); 914 SPARX5_P(50, SFP, NONE, TWI_SCL_M); 915 SPARX5_P(51, SFP, SI, TWI_SCL_M); 916 SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 917 SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 918 SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 919 SPARX5_P(55, SFP, PTP3, PCI_WAKE); 920 SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 921 SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 922 SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 923 SPARX5_P(59, MIIM, SFP, NONE); 924 SPARX5_P(60, RECO_CLK, NONE, NONE); 925 SPARX5_P(61, RECO_CLK, NONE, NONE); 926 SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 927 SPARX5_P(63, RECO_CLK, NONE, NONE); 928 929 #define SPARX5_PIN(n) { \ 930 .number = n, \ 931 .name = "GPIO_"#n, \ 932 .drv_data = &sparx5_pin_##n \ 933 } 934 935 static const struct pinctrl_pin_desc sparx5_pins[] = { 936 SPARX5_PIN(0), 937 SPARX5_PIN(1), 938 SPARX5_PIN(2), 939 SPARX5_PIN(3), 940 SPARX5_PIN(4), 941 SPARX5_PIN(5), 942 SPARX5_PIN(6), 943 SPARX5_PIN(7), 944 SPARX5_PIN(8), 945 SPARX5_PIN(9), 946 SPARX5_PIN(10), 947 SPARX5_PIN(11), 948 SPARX5_PIN(12), 949 SPARX5_PIN(13), 950 SPARX5_PIN(14), 951 SPARX5_PIN(15), 952 SPARX5_PIN(16), 953 SPARX5_PIN(17), 954 SPARX5_PIN(18), 955 SPARX5_PIN(19), 956 SPARX5_PIN(20), 957 SPARX5_PIN(21), 958 SPARX5_PIN(22), 959 SPARX5_PIN(23), 960 SPARX5_PIN(24), 961 SPARX5_PIN(25), 962 SPARX5_PIN(26), 963 SPARX5_PIN(27), 964 SPARX5_PIN(28), 965 SPARX5_PIN(29), 966 SPARX5_PIN(30), 967 SPARX5_PIN(31), 968 SPARX5_PIN(32), 969 SPARX5_PIN(33), 970 SPARX5_PIN(34), 971 SPARX5_PIN(35), 972 SPARX5_PIN(36), 973 SPARX5_PIN(37), 974 SPARX5_PIN(38), 975 SPARX5_PIN(39), 976 SPARX5_PIN(40), 977 SPARX5_PIN(41), 978 SPARX5_PIN(42), 979 SPARX5_PIN(43), 980 SPARX5_PIN(44), 981 SPARX5_PIN(45), 982 SPARX5_PIN(46), 983 SPARX5_PIN(47), 984 SPARX5_PIN(48), 985 SPARX5_PIN(49), 986 SPARX5_PIN(50), 987 SPARX5_PIN(51), 988 SPARX5_PIN(52), 989 SPARX5_PIN(53), 990 SPARX5_PIN(54), 991 SPARX5_PIN(55), 992 SPARX5_PIN(56), 993 SPARX5_PIN(57), 994 SPARX5_PIN(58), 995 SPARX5_PIN(59), 996 SPARX5_PIN(60), 997 SPARX5_PIN(61), 998 SPARX5_PIN(62), 999 SPARX5_PIN(63), 1000 }; 1001 1002 #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 1003 static struct ocelot_pin_caps lan966x_pin_##p = { \ 1004 .pin = p, \ 1005 .functions = { \ 1006 FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 1007 FUNC_##f3 \ 1008 }, \ 1009 .a_functions = { \ 1010 FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 1011 FUNC_##f7 \ 1012 }, \ 1013 } 1014 1015 /* Pinmuxing table taken from data sheet */ 1016 /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 1017 LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1018 LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1019 LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1020 LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1021 LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1022 LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1023 LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1024 LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1025 LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); 1026 LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); 1027 LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); 1028 LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 1029 LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 1030 LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 1031 LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 1032 LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 1033 LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 1034 LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 1035 LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 1036 LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 1037 LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); 1038 LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 1039 LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 1040 LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); 1041 LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); 1042 LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 1043 LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); 1044 LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R); 1045 LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 1046 LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 1047 LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 1048 LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 1049 LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); 1050 LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1051 LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1052 LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R); 1053 LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); 1054 LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1055 LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); 1056 LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); 1057 LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); 1058 LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1059 LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1060 LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1061 LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1062 LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); 1063 LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); 1064 LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); 1065 LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); 1066 LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); 1067 LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); 1068 LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R); 1069 LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); 1070 LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 1071 LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1072 LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1073 LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); 1074 LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); 1075 LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); 1076 LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1077 LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1078 LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); 1079 LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1080 LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1081 LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); 1082 LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); 1083 LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); 1084 LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1085 LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1086 LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1087 LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1088 LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1089 LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1090 LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); 1091 LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); 1092 LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); 1093 LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); 1094 LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); 1095 1096 #define LAN966X_PIN(n) { \ 1097 .number = n, \ 1098 .name = "GPIO_"#n, \ 1099 .drv_data = &lan966x_pin_##n \ 1100 } 1101 1102 static const struct pinctrl_pin_desc lan966x_pins[] = { 1103 LAN966X_PIN(0), 1104 LAN966X_PIN(1), 1105 LAN966X_PIN(2), 1106 LAN966X_PIN(3), 1107 LAN966X_PIN(4), 1108 LAN966X_PIN(5), 1109 LAN966X_PIN(6), 1110 LAN966X_PIN(7), 1111 LAN966X_PIN(8), 1112 LAN966X_PIN(9), 1113 LAN966X_PIN(10), 1114 LAN966X_PIN(11), 1115 LAN966X_PIN(12), 1116 LAN966X_PIN(13), 1117 LAN966X_PIN(14), 1118 LAN966X_PIN(15), 1119 LAN966X_PIN(16), 1120 LAN966X_PIN(17), 1121 LAN966X_PIN(18), 1122 LAN966X_PIN(19), 1123 LAN966X_PIN(20), 1124 LAN966X_PIN(21), 1125 LAN966X_PIN(22), 1126 LAN966X_PIN(23), 1127 LAN966X_PIN(24), 1128 LAN966X_PIN(25), 1129 LAN966X_PIN(26), 1130 LAN966X_PIN(27), 1131 LAN966X_PIN(28), 1132 LAN966X_PIN(29), 1133 LAN966X_PIN(30), 1134 LAN966X_PIN(31), 1135 LAN966X_PIN(32), 1136 LAN966X_PIN(33), 1137 LAN966X_PIN(34), 1138 LAN966X_PIN(35), 1139 LAN966X_PIN(36), 1140 LAN966X_PIN(37), 1141 LAN966X_PIN(38), 1142 LAN966X_PIN(39), 1143 LAN966X_PIN(40), 1144 LAN966X_PIN(41), 1145 LAN966X_PIN(42), 1146 LAN966X_PIN(43), 1147 LAN966X_PIN(44), 1148 LAN966X_PIN(45), 1149 LAN966X_PIN(46), 1150 LAN966X_PIN(47), 1151 LAN966X_PIN(48), 1152 LAN966X_PIN(49), 1153 LAN966X_PIN(50), 1154 LAN966X_PIN(51), 1155 LAN966X_PIN(52), 1156 LAN966X_PIN(53), 1157 LAN966X_PIN(54), 1158 LAN966X_PIN(55), 1159 LAN966X_PIN(56), 1160 LAN966X_PIN(57), 1161 LAN966X_PIN(58), 1162 LAN966X_PIN(59), 1163 LAN966X_PIN(60), 1164 LAN966X_PIN(61), 1165 LAN966X_PIN(62), 1166 LAN966X_PIN(63), 1167 LAN966X_PIN(64), 1168 LAN966X_PIN(65), 1169 LAN966X_PIN(66), 1170 LAN966X_PIN(67), 1171 LAN966X_PIN(68), 1172 LAN966X_PIN(69), 1173 LAN966X_PIN(70), 1174 LAN966X_PIN(71), 1175 LAN966X_PIN(72), 1176 LAN966X_PIN(73), 1177 LAN966X_PIN(74), 1178 LAN966X_PIN(75), 1179 LAN966X_PIN(76), 1180 LAN966X_PIN(77), 1181 }; 1182 1183 #define LAN969X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 1184 static struct ocelot_pin_caps lan969x_pin_##p = { \ 1185 .pin = p, \ 1186 .functions = { \ 1187 FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 1188 FUNC_##f3 \ 1189 }, \ 1190 .a_functions = { \ 1191 FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 1192 FUNC_##f7 \ 1193 }, \ 1194 } 1195 1196 /* Pinmuxing table taken from data sheet */ 1197 /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 1198 LAN969X_P(0, GPIO, IRQ0, FC_SHRD, PCIE_PERST, NONE, NONE, NONE, R); 1199 LAN969X_P(1, GPIO, IRQ1, FC_SHRD, USB_POWER, NONE, NONE, NONE, R); 1200 LAN969X_P(2, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); 1201 LAN969X_P(3, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); 1202 LAN969X_P(4, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); 1203 LAN969X_P(5, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); 1204 LAN969X_P(6, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); 1205 LAN969X_P(7, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); 1206 LAN969X_P(8, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); 1207 LAN969X_P(9, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); 1208 LAN969X_P(10, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); 1209 LAN969X_P(11, GPIO, MIIM_IRQ, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); 1210 LAN969X_P(12, GPIO, IRQ3, FC_SHRD, USB2PHY_RST, NONE, NONE, NONE, R); 1211 LAN969X_P(13, GPIO, IRQ4, FC_SHRD, USB_OVER_DETECT, NONE, NONE, NONE, R); 1212 LAN969X_P(14, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); 1213 LAN969X_P(15, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); 1214 LAN969X_P(16, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); 1215 LAN969X_P(17, GPIO, EMMC_SD, QSPI1, PTPSYNC_0, USB_POWER, NONE, NONE, R); 1216 LAN969X_P(18, GPIO, EMMC_SD, QSPI1, PTPSYNC_1, USB2PHY_RST, NONE, NONE, R); 1217 LAN969X_P(19, GPIO, EMMC_SD, QSPI1, PTPSYNC_2, USB_OVER_DETECT, NONE, NONE, R); 1218 LAN969X_P(20, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); 1219 LAN969X_P(21, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); 1220 LAN969X_P(22, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); 1221 LAN969X_P(23, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); 1222 LAN969X_P(24, GPIO, EMMC_SD, NONE, NONE, NONE, NONE, NONE, R); 1223 LAN969X_P(25, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R); 1224 LAN969X_P(26, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R); 1225 LAN969X_P(27, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R); 1226 LAN969X_P(28, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R); 1227 LAN969X_P(29, GPIO, SYNCE, FC, MIIM_IRQ, QSPI1, NONE, NONE, R); 1228 LAN969X_P(30, GPIO, PTPSYNC_0, USB_ULPI, FC_SHRD, QSPI1, NONE, NONE, R); 1229 LAN969X_P(31, GPIO, PTPSYNC_1, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); 1230 LAN969X_P(32, GPIO, PTPSYNC_2, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); 1231 LAN969X_P(33, GPIO, SD, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); 1232 LAN969X_P(34, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R); 1233 LAN969X_P(35, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R); 1234 LAN969X_P(36, GPIO, SD, USB_ULPI, PCIE_PERST, FC_SHRD, NONE, NONE, R); 1235 LAN969X_P(37, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R); 1236 LAN969X_P(38, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R); 1237 LAN969X_P(39, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R); 1238 LAN969X_P(40, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R); 1239 LAN969X_P(41, GPIO, SD, USB_ULPI, MIIM_IRQ, NONE, NONE, NONE, R); 1240 LAN969X_P(42, GPIO, PTPSYNC_3, CAN1, NONE, NONE, NONE, NONE, R); 1241 LAN969X_P(43, GPIO, PTPSYNC_4, CAN1, NONE, NONE, NONE, NONE, R); 1242 LAN969X_P(44, GPIO, PTPSYNC_5, SFP_SD, NONE, NONE, NONE, NONE, R); 1243 LAN969X_P(45, GPIO, PTPSYNC_6, SFP_SD, NONE, NONE, NONE, NONE, R); 1244 LAN969X_P(46, GPIO, PTPSYNC_7, SFP_SD, NONE, NONE, NONE, NONE, R); 1245 LAN969X_P(47, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); 1246 LAN969X_P(48, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); 1247 LAN969X_P(49, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); 1248 LAN969X_P(50, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); 1249 LAN969X_P(51, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); 1250 LAN969X_P(52, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R); 1251 LAN969X_P(53, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R); 1252 LAN969X_P(54, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); 1253 LAN969X_P(55, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); 1254 LAN969X_P(56, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); 1255 LAN969X_P(57, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_3, NONE, NONE, R); 1256 LAN969X_P(58, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_4, NONE, NONE, R); 1257 LAN969X_P(59, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_5, NONE, NONE, R); 1258 LAN969X_P(60, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_6, NONE, NONE, R); 1259 LAN969X_P(61, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R); 1260 LAN969X_P(62, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R); 1261 LAN969X_P(63, GPIO, MIIM_IRQ, FC_SHRD, TWI, NONE, NONE, NONE, R); 1262 LAN969X_P(64, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); 1263 LAN969X_P(65, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); 1264 LAN969X_P(66, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); 1265 1266 #define LAN969X_PIN(n) { \ 1267 .number = n, \ 1268 .name = "GPIO_"#n, \ 1269 .drv_data = &lan969x_pin_##n \ 1270 } 1271 1272 static const struct pinctrl_pin_desc lan969x_pins[] = { 1273 LAN969X_PIN(0), 1274 LAN969X_PIN(1), 1275 LAN969X_PIN(2), 1276 LAN969X_PIN(3), 1277 LAN969X_PIN(4), 1278 LAN969X_PIN(5), 1279 LAN969X_PIN(6), 1280 LAN969X_PIN(7), 1281 LAN969X_PIN(8), 1282 LAN969X_PIN(9), 1283 LAN969X_PIN(10), 1284 LAN969X_PIN(11), 1285 LAN969X_PIN(12), 1286 LAN969X_PIN(13), 1287 LAN969X_PIN(14), 1288 LAN969X_PIN(15), 1289 LAN969X_PIN(16), 1290 LAN969X_PIN(17), 1291 LAN969X_PIN(18), 1292 LAN969X_PIN(19), 1293 LAN969X_PIN(20), 1294 LAN969X_PIN(21), 1295 LAN969X_PIN(22), 1296 LAN969X_PIN(23), 1297 LAN969X_PIN(24), 1298 LAN969X_PIN(25), 1299 LAN969X_PIN(26), 1300 LAN969X_PIN(27), 1301 LAN969X_PIN(28), 1302 LAN969X_PIN(29), 1303 LAN969X_PIN(30), 1304 LAN969X_PIN(31), 1305 LAN969X_PIN(32), 1306 LAN969X_PIN(33), 1307 LAN969X_PIN(34), 1308 LAN969X_PIN(35), 1309 LAN969X_PIN(36), 1310 LAN969X_PIN(37), 1311 LAN969X_PIN(38), 1312 LAN969X_PIN(39), 1313 LAN969X_PIN(40), 1314 LAN969X_PIN(41), 1315 LAN969X_PIN(42), 1316 LAN969X_PIN(43), 1317 LAN969X_PIN(44), 1318 LAN969X_PIN(45), 1319 LAN969X_PIN(46), 1320 LAN969X_PIN(47), 1321 LAN969X_PIN(48), 1322 LAN969X_PIN(49), 1323 LAN969X_PIN(50), 1324 LAN969X_PIN(51), 1325 LAN969X_PIN(52), 1326 LAN969X_PIN(53), 1327 LAN969X_PIN(54), 1328 LAN969X_PIN(55), 1329 LAN969X_PIN(56), 1330 LAN969X_PIN(57), 1331 LAN969X_PIN(58), 1332 LAN969X_PIN(59), 1333 LAN969X_PIN(60), 1334 LAN969X_PIN(61), 1335 LAN969X_PIN(62), 1336 LAN969X_PIN(63), 1337 LAN969X_PIN(64), 1338 LAN969X_PIN(65), 1339 LAN969X_PIN(66), 1340 }; 1341 1342 #define LAN9645X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 1343 static struct ocelot_pin_caps lan9645x_pin_##p = { \ 1344 .pin = p, \ 1345 .functions = { \ 1346 FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 1347 FUNC_##f3 \ 1348 }, \ 1349 .a_functions = { \ 1350 FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 1351 FUNC_##f7 \ 1352 }, \ 1353 } 1354 1355 /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 1356 LAN9645X_P(0, GPIO, SPI, SI_Sa, I2C_Sa, MIIM_Sa, UART, MIIM, PHY_DBG); 1357 LAN9645X_P(1, GPIO, SPI, SI_Sa, I2C_Sa, MIIM_Sa, UART, MIIM, PHY_DBG); 1358 LAN9645X_P(2, GPIO, SPI, SI_Sa, I2C, NONE, NONE, NONE, PHY_DBG); 1359 LAN9645X_P(3, GPIO, SPI, SI_Sa, I2C, MIIM_Sa, NONE, NONE, PHY_DBG); 1360 LAN9645X_P(4, GPIO, RGMII, TWI_SCL_M, I2C, NONE, NONE, SI_Sa, PHY_DBG); 1361 LAN9645X_P(5, GPIO, RGMII, TWI_SCL_M, I2C, NONE, NONE, SI_Sa, PHY_DBG); 1362 LAN9645X_P(6, GPIO, RGMII, TWI_SCL_M, NONE, NONE, NONE, SI_Sa, PHY_DBG); 1363 LAN9645X_P(7, GPIO, RGMII, TWI_SCL_M, SFP, SGPIO_a, MIIM, SI_Sa, PHY_DBG); 1364 LAN9645X_P(8, GPIO, RGMII, TWI_SCL_M, SFP, SGPIO_a, MIIM, NONE, PHY_DBG); 1365 LAN9645X_P(9, GPIO, RGMII, TWI_SCL_M, RECO_CLK, SGPIO_a, IRQ1, UART, PHY_DBG); 1366 LAN9645X_P(10, GPIO, RGMII, TWI_SCL_M, RECO_CLK, SGPIO_a, IRQ2, UART, PHY_DBG); 1367 LAN9645X_P(11, GPIO, RGMII, TWI_SCL_M, MIIM, NONE, IRQ3, NONE, PHY_DBG); 1368 LAN9645X_P(12, GPIO, RGMII, TWI_SCL_M, MIIM, PTP0, NONE, NONE, PHY_DBG); 1369 LAN9645X_P(13, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP1, MACLED, NONE, PHY_DBG); 1370 LAN9645X_P(14, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP2, MACLED, NONE, PHY_DBG); 1371 LAN9645X_P(15, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP3, NONE, NONE, PHY_DBG); 1372 LAN9645X_P(16, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1373 LAN9645X_P(17, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1374 LAN9645X_P(18, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1375 LAN9645X_P(19, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1376 LAN9645X_P(20, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1377 LAN9645X_P(21, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1378 LAN9645X_P(22, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1379 LAN9645X_P(23, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1380 LAN9645X_P(24, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1381 LAN9645X_P(25, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1382 LAN9645X_P(26, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1383 LAN9645X_P(27, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1384 LAN9645X_P(28, GPIO, RECO_CLK, MIIM, NONE, NONE, NONE, NONE, R); 1385 LAN9645X_P(29, GPIO, RECO_CLK, MIIM, NONE, NONE, NONE, NONE, R); 1386 LAN9645X_P(30, GPIO, PTP0, I2C, UART, NONE, NONE, NONE, R); 1387 LAN9645X_P(31, GPIO, PTP1, TWI_SCL_M, UART, NONE, NONE, NONE, R); 1388 LAN9645X_P(32, GPIO, PTP2, TWI_SCL_M, NONE, NONE, NONE, NONE, R); 1389 LAN9645X_P(33, GPIO, PTP3, IRQ0, NONE, NONE, NONE, NONE, R); 1390 LAN9645X_P(34, GPIO, RECO_CLK, PHY_LED, PHY_LED, NONE, NONE, NONE, R); 1391 LAN9645X_P(35, GPIO, RECO_CLK, PHY_LED, PHY_LED, NONE, MACLED, NONE, R); 1392 LAN9645X_P(36, GPIO, PTP0, PHY_LED, PHY_LED, NONE, MACLED, NONE, R); 1393 LAN9645X_P(37, GPIO, PTP1, PHY_LED, PHY_LED, NONE, MACLED, NONE, R); 1394 LAN9645X_P(38, GPIO, NONE, PHY_LED, PHY_LED, NONE, MACLED, NONE, R); 1395 LAN9645X_P(39, GPIO, UART, PHY_LED, NONE, NONE, MACLED, NONE, R); 1396 LAN9645X_P(40, GPIO, SPI, PHY_LED, SGPIO_a, NONE, MACLED, NONE, R); 1397 LAN9645X_P(41, GPIO, SPI, PHY_LED, SGPIO_a, IRQ1, MACLED, NONE, R); 1398 LAN9645X_P(42, GPIO, SPI, PHY_LED, SGPIO_a, IRQ2, MACLED, SFP, R); 1399 LAN9645X_P(43, GPIO, SPI, PHY_LED, SGPIO_a, IRQ3, MACLED, SFP, R); 1400 LAN9645X_P(44, GPIO, MIIM, I2C, NONE, NONE, NONE, NONE, R); 1401 LAN9645X_P(45, GPIO, MIIM, I2C, NONE, NONE, NONE, NONE, R); 1402 LAN9645X_P(46, GPIO, NONE, PHY_LED, NONE, NONE, NONE, NONE, R); 1403 LAN9645X_P(47, GPIO, NONE, PHY_LED, NONE, NONE, NONE, NONE, R); 1404 LAN9645X_P(48, GPIO, MIIM_Sa, PHY_LED, NONE, NONE, NONE, NONE, R); 1405 LAN9645X_P(49, GPIO, MIIM_Sa, PHY_LED, I2C_Sa, NONE, NONE, NONE, R); 1406 LAN9645X_P(50, GPIO, MIIM_Sa, PHY_LED, I2C_Sa, NONE, NONE, NONE, R); 1407 1408 #define LAN9645X_PIN(n) { \ 1409 .number = n, \ 1410 .name = "GPIO_"#n, \ 1411 .drv_data = &lan9645x_pin_##n \ 1412 } 1413 1414 static const struct pinctrl_pin_desc lan9645x_pins[] = { 1415 LAN9645X_PIN(0), 1416 LAN9645X_PIN(1), 1417 LAN9645X_PIN(2), 1418 LAN9645X_PIN(3), 1419 LAN9645X_PIN(4), 1420 LAN9645X_PIN(5), 1421 LAN9645X_PIN(6), 1422 LAN9645X_PIN(7), 1423 LAN9645X_PIN(8), 1424 LAN9645X_PIN(9), 1425 LAN9645X_PIN(10), 1426 LAN9645X_PIN(11), 1427 LAN9645X_PIN(12), 1428 LAN9645X_PIN(13), 1429 LAN9645X_PIN(14), 1430 LAN9645X_PIN(15), 1431 LAN9645X_PIN(16), 1432 LAN9645X_PIN(17), 1433 LAN9645X_PIN(18), 1434 LAN9645X_PIN(19), 1435 LAN9645X_PIN(20), 1436 LAN9645X_PIN(21), 1437 LAN9645X_PIN(22), 1438 LAN9645X_PIN(23), 1439 LAN9645X_PIN(24), 1440 LAN9645X_PIN(25), 1441 LAN9645X_PIN(26), 1442 LAN9645X_PIN(27), 1443 LAN9645X_PIN(28), 1444 LAN9645X_PIN(29), 1445 LAN9645X_PIN(30), 1446 LAN9645X_PIN(31), 1447 LAN9645X_PIN(32), 1448 LAN9645X_PIN(33), 1449 LAN9645X_PIN(34), 1450 LAN9645X_PIN(35), 1451 LAN9645X_PIN(36), 1452 LAN9645X_PIN(37), 1453 LAN9645X_PIN(38), 1454 LAN9645X_PIN(39), 1455 LAN9645X_PIN(40), 1456 LAN9645X_PIN(41), 1457 LAN9645X_PIN(42), 1458 LAN9645X_PIN(43), 1459 LAN9645X_PIN(44), 1460 LAN9645X_PIN(45), 1461 LAN9645X_PIN(46), 1462 LAN9645X_PIN(47), 1463 LAN9645X_PIN(48), 1464 LAN9645X_PIN(49), 1465 LAN9645X_PIN(50), 1466 }; 1467 1468 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1469 { 1470 return ARRAY_SIZE(ocelot_function_names); 1471 } 1472 1473 static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 1474 unsigned int function) 1475 { 1476 return ocelot_function_names[function]; 1477 } 1478 1479 static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 1480 unsigned int function, 1481 const char *const **groups, 1482 unsigned *const num_groups) 1483 { 1484 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1485 1486 *groups = info->func[function].groups; 1487 *num_groups = info->func[function].ngroups; 1488 1489 return 0; 1490 } 1491 1492 static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 1493 unsigned int pin, unsigned int function) 1494 { 1495 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 1496 int i; 1497 1498 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 1499 if (function == p->functions[i]) 1500 return i; 1501 1502 if (function == p->a_functions[i]) 1503 return i + OCELOT_FUNC_PER_PIN; 1504 } 1505 1506 return -1; 1507 } 1508 1509 #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->altm_stride * ((p) / 32)))) 1510 1511 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 1512 unsigned int selector, unsigned int group) 1513 { 1514 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1515 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1516 unsigned int p = pin->pin % 32; 1517 int f; 1518 1519 f = ocelot_pin_function_idx(info, group, selector); 1520 if (f < 0) 1521 return -EINVAL; 1522 1523 /* 1524 * f is encoded on two bits. 1525 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1526 * ALT[1] 1527 * This is racy because both registers can't be updated at the same time 1528 * but it doesn't matter much for now. 1529 * Note: ALT0/ALT1 are organized specially for 64 gpio targets 1530 */ 1531 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1532 BIT(p), f << p); 1533 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1534 BIT(p), (f >> 1) << p); 1535 1536 return 0; 1537 } 1538 1539 static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, 1540 unsigned int selector, unsigned int group) 1541 { 1542 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1543 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1544 unsigned int p = pin->pin % 32; 1545 int f; 1546 1547 f = ocelot_pin_function_idx(info, group, selector); 1548 if (f < 0) 1549 return -EINVAL; 1550 1551 /* 1552 * f is encoded on three bits. 1553 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1554 * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] 1555 * This is racy because three registers can't be updated at the same time 1556 * but it doesn't matter much for now. 1557 * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 1558 */ 1559 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1560 BIT(p), f << p); 1561 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1562 BIT(p), (f >> 1) << p); 1563 regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), 1564 BIT(p), (f >> 2) << p); 1565 1566 return 0; 1567 } 1568 1569 #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 1570 1571 static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 1572 struct pinctrl_gpio_range *range, 1573 unsigned int pin, bool input) 1574 { 1575 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1576 unsigned int p = pin % 32; 1577 1578 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 1579 input ? 0 : BIT(p)); 1580 1581 return 0; 1582 } 1583 1584 static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 1585 struct pinctrl_gpio_range *range, 1586 unsigned int offset) 1587 { 1588 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1589 unsigned int p = offset % 32; 1590 1591 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1592 BIT(p), 0); 1593 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1594 BIT(p), 0); 1595 1596 return 0; 1597 } 1598 1599 static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, 1600 struct pinctrl_gpio_range *range, 1601 unsigned int offset) 1602 { 1603 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1604 unsigned int p = offset % 32; 1605 1606 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1607 BIT(p), 0); 1608 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1609 BIT(p), 0); 1610 regmap_update_bits(info->map, REG_ALT(2, info, offset), 1611 BIT(p), 0); 1612 1613 return 0; 1614 } 1615 1616 static int lan9645x_gpio_request_enable(struct pinctrl_dev *pctldev, 1617 struct pinctrl_gpio_range *range, 1618 unsigned int offset) 1619 { 1620 return 0; 1621 } 1622 1623 static const struct pinmux_ops ocelot_pmx_ops = { 1624 .get_functions_count = ocelot_get_functions_count, 1625 .get_function_name = ocelot_get_function_name, 1626 .get_function_groups = ocelot_get_function_groups, 1627 .set_mux = ocelot_pinmux_set_mux, 1628 .gpio_set_direction = ocelot_gpio_set_direction, 1629 .gpio_request_enable = ocelot_gpio_request_enable, 1630 }; 1631 1632 static const struct pinmux_ops lan966x_pmx_ops = { 1633 .get_functions_count = ocelot_get_functions_count, 1634 .get_function_name = ocelot_get_function_name, 1635 .get_function_groups = ocelot_get_function_groups, 1636 .set_mux = lan966x_pinmux_set_mux, 1637 .gpio_set_direction = ocelot_gpio_set_direction, 1638 .gpio_request_enable = lan966x_gpio_request_enable, 1639 }; 1640 1641 static const struct pinmux_ops lan9645x_pmx_ops = { 1642 .get_functions_count = ocelot_get_functions_count, 1643 .get_function_name = ocelot_get_function_name, 1644 .get_function_groups = ocelot_get_function_groups, 1645 .set_mux = lan966x_pinmux_set_mux, 1646 .gpio_set_direction = ocelot_gpio_set_direction, 1647 .gpio_request_enable = lan9645x_gpio_request_enable, 1648 }; 1649 1650 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 1651 { 1652 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1653 1654 return info->desc->npins; 1655 } 1656 1657 static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 1658 unsigned int group) 1659 { 1660 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1661 1662 return info->desc->pins[group].name; 1663 } 1664 1665 static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 1666 unsigned int group, 1667 const unsigned int **pins, 1668 unsigned int *num_pins) 1669 { 1670 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1671 1672 *pins = &info->desc->pins[group].number; 1673 *num_pins = 1; 1674 1675 return 0; 1676 } 1677 1678 static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 1679 unsigned int pin, 1680 unsigned int reg, 1681 int *val) 1682 { 1683 int ret = -EOPNOTSUPP; 1684 1685 if (info->pincfg) { 1686 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1687 u32 regcfg; 1688 1689 ret = regmap_read(info->pincfg, 1690 pin * regmap_get_reg_stride(info->pincfg), 1691 ®cfg); 1692 if (ret) 1693 return ret; 1694 1695 ret = 0; 1696 switch (reg) { 1697 case PINCONF_BIAS: 1698 *val = regcfg & (opd->pd_bit | opd->pu_bit); 1699 break; 1700 1701 case PINCONF_SCHMITT: 1702 *val = regcfg & opd->schmitt_bit; 1703 break; 1704 1705 case PINCONF_DRIVE_STRENGTH: 1706 *val = regcfg & opd->drive_bits; 1707 break; 1708 1709 default: 1710 ret = -EOPNOTSUPP; 1711 break; 1712 } 1713 } 1714 return ret; 1715 } 1716 1717 static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, 1718 u32 clrbits, u32 setbits) 1719 { 1720 u32 val; 1721 int ret; 1722 1723 ret = regmap_read(info->pincfg, 1724 regaddr * regmap_get_reg_stride(info->pincfg), 1725 &val); 1726 if (ret) 1727 return ret; 1728 1729 val &= ~clrbits; 1730 val |= setbits; 1731 1732 ret = regmap_write(info->pincfg, 1733 regaddr * regmap_get_reg_stride(info->pincfg), 1734 val); 1735 1736 return ret; 1737 } 1738 1739 static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 1740 unsigned int pin, 1741 unsigned int reg, 1742 int val) 1743 { 1744 int ret = -EOPNOTSUPP; 1745 1746 if (info->pincfg) { 1747 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1748 1749 switch (reg) { 1750 case PINCONF_BIAS: 1751 ret = ocelot_pincfg_clrsetbits(info, pin, 1752 opd->pd_bit | opd->pu_bit, 1753 val); 1754 break; 1755 1756 case PINCONF_SCHMITT: 1757 ret = ocelot_pincfg_clrsetbits(info, pin, 1758 opd->schmitt_bit, 1759 val); 1760 break; 1761 1762 case PINCONF_DRIVE_STRENGTH: 1763 if (val <= 3) 1764 ret = ocelot_pincfg_clrsetbits(info, pin, 1765 opd->drive_bits, 1766 val); 1767 else 1768 ret = -EINVAL; 1769 break; 1770 1771 default: 1772 ret = -EOPNOTSUPP; 1773 break; 1774 } 1775 } 1776 return ret; 1777 } 1778 1779 static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 1780 unsigned int pin, unsigned long *config) 1781 { 1782 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1783 u32 param = pinconf_to_config_param(*config); 1784 int val, err; 1785 1786 switch (param) { 1787 case PIN_CONFIG_BIAS_DISABLE: 1788 case PIN_CONFIG_BIAS_PULL_UP: 1789 case PIN_CONFIG_BIAS_PULL_DOWN: 1790 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 1791 if (err) 1792 return err; 1793 if (param == PIN_CONFIG_BIAS_DISABLE) 1794 val = (val == 0); 1795 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1796 val = !!(val & info->pincfg_data->pd_bit); 1797 else /* PIN_CONFIG_BIAS_PULL_UP */ 1798 val = !!(val & info->pincfg_data->pu_bit); 1799 break; 1800 1801 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1802 if (!info->pincfg_data->schmitt_bit) 1803 return -EOPNOTSUPP; 1804 1805 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1806 if (err) 1807 return err; 1808 1809 val = !!(val & info->pincfg_data->schmitt_bit); 1810 break; 1811 1812 case PIN_CONFIG_DRIVE_STRENGTH: 1813 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 1814 &val); 1815 if (err) 1816 return err; 1817 break; 1818 1819 case PIN_CONFIG_LEVEL: 1820 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 1821 &val); 1822 if (err) 1823 return err; 1824 val = !!(val & BIT(pin % 32)); 1825 break; 1826 1827 case PIN_CONFIG_INPUT_ENABLE: 1828 case PIN_CONFIG_OUTPUT_ENABLE: 1829 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 1830 &val); 1831 if (err) 1832 return err; 1833 val = val & BIT(pin % 32); 1834 if (param == PIN_CONFIG_OUTPUT_ENABLE) 1835 val = !!val; 1836 else 1837 val = !val; 1838 break; 1839 1840 default: 1841 return -EOPNOTSUPP; 1842 } 1843 1844 *config = pinconf_to_config_packed(param, val); 1845 1846 return 0; 1847 } 1848 1849 static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1850 unsigned long *configs, unsigned int num_configs) 1851 { 1852 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1853 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1854 u32 param, arg, p; 1855 int cfg, err = 0; 1856 1857 for (cfg = 0; cfg < num_configs; cfg++) { 1858 param = pinconf_to_config_param(configs[cfg]); 1859 arg = pinconf_to_config_argument(configs[cfg]); 1860 1861 switch (param) { 1862 case PIN_CONFIG_BIAS_DISABLE: 1863 case PIN_CONFIG_BIAS_PULL_UP: 1864 case PIN_CONFIG_BIAS_PULL_DOWN: 1865 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1866 (param == PIN_CONFIG_BIAS_PULL_UP) ? 1867 opd->pu_bit : opd->pd_bit; 1868 1869 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1870 if (err) 1871 goto err; 1872 1873 break; 1874 1875 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1876 if (!opd->schmitt_bit) 1877 return -EOPNOTSUPP; 1878 1879 arg = arg ? opd->schmitt_bit : 0; 1880 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1881 arg); 1882 if (err) 1883 goto err; 1884 1885 break; 1886 1887 case PIN_CONFIG_DRIVE_STRENGTH: 1888 err = ocelot_hw_set_value(info, pin, 1889 PINCONF_DRIVE_STRENGTH, 1890 arg); 1891 if (err) 1892 goto err; 1893 1894 break; 1895 1896 case PIN_CONFIG_OUTPUT_ENABLE: 1897 case PIN_CONFIG_INPUT_ENABLE: 1898 case PIN_CONFIG_LEVEL: 1899 p = pin % 32; 1900 if (arg) 1901 regmap_write(info->map, 1902 REG(OCELOT_GPIO_OUT_SET, info, 1903 pin), 1904 BIT(p)); 1905 else 1906 regmap_write(info->map, 1907 REG(OCELOT_GPIO_OUT_CLR, info, 1908 pin), 1909 BIT(p)); 1910 regmap_update_bits(info->map, 1911 REG(OCELOT_GPIO_OE, info, pin), 1912 BIT(p), 1913 param == PIN_CONFIG_INPUT_ENABLE ? 1914 0 : BIT(p)); 1915 break; 1916 1917 default: 1918 err = -EOPNOTSUPP; 1919 } 1920 } 1921 err: 1922 return err; 1923 } 1924 1925 static const struct pinconf_ops ocelot_confops = { 1926 .is_generic = true, 1927 .pin_config_get = ocelot_pinconf_get, 1928 .pin_config_set = ocelot_pinconf_set, 1929 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1930 }; 1931 1932 static const struct pinctrl_ops ocelot_pctl_ops = { 1933 .get_groups_count = ocelot_pctl_get_groups_count, 1934 .get_group_name = ocelot_pctl_get_group_name, 1935 .get_group_pins = ocelot_pctl_get_group_pins, 1936 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1937 .dt_free_map = pinconf_generic_dt_free_map, 1938 }; 1939 1940 static const struct ocelot_match_data luton_desc = { 1941 .desc = { 1942 .name = "luton-pinctrl", 1943 .pins = luton_pins, 1944 .npins = ARRAY_SIZE(luton_pins), 1945 .pctlops = &ocelot_pctl_ops, 1946 .pmxops = &ocelot_pmx_ops, 1947 .owner = THIS_MODULE, 1948 }, 1949 }; 1950 1951 static const struct ocelot_match_data serval_desc = { 1952 .desc = { 1953 .name = "serval-pinctrl", 1954 .pins = serval_pins, 1955 .npins = ARRAY_SIZE(serval_pins), 1956 .pctlops = &ocelot_pctl_ops, 1957 .pmxops = &ocelot_pmx_ops, 1958 .owner = THIS_MODULE, 1959 }, 1960 }; 1961 1962 static const struct ocelot_match_data ocelot_desc = { 1963 .desc = { 1964 .name = "ocelot-pinctrl", 1965 .pins = ocelot_pins, 1966 .npins = ARRAY_SIZE(ocelot_pins), 1967 .pctlops = &ocelot_pctl_ops, 1968 .pmxops = &ocelot_pmx_ops, 1969 .owner = THIS_MODULE, 1970 }, 1971 }; 1972 1973 static const struct ocelot_match_data jaguar2_desc = { 1974 .desc = { 1975 .name = "jaguar2-pinctrl", 1976 .pins = jaguar2_pins, 1977 .npins = ARRAY_SIZE(jaguar2_pins), 1978 .pctlops = &ocelot_pctl_ops, 1979 .pmxops = &ocelot_pmx_ops, 1980 .owner = THIS_MODULE, 1981 }, 1982 }; 1983 1984 static const struct ocelot_match_data servalt_desc = { 1985 .desc = { 1986 .name = "servalt-pinctrl", 1987 .pins = servalt_pins, 1988 .npins = ARRAY_SIZE(servalt_pins), 1989 .pctlops = &ocelot_pctl_ops, 1990 .pmxops = &ocelot_pmx_ops, 1991 .owner = THIS_MODULE, 1992 }, 1993 }; 1994 1995 static const struct ocelot_match_data sparx5_desc = { 1996 .desc = { 1997 .name = "sparx5-pinctrl", 1998 .pins = sparx5_pins, 1999 .npins = ARRAY_SIZE(sparx5_pins), 2000 .pctlops = &ocelot_pctl_ops, 2001 .pmxops = &ocelot_pmx_ops, 2002 .confops = &ocelot_confops, 2003 .owner = THIS_MODULE, 2004 }, 2005 .pincfg_data = { 2006 .pd_bit = BIT(4), 2007 .pu_bit = BIT(3), 2008 .drive_bits = GENMASK(1, 0), 2009 .schmitt_bit = BIT(2), 2010 }, 2011 }; 2012 2013 static const struct ocelot_match_data lan966x_desc = { 2014 .desc = { 2015 .name = "lan966x-pinctrl", 2016 .pins = lan966x_pins, 2017 .npins = ARRAY_SIZE(lan966x_pins), 2018 .pctlops = &ocelot_pctl_ops, 2019 .pmxops = &lan966x_pmx_ops, 2020 .confops = &ocelot_confops, 2021 .owner = THIS_MODULE, 2022 }, 2023 .pincfg_data = { 2024 .pd_bit = BIT(3), 2025 .pu_bit = BIT(2), 2026 .drive_bits = GENMASK(1, 0), 2027 }, 2028 }; 2029 2030 static const struct ocelot_match_data lan969x_desc = { 2031 .desc = { 2032 .name = "lan969x-pinctrl", 2033 .pins = lan969x_pins, 2034 .npins = ARRAY_SIZE(lan969x_pins), 2035 .pctlops = &ocelot_pctl_ops, 2036 .pmxops = &lan966x_pmx_ops, 2037 .confops = &ocelot_confops, 2038 .owner = THIS_MODULE, 2039 }, 2040 .pincfg_data = { 2041 .pd_bit = BIT(3), 2042 .pu_bit = BIT(2), 2043 .drive_bits = GENMASK(1, 0), 2044 }, 2045 }; 2046 2047 static struct ocelot_match_data lan9645xf_desc = { 2048 .desc = { 2049 .name = "lan9645xf-pinctrl", 2050 .pins = lan9645x_pins, 2051 .npins = ARRAY_SIZE(lan9645x_pins), 2052 .pctlops = &ocelot_pctl_ops, 2053 .pmxops = &lan9645x_pmx_ops, 2054 .confops = &ocelot_confops, 2055 .owner = THIS_MODULE, 2056 }, 2057 .pincfg_data = { 2058 .pd_bit = BIT(3), 2059 .pu_bit = BIT(2), 2060 .drive_bits = GENMASK(1, 0), 2061 }, 2062 .n_alt_modes = 7, 2063 }; 2064 2065 static int ocelot_create_group_func_map(struct device *dev, 2066 struct ocelot_pinctrl *info) 2067 { 2068 int f, npins, i; 2069 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 2070 2071 if (!pins) 2072 return -ENOMEM; 2073 2074 for (f = 0; f < FUNC_MAX; f++) { 2075 for (npins = 0, i = 0; i < info->desc->npins; i++) { 2076 if (ocelot_pin_function_idx(info, i, f) >= 0) 2077 pins[npins++] = i; 2078 } 2079 2080 if (!npins) 2081 continue; 2082 2083 info->func[f].ngroups = npins; 2084 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 2085 GFP_KERNEL); 2086 if (!info->func[f].groups) { 2087 kfree(pins); 2088 return -ENOMEM; 2089 } 2090 2091 for (i = 0; i < npins; i++) 2092 info->func[f].groups[i] = 2093 info->desc->pins[pins[i]].name; 2094 } 2095 2096 kfree(pins); 2097 2098 return 0; 2099 } 2100 2101 static int ocelot_pinctrl_register(struct platform_device *pdev, 2102 struct ocelot_pinctrl *info) 2103 { 2104 int ret; 2105 2106 ret = ocelot_create_group_func_map(&pdev->dev, info); 2107 if (ret) { 2108 dev_err(&pdev->dev, "Unable to create group func map.\n"); 2109 return ret; 2110 } 2111 2112 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 2113 if (IS_ERR(info->pctl)) { 2114 dev_err(&pdev->dev, "Failed to register pinctrl\n"); 2115 return PTR_ERR(info->pctl); 2116 } 2117 2118 return 0; 2119 } 2120 2121 static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 2122 { 2123 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2124 unsigned int val; 2125 2126 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 2127 2128 return !!(val & BIT(offset % 32)); 2129 } 2130 2131 static int ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 2132 int value) 2133 { 2134 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2135 2136 if (value) 2137 return regmap_write(info->map, 2138 REG(OCELOT_GPIO_OUT_SET, info, offset), 2139 BIT(offset % 32)); 2140 2141 return regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 2142 BIT(offset % 32)); 2143 } 2144 2145 static int ocelot_gpio_get_direction(struct gpio_chip *chip, 2146 unsigned int offset) 2147 { 2148 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2149 unsigned int val; 2150 2151 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 2152 2153 if (val & BIT(offset % 32)) 2154 return GPIO_LINE_DIRECTION_OUT; 2155 2156 return GPIO_LINE_DIRECTION_IN; 2157 } 2158 2159 static int ocelot_gpio_direction_output(struct gpio_chip *chip, 2160 unsigned int offset, int value) 2161 { 2162 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2163 unsigned int pin = BIT(offset % 32); 2164 2165 if (value) 2166 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 2167 pin); 2168 else 2169 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 2170 pin); 2171 2172 return pinctrl_gpio_direction_output(chip, offset); 2173 } 2174 2175 static const struct gpio_chip ocelot_gpiolib_chip = { 2176 .request = gpiochip_generic_request, 2177 .free = gpiochip_generic_free, 2178 .set = ocelot_gpio_set, 2179 .get = ocelot_gpio_get, 2180 .get_direction = ocelot_gpio_get_direction, 2181 .direction_input = pinctrl_gpio_direction_input, 2182 .direction_output = ocelot_gpio_direction_output, 2183 .owner = THIS_MODULE, 2184 }; 2185 2186 static void ocelot_irq_mask(struct irq_data *data) 2187 { 2188 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 2189 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2190 unsigned int gpio = irqd_to_hwirq(data); 2191 2192 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 2193 BIT(gpio % 32), 0); 2194 gpiochip_disable_irq(chip, gpio); 2195 } 2196 2197 static void ocelot_irq_work(struct work_struct *work) 2198 { 2199 struct ocelot_irq_work *w = container_of(work, struct ocelot_irq_work, irq_work); 2200 struct irq_chip *parent_chip = irq_desc_get_chip(w->irq_desc); 2201 struct gpio_chip *chip = irq_desc_get_chip_data(w->irq_desc); 2202 struct irq_data *data = irq_desc_get_irq_data(w->irq_desc); 2203 unsigned int gpio = irqd_to_hwirq(data); 2204 2205 local_irq_disable(); 2206 chained_irq_enter(parent_chip, w->irq_desc); 2207 generic_handle_domain_irq(chip->irq.domain, gpio); 2208 chained_irq_exit(parent_chip, w->irq_desc); 2209 local_irq_enable(); 2210 2211 kfree(w); 2212 } 2213 2214 static void ocelot_irq_unmask_level(struct irq_data *data) 2215 { 2216 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 2217 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2218 struct irq_desc *desc = irq_data_to_desc(data); 2219 unsigned int gpio = irqd_to_hwirq(data); 2220 unsigned int bit = BIT(gpio % 32); 2221 bool ack = false, active = false; 2222 u8 trigger_level; 2223 int val; 2224 2225 trigger_level = irqd_get_trigger_type(data); 2226 2227 /* Check if the interrupt line is still active. */ 2228 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val); 2229 if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) || 2230 (val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH)) 2231 active = true; 2232 2233 /* 2234 * Check if the interrupt controller has seen any changes in the 2235 * interrupt line. 2236 */ 2237 regmap_read(info->map, REG(OCELOT_GPIO_INTR, info, gpio), &val); 2238 if (val & bit) 2239 ack = true; 2240 2241 /* Try to clear any rising edges */ 2242 if (!active && ack) 2243 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 2244 bit, bit); 2245 2246 /* Enable the interrupt now */ 2247 gpiochip_enable_irq(chip, gpio); 2248 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 2249 bit, bit); 2250 2251 /* 2252 * In case the interrupt line is still active then it means that 2253 * there happen another interrupt while the line was active. 2254 * So we missed that one, so we need to kick the interrupt again 2255 * handler. 2256 */ 2257 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val); 2258 if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) || 2259 (val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH)) 2260 active = true; 2261 2262 if (active) { 2263 struct ocelot_irq_work *work; 2264 2265 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2266 if (!work) 2267 return; 2268 2269 work->irq_desc = desc; 2270 INIT_WORK(&work->irq_work, ocelot_irq_work); 2271 queue_work(info->wq, &work->irq_work); 2272 } 2273 } 2274 2275 static void ocelot_irq_unmask(struct irq_data *data) 2276 { 2277 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 2278 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2279 unsigned int gpio = irqd_to_hwirq(data); 2280 2281 gpiochip_enable_irq(chip, gpio); 2282 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 2283 BIT(gpio % 32), BIT(gpio % 32)); 2284 } 2285 2286 static void ocelot_irq_ack(struct irq_data *data) 2287 { 2288 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 2289 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2290 unsigned int gpio = irqd_to_hwirq(data); 2291 2292 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 2293 BIT(gpio % 32), BIT(gpio % 32)); 2294 } 2295 2296 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 2297 2298 static const struct irq_chip ocelot_level_irqchip = { 2299 .name = "gpio", 2300 .irq_mask = ocelot_irq_mask, 2301 .irq_ack = ocelot_irq_ack, 2302 .irq_unmask = ocelot_irq_unmask_level, 2303 .flags = IRQCHIP_IMMUTABLE, 2304 .irq_set_type = ocelot_irq_set_type, 2305 GPIOCHIP_IRQ_RESOURCE_HELPERS 2306 }; 2307 2308 static const struct irq_chip ocelot_irqchip = { 2309 .name = "gpio", 2310 .irq_mask = ocelot_irq_mask, 2311 .irq_ack = ocelot_irq_ack, 2312 .irq_unmask = ocelot_irq_unmask, 2313 .irq_set_type = ocelot_irq_set_type, 2314 .flags = IRQCHIP_IMMUTABLE, 2315 GPIOCHIP_IRQ_RESOURCE_HELPERS 2316 }; 2317 2318 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 2319 { 2320 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 2321 irq_set_chip_handler_name_locked(data, &ocelot_level_irqchip, 2322 handle_level_irq, NULL); 2323 if (type & IRQ_TYPE_EDGE_BOTH) 2324 irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 2325 handle_edge_irq, NULL); 2326 2327 return 0; 2328 } 2329 2330 static void ocelot_irq_handler(struct irq_desc *desc) 2331 { 2332 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 2333 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 2334 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2335 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 2336 unsigned int reg = 0, irq, i; 2337 unsigned long irqs; 2338 2339 chained_irq_enter(parent_chip, desc); 2340 2341 for (i = 0; i < info->stride; i++) { 2342 regmap_read(info->map, id_reg + 4 * i, ®); 2343 if (!reg) 2344 continue; 2345 2346 irqs = reg; 2347 2348 for_each_set_bit(irq, &irqs, 2349 min(32U, info->desc->npins - 32 * i)) 2350 generic_handle_domain_irq(chip->irq.domain, irq + 32 * i); 2351 } 2352 2353 chained_irq_exit(parent_chip, desc); 2354 } 2355 2356 static int ocelot_gpiochip_register(struct platform_device *pdev, 2357 struct ocelot_pinctrl *info) 2358 { 2359 struct gpio_chip *gc; 2360 struct gpio_irq_chip *girq; 2361 int irq; 2362 2363 info->gpio_chip = ocelot_gpiolib_chip; 2364 2365 gc = &info->gpio_chip; 2366 gc->ngpio = info->desc->npins; 2367 gc->parent = &pdev->dev; 2368 gc->base = -1; 2369 gc->label = "ocelot-gpio"; 2370 2371 irq = platform_get_irq_optional(pdev, 0); 2372 if (irq > 0) { 2373 girq = &gc->irq; 2374 gpio_irq_chip_set_chip(girq, &ocelot_irqchip); 2375 girq->parent_handler = ocelot_irq_handler; 2376 girq->num_parents = 1; 2377 girq->parents = devm_kcalloc(&pdev->dev, 1, 2378 sizeof(*girq->parents), 2379 GFP_KERNEL); 2380 if (!girq->parents) 2381 return -ENOMEM; 2382 girq->parents[0] = irq; 2383 girq->default_type = IRQ_TYPE_NONE; 2384 girq->handler = handle_edge_irq; 2385 } 2386 2387 return devm_gpiochip_add_data(&pdev->dev, gc, info); 2388 } 2389 2390 static const struct of_device_id ocelot_pinctrl_of_match[] = { 2391 { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, 2392 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, 2393 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 2394 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 2395 { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, 2396 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 2397 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 2398 { .compatible = "microchip,lan9691-pinctrl", .data = &lan969x_desc }, 2399 { .compatible = "microchip,lan96455f-pinctrl", .data = &lan9645xf_desc }, 2400 {}, 2401 }; 2402 MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match); 2403 2404 static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev, 2405 const struct ocelot_pinctrl *info) 2406 { 2407 void __iomem *base; 2408 2409 const struct regmap_config regmap_config = { 2410 .reg_bits = 32, 2411 .val_bits = 32, 2412 .reg_stride = 4, 2413 .max_register = info->desc->npins * 4, 2414 .name = "pincfg", 2415 }; 2416 2417 base = devm_platform_ioremap_resource(pdev, 1); 2418 if (IS_ERR(base)) { 2419 dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); 2420 return NULL; 2421 } 2422 2423 return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); 2424 } 2425 2426 static void ocelot_destroy_workqueue(void *data) 2427 { 2428 destroy_workqueue(data); 2429 } 2430 2431 static int ocelot_pinctrl_probe(struct platform_device *pdev) 2432 { 2433 const struct ocelot_match_data *data; 2434 struct device *dev = &pdev->dev; 2435 struct ocelot_pinctrl *info; 2436 struct reset_control *reset; 2437 struct regmap *pincfg; 2438 int ret; 2439 struct regmap_config regmap_config = { 2440 .reg_bits = 32, 2441 .val_bits = 32, 2442 .reg_stride = 4, 2443 }; 2444 2445 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 2446 if (!info) 2447 return -ENOMEM; 2448 2449 data = device_get_match_data(dev); 2450 if (!data) 2451 return -EINVAL; 2452 2453 info->desc = devm_kmemdup(dev, &data->desc, sizeof(*info->desc), 2454 GFP_KERNEL); 2455 if (!info->desc) 2456 return -ENOMEM; 2457 2458 info->wq = alloc_ordered_workqueue("ocelot_ordered", 0); 2459 if (!info->wq) 2460 return -ENOMEM; 2461 2462 ret = devm_add_action_or_reset(dev, ocelot_destroy_workqueue, 2463 info->wq); 2464 if (ret) 2465 return ret; 2466 2467 info->pincfg_data = &data->pincfg_data; 2468 2469 reset = devm_reset_control_get_optional_shared(dev, "switch"); 2470 if (IS_ERR(reset)) 2471 return dev_err_probe(dev, PTR_ERR(reset), 2472 "Failed to get reset\n"); 2473 reset_control_reset(reset); 2474 2475 info->stride = 1 + (info->desc->npins - 1) / 32; 2476 info->altm_stride = info->stride; 2477 if (data->n_alt_modes) 2478 info->altm_stride = fls(data->n_alt_modes); 2479 2480 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 2481 2482 info->map = ocelot_regmap_from_resource(pdev, 0, ®map_config); 2483 if (IS_ERR(info->map)) 2484 return dev_err_probe(dev, PTR_ERR(info->map), 2485 "Failed to create regmap\n"); 2486 dev_set_drvdata(dev, info); 2487 info->dev = dev; 2488 2489 /* Pinconf registers */ 2490 if (info->desc->confops) { 2491 pincfg = ocelot_pinctrl_create_pincfg(pdev, info); 2492 if (IS_ERR(pincfg)) 2493 dev_dbg(dev, "Failed to create pincfg regmap\n"); 2494 else 2495 info->pincfg = pincfg; 2496 } 2497 2498 ret = ocelot_pinctrl_register(pdev, info); 2499 if (ret) 2500 return ret; 2501 2502 ret = ocelot_gpiochip_register(pdev, info); 2503 if (ret) 2504 return ret; 2505 2506 dev_info(dev, "driver registered\n"); 2507 2508 return 0; 2509 } 2510 2511 static struct platform_driver ocelot_pinctrl_driver = { 2512 .driver = { 2513 .name = "pinctrl-ocelot", 2514 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 2515 .suppress_bind_attrs = true, 2516 }, 2517 .probe = ocelot_pinctrl_probe, 2518 }; 2519 module_platform_driver(ocelot_pinctrl_driver); 2520 2521 MODULE_DESCRIPTION("Ocelot Chip Pinctrl Driver"); 2522 MODULE_LICENSE("Dual MIT/GPL"); 2523