1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi SoCs pinctrl driver 4 * 5 * Author: <alexandre.belloni@free-electrons.com> 6 * License: Dual MIT/GPL 7 * Copyright (c) 2017 Microsemi Corporation 8 */ 9 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/mfd/ocelot.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 #include <linux/slab.h> 19 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 26 #include "core.h" 27 #include "pinconf.h" 28 #include "pinmux.h" 29 30 #define ocelot_clrsetbits(addr, clear, set) \ 31 writel((readl(addr) & ~(clear)) | (set), (addr)) 32 33 enum { 34 PINCONF_BIAS, 35 PINCONF_SCHMITT, 36 PINCONF_DRIVE_STRENGTH, 37 }; 38 39 /* GPIO standard registers */ 40 #define OCELOT_GPIO_OUT_SET 0x0 41 #define OCELOT_GPIO_OUT_CLR 0x4 42 #define OCELOT_GPIO_OUT 0x8 43 #define OCELOT_GPIO_IN 0xc 44 #define OCELOT_GPIO_OE 0x10 45 #define OCELOT_GPIO_INTR 0x14 46 #define OCELOT_GPIO_INTR_ENA 0x18 47 #define OCELOT_GPIO_INTR_IDENT 0x1c 48 #define OCELOT_GPIO_ALT0 0x20 49 #define OCELOT_GPIO_ALT1 0x24 50 #define OCELOT_GPIO_SD_MAP 0x28 51 52 #define OCELOT_FUNC_PER_PIN 4 53 54 enum { 55 FUNC_CAN0_a, 56 FUNC_CAN0_b, 57 FUNC_CAN1, 58 FUNC_CLKMON, 59 FUNC_NONE, 60 FUNC_FAN, 61 FUNC_FC, 62 FUNC_FC0_a, 63 FUNC_FC0_b, 64 FUNC_FC0_c, 65 FUNC_FC1_a, 66 FUNC_FC1_b, 67 FUNC_FC1_c, 68 FUNC_FC2_a, 69 FUNC_FC2_b, 70 FUNC_FC3_a, 71 FUNC_FC3_b, 72 FUNC_FC3_c, 73 FUNC_FC4_a, 74 FUNC_FC4_b, 75 FUNC_FC4_c, 76 FUNC_FC_SHRD, 77 FUNC_FC_SHRD0, 78 FUNC_FC_SHRD1, 79 FUNC_FC_SHRD2, 80 FUNC_FC_SHRD3, 81 FUNC_FC_SHRD4, 82 FUNC_FC_SHRD5, 83 FUNC_FC_SHRD6, 84 FUNC_FC_SHRD7, 85 FUNC_FC_SHRD8, 86 FUNC_FC_SHRD9, 87 FUNC_FC_SHRD10, 88 FUNC_FC_SHRD11, 89 FUNC_FC_SHRD12, 90 FUNC_FC_SHRD13, 91 FUNC_FC_SHRD14, 92 FUNC_FC_SHRD15, 93 FUNC_FC_SHRD16, 94 FUNC_FC_SHRD17, 95 FUNC_FC_SHRD18, 96 FUNC_FC_SHRD19, 97 FUNC_FC_SHRD20, 98 FUNC_FUSA, 99 FUNC_GPIO, 100 FUNC_IB_TRG_a, 101 FUNC_IB_TRG_b, 102 FUNC_IB_TRG_c, 103 FUNC_IRQ0, 104 FUNC_IRQ_IN_a, 105 FUNC_IRQ_IN_b, 106 FUNC_IRQ_IN_c, 107 FUNC_IRQ0_IN, 108 FUNC_IRQ_OUT_a, 109 FUNC_IRQ_OUT_b, 110 FUNC_IRQ_OUT_c, 111 FUNC_IRQ0_OUT, 112 FUNC_IRQ1, 113 FUNC_IRQ1_IN, 114 FUNC_IRQ1_OUT, 115 FUNC_IRQ3, 116 FUNC_IRQ4, 117 FUNC_EXT_IRQ, 118 FUNC_MIIM, 119 FUNC_MIIM_a, 120 FUNC_MIIM_b, 121 FUNC_MIIM_c, 122 FUNC_MIIM_Sa, 123 FUNC_MIIM_Sb, 124 FUNC_MIIM_IRQ, 125 FUNC_OB_TRG, 126 FUNC_OB_TRG_a, 127 FUNC_OB_TRG_b, 128 FUNC_PHY_LED, 129 FUNC_PCI_WAKE, 130 FUNC_MD, 131 FUNC_PCIE_PERST, 132 FUNC_PTP0, 133 FUNC_PTP1, 134 FUNC_PTP2, 135 FUNC_PTP3, 136 FUNC_PTPSYNC_0, 137 FUNC_PTPSYNC_1, 138 FUNC_PTPSYNC_2, 139 FUNC_PTPSYNC_3, 140 FUNC_PTPSYNC_4, 141 FUNC_PTPSYNC_5, 142 FUNC_PTPSYNC_6, 143 FUNC_PTPSYNC_7, 144 FUNC_PWM, 145 FUNC_PWM_a, 146 FUNC_PWM_b, 147 FUNC_QSPI1, 148 FUNC_QSPI2, 149 FUNC_R, 150 FUNC_RECO_a, 151 FUNC_RECO_b, 152 FUNC_RECO_CLK, 153 FUNC_SD, 154 FUNC_SFP, 155 FUNC_SFP_SD, 156 FUNC_SG0, 157 FUNC_SG1, 158 FUNC_SG2, 159 FUNC_SGPIO_a, 160 FUNC_SGPIO_b, 161 FUNC_SI, 162 FUNC_SI2, 163 FUNC_SYNCE, 164 FUNC_TACHO, 165 FUNC_TACHO_a, 166 FUNC_TACHO_b, 167 FUNC_TWI, 168 FUNC_TWI2, 169 FUNC_TWI3, 170 FUNC_TWI_SCL_M, 171 FUNC_TWI_SLC_GATE, 172 FUNC_TWI_SLC_GATE_AD, 173 FUNC_UART, 174 FUNC_UART2, 175 FUNC_UART3, 176 FUNC_USB_H_a, 177 FUNC_USB_H_b, 178 FUNC_USB_H_c, 179 FUNC_USB_S_a, 180 FUNC_USB_S_b, 181 FUNC_USB_S_c, 182 FUNC_USB_POWER, 183 FUNC_USB2PHY_RST, 184 FUNC_USB_OVER_DETECT, 185 FUNC_USB_ULPI, 186 FUNC_PLL_STAT, 187 FUNC_EMMC, 188 FUNC_EMMC_SD, 189 FUNC_REF_CLK, 190 FUNC_RCVRD_CLK, 191 FUNC_MAX 192 }; 193 194 static const char *const ocelot_function_names[] = { 195 [FUNC_CAN0_a] = "can0_a", 196 [FUNC_CAN0_b] = "can0_b", 197 [FUNC_CAN1] = "can1", 198 [FUNC_CLKMON] = "clkmon", 199 [FUNC_NONE] = "none", 200 [FUNC_FAN] = "fan", 201 [FUNC_FC] = "fc", 202 [FUNC_FC0_a] = "fc0_a", 203 [FUNC_FC0_b] = "fc0_b", 204 [FUNC_FC0_c] = "fc0_c", 205 [FUNC_FC1_a] = "fc1_a", 206 [FUNC_FC1_b] = "fc1_b", 207 [FUNC_FC1_c] = "fc1_c", 208 [FUNC_FC2_a] = "fc2_a", 209 [FUNC_FC2_b] = "fc2_b", 210 [FUNC_FC3_a] = "fc3_a", 211 [FUNC_FC3_b] = "fc3_b", 212 [FUNC_FC3_c] = "fc3_c", 213 [FUNC_FC4_a] = "fc4_a", 214 [FUNC_FC4_b] = "fc4_b", 215 [FUNC_FC4_c] = "fc4_c", 216 [FUNC_FC_SHRD] = "fc_shrd", 217 [FUNC_FC_SHRD0] = "fc_shrd0", 218 [FUNC_FC_SHRD1] = "fc_shrd1", 219 [FUNC_FC_SHRD2] = "fc_shrd2", 220 [FUNC_FC_SHRD3] = "fc_shrd3", 221 [FUNC_FC_SHRD4] = "fc_shrd4", 222 [FUNC_FC_SHRD5] = "fc_shrd5", 223 [FUNC_FC_SHRD6] = "fc_shrd6", 224 [FUNC_FC_SHRD7] = "fc_shrd7", 225 [FUNC_FC_SHRD8] = "fc_shrd8", 226 [FUNC_FC_SHRD9] = "fc_shrd9", 227 [FUNC_FC_SHRD10] = "fc_shrd10", 228 [FUNC_FC_SHRD11] = "fc_shrd11", 229 [FUNC_FC_SHRD12] = "fc_shrd12", 230 [FUNC_FC_SHRD13] = "fc_shrd13", 231 [FUNC_FC_SHRD14] = "fc_shrd14", 232 [FUNC_FC_SHRD15] = "fc_shrd15", 233 [FUNC_FC_SHRD16] = "fc_shrd16", 234 [FUNC_FC_SHRD17] = "fc_shrd17", 235 [FUNC_FC_SHRD18] = "fc_shrd18", 236 [FUNC_FC_SHRD19] = "fc_shrd19", 237 [FUNC_FC_SHRD20] = "fc_shrd20", 238 [FUNC_FUSA] = "fusa", 239 [FUNC_GPIO] = "gpio", 240 [FUNC_IB_TRG_a] = "ib_trig_a", 241 [FUNC_IB_TRG_b] = "ib_trig_b", 242 [FUNC_IB_TRG_c] = "ib_trig_c", 243 [FUNC_IRQ0] = "irq0", 244 [FUNC_IRQ_IN_a] = "irq_in_a", 245 [FUNC_IRQ_IN_b] = "irq_in_b", 246 [FUNC_IRQ_IN_c] = "irq_in_c", 247 [FUNC_IRQ0_IN] = "irq0_in", 248 [FUNC_IRQ_OUT_a] = "irq_out_a", 249 [FUNC_IRQ_OUT_b] = "irq_out_b", 250 [FUNC_IRQ_OUT_c] = "irq_out_c", 251 [FUNC_IRQ0_OUT] = "irq0_out", 252 [FUNC_IRQ1] = "irq1", 253 [FUNC_IRQ1_IN] = "irq1_in", 254 [FUNC_IRQ1_OUT] = "irq1_out", 255 [FUNC_IRQ3] = "irq3", 256 [FUNC_IRQ4] = "irq4", 257 [FUNC_EXT_IRQ] = "ext_irq", 258 [FUNC_MIIM] = "miim", 259 [FUNC_MIIM_a] = "miim_a", 260 [FUNC_MIIM_b] = "miim_b", 261 [FUNC_MIIM_c] = "miim_c", 262 [FUNC_MIIM_Sa] = "miim_slave_a", 263 [FUNC_MIIM_Sb] = "miim_slave_b", 264 [FUNC_MIIM_IRQ] = "miim_irq", 265 [FUNC_PHY_LED] = "phy_led", 266 [FUNC_PCI_WAKE] = "pci_wake", 267 [FUNC_PCIE_PERST] = "pcie_perst", 268 [FUNC_MD] = "md", 269 [FUNC_OB_TRG] = "ob_trig", 270 [FUNC_OB_TRG_a] = "ob_trig_a", 271 [FUNC_OB_TRG_b] = "ob_trig_b", 272 [FUNC_PTP0] = "ptp0", 273 [FUNC_PTP1] = "ptp1", 274 [FUNC_PTP2] = "ptp2", 275 [FUNC_PTP3] = "ptp3", 276 [FUNC_PTPSYNC_0] = "ptpsync_0", 277 [FUNC_PTPSYNC_1] = "ptpsync_1", 278 [FUNC_PTPSYNC_2] = "ptpsync_2", 279 [FUNC_PTPSYNC_3] = "ptpsync_3", 280 [FUNC_PTPSYNC_4] = "ptpsync_4", 281 [FUNC_PTPSYNC_5] = "ptpsync_5", 282 [FUNC_PTPSYNC_6] = "ptpsync_6", 283 [FUNC_PTPSYNC_7] = "ptpsync_7", 284 [FUNC_PWM] = "pwm", 285 [FUNC_PWM_a] = "pwm_a", 286 [FUNC_PWM_b] = "pwm_b", 287 [FUNC_QSPI1] = "qspi1", 288 [FUNC_QSPI2] = "qspi2", 289 [FUNC_R] = "reserved", 290 [FUNC_RECO_a] = "reco_a", 291 [FUNC_RECO_b] = "reco_b", 292 [FUNC_RECO_CLK] = "reco_clk", 293 [FUNC_SD] = "sd", 294 [FUNC_SFP] = "sfp", 295 [FUNC_SFP_SD] = "sfp_sd", 296 [FUNC_SG0] = "sg0", 297 [FUNC_SG1] = "sg1", 298 [FUNC_SG2] = "sg2", 299 [FUNC_SGPIO_a] = "sgpio_a", 300 [FUNC_SGPIO_b] = "sgpio_b", 301 [FUNC_SI] = "si", 302 [FUNC_SI2] = "si2", 303 [FUNC_SYNCE] = "synce", 304 [FUNC_TACHO] = "tacho", 305 [FUNC_TACHO_a] = "tacho_a", 306 [FUNC_TACHO_b] = "tacho_b", 307 [FUNC_TWI] = "twi", 308 [FUNC_TWI2] = "twi2", 309 [FUNC_TWI3] = "twi3", 310 [FUNC_TWI_SCL_M] = "twi_scl_m", 311 [FUNC_TWI_SLC_GATE] = "twi_slc_gate", 312 [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", 313 [FUNC_USB_H_a] = "usb_host_a", 314 [FUNC_USB_H_b] = "usb_host_b", 315 [FUNC_USB_H_c] = "usb_host_c", 316 [FUNC_USB_S_a] = "usb_slave_a", 317 [FUNC_USB_S_b] = "usb_slave_b", 318 [FUNC_USB_S_c] = "usb_slave_c", 319 [FUNC_USB_POWER] = "usb_power", 320 [FUNC_USB2PHY_RST] = "usb2phy_rst", 321 [FUNC_USB_OVER_DETECT] = "usb_over_detect", 322 [FUNC_USB_ULPI] = "usb_ulpi", 323 [FUNC_UART] = "uart", 324 [FUNC_UART2] = "uart2", 325 [FUNC_UART3] = "uart3", 326 [FUNC_PLL_STAT] = "pll_stat", 327 [FUNC_EMMC] = "emmc", 328 [FUNC_EMMC_SD] = "emmc_sd", 329 [FUNC_REF_CLK] = "ref_clk", 330 [FUNC_RCVRD_CLK] = "rcvrd_clk", 331 }; 332 333 struct ocelot_pmx_func { 334 const char **groups; 335 unsigned int ngroups; 336 }; 337 338 struct ocelot_pin_caps { 339 unsigned int pin; 340 unsigned char functions[OCELOT_FUNC_PER_PIN]; 341 unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 342 }; 343 344 struct ocelot_pincfg_data { 345 u8 pd_bit; 346 u8 pu_bit; 347 u8 drive_bits; 348 u8 schmitt_bit; 349 }; 350 351 struct ocelot_pinctrl { 352 struct device *dev; 353 struct pinctrl_dev *pctl; 354 struct gpio_chip gpio_chip; 355 struct regmap *map; 356 struct regmap *pincfg; 357 struct pinctrl_desc *desc; 358 const struct ocelot_pincfg_data *pincfg_data; 359 struct ocelot_pmx_func func[FUNC_MAX]; 360 u8 stride; 361 struct workqueue_struct *wq; 362 }; 363 364 struct ocelot_match_data { 365 struct pinctrl_desc desc; 366 struct ocelot_pincfg_data pincfg_data; 367 }; 368 369 struct ocelot_irq_work { 370 struct work_struct irq_work; 371 struct irq_desc *irq_desc; 372 }; 373 374 #define LUTON_P(p, f0, f1) \ 375 static struct ocelot_pin_caps luton_pin_##p = { \ 376 .pin = p, \ 377 .functions = { \ 378 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \ 379 }, \ 380 } 381 382 LUTON_P(0, SG0, NONE); 383 LUTON_P(1, SG0, NONE); 384 LUTON_P(2, SG0, NONE); 385 LUTON_P(3, SG0, NONE); 386 LUTON_P(4, TACHO, NONE); 387 LUTON_P(5, TWI, PHY_LED); 388 LUTON_P(6, TWI, PHY_LED); 389 LUTON_P(7, NONE, PHY_LED); 390 LUTON_P(8, EXT_IRQ, PHY_LED); 391 LUTON_P(9, EXT_IRQ, PHY_LED); 392 LUTON_P(10, SFP, PHY_LED); 393 LUTON_P(11, SFP, PHY_LED); 394 LUTON_P(12, SFP, PHY_LED); 395 LUTON_P(13, SFP, PHY_LED); 396 LUTON_P(14, SI, PHY_LED); 397 LUTON_P(15, SI, PHY_LED); 398 LUTON_P(16, SI, PHY_LED); 399 LUTON_P(17, SFP, PHY_LED); 400 LUTON_P(18, SFP, PHY_LED); 401 LUTON_P(19, SFP, PHY_LED); 402 LUTON_P(20, SFP, PHY_LED); 403 LUTON_P(21, SFP, PHY_LED); 404 LUTON_P(22, SFP, PHY_LED); 405 LUTON_P(23, SFP, PHY_LED); 406 LUTON_P(24, SFP, PHY_LED); 407 LUTON_P(25, SFP, PHY_LED); 408 LUTON_P(26, SFP, PHY_LED); 409 LUTON_P(27, SFP, PHY_LED); 410 LUTON_P(28, SFP, PHY_LED); 411 LUTON_P(29, PWM, NONE); 412 LUTON_P(30, UART, NONE); 413 LUTON_P(31, UART, NONE); 414 415 #define LUTON_PIN(n) { \ 416 .number = n, \ 417 .name = "GPIO_"#n, \ 418 .drv_data = &luton_pin_##n \ 419 } 420 421 static const struct pinctrl_pin_desc luton_pins[] = { 422 LUTON_PIN(0), 423 LUTON_PIN(1), 424 LUTON_PIN(2), 425 LUTON_PIN(3), 426 LUTON_PIN(4), 427 LUTON_PIN(5), 428 LUTON_PIN(6), 429 LUTON_PIN(7), 430 LUTON_PIN(8), 431 LUTON_PIN(9), 432 LUTON_PIN(10), 433 LUTON_PIN(11), 434 LUTON_PIN(12), 435 LUTON_PIN(13), 436 LUTON_PIN(14), 437 LUTON_PIN(15), 438 LUTON_PIN(16), 439 LUTON_PIN(17), 440 LUTON_PIN(18), 441 LUTON_PIN(19), 442 LUTON_PIN(20), 443 LUTON_PIN(21), 444 LUTON_PIN(22), 445 LUTON_PIN(23), 446 LUTON_PIN(24), 447 LUTON_PIN(25), 448 LUTON_PIN(26), 449 LUTON_PIN(27), 450 LUTON_PIN(28), 451 LUTON_PIN(29), 452 LUTON_PIN(30), 453 LUTON_PIN(31), 454 }; 455 456 #define SERVAL_P(p, f0, f1, f2) \ 457 static struct ocelot_pin_caps serval_pin_##p = { \ 458 .pin = p, \ 459 .functions = { \ 460 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 461 }, \ 462 } 463 464 SERVAL_P(0, SG0, NONE, NONE); 465 SERVAL_P(1, SG0, NONE, NONE); 466 SERVAL_P(2, SG0, NONE, NONE); 467 SERVAL_P(3, SG0, NONE, NONE); 468 SERVAL_P(4, TACHO, NONE, NONE); 469 SERVAL_P(5, PWM, NONE, NONE); 470 SERVAL_P(6, TWI, NONE, NONE); 471 SERVAL_P(7, TWI, NONE, NONE); 472 SERVAL_P(8, SI, NONE, NONE); 473 SERVAL_P(9, SI, MD, NONE); 474 SERVAL_P(10, SI, MD, NONE); 475 SERVAL_P(11, SFP, MD, TWI_SCL_M); 476 SERVAL_P(12, SFP, MD, TWI_SCL_M); 477 SERVAL_P(13, SFP, UART2, TWI_SCL_M); 478 SERVAL_P(14, SFP, UART2, TWI_SCL_M); 479 SERVAL_P(15, SFP, PTP0, TWI_SCL_M); 480 SERVAL_P(16, SFP, PTP0, TWI_SCL_M); 481 SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M); 482 SERVAL_P(18, SFP, NONE, TWI_SCL_M); 483 SERVAL_P(19, SFP, NONE, TWI_SCL_M); 484 SERVAL_P(20, SFP, NONE, TWI_SCL_M); 485 SERVAL_P(21, SFP, NONE, TWI_SCL_M); 486 SERVAL_P(22, NONE, NONE, NONE); 487 SERVAL_P(23, NONE, NONE, NONE); 488 SERVAL_P(24, NONE, NONE, NONE); 489 SERVAL_P(25, NONE, NONE, NONE); 490 SERVAL_P(26, UART, NONE, NONE); 491 SERVAL_P(27, UART, NONE, NONE); 492 SERVAL_P(28, IRQ0, NONE, NONE); 493 SERVAL_P(29, IRQ1, NONE, NONE); 494 SERVAL_P(30, PTP0, NONE, NONE); 495 SERVAL_P(31, PTP0, NONE, NONE); 496 497 #define SERVAL_PIN(n) { \ 498 .number = n, \ 499 .name = "GPIO_"#n, \ 500 .drv_data = &serval_pin_##n \ 501 } 502 503 static const struct pinctrl_pin_desc serval_pins[] = { 504 SERVAL_PIN(0), 505 SERVAL_PIN(1), 506 SERVAL_PIN(2), 507 SERVAL_PIN(3), 508 SERVAL_PIN(4), 509 SERVAL_PIN(5), 510 SERVAL_PIN(6), 511 SERVAL_PIN(7), 512 SERVAL_PIN(8), 513 SERVAL_PIN(9), 514 SERVAL_PIN(10), 515 SERVAL_PIN(11), 516 SERVAL_PIN(12), 517 SERVAL_PIN(13), 518 SERVAL_PIN(14), 519 SERVAL_PIN(15), 520 SERVAL_PIN(16), 521 SERVAL_PIN(17), 522 SERVAL_PIN(18), 523 SERVAL_PIN(19), 524 SERVAL_PIN(20), 525 SERVAL_PIN(21), 526 SERVAL_PIN(22), 527 SERVAL_PIN(23), 528 SERVAL_PIN(24), 529 SERVAL_PIN(25), 530 SERVAL_PIN(26), 531 SERVAL_PIN(27), 532 SERVAL_PIN(28), 533 SERVAL_PIN(29), 534 SERVAL_PIN(30), 535 SERVAL_PIN(31), 536 }; 537 538 #define OCELOT_P(p, f0, f1, f2) \ 539 static struct ocelot_pin_caps ocelot_pin_##p = { \ 540 .pin = p, \ 541 .functions = { \ 542 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 543 }, \ 544 } 545 546 OCELOT_P(0, SG0, NONE, NONE); 547 OCELOT_P(1, SG0, NONE, NONE); 548 OCELOT_P(2, SG0, NONE, NONE); 549 OCELOT_P(3, SG0, NONE, NONE); 550 OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 551 OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); 552 OCELOT_P(6, UART, TWI_SCL_M, NONE); 553 OCELOT_P(7, UART, TWI_SCL_M, NONE); 554 OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); 555 OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); 556 OCELOT_P(10, PTP2, TWI_SCL_M, SFP); 557 OCELOT_P(11, PTP3, TWI_SCL_M, SFP); 558 OCELOT_P(12, UART2, TWI_SCL_M, SFP); 559 OCELOT_P(13, UART2, TWI_SCL_M, SFP); 560 OCELOT_P(14, MIIM, TWI_SCL_M, SFP); 561 OCELOT_P(15, MIIM, TWI_SCL_M, SFP); 562 OCELOT_P(16, TWI, NONE, SI); 563 OCELOT_P(17, TWI, TWI_SCL_M, SI); 564 OCELOT_P(18, PTP0, TWI_SCL_M, NONE); 565 OCELOT_P(19, PTP1, TWI_SCL_M, NONE); 566 OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); 567 OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); 568 569 #define OCELOT_PIN(n) { \ 570 .number = n, \ 571 .name = "GPIO_"#n, \ 572 .drv_data = &ocelot_pin_##n \ 573 } 574 575 static const struct pinctrl_pin_desc ocelot_pins[] = { 576 OCELOT_PIN(0), 577 OCELOT_PIN(1), 578 OCELOT_PIN(2), 579 OCELOT_PIN(3), 580 OCELOT_PIN(4), 581 OCELOT_PIN(5), 582 OCELOT_PIN(6), 583 OCELOT_PIN(7), 584 OCELOT_PIN(8), 585 OCELOT_PIN(9), 586 OCELOT_PIN(10), 587 OCELOT_PIN(11), 588 OCELOT_PIN(12), 589 OCELOT_PIN(13), 590 OCELOT_PIN(14), 591 OCELOT_PIN(15), 592 OCELOT_PIN(16), 593 OCELOT_PIN(17), 594 OCELOT_PIN(18), 595 OCELOT_PIN(19), 596 OCELOT_PIN(20), 597 OCELOT_PIN(21), 598 }; 599 600 #define JAGUAR2_P(p, f0, f1) \ 601 static struct ocelot_pin_caps jaguar2_pin_##p = { \ 602 .pin = p, \ 603 .functions = { \ 604 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \ 605 }, \ 606 } 607 608 JAGUAR2_P(0, SG0, NONE); 609 JAGUAR2_P(1, SG0, NONE); 610 JAGUAR2_P(2, SG0, NONE); 611 JAGUAR2_P(3, SG0, NONE); 612 JAGUAR2_P(4, SG1, NONE); 613 JAGUAR2_P(5, SG1, NONE); 614 JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT); 615 JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT); 616 JAGUAR2_P(8, PTP0, NONE); 617 JAGUAR2_P(9, PTP1, NONE); 618 JAGUAR2_P(10, UART, NONE); 619 JAGUAR2_P(11, UART, NONE); 620 JAGUAR2_P(12, SG1, NONE); 621 JAGUAR2_P(13, SG1, NONE); 622 JAGUAR2_P(14, TWI, TWI_SCL_M); 623 JAGUAR2_P(15, TWI, NONE); 624 JAGUAR2_P(16, SI, TWI_SCL_M); 625 JAGUAR2_P(17, SI, TWI_SCL_M); 626 JAGUAR2_P(18, SI, TWI_SCL_M); 627 JAGUAR2_P(19, PCI_WAKE, NONE); 628 JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M); 629 JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M); 630 JAGUAR2_P(22, TACHO, NONE); 631 JAGUAR2_P(23, PWM, NONE); 632 JAGUAR2_P(24, UART2, NONE); 633 JAGUAR2_P(25, UART2, SI); 634 JAGUAR2_P(26, PTP2, SI); 635 JAGUAR2_P(27, PTP3, SI); 636 JAGUAR2_P(28, TWI2, SI); 637 JAGUAR2_P(29, TWI2, SI); 638 JAGUAR2_P(30, SG2, SI); 639 JAGUAR2_P(31, SG2, SI); 640 JAGUAR2_P(32, SG2, SI); 641 JAGUAR2_P(33, SG2, SI); 642 JAGUAR2_P(34, NONE, TWI_SCL_M); 643 JAGUAR2_P(35, NONE, TWI_SCL_M); 644 JAGUAR2_P(36, NONE, TWI_SCL_M); 645 JAGUAR2_P(37, NONE, TWI_SCL_M); 646 JAGUAR2_P(38, NONE, TWI_SCL_M); 647 JAGUAR2_P(39, NONE, TWI_SCL_M); 648 JAGUAR2_P(40, NONE, TWI_SCL_M); 649 JAGUAR2_P(41, NONE, TWI_SCL_M); 650 JAGUAR2_P(42, NONE, TWI_SCL_M); 651 JAGUAR2_P(43, NONE, TWI_SCL_M); 652 JAGUAR2_P(44, NONE, SFP); 653 JAGUAR2_P(45, NONE, SFP); 654 JAGUAR2_P(46, NONE, SFP); 655 JAGUAR2_P(47, NONE, SFP); 656 JAGUAR2_P(48, SFP, NONE); 657 JAGUAR2_P(49, SFP, SI); 658 JAGUAR2_P(50, SFP, SI); 659 JAGUAR2_P(51, SFP, SI); 660 JAGUAR2_P(52, SFP, NONE); 661 JAGUAR2_P(53, SFP, NONE); 662 JAGUAR2_P(54, SFP, NONE); 663 JAGUAR2_P(55, SFP, NONE); 664 JAGUAR2_P(56, MIIM, SFP); 665 JAGUAR2_P(57, MIIM, SFP); 666 JAGUAR2_P(58, MIIM, SFP); 667 JAGUAR2_P(59, MIIM, SFP); 668 JAGUAR2_P(60, NONE, NONE); 669 JAGUAR2_P(61, NONE, NONE); 670 JAGUAR2_P(62, NONE, NONE); 671 JAGUAR2_P(63, NONE, NONE); 672 673 #define JAGUAR2_PIN(n) { \ 674 .number = n, \ 675 .name = "GPIO_"#n, \ 676 .drv_data = &jaguar2_pin_##n \ 677 } 678 679 static const struct pinctrl_pin_desc jaguar2_pins[] = { 680 JAGUAR2_PIN(0), 681 JAGUAR2_PIN(1), 682 JAGUAR2_PIN(2), 683 JAGUAR2_PIN(3), 684 JAGUAR2_PIN(4), 685 JAGUAR2_PIN(5), 686 JAGUAR2_PIN(6), 687 JAGUAR2_PIN(7), 688 JAGUAR2_PIN(8), 689 JAGUAR2_PIN(9), 690 JAGUAR2_PIN(10), 691 JAGUAR2_PIN(11), 692 JAGUAR2_PIN(12), 693 JAGUAR2_PIN(13), 694 JAGUAR2_PIN(14), 695 JAGUAR2_PIN(15), 696 JAGUAR2_PIN(16), 697 JAGUAR2_PIN(17), 698 JAGUAR2_PIN(18), 699 JAGUAR2_PIN(19), 700 JAGUAR2_PIN(20), 701 JAGUAR2_PIN(21), 702 JAGUAR2_PIN(22), 703 JAGUAR2_PIN(23), 704 JAGUAR2_PIN(24), 705 JAGUAR2_PIN(25), 706 JAGUAR2_PIN(26), 707 JAGUAR2_PIN(27), 708 JAGUAR2_PIN(28), 709 JAGUAR2_PIN(29), 710 JAGUAR2_PIN(30), 711 JAGUAR2_PIN(31), 712 JAGUAR2_PIN(32), 713 JAGUAR2_PIN(33), 714 JAGUAR2_PIN(34), 715 JAGUAR2_PIN(35), 716 JAGUAR2_PIN(36), 717 JAGUAR2_PIN(37), 718 JAGUAR2_PIN(38), 719 JAGUAR2_PIN(39), 720 JAGUAR2_PIN(40), 721 JAGUAR2_PIN(41), 722 JAGUAR2_PIN(42), 723 JAGUAR2_PIN(43), 724 JAGUAR2_PIN(44), 725 JAGUAR2_PIN(45), 726 JAGUAR2_PIN(46), 727 JAGUAR2_PIN(47), 728 JAGUAR2_PIN(48), 729 JAGUAR2_PIN(49), 730 JAGUAR2_PIN(50), 731 JAGUAR2_PIN(51), 732 JAGUAR2_PIN(52), 733 JAGUAR2_PIN(53), 734 JAGUAR2_PIN(54), 735 JAGUAR2_PIN(55), 736 JAGUAR2_PIN(56), 737 JAGUAR2_PIN(57), 738 JAGUAR2_PIN(58), 739 JAGUAR2_PIN(59), 740 JAGUAR2_PIN(60), 741 JAGUAR2_PIN(61), 742 JAGUAR2_PIN(62), 743 JAGUAR2_PIN(63), 744 }; 745 746 #define SERVALT_P(p, f0, f1, f2) \ 747 static struct ocelot_pin_caps servalt_pin_##p = { \ 748 .pin = p, \ 749 .functions = { \ 750 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 751 }, \ 752 } 753 754 SERVALT_P(0, SG0, NONE, NONE); 755 SERVALT_P(1, SG0, NONE, NONE); 756 SERVALT_P(2, SG0, NONE, NONE); 757 SERVALT_P(3, SG0, NONE, NONE); 758 SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); 759 SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); 760 SERVALT_P(6, UART, NONE, NONE); 761 SERVALT_P(7, UART, NONE, NONE); 762 SERVALT_P(8, SI, SFP, TWI_SCL_M); 763 SERVALT_P(9, PCI_WAKE, SFP, SI); 764 SERVALT_P(10, PTP0, SFP, TWI_SCL_M); 765 SERVALT_P(11, PTP1, SFP, TWI_SCL_M); 766 SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); 767 SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); 768 SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); 769 SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); 770 SERVALT_P(16, TACHO, SFP, SI); 771 SERVALT_P(17, PWM, NONE, TWI_SCL_M); 772 SERVALT_P(18, PTP2, SFP, SI); 773 SERVALT_P(19, PTP3, SFP, SI); 774 SERVALT_P(20, UART2, SFP, SI); 775 SERVALT_P(21, UART2, NONE, NONE); 776 SERVALT_P(22, MIIM, SFP, TWI2); 777 SERVALT_P(23, MIIM, SFP, TWI2); 778 SERVALT_P(24, TWI, NONE, NONE); 779 SERVALT_P(25, TWI, SFP, TWI_SCL_M); 780 SERVALT_P(26, TWI_SCL_M, SFP, SI); 781 SERVALT_P(27, TWI_SCL_M, SFP, SI); 782 SERVALT_P(28, TWI_SCL_M, SFP, SI); 783 SERVALT_P(29, TWI_SCL_M, NONE, NONE); 784 SERVALT_P(30, TWI_SCL_M, NONE, NONE); 785 SERVALT_P(31, TWI_SCL_M, NONE, NONE); 786 SERVALT_P(32, TWI_SCL_M, NONE, NONE); 787 SERVALT_P(33, RCVRD_CLK, NONE, NONE); 788 SERVALT_P(34, RCVRD_CLK, NONE, NONE); 789 SERVALT_P(35, RCVRD_CLK, NONE, NONE); 790 SERVALT_P(36, RCVRD_CLK, NONE, NONE); 791 792 #define SERVALT_PIN(n) { \ 793 .number = n, \ 794 .name = "GPIO_"#n, \ 795 .drv_data = &servalt_pin_##n \ 796 } 797 798 static const struct pinctrl_pin_desc servalt_pins[] = { 799 SERVALT_PIN(0), 800 SERVALT_PIN(1), 801 SERVALT_PIN(2), 802 SERVALT_PIN(3), 803 SERVALT_PIN(4), 804 SERVALT_PIN(5), 805 SERVALT_PIN(6), 806 SERVALT_PIN(7), 807 SERVALT_PIN(8), 808 SERVALT_PIN(9), 809 SERVALT_PIN(10), 810 SERVALT_PIN(11), 811 SERVALT_PIN(12), 812 SERVALT_PIN(13), 813 SERVALT_PIN(14), 814 SERVALT_PIN(15), 815 SERVALT_PIN(16), 816 SERVALT_PIN(17), 817 SERVALT_PIN(18), 818 SERVALT_PIN(19), 819 SERVALT_PIN(20), 820 SERVALT_PIN(21), 821 SERVALT_PIN(22), 822 SERVALT_PIN(23), 823 SERVALT_PIN(24), 824 SERVALT_PIN(25), 825 SERVALT_PIN(26), 826 SERVALT_PIN(27), 827 SERVALT_PIN(28), 828 SERVALT_PIN(29), 829 SERVALT_PIN(30), 830 SERVALT_PIN(31), 831 SERVALT_PIN(32), 832 SERVALT_PIN(33), 833 SERVALT_PIN(34), 834 SERVALT_PIN(35), 835 SERVALT_PIN(36), 836 }; 837 838 #define SPARX5_P(p, f0, f1, f2) \ 839 static struct ocelot_pin_caps sparx5_pin_##p = { \ 840 .pin = p, \ 841 .functions = { \ 842 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ 843 }, \ 844 } 845 846 SPARX5_P(0, SG0, PLL_STAT, NONE); 847 SPARX5_P(1, SG0, NONE, NONE); 848 SPARX5_P(2, SG0, NONE, NONE); 849 SPARX5_P(3, SG0, NONE, NONE); 850 SPARX5_P(4, SG1, NONE, NONE); 851 SPARX5_P(5, SG1, NONE, NONE); 852 SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP); 853 SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP); 854 SPARX5_P(8, PTP0, NONE, SFP); 855 SPARX5_P(9, PTP1, SFP, TWI_SCL_M); 856 SPARX5_P(10, UART, NONE, NONE); 857 SPARX5_P(11, UART, NONE, NONE); 858 SPARX5_P(12, SG1, NONE, NONE); 859 SPARX5_P(13, SG1, NONE, NONE); 860 SPARX5_P(14, TWI, TWI_SCL_M, NONE); 861 SPARX5_P(15, TWI, NONE, NONE); 862 SPARX5_P(16, SI, TWI_SCL_M, SFP); 863 SPARX5_P(17, SI, TWI_SCL_M, SFP); 864 SPARX5_P(18, SI, TWI_SCL_M, SFP); 865 SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP); 866 SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP); 867 SPARX5_P(21, IRQ1_OUT, TACHO, SFP); 868 SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M); 869 SPARX5_P(23, PWM, UART3, TWI_SCL_M); 870 SPARX5_P(24, PTP2, UART3, TWI_SCL_M); 871 SPARX5_P(25, PTP3, SI, TWI_SCL_M); 872 SPARX5_P(26, UART2, SI, TWI_SCL_M); 873 SPARX5_P(27, UART2, SI, TWI_SCL_M); 874 SPARX5_P(28, TWI2, SI, SFP); 875 SPARX5_P(29, TWI2, SI, SFP); 876 SPARX5_P(30, SG2, SI, PWM); 877 SPARX5_P(31, SG2, SI, TWI_SCL_M); 878 SPARX5_P(32, SG2, SI, TWI_SCL_M); 879 SPARX5_P(33, SG2, SI, SFP); 880 SPARX5_P(34, NONE, TWI_SCL_M, EMMC); 881 SPARX5_P(35, SFP, TWI_SCL_M, EMMC); 882 SPARX5_P(36, SFP, TWI_SCL_M, EMMC); 883 SPARX5_P(37, SFP, NONE, EMMC); 884 SPARX5_P(38, NONE, TWI_SCL_M, EMMC); 885 SPARX5_P(39, SI2, TWI_SCL_M, EMMC); 886 SPARX5_P(40, SI2, TWI_SCL_M, EMMC); 887 SPARX5_P(41, SI2, TWI_SCL_M, EMMC); 888 SPARX5_P(42, SI2, TWI_SCL_M, EMMC); 889 SPARX5_P(43, SI2, TWI_SCL_M, EMMC); 890 SPARX5_P(44, SI, SFP, EMMC); 891 SPARX5_P(45, SI, SFP, EMMC); 892 SPARX5_P(46, NONE, SFP, EMMC); 893 SPARX5_P(47, NONE, SFP, EMMC); 894 SPARX5_P(48, TWI3, SI, SFP); 895 SPARX5_P(49, TWI3, NONE, SFP); 896 SPARX5_P(50, SFP, NONE, TWI_SCL_M); 897 SPARX5_P(51, SFP, SI, TWI_SCL_M); 898 SPARX5_P(52, SFP, MIIM, TWI_SCL_M); 899 SPARX5_P(53, SFP, MIIM, TWI_SCL_M); 900 SPARX5_P(54, SFP, PTP2, TWI_SCL_M); 901 SPARX5_P(55, SFP, PTP3, PCI_WAKE); 902 SPARX5_P(56, MIIM, SFP, TWI_SCL_M); 903 SPARX5_P(57, MIIM, SFP, TWI_SCL_M); 904 SPARX5_P(58, MIIM, SFP, TWI_SCL_M); 905 SPARX5_P(59, MIIM, SFP, NONE); 906 SPARX5_P(60, RECO_CLK, NONE, NONE); 907 SPARX5_P(61, RECO_CLK, NONE, NONE); 908 SPARX5_P(62, RECO_CLK, PLL_STAT, NONE); 909 SPARX5_P(63, RECO_CLK, NONE, NONE); 910 911 #define SPARX5_PIN(n) { \ 912 .number = n, \ 913 .name = "GPIO_"#n, \ 914 .drv_data = &sparx5_pin_##n \ 915 } 916 917 static const struct pinctrl_pin_desc sparx5_pins[] = { 918 SPARX5_PIN(0), 919 SPARX5_PIN(1), 920 SPARX5_PIN(2), 921 SPARX5_PIN(3), 922 SPARX5_PIN(4), 923 SPARX5_PIN(5), 924 SPARX5_PIN(6), 925 SPARX5_PIN(7), 926 SPARX5_PIN(8), 927 SPARX5_PIN(9), 928 SPARX5_PIN(10), 929 SPARX5_PIN(11), 930 SPARX5_PIN(12), 931 SPARX5_PIN(13), 932 SPARX5_PIN(14), 933 SPARX5_PIN(15), 934 SPARX5_PIN(16), 935 SPARX5_PIN(17), 936 SPARX5_PIN(18), 937 SPARX5_PIN(19), 938 SPARX5_PIN(20), 939 SPARX5_PIN(21), 940 SPARX5_PIN(22), 941 SPARX5_PIN(23), 942 SPARX5_PIN(24), 943 SPARX5_PIN(25), 944 SPARX5_PIN(26), 945 SPARX5_PIN(27), 946 SPARX5_PIN(28), 947 SPARX5_PIN(29), 948 SPARX5_PIN(30), 949 SPARX5_PIN(31), 950 SPARX5_PIN(32), 951 SPARX5_PIN(33), 952 SPARX5_PIN(34), 953 SPARX5_PIN(35), 954 SPARX5_PIN(36), 955 SPARX5_PIN(37), 956 SPARX5_PIN(38), 957 SPARX5_PIN(39), 958 SPARX5_PIN(40), 959 SPARX5_PIN(41), 960 SPARX5_PIN(42), 961 SPARX5_PIN(43), 962 SPARX5_PIN(44), 963 SPARX5_PIN(45), 964 SPARX5_PIN(46), 965 SPARX5_PIN(47), 966 SPARX5_PIN(48), 967 SPARX5_PIN(49), 968 SPARX5_PIN(50), 969 SPARX5_PIN(51), 970 SPARX5_PIN(52), 971 SPARX5_PIN(53), 972 SPARX5_PIN(54), 973 SPARX5_PIN(55), 974 SPARX5_PIN(56), 975 SPARX5_PIN(57), 976 SPARX5_PIN(58), 977 SPARX5_PIN(59), 978 SPARX5_PIN(60), 979 SPARX5_PIN(61), 980 SPARX5_PIN(62), 981 SPARX5_PIN(63), 982 }; 983 984 #define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 985 static struct ocelot_pin_caps lan966x_pin_##p = { \ 986 .pin = p, \ 987 .functions = { \ 988 FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 989 FUNC_##f3 \ 990 }, \ 991 .a_functions = { \ 992 FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 993 FUNC_##f7 \ 994 }, \ 995 } 996 997 /* Pinmuxing table taken from data sheet */ 998 /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 999 LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1000 LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1001 LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1002 LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1003 LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1004 LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1005 LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1006 LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); 1007 LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); 1008 LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); 1009 LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); 1010 LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 1011 LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 1012 LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); 1013 LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 1014 LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); 1015 LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 1016 LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 1017 LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 1018 LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); 1019 LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); 1020 LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 1021 LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 1022 LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); 1023 LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); 1024 LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 1025 LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); 1026 LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R); 1027 LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); 1028 LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); 1029 LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 1030 LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R); 1031 LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); 1032 LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1033 LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); 1034 LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R); 1035 LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); 1036 LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1037 LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); 1038 LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); 1039 LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); 1040 LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1041 LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); 1042 LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1043 LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); 1044 LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); 1045 LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); 1046 LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); 1047 LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); 1048 LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); 1049 LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); 1050 LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R); 1051 LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); 1052 LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); 1053 LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1054 LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); 1055 LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); 1056 LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); 1057 LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); 1058 LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1059 LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); 1060 LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); 1061 LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1062 LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); 1063 LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); 1064 LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); 1065 LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); 1066 LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1067 LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1068 LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1069 LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1070 LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1071 LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); 1072 LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); 1073 LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); 1074 LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); 1075 LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); 1076 LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); 1077 1078 #define LAN966X_PIN(n) { \ 1079 .number = n, \ 1080 .name = "GPIO_"#n, \ 1081 .drv_data = &lan966x_pin_##n \ 1082 } 1083 1084 static const struct pinctrl_pin_desc lan966x_pins[] = { 1085 LAN966X_PIN(0), 1086 LAN966X_PIN(1), 1087 LAN966X_PIN(2), 1088 LAN966X_PIN(3), 1089 LAN966X_PIN(4), 1090 LAN966X_PIN(5), 1091 LAN966X_PIN(6), 1092 LAN966X_PIN(7), 1093 LAN966X_PIN(8), 1094 LAN966X_PIN(9), 1095 LAN966X_PIN(10), 1096 LAN966X_PIN(11), 1097 LAN966X_PIN(12), 1098 LAN966X_PIN(13), 1099 LAN966X_PIN(14), 1100 LAN966X_PIN(15), 1101 LAN966X_PIN(16), 1102 LAN966X_PIN(17), 1103 LAN966X_PIN(18), 1104 LAN966X_PIN(19), 1105 LAN966X_PIN(20), 1106 LAN966X_PIN(21), 1107 LAN966X_PIN(22), 1108 LAN966X_PIN(23), 1109 LAN966X_PIN(24), 1110 LAN966X_PIN(25), 1111 LAN966X_PIN(26), 1112 LAN966X_PIN(27), 1113 LAN966X_PIN(28), 1114 LAN966X_PIN(29), 1115 LAN966X_PIN(30), 1116 LAN966X_PIN(31), 1117 LAN966X_PIN(32), 1118 LAN966X_PIN(33), 1119 LAN966X_PIN(34), 1120 LAN966X_PIN(35), 1121 LAN966X_PIN(36), 1122 LAN966X_PIN(37), 1123 LAN966X_PIN(38), 1124 LAN966X_PIN(39), 1125 LAN966X_PIN(40), 1126 LAN966X_PIN(41), 1127 LAN966X_PIN(42), 1128 LAN966X_PIN(43), 1129 LAN966X_PIN(44), 1130 LAN966X_PIN(45), 1131 LAN966X_PIN(46), 1132 LAN966X_PIN(47), 1133 LAN966X_PIN(48), 1134 LAN966X_PIN(49), 1135 LAN966X_PIN(50), 1136 LAN966X_PIN(51), 1137 LAN966X_PIN(52), 1138 LAN966X_PIN(53), 1139 LAN966X_PIN(54), 1140 LAN966X_PIN(55), 1141 LAN966X_PIN(56), 1142 LAN966X_PIN(57), 1143 LAN966X_PIN(58), 1144 LAN966X_PIN(59), 1145 LAN966X_PIN(60), 1146 LAN966X_PIN(61), 1147 LAN966X_PIN(62), 1148 LAN966X_PIN(63), 1149 LAN966X_PIN(64), 1150 LAN966X_PIN(65), 1151 LAN966X_PIN(66), 1152 LAN966X_PIN(67), 1153 LAN966X_PIN(68), 1154 LAN966X_PIN(69), 1155 LAN966X_PIN(70), 1156 LAN966X_PIN(71), 1157 LAN966X_PIN(72), 1158 LAN966X_PIN(73), 1159 LAN966X_PIN(74), 1160 LAN966X_PIN(75), 1161 LAN966X_PIN(76), 1162 LAN966X_PIN(77), 1163 }; 1164 1165 #define LAN969X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 1166 static struct ocelot_pin_caps lan969x_pin_##p = { \ 1167 .pin = p, \ 1168 .functions = { \ 1169 FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 1170 FUNC_##f3 \ 1171 }, \ 1172 .a_functions = { \ 1173 FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 1174 FUNC_##f7 \ 1175 }, \ 1176 } 1177 1178 /* Pinmuxing table taken from data sheet */ 1179 /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 1180 LAN969X_P(0, GPIO, IRQ0, FC_SHRD, PCIE_PERST, NONE, NONE, NONE, R); 1181 LAN969X_P(1, GPIO, IRQ1, FC_SHRD, USB_POWER, NONE, NONE, NONE, R); 1182 LAN969X_P(2, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); 1183 LAN969X_P(3, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); 1184 LAN969X_P(4, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); 1185 LAN969X_P(5, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); 1186 LAN969X_P(6, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); 1187 LAN969X_P(7, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); 1188 LAN969X_P(8, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); 1189 LAN969X_P(9, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); 1190 LAN969X_P(10, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); 1191 LAN969X_P(11, GPIO, MIIM_IRQ, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); 1192 LAN969X_P(12, GPIO, IRQ3, FC_SHRD, USB2PHY_RST, NONE, NONE, NONE, R); 1193 LAN969X_P(13, GPIO, IRQ4, FC_SHRD, USB_OVER_DETECT, NONE, NONE, NONE, R); 1194 LAN969X_P(14, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); 1195 LAN969X_P(15, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); 1196 LAN969X_P(16, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); 1197 LAN969X_P(17, GPIO, EMMC_SD, QSPI1, PTPSYNC_0, USB_POWER, NONE, NONE, R); 1198 LAN969X_P(18, GPIO, EMMC_SD, QSPI1, PTPSYNC_1, USB2PHY_RST, NONE, NONE, R); 1199 LAN969X_P(19, GPIO, EMMC_SD, QSPI1, PTPSYNC_2, USB_OVER_DETECT, NONE, NONE, R); 1200 LAN969X_P(20, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); 1201 LAN969X_P(21, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); 1202 LAN969X_P(22, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); 1203 LAN969X_P(23, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); 1204 LAN969X_P(24, GPIO, EMMC_SD, NONE, NONE, NONE, NONE, NONE, R); 1205 LAN969X_P(25, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R); 1206 LAN969X_P(26, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R); 1207 LAN969X_P(27, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R); 1208 LAN969X_P(28, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R); 1209 LAN969X_P(29, GPIO, SYNCE, FC, MIIM_IRQ, QSPI1, NONE, NONE, R); 1210 LAN969X_P(30, GPIO, PTPSYNC_0, USB_ULPI, FC_SHRD, QSPI1, NONE, NONE, R); 1211 LAN969X_P(31, GPIO, PTPSYNC_1, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); 1212 LAN969X_P(32, GPIO, PTPSYNC_2, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); 1213 LAN969X_P(33, GPIO, SD, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); 1214 LAN969X_P(34, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R); 1215 LAN969X_P(35, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R); 1216 LAN969X_P(36, GPIO, SD, USB_ULPI, PCIE_PERST, FC_SHRD, NONE, NONE, R); 1217 LAN969X_P(37, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R); 1218 LAN969X_P(38, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R); 1219 LAN969X_P(39, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R); 1220 LAN969X_P(40, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R); 1221 LAN969X_P(41, GPIO, SD, USB_ULPI, MIIM_IRQ, NONE, NONE, NONE, R); 1222 LAN969X_P(42, GPIO, PTPSYNC_3, CAN1, NONE, NONE, NONE, NONE, R); 1223 LAN969X_P(43, GPIO, PTPSYNC_4, CAN1, NONE, NONE, NONE, NONE, R); 1224 LAN969X_P(44, GPIO, PTPSYNC_5, SFP_SD, NONE, NONE, NONE, NONE, R); 1225 LAN969X_P(45, GPIO, PTPSYNC_6, SFP_SD, NONE, NONE, NONE, NONE, R); 1226 LAN969X_P(46, GPIO, PTPSYNC_7, SFP_SD, NONE, NONE, NONE, NONE, R); 1227 LAN969X_P(47, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); 1228 LAN969X_P(48, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); 1229 LAN969X_P(49, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); 1230 LAN969X_P(50, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); 1231 LAN969X_P(51, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); 1232 LAN969X_P(52, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R); 1233 LAN969X_P(53, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R); 1234 LAN969X_P(54, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); 1235 LAN969X_P(55, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); 1236 LAN969X_P(56, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); 1237 LAN969X_P(57, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_3, NONE, NONE, R); 1238 LAN969X_P(58, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_4, NONE, NONE, R); 1239 LAN969X_P(59, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_5, NONE, NONE, R); 1240 LAN969X_P(60, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_6, NONE, NONE, R); 1241 LAN969X_P(61, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R); 1242 LAN969X_P(62, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R); 1243 LAN969X_P(63, GPIO, MIIM_IRQ, FC_SHRD, TWI, NONE, NONE, NONE, R); 1244 LAN969X_P(64, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); 1245 LAN969X_P(65, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); 1246 LAN969X_P(66, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); 1247 1248 #define LAN969X_PIN(n) { \ 1249 .number = n, \ 1250 .name = "GPIO_"#n, \ 1251 .drv_data = &lan969x_pin_##n \ 1252 } 1253 1254 static const struct pinctrl_pin_desc lan969x_pins[] = { 1255 LAN969X_PIN(0), 1256 LAN969X_PIN(1), 1257 LAN969X_PIN(2), 1258 LAN969X_PIN(3), 1259 LAN969X_PIN(4), 1260 LAN969X_PIN(5), 1261 LAN969X_PIN(6), 1262 LAN969X_PIN(7), 1263 LAN969X_PIN(8), 1264 LAN969X_PIN(9), 1265 LAN969X_PIN(10), 1266 LAN969X_PIN(11), 1267 LAN969X_PIN(12), 1268 LAN969X_PIN(13), 1269 LAN969X_PIN(14), 1270 LAN969X_PIN(15), 1271 LAN969X_PIN(16), 1272 LAN969X_PIN(17), 1273 LAN969X_PIN(18), 1274 LAN969X_PIN(19), 1275 LAN969X_PIN(20), 1276 LAN969X_PIN(21), 1277 LAN969X_PIN(22), 1278 LAN969X_PIN(23), 1279 LAN969X_PIN(24), 1280 LAN969X_PIN(25), 1281 LAN969X_PIN(26), 1282 LAN969X_PIN(27), 1283 LAN969X_PIN(28), 1284 LAN969X_PIN(29), 1285 LAN969X_PIN(30), 1286 LAN969X_PIN(31), 1287 LAN969X_PIN(32), 1288 LAN969X_PIN(33), 1289 LAN969X_PIN(34), 1290 LAN969X_PIN(35), 1291 LAN969X_PIN(36), 1292 LAN969X_PIN(37), 1293 LAN969X_PIN(38), 1294 LAN969X_PIN(39), 1295 LAN969X_PIN(40), 1296 LAN969X_PIN(41), 1297 LAN969X_PIN(42), 1298 LAN969X_PIN(43), 1299 LAN969X_PIN(44), 1300 LAN969X_PIN(45), 1301 LAN969X_PIN(46), 1302 LAN969X_PIN(47), 1303 LAN969X_PIN(48), 1304 LAN969X_PIN(49), 1305 LAN969X_PIN(50), 1306 LAN969X_PIN(51), 1307 LAN969X_PIN(52), 1308 LAN969X_PIN(53), 1309 LAN969X_PIN(54), 1310 LAN969X_PIN(55), 1311 LAN969X_PIN(56), 1312 LAN969X_PIN(57), 1313 LAN969X_PIN(58), 1314 LAN969X_PIN(59), 1315 LAN969X_PIN(60), 1316 LAN969X_PIN(61), 1317 LAN969X_PIN(62), 1318 LAN969X_PIN(63), 1319 LAN969X_PIN(64), 1320 LAN969X_PIN(65), 1321 LAN969X_PIN(66), 1322 }; 1323 1324 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1325 { 1326 return ARRAY_SIZE(ocelot_function_names); 1327 } 1328 1329 static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev, 1330 unsigned int function) 1331 { 1332 return ocelot_function_names[function]; 1333 } 1334 1335 static int ocelot_get_function_groups(struct pinctrl_dev *pctldev, 1336 unsigned int function, 1337 const char *const **groups, 1338 unsigned *const num_groups) 1339 { 1340 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1341 1342 *groups = info->func[function].groups; 1343 *num_groups = info->func[function].ngroups; 1344 1345 return 0; 1346 } 1347 1348 static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, 1349 unsigned int pin, unsigned int function) 1350 { 1351 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; 1352 int i; 1353 1354 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { 1355 if (function == p->functions[i]) 1356 return i; 1357 1358 if (function == p->a_functions[i]) 1359 return i + OCELOT_FUNC_PER_PIN; 1360 } 1361 1362 return -1; 1363 } 1364 1365 #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32)))) 1366 1367 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, 1368 unsigned int selector, unsigned int group) 1369 { 1370 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1371 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1372 unsigned int p = pin->pin % 32; 1373 int f; 1374 1375 f = ocelot_pin_function_idx(info, group, selector); 1376 if (f < 0) 1377 return -EINVAL; 1378 1379 /* 1380 * f is encoded on two bits. 1381 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1382 * ALT[1] 1383 * This is racy because both registers can't be updated at the same time 1384 * but it doesn't matter much for now. 1385 * Note: ALT0/ALT1 are organized specially for 64 gpio targets 1386 */ 1387 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1388 BIT(p), f << p); 1389 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1390 BIT(p), (f >> 1) << p); 1391 1392 return 0; 1393 } 1394 1395 static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, 1396 unsigned int selector, unsigned int group) 1397 { 1398 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1399 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; 1400 unsigned int p = pin->pin % 32; 1401 int f; 1402 1403 f = ocelot_pin_function_idx(info, group, selector); 1404 if (f < 0) 1405 return -EINVAL; 1406 1407 /* 1408 * f is encoded on three bits. 1409 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of 1410 * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] 1411 * This is racy because three registers can't be updated at the same time 1412 * but it doesn't matter much for now. 1413 * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 1414 */ 1415 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1416 BIT(p), f << p); 1417 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1418 BIT(p), (f >> 1) << p); 1419 regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), 1420 BIT(p), (f >> 2) << p); 1421 1422 return 0; 1423 } 1424 1425 #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) 1426 1427 static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, 1428 struct pinctrl_gpio_range *range, 1429 unsigned int pin, bool input) 1430 { 1431 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1432 unsigned int p = pin % 32; 1433 1434 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), 1435 input ? 0 : BIT(p)); 1436 1437 return 0; 1438 } 1439 1440 static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, 1441 struct pinctrl_gpio_range *range, 1442 unsigned int offset) 1443 { 1444 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1445 unsigned int p = offset % 32; 1446 1447 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1448 BIT(p), 0); 1449 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1450 BIT(p), 0); 1451 1452 return 0; 1453 } 1454 1455 static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, 1456 struct pinctrl_gpio_range *range, 1457 unsigned int offset) 1458 { 1459 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1460 unsigned int p = offset % 32; 1461 1462 regmap_update_bits(info->map, REG_ALT(0, info, offset), 1463 BIT(p), 0); 1464 regmap_update_bits(info->map, REG_ALT(1, info, offset), 1465 BIT(p), 0); 1466 regmap_update_bits(info->map, REG_ALT(2, info, offset), 1467 BIT(p), 0); 1468 1469 return 0; 1470 } 1471 1472 static const struct pinmux_ops ocelot_pmx_ops = { 1473 .get_functions_count = ocelot_get_functions_count, 1474 .get_function_name = ocelot_get_function_name, 1475 .get_function_groups = ocelot_get_function_groups, 1476 .set_mux = ocelot_pinmux_set_mux, 1477 .gpio_set_direction = ocelot_gpio_set_direction, 1478 .gpio_request_enable = ocelot_gpio_request_enable, 1479 }; 1480 1481 static const struct pinmux_ops lan966x_pmx_ops = { 1482 .get_functions_count = ocelot_get_functions_count, 1483 .get_function_name = ocelot_get_function_name, 1484 .get_function_groups = ocelot_get_function_groups, 1485 .set_mux = lan966x_pinmux_set_mux, 1486 .gpio_set_direction = ocelot_gpio_set_direction, 1487 .gpio_request_enable = lan966x_gpio_request_enable, 1488 }; 1489 1490 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) 1491 { 1492 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1493 1494 return info->desc->npins; 1495 } 1496 1497 static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev, 1498 unsigned int group) 1499 { 1500 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1501 1502 return info->desc->pins[group].name; 1503 } 1504 1505 static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev, 1506 unsigned int group, 1507 const unsigned int **pins, 1508 unsigned int *num_pins) 1509 { 1510 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1511 1512 *pins = &info->desc->pins[group].number; 1513 *num_pins = 1; 1514 1515 return 0; 1516 } 1517 1518 static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 1519 unsigned int pin, 1520 unsigned int reg, 1521 int *val) 1522 { 1523 int ret = -EOPNOTSUPP; 1524 1525 if (info->pincfg) { 1526 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1527 u32 regcfg; 1528 1529 ret = regmap_read(info->pincfg, 1530 pin * regmap_get_reg_stride(info->pincfg), 1531 ®cfg); 1532 if (ret) 1533 return ret; 1534 1535 ret = 0; 1536 switch (reg) { 1537 case PINCONF_BIAS: 1538 *val = regcfg & (opd->pd_bit | opd->pu_bit); 1539 break; 1540 1541 case PINCONF_SCHMITT: 1542 *val = regcfg & opd->schmitt_bit; 1543 break; 1544 1545 case PINCONF_DRIVE_STRENGTH: 1546 *val = regcfg & opd->drive_bits; 1547 break; 1548 1549 default: 1550 ret = -EOPNOTSUPP; 1551 break; 1552 } 1553 } 1554 return ret; 1555 } 1556 1557 static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, 1558 u32 clrbits, u32 setbits) 1559 { 1560 u32 val; 1561 int ret; 1562 1563 ret = regmap_read(info->pincfg, 1564 regaddr * regmap_get_reg_stride(info->pincfg), 1565 &val); 1566 if (ret) 1567 return ret; 1568 1569 val &= ~clrbits; 1570 val |= setbits; 1571 1572 ret = regmap_write(info->pincfg, 1573 regaddr * regmap_get_reg_stride(info->pincfg), 1574 val); 1575 1576 return ret; 1577 } 1578 1579 static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 1580 unsigned int pin, 1581 unsigned int reg, 1582 int val) 1583 { 1584 int ret = -EOPNOTSUPP; 1585 1586 if (info->pincfg) { 1587 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1588 1589 switch (reg) { 1590 case PINCONF_BIAS: 1591 ret = ocelot_pincfg_clrsetbits(info, pin, 1592 opd->pd_bit | opd->pu_bit, 1593 val); 1594 break; 1595 1596 case PINCONF_SCHMITT: 1597 ret = ocelot_pincfg_clrsetbits(info, pin, 1598 opd->schmitt_bit, 1599 val); 1600 break; 1601 1602 case PINCONF_DRIVE_STRENGTH: 1603 if (val <= 3) 1604 ret = ocelot_pincfg_clrsetbits(info, pin, 1605 opd->drive_bits, 1606 val); 1607 else 1608 ret = -EINVAL; 1609 break; 1610 1611 default: 1612 ret = -EOPNOTSUPP; 1613 break; 1614 } 1615 } 1616 return ret; 1617 } 1618 1619 static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 1620 unsigned int pin, unsigned long *config) 1621 { 1622 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1623 u32 param = pinconf_to_config_param(*config); 1624 int val, err; 1625 1626 switch (param) { 1627 case PIN_CONFIG_BIAS_DISABLE: 1628 case PIN_CONFIG_BIAS_PULL_UP: 1629 case PIN_CONFIG_BIAS_PULL_DOWN: 1630 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 1631 if (err) 1632 return err; 1633 if (param == PIN_CONFIG_BIAS_DISABLE) 1634 val = (val == 0); 1635 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1636 val = !!(val & info->pincfg_data->pd_bit); 1637 else /* PIN_CONFIG_BIAS_PULL_UP */ 1638 val = !!(val & info->pincfg_data->pu_bit); 1639 break; 1640 1641 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1642 if (!info->pincfg_data->schmitt_bit) 1643 return -EOPNOTSUPP; 1644 1645 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1646 if (err) 1647 return err; 1648 1649 val = !!(val & info->pincfg_data->schmitt_bit); 1650 break; 1651 1652 case PIN_CONFIG_DRIVE_STRENGTH: 1653 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 1654 &val); 1655 if (err) 1656 return err; 1657 break; 1658 1659 case PIN_CONFIG_OUTPUT: 1660 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 1661 &val); 1662 if (err) 1663 return err; 1664 val = !!(val & BIT(pin % 32)); 1665 break; 1666 1667 case PIN_CONFIG_INPUT_ENABLE: 1668 case PIN_CONFIG_OUTPUT_ENABLE: 1669 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 1670 &val); 1671 if (err) 1672 return err; 1673 val = val & BIT(pin % 32); 1674 if (param == PIN_CONFIG_OUTPUT_ENABLE) 1675 val = !!val; 1676 else 1677 val = !val; 1678 break; 1679 1680 default: 1681 return -EOPNOTSUPP; 1682 } 1683 1684 *config = pinconf_to_config_packed(param, val); 1685 1686 return 0; 1687 } 1688 1689 static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1690 unsigned long *configs, unsigned int num_configs) 1691 { 1692 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1693 const struct ocelot_pincfg_data *opd = info->pincfg_data; 1694 u32 param, arg, p; 1695 int cfg, err = 0; 1696 1697 for (cfg = 0; cfg < num_configs; cfg++) { 1698 param = pinconf_to_config_param(configs[cfg]); 1699 arg = pinconf_to_config_argument(configs[cfg]); 1700 1701 switch (param) { 1702 case PIN_CONFIG_BIAS_DISABLE: 1703 case PIN_CONFIG_BIAS_PULL_UP: 1704 case PIN_CONFIG_BIAS_PULL_DOWN: 1705 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1706 (param == PIN_CONFIG_BIAS_PULL_UP) ? 1707 opd->pu_bit : opd->pd_bit; 1708 1709 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1710 if (err) 1711 goto err; 1712 1713 break; 1714 1715 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1716 if (!opd->schmitt_bit) 1717 return -EOPNOTSUPP; 1718 1719 arg = arg ? opd->schmitt_bit : 0; 1720 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1721 arg); 1722 if (err) 1723 goto err; 1724 1725 break; 1726 1727 case PIN_CONFIG_DRIVE_STRENGTH: 1728 err = ocelot_hw_set_value(info, pin, 1729 PINCONF_DRIVE_STRENGTH, 1730 arg); 1731 if (err) 1732 goto err; 1733 1734 break; 1735 1736 case PIN_CONFIG_OUTPUT_ENABLE: 1737 case PIN_CONFIG_INPUT_ENABLE: 1738 case PIN_CONFIG_OUTPUT: 1739 p = pin % 32; 1740 if (arg) 1741 regmap_write(info->map, 1742 REG(OCELOT_GPIO_OUT_SET, info, 1743 pin), 1744 BIT(p)); 1745 else 1746 regmap_write(info->map, 1747 REG(OCELOT_GPIO_OUT_CLR, info, 1748 pin), 1749 BIT(p)); 1750 regmap_update_bits(info->map, 1751 REG(OCELOT_GPIO_OE, info, pin), 1752 BIT(p), 1753 param == PIN_CONFIG_INPUT_ENABLE ? 1754 0 : BIT(p)); 1755 break; 1756 1757 default: 1758 err = -EOPNOTSUPP; 1759 } 1760 } 1761 err: 1762 return err; 1763 } 1764 1765 static const struct pinconf_ops ocelot_confops = { 1766 .is_generic = true, 1767 .pin_config_get = ocelot_pinconf_get, 1768 .pin_config_set = ocelot_pinconf_set, 1769 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1770 }; 1771 1772 static const struct pinctrl_ops ocelot_pctl_ops = { 1773 .get_groups_count = ocelot_pctl_get_groups_count, 1774 .get_group_name = ocelot_pctl_get_group_name, 1775 .get_group_pins = ocelot_pctl_get_group_pins, 1776 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1777 .dt_free_map = pinconf_generic_dt_free_map, 1778 }; 1779 1780 static struct ocelot_match_data luton_desc = { 1781 .desc = { 1782 .name = "luton-pinctrl", 1783 .pins = luton_pins, 1784 .npins = ARRAY_SIZE(luton_pins), 1785 .pctlops = &ocelot_pctl_ops, 1786 .pmxops = &ocelot_pmx_ops, 1787 .owner = THIS_MODULE, 1788 }, 1789 }; 1790 1791 static struct ocelot_match_data serval_desc = { 1792 .desc = { 1793 .name = "serval-pinctrl", 1794 .pins = serval_pins, 1795 .npins = ARRAY_SIZE(serval_pins), 1796 .pctlops = &ocelot_pctl_ops, 1797 .pmxops = &ocelot_pmx_ops, 1798 .owner = THIS_MODULE, 1799 }, 1800 }; 1801 1802 static struct ocelot_match_data ocelot_desc = { 1803 .desc = { 1804 .name = "ocelot-pinctrl", 1805 .pins = ocelot_pins, 1806 .npins = ARRAY_SIZE(ocelot_pins), 1807 .pctlops = &ocelot_pctl_ops, 1808 .pmxops = &ocelot_pmx_ops, 1809 .owner = THIS_MODULE, 1810 }, 1811 }; 1812 1813 static struct ocelot_match_data jaguar2_desc = { 1814 .desc = { 1815 .name = "jaguar2-pinctrl", 1816 .pins = jaguar2_pins, 1817 .npins = ARRAY_SIZE(jaguar2_pins), 1818 .pctlops = &ocelot_pctl_ops, 1819 .pmxops = &ocelot_pmx_ops, 1820 .owner = THIS_MODULE, 1821 }, 1822 }; 1823 1824 static struct ocelot_match_data servalt_desc = { 1825 .desc = { 1826 .name = "servalt-pinctrl", 1827 .pins = servalt_pins, 1828 .npins = ARRAY_SIZE(servalt_pins), 1829 .pctlops = &ocelot_pctl_ops, 1830 .pmxops = &ocelot_pmx_ops, 1831 .owner = THIS_MODULE, 1832 }, 1833 }; 1834 1835 static struct ocelot_match_data sparx5_desc = { 1836 .desc = { 1837 .name = "sparx5-pinctrl", 1838 .pins = sparx5_pins, 1839 .npins = ARRAY_SIZE(sparx5_pins), 1840 .pctlops = &ocelot_pctl_ops, 1841 .pmxops = &ocelot_pmx_ops, 1842 .confops = &ocelot_confops, 1843 .owner = THIS_MODULE, 1844 }, 1845 .pincfg_data = { 1846 .pd_bit = BIT(4), 1847 .pu_bit = BIT(3), 1848 .drive_bits = GENMASK(1, 0), 1849 .schmitt_bit = BIT(2), 1850 }, 1851 }; 1852 1853 static struct ocelot_match_data lan966x_desc = { 1854 .desc = { 1855 .name = "lan966x-pinctrl", 1856 .pins = lan966x_pins, 1857 .npins = ARRAY_SIZE(lan966x_pins), 1858 .pctlops = &ocelot_pctl_ops, 1859 .pmxops = &lan966x_pmx_ops, 1860 .confops = &ocelot_confops, 1861 .owner = THIS_MODULE, 1862 }, 1863 .pincfg_data = { 1864 .pd_bit = BIT(3), 1865 .pu_bit = BIT(2), 1866 .drive_bits = GENMASK(1, 0), 1867 }, 1868 }; 1869 1870 static struct ocelot_match_data lan969x_desc = { 1871 .desc = { 1872 .name = "lan969x-pinctrl", 1873 .pins = lan969x_pins, 1874 .npins = ARRAY_SIZE(lan969x_pins), 1875 .pctlops = &ocelot_pctl_ops, 1876 .pmxops = &lan966x_pmx_ops, 1877 .confops = &ocelot_confops, 1878 .owner = THIS_MODULE, 1879 }, 1880 .pincfg_data = { 1881 .pd_bit = BIT(3), 1882 .pu_bit = BIT(2), 1883 .drive_bits = GENMASK(1, 0), 1884 }, 1885 }; 1886 1887 static int ocelot_create_group_func_map(struct device *dev, 1888 struct ocelot_pinctrl *info) 1889 { 1890 int f, npins, i; 1891 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL); 1892 1893 if (!pins) 1894 return -ENOMEM; 1895 1896 for (f = 0; f < FUNC_MAX; f++) { 1897 for (npins = 0, i = 0; i < info->desc->npins; i++) { 1898 if (ocelot_pin_function_idx(info, i, f) >= 0) 1899 pins[npins++] = i; 1900 } 1901 1902 if (!npins) 1903 continue; 1904 1905 info->func[f].ngroups = npins; 1906 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *), 1907 GFP_KERNEL); 1908 if (!info->func[f].groups) { 1909 kfree(pins); 1910 return -ENOMEM; 1911 } 1912 1913 for (i = 0; i < npins; i++) 1914 info->func[f].groups[i] = 1915 info->desc->pins[pins[i]].name; 1916 } 1917 1918 kfree(pins); 1919 1920 return 0; 1921 } 1922 1923 static int ocelot_pinctrl_register(struct platform_device *pdev, 1924 struct ocelot_pinctrl *info) 1925 { 1926 int ret; 1927 1928 ret = ocelot_create_group_func_map(&pdev->dev, info); 1929 if (ret) { 1930 dev_err(&pdev->dev, "Unable to create group func map.\n"); 1931 return ret; 1932 } 1933 1934 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info); 1935 if (IS_ERR(info->pctl)) { 1936 dev_err(&pdev->dev, "Failed to register pinctrl\n"); 1937 return PTR_ERR(info->pctl); 1938 } 1939 1940 return 0; 1941 } 1942 1943 static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) 1944 { 1945 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1946 unsigned int val; 1947 1948 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); 1949 1950 return !!(val & BIT(offset % 32)); 1951 } 1952 1953 static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, 1954 int value) 1955 { 1956 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1957 1958 if (value) 1959 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1960 BIT(offset % 32)); 1961 else 1962 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1963 BIT(offset % 32)); 1964 } 1965 1966 static int ocelot_gpio_get_direction(struct gpio_chip *chip, 1967 unsigned int offset) 1968 { 1969 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1970 unsigned int val; 1971 1972 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); 1973 1974 if (val & BIT(offset % 32)) 1975 return GPIO_LINE_DIRECTION_OUT; 1976 1977 return GPIO_LINE_DIRECTION_IN; 1978 } 1979 1980 static int ocelot_gpio_direction_output(struct gpio_chip *chip, 1981 unsigned int offset, int value) 1982 { 1983 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 1984 unsigned int pin = BIT(offset % 32); 1985 1986 if (value) 1987 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), 1988 pin); 1989 else 1990 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), 1991 pin); 1992 1993 return pinctrl_gpio_direction_output(chip, offset); 1994 } 1995 1996 static const struct gpio_chip ocelot_gpiolib_chip = { 1997 .request = gpiochip_generic_request, 1998 .free = gpiochip_generic_free, 1999 .set = ocelot_gpio_set, 2000 .get = ocelot_gpio_get, 2001 .get_direction = ocelot_gpio_get_direction, 2002 .direction_input = pinctrl_gpio_direction_input, 2003 .direction_output = ocelot_gpio_direction_output, 2004 .owner = THIS_MODULE, 2005 }; 2006 2007 static void ocelot_irq_mask(struct irq_data *data) 2008 { 2009 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 2010 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2011 unsigned int gpio = irqd_to_hwirq(data); 2012 2013 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 2014 BIT(gpio % 32), 0); 2015 gpiochip_disable_irq(chip, gpio); 2016 } 2017 2018 static void ocelot_irq_work(struct work_struct *work) 2019 { 2020 struct ocelot_irq_work *w = container_of(work, struct ocelot_irq_work, irq_work); 2021 struct irq_chip *parent_chip = irq_desc_get_chip(w->irq_desc); 2022 struct gpio_chip *chip = irq_desc_get_chip_data(w->irq_desc); 2023 struct irq_data *data = irq_desc_get_irq_data(w->irq_desc); 2024 unsigned int gpio = irqd_to_hwirq(data); 2025 2026 local_irq_disable(); 2027 chained_irq_enter(parent_chip, w->irq_desc); 2028 generic_handle_domain_irq(chip->irq.domain, gpio); 2029 chained_irq_exit(parent_chip, w->irq_desc); 2030 local_irq_enable(); 2031 2032 kfree(w); 2033 } 2034 2035 static void ocelot_irq_unmask_level(struct irq_data *data) 2036 { 2037 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 2038 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2039 struct irq_desc *desc = irq_data_to_desc(data); 2040 unsigned int gpio = irqd_to_hwirq(data); 2041 unsigned int bit = BIT(gpio % 32); 2042 bool ack = false, active = false; 2043 u8 trigger_level; 2044 int val; 2045 2046 trigger_level = irqd_get_trigger_type(data); 2047 2048 /* Check if the interrupt line is still active. */ 2049 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val); 2050 if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) || 2051 (val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH)) 2052 active = true; 2053 2054 /* 2055 * Check if the interrupt controller has seen any changes in the 2056 * interrupt line. 2057 */ 2058 regmap_read(info->map, REG(OCELOT_GPIO_INTR, info, gpio), &val); 2059 if (val & bit) 2060 ack = true; 2061 2062 /* Try to clear any rising edges */ 2063 if (!active && ack) 2064 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 2065 bit, bit); 2066 2067 /* Enable the interrupt now */ 2068 gpiochip_enable_irq(chip, gpio); 2069 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 2070 bit, bit); 2071 2072 /* 2073 * In case the interrupt line is still active then it means that 2074 * there happen another interrupt while the line was active. 2075 * So we missed that one, so we need to kick the interrupt again 2076 * handler. 2077 */ 2078 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val); 2079 if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) || 2080 (val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH)) 2081 active = true; 2082 2083 if (active) { 2084 struct ocelot_irq_work *work; 2085 2086 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2087 if (!work) 2088 return; 2089 2090 work->irq_desc = desc; 2091 INIT_WORK(&work->irq_work, ocelot_irq_work); 2092 queue_work(info->wq, &work->irq_work); 2093 } 2094 } 2095 2096 static void ocelot_irq_unmask(struct irq_data *data) 2097 { 2098 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 2099 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2100 unsigned int gpio = irqd_to_hwirq(data); 2101 2102 gpiochip_enable_irq(chip, gpio); 2103 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), 2104 BIT(gpio % 32), BIT(gpio % 32)); 2105 } 2106 2107 static void ocelot_irq_ack(struct irq_data *data) 2108 { 2109 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 2110 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2111 unsigned int gpio = irqd_to_hwirq(data); 2112 2113 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), 2114 BIT(gpio % 32), BIT(gpio % 32)); 2115 } 2116 2117 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type); 2118 2119 static struct irq_chip ocelot_level_irqchip = { 2120 .name = "gpio", 2121 .irq_mask = ocelot_irq_mask, 2122 .irq_ack = ocelot_irq_ack, 2123 .irq_unmask = ocelot_irq_unmask_level, 2124 .flags = IRQCHIP_IMMUTABLE, 2125 .irq_set_type = ocelot_irq_set_type, 2126 GPIOCHIP_IRQ_RESOURCE_HELPERS 2127 }; 2128 2129 static struct irq_chip ocelot_irqchip = { 2130 .name = "gpio", 2131 .irq_mask = ocelot_irq_mask, 2132 .irq_ack = ocelot_irq_ack, 2133 .irq_unmask = ocelot_irq_unmask, 2134 .irq_set_type = ocelot_irq_set_type, 2135 .flags = IRQCHIP_IMMUTABLE, 2136 GPIOCHIP_IRQ_RESOURCE_HELPERS 2137 }; 2138 2139 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) 2140 { 2141 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 2142 irq_set_chip_handler_name_locked(data, &ocelot_level_irqchip, 2143 handle_level_irq, NULL); 2144 if (type & IRQ_TYPE_EDGE_BOTH) 2145 irq_set_chip_handler_name_locked(data, &ocelot_irqchip, 2146 handle_edge_irq, NULL); 2147 2148 return 0; 2149 } 2150 2151 static void ocelot_irq_handler(struct irq_desc *desc) 2152 { 2153 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 2154 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 2155 struct ocelot_pinctrl *info = gpiochip_get_data(chip); 2156 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; 2157 unsigned int reg = 0, irq, i; 2158 unsigned long irqs; 2159 2160 chained_irq_enter(parent_chip, desc); 2161 2162 for (i = 0; i < info->stride; i++) { 2163 regmap_read(info->map, id_reg + 4 * i, ®); 2164 if (!reg) 2165 continue; 2166 2167 irqs = reg; 2168 2169 for_each_set_bit(irq, &irqs, 2170 min(32U, info->desc->npins - 32 * i)) 2171 generic_handle_domain_irq(chip->irq.domain, irq + 32 * i); 2172 } 2173 2174 chained_irq_exit(parent_chip, desc); 2175 } 2176 2177 static int ocelot_gpiochip_register(struct platform_device *pdev, 2178 struct ocelot_pinctrl *info) 2179 { 2180 struct gpio_chip *gc; 2181 struct gpio_irq_chip *girq; 2182 int irq; 2183 2184 info->gpio_chip = ocelot_gpiolib_chip; 2185 2186 gc = &info->gpio_chip; 2187 gc->ngpio = info->desc->npins; 2188 gc->parent = &pdev->dev; 2189 gc->base = -1; 2190 gc->label = "ocelot-gpio"; 2191 2192 irq = platform_get_irq_optional(pdev, 0); 2193 if (irq > 0) { 2194 girq = &gc->irq; 2195 gpio_irq_chip_set_chip(girq, &ocelot_irqchip); 2196 girq->parent_handler = ocelot_irq_handler; 2197 girq->num_parents = 1; 2198 girq->parents = devm_kcalloc(&pdev->dev, 1, 2199 sizeof(*girq->parents), 2200 GFP_KERNEL); 2201 if (!girq->parents) 2202 return -ENOMEM; 2203 girq->parents[0] = irq; 2204 girq->default_type = IRQ_TYPE_NONE; 2205 girq->handler = handle_edge_irq; 2206 } 2207 2208 return devm_gpiochip_add_data(&pdev->dev, gc, info); 2209 } 2210 2211 static const struct of_device_id ocelot_pinctrl_of_match[] = { 2212 { .compatible = "mscc,luton-pinctrl", .data = &luton_desc }, 2213 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, 2214 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, 2215 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, 2216 { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, 2217 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 2218 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 2219 { .compatible = "microchip,lan9691-pinctrl", .data = &lan969x_desc }, 2220 {}, 2221 }; 2222 MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match); 2223 2224 static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev, 2225 const struct ocelot_pinctrl *info) 2226 { 2227 void __iomem *base; 2228 2229 const struct regmap_config regmap_config = { 2230 .reg_bits = 32, 2231 .val_bits = 32, 2232 .reg_stride = 4, 2233 .max_register = info->desc->npins * 4, 2234 .name = "pincfg", 2235 }; 2236 2237 base = devm_platform_ioremap_resource(pdev, 1); 2238 if (IS_ERR(base)) { 2239 dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); 2240 return NULL; 2241 } 2242 2243 return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); 2244 } 2245 2246 static void ocelot_destroy_workqueue(void *data) 2247 { 2248 destroy_workqueue(data); 2249 } 2250 2251 static int ocelot_pinctrl_probe(struct platform_device *pdev) 2252 { 2253 const struct ocelot_match_data *data; 2254 struct device *dev = &pdev->dev; 2255 struct ocelot_pinctrl *info; 2256 struct reset_control *reset; 2257 struct regmap *pincfg; 2258 int ret; 2259 struct regmap_config regmap_config = { 2260 .reg_bits = 32, 2261 .val_bits = 32, 2262 .reg_stride = 4, 2263 }; 2264 2265 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 2266 if (!info) 2267 return -ENOMEM; 2268 2269 data = device_get_match_data(dev); 2270 if (!data) 2271 return -EINVAL; 2272 2273 info->desc = devm_kmemdup(dev, &data->desc, sizeof(*info->desc), 2274 GFP_KERNEL); 2275 if (!info->desc) 2276 return -ENOMEM; 2277 2278 info->wq = alloc_ordered_workqueue("ocelot_ordered", 0); 2279 if (!info->wq) 2280 return -ENOMEM; 2281 2282 ret = devm_add_action_or_reset(dev, ocelot_destroy_workqueue, 2283 info->wq); 2284 if (ret) 2285 return ret; 2286 2287 info->pincfg_data = &data->pincfg_data; 2288 2289 reset = devm_reset_control_get_optional_shared(dev, "switch"); 2290 if (IS_ERR(reset)) 2291 return dev_err_probe(dev, PTR_ERR(reset), 2292 "Failed to get reset\n"); 2293 reset_control_reset(reset); 2294 2295 info->stride = 1 + (info->desc->npins - 1) / 32; 2296 2297 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; 2298 2299 info->map = ocelot_regmap_from_resource(pdev, 0, ®map_config); 2300 if (IS_ERR(info->map)) 2301 return dev_err_probe(dev, PTR_ERR(info->map), 2302 "Failed to create regmap\n"); 2303 dev_set_drvdata(dev, info); 2304 info->dev = dev; 2305 2306 /* Pinconf registers */ 2307 if (info->desc->confops) { 2308 pincfg = ocelot_pinctrl_create_pincfg(pdev, info); 2309 if (IS_ERR(pincfg)) 2310 dev_dbg(dev, "Failed to create pincfg regmap\n"); 2311 else 2312 info->pincfg = pincfg; 2313 } 2314 2315 ret = ocelot_pinctrl_register(pdev, info); 2316 if (ret) 2317 return ret; 2318 2319 ret = ocelot_gpiochip_register(pdev, info); 2320 if (ret) 2321 return ret; 2322 2323 dev_info(dev, "driver registered\n"); 2324 2325 return 0; 2326 } 2327 2328 static struct platform_driver ocelot_pinctrl_driver = { 2329 .driver = { 2330 .name = "pinctrl-ocelot", 2331 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match), 2332 .suppress_bind_attrs = true, 2333 }, 2334 .probe = ocelot_pinctrl_probe, 2335 }; 2336 module_platform_driver(ocelot_pinctrl_driver); 2337 2338 MODULE_DESCRIPTION("Ocelot Chip Pinctrl Driver"); 2339 MODULE_LICENSE("Dual MIT/GPL"); 2340