1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Microsemi/Microchip SoCs serial gpio driver 4 * 5 * Author: Lars Povlsen <lars.povlsen@microchip.com> 6 * 7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/clk.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/io.h> 15 #include <linux/mfd/ocelot.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/property.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 #include <linux/spinlock.h> 22 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinmux.h> 25 26 #include "core.h" 27 #include "pinconf.h" 28 29 #define SGPIO_BITS_PER_WORD 32 30 #define SGPIO_MAX_BITS 4 31 #define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */ 32 33 enum { 34 REG_INPUT_DATA, 35 REG_PORT_CONFIG, 36 REG_PORT_ENABLE, 37 REG_SIO_CONFIG, 38 REG_SIO_CLOCK, 39 REG_INT_POLARITY, 40 REG_INT_TRIGGER, 41 REG_INT_ACK, 42 REG_INT_ENABLE, 43 REG_INT_IDENT, 44 MAXREG 45 }; 46 47 enum { 48 SGPIO_ARCH_LUTON, 49 SGPIO_ARCH_OCELOT, 50 SGPIO_ARCH_SPARX5, 51 }; 52 53 enum { 54 SGPIO_FLAGS_HAS_IRQ = BIT(0), 55 }; 56 57 struct sgpio_properties { 58 int arch; 59 int flags; 60 u8 regoff[MAXREG]; 61 }; 62 63 #define SGPIO_LUTON_AUTO_REPEAT BIT(5) 64 #define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2) 65 #define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0) 66 #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0) 67 68 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10) 69 #define SGPIO_OCELOT_SINGLE_SHOT BIT(11) 70 #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7) 71 #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8) 72 #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12) 73 74 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6) 75 #define SGPIO_SPARX5_SINGLE_SHOT BIT(7) 76 #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3) 77 #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8) 78 #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12) 79 80 #define SGPIO_MASTER_INTR_ENA BIT(0) 81 82 #define SGPIO_INT_TRG_LEVEL 0 83 #define SGPIO_INT_TRG_EDGE 1 84 #define SGPIO_INT_TRG_EDGE_FALL 2 85 #define SGPIO_INT_TRG_EDGE_RISE 3 86 87 #define SGPIO_TRG_LEVEL_HIGH 0 88 #define SGPIO_TRG_LEVEL_LOW 1 89 90 static const struct sgpio_properties properties_luton = { 91 .arch = SGPIO_ARCH_LUTON, 92 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b }, 93 }; 94 95 static const struct sgpio_properties properties_ocelot = { 96 .arch = SGPIO_ARCH_OCELOT, 97 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, 98 }; 99 100 static const struct sgpio_properties properties_sparx5 = { 101 .arch = SGPIO_ARCH_SPARX5, 102 .flags = SGPIO_FLAGS_HAS_IRQ, 103 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 }, 104 }; 105 106 static const char * const functions[] = { "gpio" }; 107 108 struct sgpio_bank { 109 struct sgpio_priv *priv; 110 bool is_input; 111 struct gpio_chip gpio; 112 struct pinctrl_desc pctl_desc; 113 }; 114 115 struct sgpio_priv { 116 struct device *dev; 117 struct sgpio_bank in; 118 struct sgpio_bank out; 119 u32 bitcount; 120 u32 ports; 121 u32 clock; 122 struct regmap *regs; 123 const struct sgpio_properties *properties; 124 spinlock_t lock; 125 /* protects the config register and single shot mode */ 126 struct mutex poll_lock; 127 }; 128 129 struct sgpio_port_addr { 130 u8 port; 131 u8 bit; 132 }; 133 134 static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin, 135 struct sgpio_port_addr *addr) 136 { 137 addr->port = pin / priv->bitcount; 138 addr->bit = pin % priv->bitcount; 139 } 140 141 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit) 142 { 143 return bit + port * priv->bitcount; 144 } 145 146 static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off) 147 { 148 return (priv->properties->regoff[rno] + off) * 149 regmap_get_reg_stride(priv->regs); 150 } 151 152 static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) 153 { 154 u32 addr = sgpio_get_addr(priv, rno, off); 155 u32 val = 0; 156 int ret; 157 158 ret = regmap_read(priv->regs, addr, &val); 159 WARN_ONCE(ret, "error reading sgpio reg %d\n", ret); 160 161 return val; 162 } 163 164 static void sgpio_writel(struct sgpio_priv *priv, 165 u32 val, u32 rno, u32 off) 166 { 167 u32 addr = sgpio_get_addr(priv, rno, off); 168 int ret; 169 170 ret = regmap_write(priv->regs, addr, val); 171 WARN_ONCE(ret, "error writing sgpio reg %d\n", ret); 172 } 173 174 static inline void sgpio_clrsetbits(struct sgpio_priv *priv, 175 u32 rno, u32 off, u32 clear, u32 set) 176 { 177 u32 addr = sgpio_get_addr(priv, rno, off); 178 int ret; 179 180 ret = regmap_update_bits(priv->regs, addr, clear | set, set); 181 WARN_ONCE(ret, "error updating sgpio reg %d\n", ret); 182 } 183 184 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv) 185 { 186 int width = priv->bitcount - 1; 187 u32 clr, set; 188 189 switch (priv->properties->arch) { 190 case SGPIO_ARCH_LUTON: 191 clr = SGPIO_LUTON_PORT_WIDTH; 192 set = SGPIO_LUTON_AUTO_REPEAT | 193 FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width); 194 break; 195 case SGPIO_ARCH_OCELOT: 196 clr = SGPIO_OCELOT_PORT_WIDTH; 197 set = SGPIO_OCELOT_AUTO_REPEAT | 198 FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width); 199 break; 200 case SGPIO_ARCH_SPARX5: 201 clr = SGPIO_SPARX5_PORT_WIDTH; 202 set = SGPIO_SPARX5_AUTO_REPEAT | 203 FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width); 204 break; 205 default: 206 return; 207 } 208 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); 209 } 210 211 static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq) 212 { 213 u32 clr, set; 214 215 switch (priv->properties->arch) { 216 case SGPIO_ARCH_LUTON: 217 clr = SGPIO_LUTON_CLK_FREQ; 218 set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq); 219 break; 220 case SGPIO_ARCH_OCELOT: 221 clr = SGPIO_OCELOT_CLK_FREQ; 222 set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq); 223 break; 224 case SGPIO_ARCH_SPARX5: 225 clr = SGPIO_SPARX5_CLK_FREQ; 226 set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq); 227 break; 228 default: 229 return; 230 } 231 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); 232 } 233 234 static int sgpio_single_shot(struct sgpio_priv *priv) 235 { 236 u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0); 237 int ret, ret2; 238 u32 ctrl; 239 unsigned int single_shot; 240 unsigned int auto_repeat; 241 242 switch (priv->properties->arch) { 243 case SGPIO_ARCH_LUTON: 244 /* not supported for now */ 245 return 0; 246 case SGPIO_ARCH_OCELOT: 247 single_shot = SGPIO_OCELOT_SINGLE_SHOT; 248 auto_repeat = SGPIO_OCELOT_AUTO_REPEAT; 249 break; 250 case SGPIO_ARCH_SPARX5: 251 single_shot = SGPIO_SPARX5_SINGLE_SHOT; 252 auto_repeat = SGPIO_SPARX5_AUTO_REPEAT; 253 break; 254 default: 255 return -EINVAL; 256 } 257 258 /* 259 * Trigger immediate burst. This only works when auto repeat is turned 260 * off. Otherwise, the single shot bit will never be cleared by the 261 * hardware. Measurements showed that an update might take as long as 262 * the burst gap. On a LAN9668 this is about 50ms for the largest 263 * setting. 264 * After the manual burst, reenable the auto repeat mode again. 265 */ 266 guard(mutex)(&priv->poll_lock); 267 ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat, 268 single_shot); 269 if (ret) 270 return ret; 271 272 ret = regmap_read_poll_timeout(priv->regs, addr, ctrl, 273 !(ctrl & single_shot), 100, 60000); 274 275 /* reenable auto repeat mode even if there was an error */ 276 ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat); 277 278 return ret ?: ret2; 279 } 280 281 static int sgpio_output_set(struct sgpio_priv *priv, 282 struct sgpio_port_addr *addr, 283 int value) 284 { 285 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 286 u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port); 287 bool changed; 288 u32 clr, set; 289 int ret; 290 291 switch (priv->properties->arch) { 292 case SGPIO_ARCH_LUTON: 293 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit)); 294 set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit); 295 break; 296 case SGPIO_ARCH_OCELOT: 297 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit)); 298 set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit); 299 break; 300 case SGPIO_ARCH_SPARX5: 301 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit)); 302 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit); 303 break; 304 default: 305 return -EINVAL; 306 } 307 308 ret = regmap_update_bits_check(priv->regs, reg, clr | set, set, 309 &changed); 310 if (ret) 311 return ret; 312 313 if (changed) { 314 ret = sgpio_single_shot(priv); 315 if (ret) 316 return ret; 317 } 318 319 return 0; 320 } 321 322 static int sgpio_output_get(struct sgpio_priv *priv, 323 struct sgpio_port_addr *addr) 324 { 325 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port); 326 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 327 328 switch (priv->properties->arch) { 329 case SGPIO_ARCH_LUTON: 330 val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval); 331 break; 332 case SGPIO_ARCH_OCELOT: 333 val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval); 334 break; 335 case SGPIO_ARCH_SPARX5: 336 val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval); 337 break; 338 default: 339 val = 0; 340 break; 341 } 342 return !!(val & BIT(bit)); 343 } 344 345 static int sgpio_input_get(struct sgpio_priv *priv, 346 struct sgpio_port_addr *addr) 347 { 348 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port)); 349 } 350 351 static int sgpio_pinconf_get(struct pinctrl_dev *pctldev, 352 unsigned int pin, unsigned long *config) 353 { 354 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 355 u32 param = pinconf_to_config_param(*config); 356 struct sgpio_priv *priv = bank->priv; 357 struct sgpio_port_addr addr; 358 int val; 359 360 sgpio_pin_to_addr(priv, pin, &addr); 361 362 switch (param) { 363 case PIN_CONFIG_INPUT_ENABLE: 364 val = bank->is_input; 365 break; 366 367 case PIN_CONFIG_OUTPUT_ENABLE: 368 val = !bank->is_input; 369 break; 370 371 case PIN_CONFIG_LEVEL: 372 if (bank->is_input) 373 return -EINVAL; 374 val = sgpio_output_get(priv, &addr); 375 break; 376 377 default: 378 return -ENOTSUPP; 379 } 380 381 *config = pinconf_to_config_packed(param, val); 382 383 return 0; 384 } 385 386 static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 387 unsigned long *configs, unsigned int num_configs) 388 { 389 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 390 struct sgpio_priv *priv = bank->priv; 391 struct sgpio_port_addr addr; 392 int cfg, err = 0; 393 u32 param, arg; 394 395 sgpio_pin_to_addr(priv, pin, &addr); 396 397 for (cfg = 0; cfg < num_configs; cfg++) { 398 param = pinconf_to_config_param(configs[cfg]); 399 arg = pinconf_to_config_argument(configs[cfg]); 400 401 switch (param) { 402 case PIN_CONFIG_LEVEL: 403 if (bank->is_input) 404 return -EINVAL; 405 err = sgpio_output_set(priv, &addr, arg); 406 break; 407 408 default: 409 err = -ENOTSUPP; 410 } 411 } 412 413 return err; 414 } 415 416 static const struct pinconf_ops sgpio_confops = { 417 .is_generic = true, 418 .pin_config_get = sgpio_pinconf_get, 419 .pin_config_set = sgpio_pinconf_set, 420 .pin_config_config_dbg_show = pinconf_generic_dump_config, 421 }; 422 423 static int sgpio_get_functions_count(struct pinctrl_dev *pctldev) 424 { 425 return 1; 426 } 427 428 static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev, 429 unsigned int function) 430 { 431 return functions[0]; 432 } 433 434 static int sgpio_get_function_groups(struct pinctrl_dev *pctldev, 435 unsigned int function, 436 const char *const **groups, 437 unsigned *const num_groups) 438 { 439 *groups = functions; 440 *num_groups = ARRAY_SIZE(functions); 441 442 return 0; 443 } 444 445 static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev, 446 unsigned int selector, unsigned int group) 447 { 448 return 0; 449 } 450 451 static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev, 452 struct pinctrl_gpio_range *range, 453 unsigned int pin, bool input) 454 { 455 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 456 457 return (input == bank->is_input) ? 0 : -EINVAL; 458 } 459 460 static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev, 461 struct pinctrl_gpio_range *range, 462 unsigned int offset) 463 { 464 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 465 struct sgpio_priv *priv = bank->priv; 466 struct sgpio_port_addr addr; 467 468 sgpio_pin_to_addr(priv, offset, &addr); 469 470 if ((priv->ports & BIT(addr.port)) == 0) { 471 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n", 472 addr.port, addr.bit); 473 return -EINVAL; 474 } 475 476 return 0; 477 } 478 479 static const struct pinmux_ops sgpio_pmx_ops = { 480 .get_functions_count = sgpio_get_functions_count, 481 .get_function_name = sgpio_get_function_name, 482 .get_function_groups = sgpio_get_function_groups, 483 .set_mux = sgpio_pinmux_set_mux, 484 .gpio_set_direction = sgpio_gpio_set_direction, 485 .gpio_request_enable = sgpio_gpio_request_enable, 486 }; 487 488 static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev) 489 { 490 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 491 492 return bank->pctl_desc.npins; 493 } 494 495 static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev, 496 unsigned int group) 497 { 498 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 499 500 return bank->pctl_desc.pins[group].name; 501 } 502 503 static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev, 504 unsigned int group, 505 const unsigned int **pins, 506 unsigned int *num_pins) 507 { 508 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 509 510 *pins = &bank->pctl_desc.pins[group].number; 511 *num_pins = 1; 512 513 return 0; 514 } 515 516 static const struct pinctrl_ops sgpio_pctl_ops = { 517 .get_groups_count = sgpio_pctl_get_groups_count, 518 .get_group_name = sgpio_pctl_get_group_name, 519 .get_group_pins = sgpio_pctl_get_group_pins, 520 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 521 .dt_free_map = pinconf_generic_dt_free_map, 522 }; 523 524 static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio) 525 { 526 struct sgpio_bank *bank = gpiochip_get_data(gc); 527 528 /* Fixed-position function */ 529 return bank->is_input ? 0 : -EINVAL; 530 } 531 532 static int microchip_sgpio_direction_output(struct gpio_chip *gc, 533 unsigned int gpio, int value) 534 { 535 struct sgpio_bank *bank = gpiochip_get_data(gc); 536 struct sgpio_priv *priv = bank->priv; 537 struct sgpio_port_addr addr; 538 539 /* Fixed-position function */ 540 if (bank->is_input) 541 return -EINVAL; 542 543 sgpio_pin_to_addr(priv, gpio, &addr); 544 545 return sgpio_output_set(priv, &addr, value); 546 } 547 548 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 549 { 550 struct sgpio_bank *bank = gpiochip_get_data(gc); 551 552 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 553 } 554 555 static int microchip_sgpio_set_value(struct gpio_chip *gc, unsigned int gpio, 556 int value) 557 { 558 return microchip_sgpio_direction_output(gc, gpio, value); 559 } 560 561 static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio) 562 { 563 struct sgpio_bank *bank = gpiochip_get_data(gc); 564 struct sgpio_priv *priv = bank->priv; 565 struct sgpio_port_addr addr; 566 567 sgpio_pin_to_addr(priv, gpio, &addr); 568 569 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr); 570 } 571 572 static int microchip_sgpio_of_xlate(struct gpio_chip *gc, 573 const struct of_phandle_args *gpiospec, 574 u32 *flags) 575 { 576 struct sgpio_bank *bank = gpiochip_get_data(gc); 577 struct sgpio_priv *priv = bank->priv; 578 int pin; 579 580 /* 581 * Note that the SGIO pin is defined by *2* numbers, a port 582 * number between 0 and 31, and a bit index, 0 to 3. 583 */ 584 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD || 585 gpiospec->args[1] > priv->bitcount) 586 return -EINVAL; 587 588 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]); 589 590 if (pin > gc->ngpio) 591 return -EINVAL; 592 593 if (flags) 594 *flags = gpiospec->args[2]; 595 596 return pin; 597 } 598 599 static int microchip_sgpio_get_ports(struct sgpio_priv *priv) 600 { 601 const char *range_property_name = "microchip,sgpio-port-ranges"; 602 struct device *dev = priv->dev; 603 u32 range_params[64]; 604 int i, nranges, ret; 605 606 /* Calculate port mask */ 607 nranges = device_property_count_u32(dev, range_property_name); 608 if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) { 609 dev_err(dev, "%s port range: '%s' property\n", 610 nranges == -EINVAL ? "Missing" : "Invalid", 611 range_property_name); 612 return -EINVAL; 613 } 614 615 ret = device_property_read_u32_array(dev, range_property_name, 616 range_params, nranges); 617 if (ret) { 618 dev_err(dev, "failed to parse '%s' property: %d\n", 619 range_property_name, ret); 620 return ret; 621 } 622 for (i = 0; i < nranges; i += 2) { 623 int start, end; 624 625 start = range_params[i]; 626 end = range_params[i + 1]; 627 if (start > end || end >= SGPIO_BITS_PER_WORD) { 628 dev_err(dev, "Ill-formed port-range [%d:%d]\n", 629 start, end); 630 } 631 priv->ports |= GENMASK(end, start); 632 } 633 634 return 0; 635 } 636 637 static void microchip_sgpio_irq_settype(struct irq_data *data, 638 int type, 639 int polarity) 640 { 641 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 642 struct sgpio_bank *bank = gpiochip_get_data(chip); 643 unsigned int gpio = irqd_to_hwirq(data); 644 struct sgpio_port_addr addr; 645 unsigned long flags; 646 u32 ena; 647 648 sgpio_pin_to_addr(bank->priv, gpio, &addr); 649 650 spin_lock_irqsave(&bank->priv->lock, flags); 651 652 /* Disable interrupt while changing type */ 653 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit); 654 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit); 655 656 /* Type value spread over 2 registers sets: low, high bit */ 657 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit, 658 BIT(addr.port), (!!(type & 0x1)) << addr.port); 659 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit, 660 BIT(addr.port), (!!(type & 0x2)) << addr.port); 661 662 if (type == SGPIO_INT_TRG_LEVEL) 663 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit, 664 BIT(addr.port), polarity << addr.port); 665 666 /* Possibly re-enable interrupts */ 667 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit); 668 669 spin_unlock_irqrestore(&bank->priv->lock, flags); 670 } 671 672 static void microchip_sgpio_irq_setreg(struct irq_data *data, 673 int reg, 674 bool clear) 675 { 676 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 677 struct sgpio_bank *bank = gpiochip_get_data(chip); 678 unsigned int gpio = irqd_to_hwirq(data); 679 struct sgpio_port_addr addr; 680 681 sgpio_pin_to_addr(bank->priv, gpio, &addr); 682 683 if (clear) 684 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0); 685 else 686 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port)); 687 } 688 689 static void microchip_sgpio_irq_mask(struct irq_data *data) 690 { 691 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 692 693 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true); 694 gpiochip_disable_irq(chip, data->hwirq); 695 } 696 697 static void microchip_sgpio_irq_unmask(struct irq_data *data) 698 { 699 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 700 701 gpiochip_enable_irq(chip, data->hwirq); 702 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false); 703 } 704 705 static void microchip_sgpio_irq_ack(struct irq_data *data) 706 { 707 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 708 struct sgpio_bank *bank = gpiochip_get_data(chip); 709 unsigned int gpio = irqd_to_hwirq(data); 710 struct sgpio_port_addr addr; 711 712 sgpio_pin_to_addr(bank->priv, gpio, &addr); 713 714 sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit); 715 } 716 717 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type) 718 { 719 switch (type) { 720 case IRQ_TYPE_EDGE_BOTH: 721 irq_set_handler_locked(data, handle_edge_irq); 722 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0); 723 break; 724 case IRQ_TYPE_EDGE_RISING: 725 irq_set_handler_locked(data, handle_edge_irq); 726 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0); 727 break; 728 case IRQ_TYPE_EDGE_FALLING: 729 irq_set_handler_locked(data, handle_edge_irq); 730 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0); 731 break; 732 case IRQ_TYPE_LEVEL_HIGH: 733 irq_set_handler_locked(data, handle_level_irq); 734 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH); 735 break; 736 case IRQ_TYPE_LEVEL_LOW: 737 irq_set_handler_locked(data, handle_level_irq); 738 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW); 739 break; 740 default: 741 return -EINVAL; 742 } 743 744 return 0; 745 } 746 747 static const struct irq_chip microchip_sgpio_irqchip = { 748 .name = "gpio", 749 .irq_mask = microchip_sgpio_irq_mask, 750 .irq_ack = microchip_sgpio_irq_ack, 751 .irq_unmask = microchip_sgpio_irq_unmask, 752 .irq_set_type = microchip_sgpio_irq_set_type, 753 .flags = IRQCHIP_IMMUTABLE, 754 GPIOCHIP_IRQ_RESOURCE_HELPERS, 755 }; 756 757 static void sgpio_irq_handler(struct irq_desc *desc) 758 { 759 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 760 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 761 struct sgpio_bank *bank = gpiochip_get_data(chip); 762 struct sgpio_priv *priv = bank->priv; 763 int bit, port, gpio; 764 long val; 765 766 for (bit = 0; bit < priv->bitcount; bit++) { 767 val = sgpio_readl(priv, REG_INT_IDENT, bit); 768 if (!val) 769 continue; 770 771 chained_irq_enter(parent_chip, desc); 772 773 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) { 774 gpio = sgpio_addr_to_pin(priv, port, bit); 775 generic_handle_domain_irq(chip->irq.domain, gpio); 776 } 777 778 chained_irq_exit(parent_chip, desc); 779 } 780 } 781 782 static int microchip_sgpio_register_bank(struct device *dev, 783 struct sgpio_priv *priv, 784 struct fwnode_handle *fwnode, 785 int bankno) 786 { 787 struct pinctrl_pin_desc *pins; 788 struct pinctrl_desc *pctl_desc; 789 struct pinctrl_dev *pctldev; 790 struct sgpio_bank *bank; 791 struct gpio_chip *gc; 792 u32 ngpios; 793 int i, ret; 794 795 /* Get overall bank struct */ 796 bank = (bankno == 0) ? &priv->in : &priv->out; 797 bank->priv = priv; 798 799 if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) { 800 dev_info(dev, "failed to get number of gpios for bank%d\n", 801 bankno); 802 ngpios = 64; 803 } 804 805 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD; 806 if (priv->bitcount > SGPIO_MAX_BITS) { 807 dev_err(dev, "Bit width exceeds maximum (%d)\n", 808 SGPIO_MAX_BITS); 809 return -EINVAL; 810 } 811 812 pctl_desc = &bank->pctl_desc; 813 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput", 814 dev_name(dev), 815 bank->is_input ? "in" : "out"); 816 if (!pctl_desc->name) 817 return -ENOMEM; 818 819 pctl_desc->pctlops = &sgpio_pctl_ops; 820 pctl_desc->pmxops = &sgpio_pmx_ops; 821 pctl_desc->confops = &sgpio_confops; 822 pctl_desc->owner = THIS_MODULE; 823 824 pins = devm_kcalloc(dev, ngpios, sizeof(*pins), GFP_KERNEL); 825 if (!pins) 826 return -ENOMEM; 827 828 pctl_desc->npins = ngpios; 829 pctl_desc->pins = pins; 830 831 for (i = 0; i < ngpios; i++) { 832 struct sgpio_port_addr addr; 833 834 sgpio_pin_to_addr(priv, i, &addr); 835 836 pins[i].number = i; 837 pins[i].name = devm_kasprintf(dev, GFP_KERNEL, 838 "SGPIO_%c_p%db%d", 839 bank->is_input ? 'I' : 'O', 840 addr.port, addr.bit); 841 if (!pins[i].name) 842 return -ENOMEM; 843 } 844 845 pctldev = devm_pinctrl_register(dev, pctl_desc, bank); 846 if (IS_ERR(pctldev)) 847 return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n"); 848 849 gc = &bank->gpio; 850 gc->label = pctl_desc->name; 851 gc->parent = dev; 852 gc->fwnode = fwnode; 853 gc->owner = THIS_MODULE; 854 gc->get_direction = microchip_sgpio_get_direction; 855 gc->direction_input = microchip_sgpio_direction_input; 856 gc->direction_output = microchip_sgpio_direction_output; 857 gc->get = microchip_sgpio_get_value; 858 gc->set = microchip_sgpio_set_value; 859 gc->request = gpiochip_generic_request; 860 gc->free = gpiochip_generic_free; 861 gc->of_xlate = microchip_sgpio_of_xlate; 862 gc->of_gpio_n_cells = 3; 863 gc->base = -1; 864 gc->ngpio = ngpios; 865 gc->can_sleep = !bank->is_input; 866 867 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) { 868 int irq; 869 870 irq = fwnode_irq_get(fwnode, 0); 871 if (irq > 0) { 872 struct gpio_irq_chip *girq = &gc->irq; 873 874 gpio_irq_chip_set_chip(girq, µchip_sgpio_irqchip); 875 girq->parent_handler = sgpio_irq_handler; 876 girq->num_parents = 1; 877 girq->parents = devm_kcalloc(dev, 1, 878 sizeof(*girq->parents), 879 GFP_KERNEL); 880 if (!girq->parents) 881 return -ENOMEM; 882 girq->parents[0] = irq; 883 girq->default_type = IRQ_TYPE_NONE; 884 girq->handler = handle_bad_irq; 885 886 /* Disable all individual pins */ 887 for (i = 0; i < SGPIO_MAX_BITS; i++) 888 sgpio_writel(priv, 0, REG_INT_ENABLE, i); 889 /* Master enable */ 890 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA); 891 } 892 } 893 894 ret = devm_gpiochip_add_data(dev, gc, bank); 895 if (ret) 896 dev_err(dev, "Failed to register: ret %d\n", ret); 897 898 return ret; 899 } 900 901 static int microchip_sgpio_probe(struct platform_device *pdev) 902 { 903 int div_clock = 0, ret, port, i, nbanks; 904 struct device *dev = &pdev->dev; 905 struct fwnode_handle *fwnode; 906 struct reset_control *reset; 907 struct sgpio_priv *priv; 908 struct clk *clk; 909 u32 val; 910 struct regmap_config regmap_config = { 911 .reg_bits = 32, 912 .val_bits = 32, 913 .reg_stride = 4, 914 }; 915 916 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 917 if (!priv) 918 return -ENOMEM; 919 920 priv->dev = dev; 921 spin_lock_init(&priv->lock); 922 mutex_init(&priv->poll_lock); 923 924 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); 925 if (IS_ERR(reset)) 926 return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n"); 927 reset_control_reset(reset); 928 929 clk = devm_clk_get(dev, NULL); 930 if (IS_ERR(clk)) 931 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n"); 932 933 div_clock = clk_get_rate(clk); 934 if (device_property_read_u32(dev, "bus-frequency", &priv->clock)) 935 priv->clock = 12500000; 936 if (priv->clock == 0 || priv->clock > (div_clock / 2)) { 937 dev_err(dev, "Invalid frequency %d\n", priv->clock); 938 return -EINVAL; 939 } 940 941 priv->regs = ocelot_regmap_from_resource(pdev, 0, ®map_config); 942 if (IS_ERR(priv->regs)) 943 return PTR_ERR(priv->regs); 944 945 priv->properties = device_get_match_data(dev); 946 priv->in.is_input = true; 947 948 /* Get rest of device properties */ 949 ret = microchip_sgpio_get_ports(priv); 950 if (ret) 951 return ret; 952 953 nbanks = device_get_child_node_count(dev); 954 if (nbanks != 2) { 955 dev_err(dev, "Must have 2 banks (have %d)\n", nbanks); 956 return -EINVAL; 957 } 958 959 i = 0; 960 device_for_each_child_node(dev, fwnode) { 961 ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++); 962 if (ret) { 963 fwnode_handle_put(fwnode); 964 return ret; 965 } 966 } 967 968 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) { 969 dev_err(dev, "Banks must have same GPIO count\n"); 970 return -ERANGE; 971 } 972 973 sgpio_configure_bitstream(priv); 974 975 val = max(2U, div_clock / priv->clock); 976 sgpio_configure_clock(priv, val); 977 978 for (port = 0; port < SGPIO_BITS_PER_WORD; port++) 979 sgpio_writel(priv, 0, REG_PORT_CONFIG, port); 980 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0); 981 982 return 0; 983 } 984 985 static const struct of_device_id microchip_sgpio_gpio_of_match[] = { 986 { 987 .compatible = "microchip,sparx5-sgpio", 988 .data = &properties_sparx5, 989 }, { 990 .compatible = "mscc,luton-sgpio", 991 .data = &properties_luton, 992 }, { 993 .compatible = "mscc,ocelot-sgpio", 994 .data = &properties_ocelot, 995 }, { 996 /* sentinel */ 997 } 998 }; 999 MODULE_DEVICE_TABLE(of, microchip_sgpio_gpio_of_match); 1000 1001 static struct platform_driver microchip_sgpio_pinctrl_driver = { 1002 .driver = { 1003 .name = "pinctrl-microchip-sgpio", 1004 .of_match_table = microchip_sgpio_gpio_of_match, 1005 .suppress_bind_attrs = true, 1006 }, 1007 .probe = microchip_sgpio_probe, 1008 }; 1009 module_platform_driver(microchip_sgpio_pinctrl_driver); 1010 1011 MODULE_DESCRIPTION("Microchip SGPIO Pinctrl Driver"); 1012 MODULE_LICENSE("GPL"); 1013