1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Microsemi/Microchip SoCs serial gpio driver 4 * 5 * Author: Lars Povlsen <lars.povlsen@microchip.com> 6 * 7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/clk.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/io.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 21 #include "core.h" 22 #include "pinconf.h" 23 24 #define SGPIO_BITS_PER_WORD 32 25 #define SGPIO_MAX_BITS 4 26 #define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */ 27 28 enum { 29 REG_INPUT_DATA, 30 REG_PORT_CONFIG, 31 REG_PORT_ENABLE, 32 REG_SIO_CONFIG, 33 REG_SIO_CLOCK, 34 REG_INT_POLARITY, 35 REG_INT_TRIGGER, 36 REG_INT_ACK, 37 REG_INT_ENABLE, 38 REG_INT_IDENT, 39 MAXREG 40 }; 41 42 enum { 43 SGPIO_ARCH_LUTON, 44 SGPIO_ARCH_OCELOT, 45 SGPIO_ARCH_SPARX5, 46 }; 47 48 enum { 49 SGPIO_FLAGS_HAS_IRQ = BIT(0), 50 }; 51 52 struct sgpio_properties { 53 int arch; 54 int flags; 55 u8 regoff[MAXREG]; 56 }; 57 58 #define SGPIO_LUTON_AUTO_REPEAT BIT(5) 59 #define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2) 60 #define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0) 61 #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0) 62 63 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10) 64 #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7) 65 #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8) 66 #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12) 67 68 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6) 69 #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3) 70 #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8) 71 #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12) 72 73 #define SGPIO_MASTER_INTR_ENA BIT(0) 74 75 #define SGPIO_INT_TRG_LEVEL 0 76 #define SGPIO_INT_TRG_EDGE 1 77 #define SGPIO_INT_TRG_EDGE_FALL 2 78 #define SGPIO_INT_TRG_EDGE_RISE 3 79 80 #define SGPIO_TRG_LEVEL_HIGH 0 81 #define SGPIO_TRG_LEVEL_LOW 1 82 83 static const struct sgpio_properties properties_luton = { 84 .arch = SGPIO_ARCH_LUTON, 85 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b }, 86 }; 87 88 static const struct sgpio_properties properties_ocelot = { 89 .arch = SGPIO_ARCH_OCELOT, 90 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, 91 }; 92 93 static const struct sgpio_properties properties_sparx5 = { 94 .arch = SGPIO_ARCH_SPARX5, 95 .flags = SGPIO_FLAGS_HAS_IRQ, 96 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 }, 97 }; 98 99 static const char * const functions[] = { "gpio" }; 100 101 struct sgpio_bank { 102 struct sgpio_priv *priv; 103 bool is_input; 104 struct gpio_chip gpio; 105 struct pinctrl_desc pctl_desc; 106 }; 107 108 struct sgpio_priv { 109 struct device *dev; 110 struct sgpio_bank in; 111 struct sgpio_bank out; 112 u32 bitcount; 113 u32 ports; 114 u32 clock; 115 u32 __iomem *regs; 116 const struct sgpio_properties *properties; 117 }; 118 119 struct sgpio_port_addr { 120 u8 port; 121 u8 bit; 122 }; 123 124 static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin, 125 struct sgpio_port_addr *addr) 126 { 127 addr->port = pin / priv->bitcount; 128 addr->bit = pin % priv->bitcount; 129 } 130 131 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit) 132 { 133 return bit + port * priv->bitcount; 134 } 135 136 static inline u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) 137 { 138 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; 139 140 return readl(reg); 141 } 142 143 static inline void sgpio_writel(struct sgpio_priv *priv, 144 u32 val, u32 rno, u32 off) 145 { 146 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; 147 148 writel(val, reg); 149 } 150 151 static inline void sgpio_clrsetbits(struct sgpio_priv *priv, 152 u32 rno, u32 off, u32 clear, u32 set) 153 { 154 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; 155 u32 val = readl(reg); 156 157 val &= ~clear; 158 val |= set; 159 160 writel(val, reg); 161 } 162 163 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv) 164 { 165 int width = priv->bitcount - 1; 166 u32 clr, set; 167 168 switch (priv->properties->arch) { 169 case SGPIO_ARCH_LUTON: 170 clr = SGPIO_LUTON_PORT_WIDTH; 171 set = SGPIO_LUTON_AUTO_REPEAT | 172 FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width); 173 break; 174 case SGPIO_ARCH_OCELOT: 175 clr = SGPIO_OCELOT_PORT_WIDTH; 176 set = SGPIO_OCELOT_AUTO_REPEAT | 177 FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width); 178 break; 179 case SGPIO_ARCH_SPARX5: 180 clr = SGPIO_SPARX5_PORT_WIDTH; 181 set = SGPIO_SPARX5_AUTO_REPEAT | 182 FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width); 183 break; 184 default: 185 return; 186 } 187 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); 188 } 189 190 static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq) 191 { 192 u32 clr, set; 193 194 switch (priv->properties->arch) { 195 case SGPIO_ARCH_LUTON: 196 clr = SGPIO_LUTON_CLK_FREQ; 197 set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq); 198 break; 199 case SGPIO_ARCH_OCELOT: 200 clr = SGPIO_OCELOT_CLK_FREQ; 201 set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq); 202 break; 203 case SGPIO_ARCH_SPARX5: 204 clr = SGPIO_SPARX5_CLK_FREQ; 205 set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq); 206 break; 207 default: 208 return; 209 } 210 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); 211 } 212 213 static void sgpio_output_set(struct sgpio_priv *priv, 214 struct sgpio_port_addr *addr, 215 int value) 216 { 217 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 218 u32 clr, set; 219 220 switch (priv->properties->arch) { 221 case SGPIO_ARCH_LUTON: 222 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit)); 223 set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit); 224 break; 225 case SGPIO_ARCH_OCELOT: 226 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit)); 227 set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit); 228 break; 229 case SGPIO_ARCH_SPARX5: 230 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit)); 231 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit); 232 break; 233 default: 234 return; 235 } 236 sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set); 237 } 238 239 static int sgpio_output_get(struct sgpio_priv *priv, 240 struct sgpio_port_addr *addr) 241 { 242 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port); 243 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 244 245 switch (priv->properties->arch) { 246 case SGPIO_ARCH_LUTON: 247 val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval); 248 break; 249 case SGPIO_ARCH_OCELOT: 250 val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval); 251 break; 252 case SGPIO_ARCH_SPARX5: 253 val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval); 254 break; 255 default: 256 val = 0; 257 break; 258 } 259 return !!(val & BIT(bit)); 260 } 261 262 static int sgpio_input_get(struct sgpio_priv *priv, 263 struct sgpio_port_addr *addr) 264 { 265 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port)); 266 } 267 268 static int sgpio_pinconf_get(struct pinctrl_dev *pctldev, 269 unsigned int pin, unsigned long *config) 270 { 271 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 272 u32 param = pinconf_to_config_param(*config); 273 struct sgpio_priv *priv = bank->priv; 274 struct sgpio_port_addr addr; 275 int val; 276 277 sgpio_pin_to_addr(priv, pin, &addr); 278 279 switch (param) { 280 case PIN_CONFIG_INPUT_ENABLE: 281 val = bank->is_input; 282 break; 283 284 case PIN_CONFIG_OUTPUT_ENABLE: 285 val = !bank->is_input; 286 break; 287 288 case PIN_CONFIG_OUTPUT: 289 if (bank->is_input) 290 return -EINVAL; 291 val = sgpio_output_get(priv, &addr); 292 break; 293 294 default: 295 return -ENOTSUPP; 296 } 297 298 *config = pinconf_to_config_packed(param, val); 299 300 return 0; 301 } 302 303 static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 304 unsigned long *configs, unsigned int num_configs) 305 { 306 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 307 struct sgpio_priv *priv = bank->priv; 308 struct sgpio_port_addr addr; 309 int cfg, err = 0; 310 u32 param, arg; 311 312 sgpio_pin_to_addr(priv, pin, &addr); 313 314 for (cfg = 0; cfg < num_configs; cfg++) { 315 param = pinconf_to_config_param(configs[cfg]); 316 arg = pinconf_to_config_argument(configs[cfg]); 317 318 switch (param) { 319 case PIN_CONFIG_OUTPUT: 320 if (bank->is_input) 321 return -EINVAL; 322 sgpio_output_set(priv, &addr, arg); 323 break; 324 325 default: 326 err = -ENOTSUPP; 327 } 328 } 329 330 return err; 331 } 332 333 static const struct pinconf_ops sgpio_confops = { 334 .is_generic = true, 335 .pin_config_get = sgpio_pinconf_get, 336 .pin_config_set = sgpio_pinconf_set, 337 .pin_config_config_dbg_show = pinconf_generic_dump_config, 338 }; 339 340 static int sgpio_get_functions_count(struct pinctrl_dev *pctldev) 341 { 342 return 1; 343 } 344 345 static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev, 346 unsigned int function) 347 { 348 return functions[0]; 349 } 350 351 static int sgpio_get_function_groups(struct pinctrl_dev *pctldev, 352 unsigned int function, 353 const char *const **groups, 354 unsigned *const num_groups) 355 { 356 *groups = functions; 357 *num_groups = ARRAY_SIZE(functions); 358 359 return 0; 360 } 361 362 static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev, 363 unsigned int selector, unsigned int group) 364 { 365 return 0; 366 } 367 368 static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev, 369 struct pinctrl_gpio_range *range, 370 unsigned int pin, bool input) 371 { 372 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 373 374 return (input == bank->is_input) ? 0 : -EINVAL; 375 } 376 377 static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev, 378 struct pinctrl_gpio_range *range, 379 unsigned int offset) 380 { 381 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 382 struct sgpio_priv *priv = bank->priv; 383 struct sgpio_port_addr addr; 384 385 sgpio_pin_to_addr(priv, offset, &addr); 386 387 if ((priv->ports & BIT(addr.port)) == 0) { 388 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n", 389 addr.port, addr.bit); 390 return -EINVAL; 391 } 392 393 return 0; 394 } 395 396 static const struct pinmux_ops sgpio_pmx_ops = { 397 .get_functions_count = sgpio_get_functions_count, 398 .get_function_name = sgpio_get_function_name, 399 .get_function_groups = sgpio_get_function_groups, 400 .set_mux = sgpio_pinmux_set_mux, 401 .gpio_set_direction = sgpio_gpio_set_direction, 402 .gpio_request_enable = sgpio_gpio_request_enable, 403 }; 404 405 static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev) 406 { 407 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 408 409 return bank->pctl_desc.npins; 410 } 411 412 static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev, 413 unsigned int group) 414 { 415 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 416 417 return bank->pctl_desc.pins[group].name; 418 } 419 420 static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev, 421 unsigned int group, 422 const unsigned int **pins, 423 unsigned int *num_pins) 424 { 425 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 426 427 *pins = &bank->pctl_desc.pins[group].number; 428 *num_pins = 1; 429 430 return 0; 431 } 432 433 static const struct pinctrl_ops sgpio_pctl_ops = { 434 .get_groups_count = sgpio_pctl_get_groups_count, 435 .get_group_name = sgpio_pctl_get_group_name, 436 .get_group_pins = sgpio_pctl_get_group_pins, 437 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 438 .dt_free_map = pinconf_generic_dt_free_map, 439 }; 440 441 static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio) 442 { 443 struct sgpio_bank *bank = gpiochip_get_data(gc); 444 445 /* Fixed-position function */ 446 return bank->is_input ? 0 : -EINVAL; 447 } 448 449 static int microchip_sgpio_direction_output(struct gpio_chip *gc, 450 unsigned int gpio, int value) 451 { 452 struct sgpio_bank *bank = gpiochip_get_data(gc); 453 struct sgpio_priv *priv = bank->priv; 454 struct sgpio_port_addr addr; 455 456 /* Fixed-position function */ 457 if (bank->is_input) 458 return -EINVAL; 459 460 sgpio_pin_to_addr(priv, gpio, &addr); 461 462 sgpio_output_set(priv, &addr, value); 463 464 return 0; 465 } 466 467 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 468 { 469 struct sgpio_bank *bank = gpiochip_get_data(gc); 470 471 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 472 } 473 474 static void microchip_sgpio_set_value(struct gpio_chip *gc, 475 unsigned int gpio, int value) 476 { 477 microchip_sgpio_direction_output(gc, gpio, value); 478 } 479 480 static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio) 481 { 482 struct sgpio_bank *bank = gpiochip_get_data(gc); 483 struct sgpio_priv *priv = bank->priv; 484 struct sgpio_port_addr addr; 485 486 sgpio_pin_to_addr(priv, gpio, &addr); 487 488 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr); 489 } 490 491 static int microchip_sgpio_of_xlate(struct gpio_chip *gc, 492 const struct of_phandle_args *gpiospec, 493 u32 *flags) 494 { 495 struct sgpio_bank *bank = gpiochip_get_data(gc); 496 struct sgpio_priv *priv = bank->priv; 497 int pin; 498 499 /* 500 * Note that the SGIO pin is defined by *2* numbers, a port 501 * number between 0 and 31, and a bit index, 0 to 3. 502 */ 503 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD || 504 gpiospec->args[1] > priv->bitcount) 505 return -EINVAL; 506 507 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]); 508 509 if (pin > gc->ngpio) 510 return -EINVAL; 511 512 if (flags) 513 *flags = gpiospec->args[2]; 514 515 return pin; 516 } 517 518 static int microchip_sgpio_get_ports(struct sgpio_priv *priv) 519 { 520 const char *range_property_name = "microchip,sgpio-port-ranges"; 521 struct device *dev = priv->dev; 522 u32 range_params[64]; 523 int i, nranges, ret; 524 525 /* Calculate port mask */ 526 nranges = device_property_count_u32(dev, range_property_name); 527 if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) { 528 dev_err(dev, "%s port range: '%s' property\n", 529 nranges == -EINVAL ? "Missing" : "Invalid", 530 range_property_name); 531 return -EINVAL; 532 } 533 534 ret = device_property_read_u32_array(dev, range_property_name, 535 range_params, nranges); 536 if (ret) { 537 dev_err(dev, "failed to parse '%s' property: %d\n", 538 range_property_name, ret); 539 return ret; 540 } 541 for (i = 0; i < nranges; i += 2) { 542 int start, end; 543 544 start = range_params[i]; 545 end = range_params[i + 1]; 546 if (start > end || end >= SGPIO_BITS_PER_WORD) { 547 dev_err(dev, "Ill-formed port-range [%d:%d]\n", 548 start, end); 549 } 550 priv->ports |= GENMASK(end, start); 551 } 552 553 return 0; 554 } 555 556 static void microchip_sgpio_irq_settype(struct irq_data *data, 557 int type, 558 int polarity) 559 { 560 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 561 struct sgpio_bank *bank = gpiochip_get_data(chip); 562 unsigned int gpio = irqd_to_hwirq(data); 563 struct sgpio_port_addr addr; 564 u32 ena; 565 566 sgpio_pin_to_addr(bank->priv, gpio, &addr); 567 568 /* Disable interrupt while changing type */ 569 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit); 570 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit); 571 572 /* Type value spread over 2 registers sets: low, high bit */ 573 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit, 574 BIT(addr.port), (!!(type & 0x1)) << addr.port); 575 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit, 576 BIT(addr.port), (!!(type & 0x2)) << addr.port); 577 578 if (type == SGPIO_INT_TRG_LEVEL) 579 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit, 580 BIT(addr.port), polarity << addr.port); 581 582 /* Possibly re-enable interrupts */ 583 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit); 584 } 585 586 static void microchip_sgpio_irq_setreg(struct irq_data *data, 587 int reg, 588 bool clear) 589 { 590 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 591 struct sgpio_bank *bank = gpiochip_get_data(chip); 592 unsigned int gpio = irqd_to_hwirq(data); 593 struct sgpio_port_addr addr; 594 595 sgpio_pin_to_addr(bank->priv, gpio, &addr); 596 597 if (clear) 598 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0); 599 else 600 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port)); 601 } 602 603 static void microchip_sgpio_irq_mask(struct irq_data *data) 604 { 605 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true); 606 } 607 608 static void microchip_sgpio_irq_unmask(struct irq_data *data) 609 { 610 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false); 611 } 612 613 static void microchip_sgpio_irq_ack(struct irq_data *data) 614 { 615 microchip_sgpio_irq_setreg(data, REG_INT_ACK, false); 616 } 617 618 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type) 619 { 620 type &= IRQ_TYPE_SENSE_MASK; 621 622 switch (type) { 623 case IRQ_TYPE_EDGE_BOTH: 624 irq_set_handler_locked(data, handle_edge_irq); 625 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0); 626 break; 627 case IRQ_TYPE_EDGE_RISING: 628 irq_set_handler_locked(data, handle_edge_irq); 629 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0); 630 break; 631 case IRQ_TYPE_EDGE_FALLING: 632 irq_set_handler_locked(data, handle_edge_irq); 633 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0); 634 break; 635 case IRQ_TYPE_LEVEL_HIGH: 636 irq_set_handler_locked(data, handle_level_irq); 637 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH); 638 break; 639 case IRQ_TYPE_LEVEL_LOW: 640 irq_set_handler_locked(data, handle_level_irq); 641 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW); 642 break; 643 default: 644 return -EINVAL; 645 } 646 647 return 0; 648 } 649 650 static const struct irq_chip microchip_sgpio_irqchip = { 651 .name = "gpio", 652 .irq_mask = microchip_sgpio_irq_mask, 653 .irq_ack = microchip_sgpio_irq_ack, 654 .irq_unmask = microchip_sgpio_irq_unmask, 655 .irq_set_type = microchip_sgpio_irq_set_type, 656 }; 657 658 static void sgpio_irq_handler(struct irq_desc *desc) 659 { 660 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 661 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 662 struct sgpio_bank *bank = gpiochip_get_data(chip); 663 struct sgpio_priv *priv = bank->priv; 664 int bit, port, gpio; 665 long val; 666 667 for (bit = 0; bit < priv->bitcount; bit++) { 668 val = sgpio_readl(priv, REG_INT_IDENT, bit); 669 if (!val) 670 continue; 671 672 chained_irq_enter(parent_chip, desc); 673 674 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) { 675 gpio = sgpio_addr_to_pin(priv, port, bit); 676 generic_handle_domain_irq(chip->irq.domain, gpio); 677 } 678 679 chained_irq_exit(parent_chip, desc); 680 } 681 } 682 683 static int microchip_sgpio_register_bank(struct device *dev, 684 struct sgpio_priv *priv, 685 struct fwnode_handle *fwnode, 686 int bankno) 687 { 688 struct pinctrl_pin_desc *pins; 689 struct pinctrl_desc *pctl_desc; 690 struct pinctrl_dev *pctldev; 691 struct sgpio_bank *bank; 692 struct gpio_chip *gc; 693 u32 ngpios; 694 int i, ret; 695 696 /* Get overall bank struct */ 697 bank = (bankno == 0) ? &priv->in : &priv->out; 698 bank->priv = priv; 699 700 if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) { 701 dev_info(dev, "failed to get number of gpios for bank%d\n", 702 bankno); 703 ngpios = 64; 704 } 705 706 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD; 707 if (priv->bitcount > SGPIO_MAX_BITS) { 708 dev_err(dev, "Bit width exceeds maximum (%d)\n", 709 SGPIO_MAX_BITS); 710 return -EINVAL; 711 } 712 713 pctl_desc = &bank->pctl_desc; 714 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput", 715 dev_name(dev), 716 bank->is_input ? "in" : "out"); 717 pctl_desc->pctlops = &sgpio_pctl_ops; 718 pctl_desc->pmxops = &sgpio_pmx_ops; 719 pctl_desc->confops = &sgpio_confops; 720 pctl_desc->owner = THIS_MODULE; 721 722 pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL); 723 if (!pins) 724 return -ENOMEM; 725 726 pctl_desc->npins = ngpios; 727 pctl_desc->pins = pins; 728 729 for (i = 0; i < ngpios; i++) { 730 struct sgpio_port_addr addr; 731 732 sgpio_pin_to_addr(priv, i, &addr); 733 734 pins[i].number = i; 735 pins[i].name = devm_kasprintf(dev, GFP_KERNEL, 736 "SGPIO_%c_p%db%d", 737 bank->is_input ? 'I' : 'O', 738 addr.port, addr.bit); 739 if (!pins[i].name) 740 return -ENOMEM; 741 } 742 743 pctldev = devm_pinctrl_register(dev, pctl_desc, bank); 744 if (IS_ERR(pctldev)) 745 return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n"); 746 747 gc = &bank->gpio; 748 gc->label = pctl_desc->name; 749 gc->parent = dev; 750 gc->of_node = to_of_node(fwnode); 751 gc->owner = THIS_MODULE; 752 gc->get_direction = microchip_sgpio_get_direction; 753 gc->direction_input = microchip_sgpio_direction_input; 754 gc->direction_output = microchip_sgpio_direction_output; 755 gc->get = microchip_sgpio_get_value; 756 gc->set = microchip_sgpio_set_value; 757 gc->request = gpiochip_generic_request; 758 gc->free = gpiochip_generic_free; 759 gc->of_xlate = microchip_sgpio_of_xlate; 760 gc->of_gpio_n_cells = 3; 761 gc->base = -1; 762 gc->ngpio = ngpios; 763 764 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) { 765 int irq = fwnode_irq_get(fwnode, 0); 766 767 if (irq) { 768 struct gpio_irq_chip *girq = &gc->irq; 769 770 girq->chip = devm_kmemdup(dev, µchip_sgpio_irqchip, 771 sizeof(microchip_sgpio_irqchip), 772 GFP_KERNEL); 773 if (!girq->chip) 774 return -ENOMEM; 775 girq->parent_handler = sgpio_irq_handler; 776 girq->num_parents = 1; 777 girq->parents = devm_kcalloc(dev, 1, 778 sizeof(*girq->parents), 779 GFP_KERNEL); 780 if (!girq->parents) 781 return -ENOMEM; 782 girq->parents[0] = irq; 783 girq->default_type = IRQ_TYPE_NONE; 784 girq->handler = handle_bad_irq; 785 786 /* Disable all individual pins */ 787 for (i = 0; i < SGPIO_MAX_BITS; i++) 788 sgpio_writel(priv, 0, REG_INT_ENABLE, i); 789 /* Master enable */ 790 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA); 791 } 792 } 793 794 ret = devm_gpiochip_add_data(dev, gc, bank); 795 if (ret) 796 dev_err(dev, "Failed to register: ret %d\n", ret); 797 798 return ret; 799 } 800 801 static int microchip_sgpio_probe(struct platform_device *pdev) 802 { 803 int div_clock = 0, ret, port, i, nbanks; 804 struct device *dev = &pdev->dev; 805 struct fwnode_handle *fwnode; 806 struct sgpio_priv *priv; 807 struct clk *clk; 808 u32 val; 809 810 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 811 if (!priv) 812 return -ENOMEM; 813 814 priv->dev = dev; 815 816 clk = devm_clk_get(dev, NULL); 817 if (IS_ERR(clk)) 818 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n"); 819 820 div_clock = clk_get_rate(clk); 821 if (device_property_read_u32(dev, "bus-frequency", &priv->clock)) 822 priv->clock = 12500000; 823 if (priv->clock == 0 || priv->clock > (div_clock / 2)) { 824 dev_err(dev, "Invalid frequency %d\n", priv->clock); 825 return -EINVAL; 826 } 827 828 priv->regs = devm_platform_ioremap_resource(pdev, 0); 829 if (IS_ERR(priv->regs)) 830 return PTR_ERR(priv->regs); 831 priv->properties = device_get_match_data(dev); 832 priv->in.is_input = true; 833 834 /* Get rest of device properties */ 835 ret = microchip_sgpio_get_ports(priv); 836 if (ret) 837 return ret; 838 839 nbanks = device_get_child_node_count(dev); 840 if (nbanks != 2) { 841 dev_err(dev, "Must have 2 banks (have %d)\n", nbanks); 842 return -EINVAL; 843 } 844 845 i = 0; 846 device_for_each_child_node(dev, fwnode) { 847 ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++); 848 if (ret) { 849 fwnode_handle_put(fwnode); 850 return ret; 851 } 852 } 853 854 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) { 855 dev_err(dev, "Banks must have same GPIO count\n"); 856 return -ERANGE; 857 } 858 859 sgpio_configure_bitstream(priv); 860 861 val = max(2U, div_clock / priv->clock); 862 sgpio_configure_clock(priv, val); 863 864 for (port = 0; port < SGPIO_BITS_PER_WORD; port++) 865 sgpio_writel(priv, 0, REG_PORT_CONFIG, port); 866 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0); 867 868 return 0; 869 } 870 871 static const struct of_device_id microchip_sgpio_gpio_of_match[] = { 872 { 873 .compatible = "microchip,sparx5-sgpio", 874 .data = &properties_sparx5, 875 }, { 876 .compatible = "mscc,luton-sgpio", 877 .data = &properties_luton, 878 }, { 879 .compatible = "mscc,ocelot-sgpio", 880 .data = &properties_ocelot, 881 }, { 882 /* sentinel */ 883 } 884 }; 885 886 static struct platform_driver microchip_sgpio_pinctrl_driver = { 887 .driver = { 888 .name = "pinctrl-microchip-sgpio", 889 .of_match_table = microchip_sgpio_gpio_of_match, 890 .suppress_bind_attrs = true, 891 }, 892 .probe = microchip_sgpio_probe, 893 }; 894 builtin_platform_driver(microchip_sgpio_pinctrl_driver); 895