1 // SPDX-License-Identifier: GPL-2.0-only 2 /* MCP23S08 SPI/I2C GPIO driver */ 3 4 #include <linux/bitops.h> 5 #include <linux/kernel.h> 6 #include <linux/device.h> 7 #include <linux/mutex.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/export.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/slab.h> 14 #include <asm/byteorder.h> 15 #include <linux/interrupt.h> 16 #include <linux/regmap.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 21 #include "pinctrl-mcp23s08.h" 22 23 /* Registers are all 8 bits wide. 24 * 25 * The mcp23s17 has twice as many bits, and can be configured to work 26 * with either 16 bit registers or with two adjacent 8 bit banks. 27 */ 28 #define MCP_IODIR 0x00 /* init/reset: all ones */ 29 #define MCP_IPOL 0x01 30 #define MCP_GPINTEN 0x02 31 #define MCP_DEFVAL 0x03 32 #define MCP_INTCON 0x04 33 #define MCP_IOCON 0x05 34 # define IOCON_MIRROR (1 << 6) 35 # define IOCON_SEQOP (1 << 5) 36 # define IOCON_HAEN (1 << 3) 37 # define IOCON_ODR (1 << 2) 38 # define IOCON_INTPOL (1 << 1) 39 # define IOCON_INTCC (1) 40 #define MCP_GPPU 0x06 41 #define MCP_INTF 0x07 42 #define MCP_INTCAP 0x08 43 #define MCP_GPIO 0x09 44 #define MCP_OLAT 0x0a 45 46 static const struct reg_default mcp23x08_defaults[] = { 47 {.reg = MCP_IODIR, .def = 0xff}, 48 {.reg = MCP_IPOL, .def = 0x00}, 49 {.reg = MCP_GPINTEN, .def = 0x00}, 50 {.reg = MCP_DEFVAL, .def = 0x00}, 51 {.reg = MCP_INTCON, .def = 0x00}, 52 {.reg = MCP_IOCON, .def = 0x00}, 53 {.reg = MCP_GPPU, .def = 0x00}, 54 {.reg = MCP_OLAT, .def = 0x00}, 55 }; 56 57 static const struct regmap_range mcp23x08_volatile_range = { 58 .range_min = MCP_INTF, 59 .range_max = MCP_GPIO, 60 }; 61 62 static const struct regmap_access_table mcp23x08_volatile_table = { 63 .yes_ranges = &mcp23x08_volatile_range, 64 .n_yes_ranges = 1, 65 }; 66 67 static const struct regmap_range mcp23x08_precious_range = { 68 .range_min = MCP_GPIO, 69 .range_max = MCP_GPIO, 70 }; 71 72 static const struct regmap_access_table mcp23x08_precious_table = { 73 .yes_ranges = &mcp23x08_precious_range, 74 .n_yes_ranges = 1, 75 }; 76 77 const struct regmap_config mcp23x08_regmap = { 78 .reg_bits = 8, 79 .val_bits = 8, 80 81 .reg_stride = 1, 82 .volatile_table = &mcp23x08_volatile_table, 83 .precious_table = &mcp23x08_precious_table, 84 .reg_defaults = mcp23x08_defaults, 85 .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults), 86 .cache_type = REGCACHE_FLAT, 87 .max_register = MCP_OLAT, 88 }; 89 EXPORT_SYMBOL_GPL(mcp23x08_regmap); 90 91 static const struct reg_default mcp23x17_defaults[] = { 92 {.reg = MCP_IODIR << 1, .def = 0xffff}, 93 {.reg = MCP_IPOL << 1, .def = 0x0000}, 94 {.reg = MCP_GPINTEN << 1, .def = 0x0000}, 95 {.reg = MCP_DEFVAL << 1, .def = 0x0000}, 96 {.reg = MCP_INTCON << 1, .def = 0x0000}, 97 {.reg = MCP_IOCON << 1, .def = 0x0000}, 98 {.reg = MCP_GPPU << 1, .def = 0x0000}, 99 {.reg = MCP_OLAT << 1, .def = 0x0000}, 100 }; 101 102 static const struct regmap_range mcp23x17_volatile_range = { 103 .range_min = MCP_INTF << 1, 104 .range_max = MCP_GPIO << 1, 105 }; 106 107 static const struct regmap_access_table mcp23x17_volatile_table = { 108 .yes_ranges = &mcp23x17_volatile_range, 109 .n_yes_ranges = 1, 110 }; 111 112 static const struct regmap_range mcp23x17_precious_range = { 113 .range_min = MCP_INTCAP << 1, 114 .range_max = MCP_GPIO << 1, 115 }; 116 117 static const struct regmap_access_table mcp23x17_precious_table = { 118 .yes_ranges = &mcp23x17_precious_range, 119 .n_yes_ranges = 1, 120 }; 121 122 const struct regmap_config mcp23x17_regmap = { 123 .reg_bits = 8, 124 .val_bits = 16, 125 126 .reg_stride = 2, 127 .max_register = MCP_OLAT << 1, 128 .volatile_table = &mcp23x17_volatile_table, 129 .precious_table = &mcp23x17_precious_table, 130 .reg_defaults = mcp23x17_defaults, 131 .num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults), 132 .cache_type = REGCACHE_FLAT, 133 .val_format_endian = REGMAP_ENDIAN_LITTLE, 134 }; 135 EXPORT_SYMBOL_GPL(mcp23x17_regmap); 136 137 static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) 138 { 139 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); 140 } 141 142 static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) 143 { 144 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); 145 } 146 147 static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg, 148 unsigned int mask, bool enabled) 149 { 150 u16 val = enabled ? 0xffff : 0x0000; 151 return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, 152 mask, val); 153 } 154 155 static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg, 156 unsigned int pin, bool enabled) 157 { 158 u16 mask = BIT(pin); 159 return mcp_set_mask(mcp, reg, mask, enabled); 160 } 161 162 static const struct pinctrl_pin_desc mcp23x08_pins[] = { 163 PINCTRL_PIN(0, "gpio0"), 164 PINCTRL_PIN(1, "gpio1"), 165 PINCTRL_PIN(2, "gpio2"), 166 PINCTRL_PIN(3, "gpio3"), 167 PINCTRL_PIN(4, "gpio4"), 168 PINCTRL_PIN(5, "gpio5"), 169 PINCTRL_PIN(6, "gpio6"), 170 PINCTRL_PIN(7, "gpio7"), 171 }; 172 173 static const struct pinctrl_pin_desc mcp23x17_pins[] = { 174 PINCTRL_PIN(0, "gpio0"), 175 PINCTRL_PIN(1, "gpio1"), 176 PINCTRL_PIN(2, "gpio2"), 177 PINCTRL_PIN(3, "gpio3"), 178 PINCTRL_PIN(4, "gpio4"), 179 PINCTRL_PIN(5, "gpio5"), 180 PINCTRL_PIN(6, "gpio6"), 181 PINCTRL_PIN(7, "gpio7"), 182 PINCTRL_PIN(8, "gpio8"), 183 PINCTRL_PIN(9, "gpio9"), 184 PINCTRL_PIN(10, "gpio10"), 185 PINCTRL_PIN(11, "gpio11"), 186 PINCTRL_PIN(12, "gpio12"), 187 PINCTRL_PIN(13, "gpio13"), 188 PINCTRL_PIN(14, "gpio14"), 189 PINCTRL_PIN(15, "gpio15"), 190 }; 191 192 static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 193 { 194 return 0; 195 } 196 197 static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 198 unsigned int group) 199 { 200 return NULL; 201 } 202 203 static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 204 unsigned int group, 205 const unsigned int **pins, 206 unsigned int *num_pins) 207 { 208 return -ENOTSUPP; 209 } 210 211 static const struct pinctrl_ops mcp_pinctrl_ops = { 212 .get_groups_count = mcp_pinctrl_get_groups_count, 213 .get_group_name = mcp_pinctrl_get_group_name, 214 .get_group_pins = mcp_pinctrl_get_group_pins, 215 #ifdef CONFIG_OF 216 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 217 .dt_free_map = pinconf_generic_dt_free_map, 218 #endif 219 }; 220 221 static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 222 unsigned long *config) 223 { 224 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); 225 enum pin_config_param param = pinconf_to_config_param(*config); 226 unsigned int data, status; 227 int ret; 228 229 switch (param) { 230 case PIN_CONFIG_BIAS_PULL_UP: 231 ret = mcp_read(mcp, MCP_GPPU, &data); 232 if (ret < 0) 233 return ret; 234 status = (data & BIT(pin)) ? 1 : 0; 235 break; 236 default: 237 return -ENOTSUPP; 238 } 239 240 *config = 0; 241 242 return status ? 0 : -EINVAL; 243 } 244 245 static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 246 unsigned long *configs, unsigned int num_configs) 247 { 248 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); 249 enum pin_config_param param; 250 u32 arg; 251 int ret = 0; 252 int i; 253 254 for (i = 0; i < num_configs; i++) { 255 param = pinconf_to_config_param(configs[i]); 256 arg = pinconf_to_config_argument(configs[i]); 257 258 switch (param) { 259 case PIN_CONFIG_BIAS_PULL_UP: 260 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); 261 break; 262 default: 263 dev_dbg(mcp->dev, "Invalid config param %04x\n", param); 264 return -ENOTSUPP; 265 } 266 } 267 268 return ret; 269 } 270 271 static const struct pinconf_ops mcp_pinconf_ops = { 272 .pin_config_get = mcp_pinconf_get, 273 .pin_config_set = mcp_pinconf_set, 274 .is_generic = true, 275 }; 276 277 /*----------------------------------------------------------------------*/ 278 279 static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) 280 { 281 struct mcp23s08 *mcp = gpiochip_get_data(chip); 282 int status; 283 284 mutex_lock(&mcp->lock); 285 status = mcp_set_bit(mcp, MCP_IODIR, offset, true); 286 mutex_unlock(&mcp->lock); 287 288 return status; 289 } 290 291 static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) 292 { 293 struct mcp23s08 *mcp = gpiochip_get_data(chip); 294 int status, ret; 295 296 mutex_lock(&mcp->lock); 297 298 /* REVISIT reading this clears any IRQ ... */ 299 ret = mcp_read(mcp, MCP_GPIO, &status); 300 if (ret < 0) 301 status = 0; 302 else { 303 mcp->cached_gpio = status; 304 status = !!(status & (1 << offset)); 305 } 306 307 mutex_unlock(&mcp->lock); 308 return status; 309 } 310 311 static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value) 312 { 313 return mcp_set_mask(mcp, MCP_OLAT, mask, value); 314 } 315 316 static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) 317 { 318 struct mcp23s08 *mcp = gpiochip_get_data(chip); 319 unsigned mask = BIT(offset); 320 321 mutex_lock(&mcp->lock); 322 __mcp23s08_set(mcp, mask, !!value); 323 mutex_unlock(&mcp->lock); 324 } 325 326 static int 327 mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) 328 { 329 struct mcp23s08 *mcp = gpiochip_get_data(chip); 330 unsigned mask = BIT(offset); 331 int status; 332 333 mutex_lock(&mcp->lock); 334 status = __mcp23s08_set(mcp, mask, value); 335 if (status == 0) { 336 status = mcp_set_mask(mcp, MCP_IODIR, mask, false); 337 } 338 mutex_unlock(&mcp->lock); 339 return status; 340 } 341 342 /*----------------------------------------------------------------------*/ 343 static irqreturn_t mcp23s08_irq(int irq, void *data) 344 { 345 struct mcp23s08 *mcp = data; 346 int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval; 347 unsigned int child_irq; 348 bool intf_set, intcap_changed, gpio_bit_changed, 349 defval_changed, gpio_set; 350 351 mutex_lock(&mcp->lock); 352 if (mcp_read(mcp, MCP_INTF, &intf)) 353 goto unlock; 354 355 if (intf == 0) { 356 /* There is no interrupt pending */ 357 goto unlock; 358 } 359 360 if (mcp_read(mcp, MCP_INTCAP, &intcap)) 361 goto unlock; 362 363 if (mcp_read(mcp, MCP_INTCON, &intcon)) 364 goto unlock; 365 366 if (mcp_read(mcp, MCP_DEFVAL, &defval)) 367 goto unlock; 368 369 /* This clears the interrupt(configurable on S18) */ 370 if (mcp_read(mcp, MCP_GPIO, &gpio)) 371 goto unlock; 372 373 gpio_orig = mcp->cached_gpio; 374 mcp->cached_gpio = gpio; 375 mutex_unlock(&mcp->lock); 376 377 dev_dbg(mcp->chip.parent, 378 "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n", 379 intcap, intf, gpio_orig, gpio); 380 381 for (i = 0; i < mcp->chip.ngpio; i++) { 382 /* We must check all of the inputs on the chip, 383 * otherwise we may not notice a change on >=2 pins. 384 * 385 * On at least the mcp23s17, INTCAP is only updated 386 * one byte at a time(INTCAPA and INTCAPB are 387 * not written to at the same time - only on a per-bank 388 * basis). 389 * 390 * INTF only contains the single bit that caused the 391 * interrupt per-bank. On the mcp23s17, there is 392 * INTFA and INTFB. If two pins are changed on the A 393 * side at the same time, INTF will only have one bit 394 * set. If one pin on the A side and one pin on the B 395 * side are changed at the same time, INTF will have 396 * two bits set. Thus, INTF can't be the only check 397 * to see if the input has changed. 398 */ 399 400 intf_set = intf & BIT(i); 401 if (i < 8 && intf_set) 402 intcap_mask = 0x00FF; 403 else if (i >= 8 && intf_set) 404 intcap_mask = 0xFF00; 405 else 406 intcap_mask = 0x00; 407 408 intcap_changed = (intcap_mask & 409 (intcap & BIT(i))) != 410 (intcap_mask & (BIT(i) & gpio_orig)); 411 gpio_set = BIT(i) & gpio; 412 gpio_bit_changed = (BIT(i) & gpio_orig) != 413 (BIT(i) & gpio); 414 defval_changed = (BIT(i) & intcon) && 415 ((BIT(i) & gpio) != 416 (BIT(i) & defval)); 417 418 if (((gpio_bit_changed || intcap_changed) && 419 (BIT(i) & mcp->irq_rise) && gpio_set) || 420 ((gpio_bit_changed || intcap_changed) && 421 (BIT(i) & mcp->irq_fall) && !gpio_set) || 422 defval_changed) { 423 child_irq = irq_find_mapping(mcp->chip.irq.domain, i); 424 handle_nested_irq(child_irq); 425 } 426 } 427 428 return IRQ_HANDLED; 429 430 unlock: 431 mutex_unlock(&mcp->lock); 432 return IRQ_HANDLED; 433 } 434 435 static void mcp23s08_irq_mask(struct irq_data *data) 436 { 437 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 438 struct mcp23s08 *mcp = gpiochip_get_data(gc); 439 unsigned int pos = data->hwirq; 440 441 mcp_set_bit(mcp, MCP_GPINTEN, pos, false); 442 } 443 444 static void mcp23s08_irq_unmask(struct irq_data *data) 445 { 446 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 447 struct mcp23s08 *mcp = gpiochip_get_data(gc); 448 unsigned int pos = data->hwirq; 449 450 mcp_set_bit(mcp, MCP_GPINTEN, pos, true); 451 } 452 453 static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) 454 { 455 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 456 struct mcp23s08 *mcp = gpiochip_get_data(gc); 457 unsigned int pos = data->hwirq; 458 459 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 460 mcp_set_bit(mcp, MCP_INTCON, pos, false); 461 mcp->irq_rise |= BIT(pos); 462 mcp->irq_fall |= BIT(pos); 463 } else if (type & IRQ_TYPE_EDGE_RISING) { 464 mcp_set_bit(mcp, MCP_INTCON, pos, false); 465 mcp->irq_rise |= BIT(pos); 466 mcp->irq_fall &= ~BIT(pos); 467 } else if (type & IRQ_TYPE_EDGE_FALLING) { 468 mcp_set_bit(mcp, MCP_INTCON, pos, false); 469 mcp->irq_rise &= ~BIT(pos); 470 mcp->irq_fall |= BIT(pos); 471 } else if (type & IRQ_TYPE_LEVEL_HIGH) { 472 mcp_set_bit(mcp, MCP_INTCON, pos, true); 473 mcp_set_bit(mcp, MCP_DEFVAL, pos, false); 474 } else if (type & IRQ_TYPE_LEVEL_LOW) { 475 mcp_set_bit(mcp, MCP_INTCON, pos, true); 476 mcp_set_bit(mcp, MCP_DEFVAL, pos, true); 477 } else 478 return -EINVAL; 479 480 return 0; 481 } 482 483 static void mcp23s08_irq_bus_lock(struct irq_data *data) 484 { 485 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 486 struct mcp23s08 *mcp = gpiochip_get_data(gc); 487 488 mutex_lock(&mcp->lock); 489 regcache_cache_only(mcp->regmap, true); 490 } 491 492 static void mcp23s08_irq_bus_unlock(struct irq_data *data) 493 { 494 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 495 struct mcp23s08 *mcp = gpiochip_get_data(gc); 496 497 regcache_cache_only(mcp->regmap, false); 498 regcache_sync(mcp->regmap); 499 500 mutex_unlock(&mcp->lock); 501 } 502 503 static int mcp23s08_irq_setup(struct mcp23s08 *mcp) 504 { 505 struct gpio_chip *chip = &mcp->chip; 506 int err; 507 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; 508 509 if (mcp->irq_active_high) 510 irqflags |= IRQF_TRIGGER_HIGH; 511 else 512 irqflags |= IRQF_TRIGGER_LOW; 513 514 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, 515 mcp23s08_irq, 516 irqflags, dev_name(chip->parent), mcp); 517 if (err != 0) { 518 dev_err(chip->parent, "unable to request IRQ#%d: %d\n", 519 mcp->irq, err); 520 return err; 521 } 522 523 return 0; 524 } 525 526 /*----------------------------------------------------------------------*/ 527 528 int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, 529 unsigned int addr, unsigned int type, unsigned int base) 530 { 531 int status, ret; 532 bool mirror = false; 533 bool open_drain = false; 534 535 mutex_init(&mcp->lock); 536 537 mcp->dev = dev; 538 mcp->addr = addr; 539 540 mcp->irq_active_high = false; 541 mcp->irq_chip.name = dev_name(dev); 542 mcp->irq_chip.irq_mask = mcp23s08_irq_mask; 543 mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask; 544 mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type; 545 mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; 546 mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock; 547 548 mcp->chip.direction_input = mcp23s08_direction_input; 549 mcp->chip.get = mcp23s08_get; 550 mcp->chip.direction_output = mcp23s08_direction_output; 551 mcp->chip.set = mcp23s08_set; 552 #ifdef CONFIG_OF_GPIO 553 mcp->chip.of_gpio_n_cells = 2; 554 #endif 555 556 mcp->chip.base = base; 557 mcp->chip.can_sleep = true; 558 mcp->chip.parent = dev; 559 mcp->chip.owner = THIS_MODULE; 560 561 mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 562 563 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, 564 * and MCP_IOCON.HAEN = 1, so we work with all chips. 565 */ 566 567 ret = mcp_read(mcp, MCP_IOCON, &status); 568 if (ret < 0) 569 return dev_err_probe(dev, ret, "can't identify chip %d\n", addr); 570 571 mcp->irq_controller = 572 device_property_read_bool(dev, "interrupt-controller"); 573 if (mcp->irq && mcp->irq_controller) { 574 mcp->irq_active_high = 575 device_property_read_bool(dev, 576 "microchip,irq-active-high"); 577 578 mirror = device_property_read_bool(dev, "microchip,irq-mirror"); 579 open_drain = device_property_read_bool(dev, "drive-open-drain"); 580 } 581 582 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || 583 mcp->irq_active_high || open_drain) { 584 /* mcp23s17 has IOCON twice, make sure they are in sync */ 585 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); 586 status |= IOCON_HAEN | (IOCON_HAEN << 8); 587 if (mcp->irq_active_high) 588 status |= IOCON_INTPOL | (IOCON_INTPOL << 8); 589 else 590 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); 591 592 if (mirror) 593 status |= IOCON_MIRROR | (IOCON_MIRROR << 8); 594 595 if (open_drain) 596 status |= IOCON_ODR | (IOCON_ODR << 8); 597 598 if (type == MCP_TYPE_S18 || type == MCP_TYPE_018) 599 status |= IOCON_INTCC | (IOCON_INTCC << 8); 600 601 ret = mcp_write(mcp, MCP_IOCON, status); 602 if (ret < 0) 603 return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr); 604 } 605 606 if (mcp->irq && mcp->irq_controller) { 607 struct gpio_irq_chip *girq = &mcp->chip.irq; 608 609 girq->chip = &mcp->irq_chip; 610 /* This will let us handle the parent IRQ in the driver */ 611 girq->parent_handler = NULL; 612 girq->num_parents = 0; 613 girq->parents = NULL; 614 girq->default_type = IRQ_TYPE_NONE; 615 girq->handler = handle_simple_irq; 616 girq->threaded = true; 617 } 618 619 ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp); 620 if (ret < 0) 621 return dev_err_probe(dev, ret, "can't add GPIO chip\n"); 622 623 mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; 624 mcp->pinctrl_desc.confops = &mcp_pinconf_ops; 625 mcp->pinctrl_desc.npins = mcp->chip.ngpio; 626 if (mcp->pinctrl_desc.npins == 8) 627 mcp->pinctrl_desc.pins = mcp23x08_pins; 628 else if (mcp->pinctrl_desc.npins == 16) 629 mcp->pinctrl_desc.pins = mcp23x17_pins; 630 mcp->pinctrl_desc.owner = THIS_MODULE; 631 632 mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp); 633 if (IS_ERR(mcp->pctldev)) 634 return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n"); 635 636 if (mcp->irq) { 637 ret = mcp23s08_irq_setup(mcp); 638 if (ret) 639 return dev_err_probe(dev, ret, "can't setup IRQ\n"); 640 } 641 642 return 0; 643 } 644 EXPORT_SYMBOL_GPL(mcp23s08_probe_one); 645 646 MODULE_LICENSE("GPL"); 647