1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ingenic SoCs pinctrl driver 4 * 5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> 6 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk> 7 * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 8 */ 9 10 #include <linux/compiler.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/property.h> 19 #include <linux/regmap.h> 20 #include <linux/seq_file.h> 21 #include <linux/slab.h> 22 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinmux.h> 28 29 #include "core.h" 30 #include "pinconf.h" 31 #include "pinmux.h" 32 33 #define GPIO_PIN 0x00 34 #define GPIO_MSK 0x20 35 36 #define JZ4730_GPIO_DATA 0x00 37 #define JZ4730_GPIO_GPDIR 0x04 38 #define JZ4730_GPIO_GPPUR 0x0c 39 #define JZ4730_GPIO_GPALR 0x10 40 #define JZ4730_GPIO_GPAUR 0x14 41 #define JZ4730_GPIO_GPIDLR 0x18 42 #define JZ4730_GPIO_GPIDUR 0x1c 43 #define JZ4730_GPIO_GPIER 0x20 44 #define JZ4730_GPIO_GPIMR 0x24 45 #define JZ4730_GPIO_GPFR 0x28 46 47 #define JZ4740_GPIO_DATA 0x10 48 #define JZ4740_GPIO_PULL_DIS 0x30 49 #define JZ4740_GPIO_FUNC 0x40 50 #define JZ4740_GPIO_SELECT 0x50 51 #define JZ4740_GPIO_DIR 0x60 52 #define JZ4740_GPIO_TRIG 0x70 53 #define JZ4740_GPIO_FLAG 0x80 54 55 #define JZ4770_GPIO_INT 0x10 56 #define JZ4770_GPIO_PAT1 0x30 57 #define JZ4770_GPIO_PAT0 0x40 58 #define JZ4770_GPIO_FLAG 0x50 59 #define JZ4770_GPIO_PEN 0x70 60 61 #define X1830_GPIO_PEL 0x110 62 #define X1830_GPIO_PEH 0x120 63 #define X1830_GPIO_SR 0x150 64 #define X1830_GPIO_SMT 0x160 65 66 #define X2000_GPIO_EDG 0x70 67 #define X2000_GPIO_PEPU 0x80 68 #define X2000_GPIO_PEPD 0x90 69 #define X2000_GPIO_SR 0xd0 70 #define X2000_GPIO_SMT 0xe0 71 72 #define REG_SET(x) ((x) + 0x4) 73 #define REG_CLEAR(x) ((x) + 0x8) 74 75 #define REG_PZ_BASE(x) ((x) * 7) 76 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) 77 78 #define GPIO_PULL_DIS 0 79 #define GPIO_PULL_UP 1 80 #define GPIO_PULL_DOWN 2 81 82 #define PINS_PER_GPIO_CHIP 32 83 #define JZ4730_PINS_PER_PAIRED_REG 16 84 85 #define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \ 86 { \ 87 name, \ 88 id##_pins, \ 89 ARRAY_SIZE(id##_pins), \ 90 funcs, \ 91 } 92 93 #define INGENIC_PIN_GROUP(name, id, func) \ 94 INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func)) 95 96 enum jz_version { 97 ID_JZ4730, 98 ID_JZ4740, 99 ID_JZ4725B, 100 ID_JZ4750, 101 ID_JZ4755, 102 ID_JZ4760, 103 ID_JZ4770, 104 ID_JZ4775, 105 ID_JZ4780, 106 ID_X1000, 107 ID_X1500, 108 ID_X1830, 109 ID_X2000, 110 ID_X2100, 111 }; 112 113 struct ingenic_chip_info { 114 unsigned int num_chips; 115 unsigned int reg_offset; 116 enum jz_version version; 117 118 const struct group_desc *groups; 119 unsigned int num_groups; 120 121 const struct function_desc *functions; 122 unsigned int num_functions; 123 124 const u32 *pull_ups, *pull_downs; 125 126 const struct regmap_access_table *access_table; 127 }; 128 129 struct ingenic_pinctrl { 130 struct device *dev; 131 struct regmap *map; 132 struct pinctrl_dev *pctl; 133 struct pinctrl_pin_desc *pdesc; 134 135 const struct ingenic_chip_info *info; 136 137 struct gpio_chip *gc; 138 }; 139 140 struct ingenic_gpio_chip { 141 struct ingenic_pinctrl *jzpc; 142 struct gpio_chip gc; 143 unsigned int irq, reg_base; 144 }; 145 146 static const unsigned long enabled_socs = 147 IS_ENABLED(CONFIG_MACH_JZ4730) << ID_JZ4730 | 148 IS_ENABLED(CONFIG_MACH_JZ4740) << ID_JZ4740 | 149 IS_ENABLED(CONFIG_MACH_JZ4725B) << ID_JZ4725B | 150 IS_ENABLED(CONFIG_MACH_JZ4750) << ID_JZ4750 | 151 IS_ENABLED(CONFIG_MACH_JZ4755) << ID_JZ4755 | 152 IS_ENABLED(CONFIG_MACH_JZ4760) << ID_JZ4760 | 153 IS_ENABLED(CONFIG_MACH_JZ4770) << ID_JZ4770 | 154 IS_ENABLED(CONFIG_MACH_JZ4775) << ID_JZ4775 | 155 IS_ENABLED(CONFIG_MACH_JZ4780) << ID_JZ4780 | 156 IS_ENABLED(CONFIG_MACH_X1000) << ID_X1000 | 157 IS_ENABLED(CONFIG_MACH_X1500) << ID_X1500 | 158 IS_ENABLED(CONFIG_MACH_X1830) << ID_X1830 | 159 IS_ENABLED(CONFIG_MACH_X2000) << ID_X2000 | 160 IS_ENABLED(CONFIG_MACH_X2100) << ID_X2100; 161 162 static bool 163 is_soc_or_above(const struct ingenic_pinctrl *jzpc, enum jz_version version) 164 { 165 return (enabled_socs >> version) && 166 (!(enabled_socs & GENMASK(version - 1, 0)) 167 || jzpc->info->version >= version); 168 } 169 170 static const u32 jz4730_pull_ups[4] = { 171 0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff, 172 }; 173 174 static const u32 jz4730_pull_downs[4] = { 175 0x00000df0, 0x0dff0000, 0x00000000, 0x00000000, 176 }; 177 178 static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, }; 179 static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, }; 180 static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, }; 181 static int jz4730_uart1_data_pins[] = { 0x18, 0x19, }; 182 static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, }; 183 static int jz4730_uart3_data_pins[] = { 0x10, 0x15, }; 184 static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, }; 185 static int jz4730_lcd_8bit_pins[] = { 186 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 187 0x3a, 0x39, 0x38, 188 }; 189 static int jz4730_lcd_16bit_pins[] = { 190 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 191 }; 192 static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, }; 193 static int jz4730_lcd_generic_pins[] = { 0x3b, }; 194 static int jz4730_nand_cs1_pins[] = { 0x53, }; 195 static int jz4730_nand_cs2_pins[] = { 0x54, }; 196 static int jz4730_nand_cs3_pins[] = { 0x55, }; 197 static int jz4730_nand_cs4_pins[] = { 0x56, }; 198 static int jz4730_nand_cs5_pins[] = { 0x57, }; 199 static int jz4730_pwm_pwm0_pins[] = { 0x5e, }; 200 static int jz4730_pwm_pwm1_pins[] = { 0x5f, }; 201 202 static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, }; 203 204 static const struct group_desc jz4730_groups[] = { 205 INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1), 206 INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1), 207 INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1), 208 INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1), 209 INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1), 210 INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1), 211 INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1), 212 INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs), 213 INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1), 214 INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1), 215 INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1), 216 INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1), 217 INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1), 218 INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1), 219 INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1), 220 INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1), 221 INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1), 222 INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1), 223 }; 224 225 static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 226 static const char *jz4730_uart0_groups[] = { "uart0-data", }; 227 static const char *jz4730_uart1_groups[] = { "uart1-data", }; 228 static const char *jz4730_uart2_groups[] = { "uart2-data", }; 229 static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 230 static const char *jz4730_lcd_groups[] = { 231 "lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic", 232 }; 233 static const char *jz4730_nand_groups[] = { 234 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5", 235 }; 236 static const char *jz4730_pwm0_groups[] = { "pwm0", }; 237 static const char *jz4730_pwm1_groups[] = { "pwm1", }; 238 239 static const struct function_desc jz4730_functions[] = { 240 { "mmc", jz4730_mmc_groups, ARRAY_SIZE(jz4730_mmc_groups), }, 241 { "uart0", jz4730_uart0_groups, ARRAY_SIZE(jz4730_uart0_groups), }, 242 { "uart1", jz4730_uart1_groups, ARRAY_SIZE(jz4730_uart1_groups), }, 243 { "uart2", jz4730_uart2_groups, ARRAY_SIZE(jz4730_uart2_groups), }, 244 { "uart3", jz4730_uart3_groups, ARRAY_SIZE(jz4730_uart3_groups), }, 245 { "lcd", jz4730_lcd_groups, ARRAY_SIZE(jz4730_lcd_groups), }, 246 { "nand", jz4730_nand_groups, ARRAY_SIZE(jz4730_nand_groups), }, 247 { "pwm0", jz4730_pwm0_groups, ARRAY_SIZE(jz4730_pwm0_groups), }, 248 { "pwm1", jz4730_pwm1_groups, ARRAY_SIZE(jz4730_pwm1_groups), }, 249 }; 250 251 static const struct ingenic_chip_info jz4730_chip_info = { 252 .num_chips = 4, 253 .reg_offset = 0x30, 254 .version = ID_JZ4730, 255 .groups = jz4730_groups, 256 .num_groups = ARRAY_SIZE(jz4730_groups), 257 .functions = jz4730_functions, 258 .num_functions = ARRAY_SIZE(jz4730_functions), 259 .pull_ups = jz4730_pull_ups, 260 .pull_downs = jz4730_pull_downs, 261 }; 262 263 static const u32 jz4740_pull_ups[4] = { 264 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 265 }; 266 267 static const u32 jz4740_pull_downs[4] = { 268 0x00000000, 0x00000000, 0x00000000, 0x00000000, 269 }; 270 271 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, }; 272 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 273 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; 274 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 275 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; 276 static int jz4740_lcd_8bit_pins[] = { 277 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 278 0x52, 0x53, 0x54, 279 }; 280 static int jz4740_lcd_16bit_pins[] = { 281 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 282 }; 283 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; 284 static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, }; 285 static int jz4740_lcd_generic_pins[] = { 0x55, }; 286 static int jz4740_nand_cs1_pins[] = { 0x39, }; 287 static int jz4740_nand_cs2_pins[] = { 0x3a, }; 288 static int jz4740_nand_cs3_pins[] = { 0x3b, }; 289 static int jz4740_nand_cs4_pins[] = { 0x3c, }; 290 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 291 static int jz4740_pwm_pwm0_pins[] = { 0x77, }; 292 static int jz4740_pwm_pwm1_pins[] = { 0x78, }; 293 static int jz4740_pwm_pwm2_pins[] = { 0x79, }; 294 static int jz4740_pwm_pwm3_pins[] = { 0x7a, }; 295 static int jz4740_pwm_pwm4_pins[] = { 0x7b, }; 296 static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; 297 static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; 298 static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; 299 300 static const struct group_desc jz4740_groups[] = { 301 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0), 302 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0), 303 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1), 304 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1), 305 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2), 306 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0), 307 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0), 308 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0), 309 INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0), 310 INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0), 311 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0), 312 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0), 313 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0), 314 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0), 315 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0), 316 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0), 317 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0), 318 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0), 319 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0), 320 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0), 321 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0), 322 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0), 323 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0), 324 }; 325 326 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 327 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 328 static const char *jz4740_uart1_groups[] = { "uart1-data", }; 329 static const char *jz4740_lcd_groups[] = { 330 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic", 331 }; 332 static const char *jz4740_nand_groups[] = { 333 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 334 }; 335 static const char *jz4740_pwm0_groups[] = { "pwm0", }; 336 static const char *jz4740_pwm1_groups[] = { "pwm1", }; 337 static const char *jz4740_pwm2_groups[] = { "pwm2", }; 338 static const char *jz4740_pwm3_groups[] = { "pwm3", }; 339 static const char *jz4740_pwm4_groups[] = { "pwm4", }; 340 static const char *jz4740_pwm5_groups[] = { "pwm5", }; 341 static const char *jz4740_pwm6_groups[] = { "pwm6", }; 342 static const char *jz4740_pwm7_groups[] = { "pwm7", }; 343 344 static const struct function_desc jz4740_functions[] = { 345 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), }, 346 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), }, 347 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), }, 348 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), }, 349 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), }, 350 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), }, 351 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), }, 352 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), }, 353 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), }, 354 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), }, 355 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), }, 356 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), }, 357 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), }, 358 }; 359 360 static const struct ingenic_chip_info jz4740_chip_info = { 361 .num_chips = 4, 362 .reg_offset = 0x100, 363 .version = ID_JZ4740, 364 .groups = jz4740_groups, 365 .num_groups = ARRAY_SIZE(jz4740_groups), 366 .functions = jz4740_functions, 367 .num_functions = ARRAY_SIZE(jz4740_functions), 368 .pull_ups = jz4740_pull_ups, 369 .pull_downs = jz4740_pull_downs, 370 }; 371 372 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, }; 373 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, }; 374 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, }; 375 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, }; 376 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, }; 377 static int jz4725b_lcd_8bit_pins[] = { 378 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 379 0x72, 0x73, 0x74, 380 }; 381 static int jz4725b_lcd_16bit_pins[] = { 382 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 383 }; 384 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; 385 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 386 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 387 static int jz4725b_lcd_generic_pins[] = { 0x75, }; 388 static int jz4725b_nand_cs1_pins[] = { 0x55, }; 389 static int jz4725b_nand_cs2_pins[] = { 0x56, }; 390 static int jz4725b_nand_cs3_pins[] = { 0x57, }; 391 static int jz4725b_nand_cs4_pins[] = { 0x58, }; 392 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 }; 393 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d }; 394 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, }; 395 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, }; 396 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, }; 397 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, }; 398 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, }; 399 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, }; 400 401 static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; 402 403 static const struct group_desc jz4725b_groups[] = { 404 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1), 405 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit, 406 jz4725b_mmc0_4bit_funcs), 407 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0), 408 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0), 409 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1), 410 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0), 411 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0), 412 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0), 413 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1), 414 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0), 415 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0), 416 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0), 417 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0), 418 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0), 419 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0), 420 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0), 421 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0), 422 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0), 423 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0), 424 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0), 425 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0), 426 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0), 427 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0), 428 }; 429 430 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 431 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 432 static const char *jz4725b_uart_groups[] = { "uart-data", }; 433 static const char *jz4725b_lcd_groups[] = { 434 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 435 "lcd-special", "lcd-generic", 436 }; 437 static const char *jz4725b_nand_groups[] = { 438 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 439 "nand-cle-ale", "nand-fre-fwe", 440 }; 441 static const char *jz4725b_pwm0_groups[] = { "pwm0", }; 442 static const char *jz4725b_pwm1_groups[] = { "pwm1", }; 443 static const char *jz4725b_pwm2_groups[] = { "pwm2", }; 444 static const char *jz4725b_pwm3_groups[] = { "pwm3", }; 445 static const char *jz4725b_pwm4_groups[] = { "pwm4", }; 446 static const char *jz4725b_pwm5_groups[] = { "pwm5", }; 447 448 static const struct function_desc jz4725b_functions[] = { 449 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), }, 450 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), }, 451 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), }, 452 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), }, 453 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), }, 454 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), }, 455 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), }, 456 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), }, 457 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), }, 458 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), }, 459 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), }, 460 }; 461 462 static const struct ingenic_chip_info jz4725b_chip_info = { 463 .num_chips = 4, 464 .reg_offset = 0x100, 465 .version = ID_JZ4725B, 466 .groups = jz4725b_groups, 467 .num_groups = ARRAY_SIZE(jz4725b_groups), 468 .functions = jz4725b_functions, 469 .num_functions = ARRAY_SIZE(jz4725b_functions), 470 .pull_ups = jz4740_pull_ups, 471 .pull_downs = jz4740_pull_downs, 472 }; 473 474 static const u32 jz4750_pull_ups[6] = { 475 0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff, 476 }; 477 478 static const u32 jz4750_pull_downs[6] = { 479 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 480 }; 481 482 static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, }; 483 static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, }; 484 static int jz4750_uart1_data_pins[] = { 0x90, 0x91, }; 485 static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, }; 486 static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, }; 487 static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, }; 488 static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, }; 489 static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, }; 490 static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, }; 491 static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, }; 492 static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, }; 493 static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, }; 494 static int jz4750_i2c_pins[] = { 0x8c, 0x8d, }; 495 static int jz4750_cim_pins[] = { 496 0x89, 0x8b, 0x8a, 0x88, 497 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 498 }; 499 static int jz4750_lcd_8bit_pins[] = { 500 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 501 0x72, 0x73, 0x74, 502 }; 503 static int jz4750_lcd_16bit_pins[] = { 504 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 505 }; 506 static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, }; 507 static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, }; 508 static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 509 static int jz4750_lcd_generic_pins[] = { 0x75, }; 510 static int jz4750_nand_cs1_pins[] = { 0x55, }; 511 static int jz4750_nand_cs2_pins[] = { 0x56, }; 512 static int jz4750_nand_cs3_pins[] = { 0x57, }; 513 static int jz4750_nand_cs4_pins[] = { 0x58, }; 514 static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 515 static int jz4750_pwm_pwm0_pins[] = { 0x94, }; 516 static int jz4750_pwm_pwm1_pins[] = { 0x95, }; 517 static int jz4750_pwm_pwm2_pins[] = { 0x96, }; 518 static int jz4750_pwm_pwm3_pins[] = { 0x97, }; 519 static int jz4750_pwm_pwm4_pins[] = { 0x98, }; 520 static int jz4750_pwm_pwm5_pins[] = { 0x99, }; 521 522 static const struct group_desc jz4750_groups[] = { 523 INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1), 524 INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1), 525 INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0), 526 INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0), 527 INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1), 528 INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0), 529 INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0), 530 INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0), 531 INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0), 532 INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0), 533 INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0), 534 INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0), 535 INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0), 536 INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0), 537 INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0), 538 INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0), 539 INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0), 540 INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1), 541 INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0), 542 INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0), 543 INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0), 544 INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0), 545 INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0), 546 INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0), 547 INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0), 548 INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0), 549 INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0), 550 INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0), 551 INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0), 552 INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0), 553 INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0), 554 }; 555 556 static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 557 static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 558 static const char *jz4750_uart2_groups[] = { "uart2-data", }; 559 static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 560 static const char *jz4750_mmc0_groups[] = { 561 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 562 }; 563 static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 564 static const char *jz4750_i2c_groups[] = { "i2c-data", }; 565 static const char *jz4750_cim_groups[] = { "cim-data", }; 566 static const char *jz4750_lcd_groups[] = { 567 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 568 "lcd-special", "lcd-generic", 569 }; 570 static const char *jz4750_nand_groups[] = { 571 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 572 }; 573 static const char *jz4750_pwm0_groups[] = { "pwm0", }; 574 static const char *jz4750_pwm1_groups[] = { "pwm1", }; 575 static const char *jz4750_pwm2_groups[] = { "pwm2", }; 576 static const char *jz4750_pwm3_groups[] = { "pwm3", }; 577 static const char *jz4750_pwm4_groups[] = { "pwm4", }; 578 static const char *jz4750_pwm5_groups[] = { "pwm5", }; 579 580 static const struct function_desc jz4750_functions[] = { 581 { "uart0", jz4750_uart0_groups, ARRAY_SIZE(jz4750_uart0_groups), }, 582 { "uart1", jz4750_uart1_groups, ARRAY_SIZE(jz4750_uart1_groups), }, 583 { "uart2", jz4750_uart2_groups, ARRAY_SIZE(jz4750_uart2_groups), }, 584 { "uart3", jz4750_uart3_groups, ARRAY_SIZE(jz4750_uart3_groups), }, 585 { "mmc0", jz4750_mmc0_groups, ARRAY_SIZE(jz4750_mmc0_groups), }, 586 { "mmc1", jz4750_mmc1_groups, ARRAY_SIZE(jz4750_mmc1_groups), }, 587 { "i2c", jz4750_i2c_groups, ARRAY_SIZE(jz4750_i2c_groups), }, 588 { "cim", jz4750_cim_groups, ARRAY_SIZE(jz4750_cim_groups), }, 589 { "lcd", jz4750_lcd_groups, ARRAY_SIZE(jz4750_lcd_groups), }, 590 { "nand", jz4750_nand_groups, ARRAY_SIZE(jz4750_nand_groups), }, 591 { "pwm0", jz4750_pwm0_groups, ARRAY_SIZE(jz4750_pwm0_groups), }, 592 { "pwm1", jz4750_pwm1_groups, ARRAY_SIZE(jz4750_pwm1_groups), }, 593 { "pwm2", jz4750_pwm2_groups, ARRAY_SIZE(jz4750_pwm2_groups), }, 594 { "pwm3", jz4750_pwm3_groups, ARRAY_SIZE(jz4750_pwm3_groups), }, 595 { "pwm4", jz4750_pwm4_groups, ARRAY_SIZE(jz4750_pwm4_groups), }, 596 { "pwm5", jz4750_pwm5_groups, ARRAY_SIZE(jz4750_pwm5_groups), }, 597 }; 598 599 static const struct ingenic_chip_info jz4750_chip_info = { 600 .num_chips = 6, 601 .reg_offset = 0x100, 602 .version = ID_JZ4750, 603 .groups = jz4750_groups, 604 .num_groups = ARRAY_SIZE(jz4750_groups), 605 .functions = jz4750_functions, 606 .num_functions = ARRAY_SIZE(jz4750_functions), 607 .pull_ups = jz4750_pull_ups, 608 .pull_downs = jz4750_pull_downs, 609 }; 610 611 static const u32 jz4755_pull_ups[6] = { 612 0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00, 613 }; 614 615 static const u32 jz4755_pull_downs[6] = { 616 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 617 }; 618 619 static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, }; 620 static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 621 static int jz4755_uart1_data_pins[] = { 0x97, 0x99, }; 622 static int jz4755_uart2_data_pins[] = { 0x9f, }; 623 static int jz4755_ssi_dt_b_pins[] = { 0x3b, }; 624 static int jz4755_ssi_dt_f_pins[] = { 0xa1, }; 625 static int jz4755_ssi_dr_b_pins[] = { 0x3c, }; 626 static int jz4755_ssi_dr_f_pins[] = { 0xa2, }; 627 static int jz4755_ssi_clk_b_pins[] = { 0x3a, }; 628 static int jz4755_ssi_clk_f_pins[] = { 0xa0, }; 629 static int jz4755_ssi_gpc_b_pins[] = { 0x3e, }; 630 static int jz4755_ssi_gpc_f_pins[] = { 0xa4, }; 631 static int jz4755_ssi_ce0_b_pins[] = { 0x3d, }; 632 static int jz4755_ssi_ce0_f_pins[] = { 0xa3, }; 633 static int jz4755_ssi_ce1_b_pins[] = { 0x3f, }; 634 static int jz4755_ssi_ce1_f_pins[] = { 0xa5, }; 635 static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, }; 636 static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, }; 637 static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, }; 638 static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, }; 639 static int jz4755_i2c_pins[] = { 0x8c, 0x8d, }; 640 static int jz4755_cim_pins[] = { 641 0x89, 0x8b, 0x8a, 0x88, 642 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 643 }; 644 static int jz4755_lcd_8bit_pins[] = { 645 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 646 0x72, 0x73, 0x74, 647 }; 648 static int jz4755_lcd_16bit_pins[] = { 649 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 650 }; 651 static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, }; 652 static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, }; 653 static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 654 static int jz4755_lcd_generic_pins[] = { 0x75, }; 655 static int jz4755_nand_cs1_pins[] = { 0x55, }; 656 static int jz4755_nand_cs2_pins[] = { 0x56, }; 657 static int jz4755_nand_cs3_pins[] = { 0x57, }; 658 static int jz4755_nand_cs4_pins[] = { 0x58, }; 659 static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 660 static int jz4755_pwm_pwm0_pins[] = { 0x94, }; 661 static int jz4755_pwm_pwm1_pins[] = { 0xab, }; 662 static int jz4755_pwm_pwm2_pins[] = { 0x96, }; 663 static int jz4755_pwm_pwm3_pins[] = { 0x97, }; 664 static int jz4755_pwm_pwm4_pins[] = { 0x98, }; 665 static int jz4755_pwm_pwm5_pins[] = { 0x99, }; 666 667 static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, }; 668 static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, }; 669 static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, }; 670 671 static const struct group_desc jz4755_groups[] = { 672 INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0), 673 INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0), 674 INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1), 675 INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1), 676 INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0), 677 INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0), 678 INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0), 679 INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0), 680 INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0), 681 INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0), 682 INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0), 683 INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0), 684 INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0), 685 INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0), 686 INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0), 687 INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0), 688 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit, 689 jz4755_mmc0_1bit_funcs), 690 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit, 691 jz4755_mmc0_4bit_funcs), 692 INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1), 693 INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1), 694 INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0), 695 INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0), 696 INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0), 697 INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0), 698 INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0), 699 INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit, 700 jz4755_lcd_24bit_funcs), 701 INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0), 702 INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0), 703 INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0), 704 INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0), 705 INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0), 706 INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0), 707 INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0), 708 INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0), 709 INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1), 710 INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0), 711 INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0), 712 INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0), 713 INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0), 714 }; 715 716 static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 717 static const char *jz4755_uart1_groups[] = { "uart1-data", }; 718 static const char *jz4755_uart2_groups[] = { "uart2-data", }; 719 static const char *jz4755_ssi_groups[] = { 720 "ssi-dt-b", "ssi-dt-f", 721 "ssi-dr-b", "ssi-dr-f", 722 "ssi-clk-b", "ssi-clk-f", 723 "ssi-gpc-b", "ssi-gpc-f", 724 "ssi-ce0-b", "ssi-ce0-f", 725 "ssi-ce1-b", "ssi-ce1-f", 726 }; 727 static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 728 static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 729 static const char *jz4755_i2c_groups[] = { "i2c-data", }; 730 static const char *jz4755_cim_groups[] = { "cim-data", }; 731 static const char *jz4755_lcd_groups[] = { 732 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 733 "lcd-special", "lcd-generic", 734 }; 735 static const char *jz4755_nand_groups[] = { 736 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 737 }; 738 static const char *jz4755_pwm0_groups[] = { "pwm0", }; 739 static const char *jz4755_pwm1_groups[] = { "pwm1", }; 740 static const char *jz4755_pwm2_groups[] = { "pwm2", }; 741 static const char *jz4755_pwm3_groups[] = { "pwm3", }; 742 static const char *jz4755_pwm4_groups[] = { "pwm4", }; 743 static const char *jz4755_pwm5_groups[] = { "pwm5", }; 744 745 static const struct function_desc jz4755_functions[] = { 746 { "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), }, 747 { "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), }, 748 { "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), }, 749 { "ssi", jz4755_ssi_groups, ARRAY_SIZE(jz4755_ssi_groups), }, 750 { "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), }, 751 { "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), }, 752 { "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), }, 753 { "cim", jz4755_cim_groups, ARRAY_SIZE(jz4755_cim_groups), }, 754 { "lcd", jz4755_lcd_groups, ARRAY_SIZE(jz4755_lcd_groups), }, 755 { "nand", jz4755_nand_groups, ARRAY_SIZE(jz4755_nand_groups), }, 756 { "pwm0", jz4755_pwm0_groups, ARRAY_SIZE(jz4755_pwm0_groups), }, 757 { "pwm1", jz4755_pwm1_groups, ARRAY_SIZE(jz4755_pwm1_groups), }, 758 { "pwm2", jz4755_pwm2_groups, ARRAY_SIZE(jz4755_pwm2_groups), }, 759 { "pwm3", jz4755_pwm3_groups, ARRAY_SIZE(jz4755_pwm3_groups), }, 760 { "pwm4", jz4755_pwm4_groups, ARRAY_SIZE(jz4755_pwm4_groups), }, 761 { "pwm5", jz4755_pwm5_groups, ARRAY_SIZE(jz4755_pwm5_groups), }, 762 }; 763 764 static const struct ingenic_chip_info jz4755_chip_info = { 765 .num_chips = 6, 766 .reg_offset = 0x100, 767 .version = ID_JZ4755, 768 .groups = jz4755_groups, 769 .num_groups = ARRAY_SIZE(jz4755_groups), 770 .functions = jz4755_functions, 771 .num_functions = ARRAY_SIZE(jz4755_functions), 772 .pull_ups = jz4755_pull_ups, 773 .pull_downs = jz4755_pull_downs, 774 }; 775 776 static const u32 jz4760_pull_ups[6] = { 777 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f, 778 }; 779 780 static const u32 jz4760_pull_downs[6] = { 781 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, 782 }; 783 784 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; 785 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 786 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; 787 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 788 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; 789 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 790 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; 791 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; 792 static int jz4760_ssi0_dt_a_pins[] = { 0x15, }; 793 static int jz4760_ssi0_dt_b_pins[] = { 0x35, }; 794 static int jz4760_ssi0_dt_d_pins[] = { 0x75, }; 795 static int jz4760_ssi0_dt_e_pins[] = { 0x91, }; 796 static int jz4760_ssi0_dr_a_pins[] = { 0x14, }; 797 static int jz4760_ssi0_dr_b_pins[] = { 0x34, }; 798 static int jz4760_ssi0_dr_d_pins[] = { 0x74, }; 799 static int jz4760_ssi0_dr_e_pins[] = { 0x8e, }; 800 static int jz4760_ssi0_clk_a_pins[] = { 0x12, }; 801 static int jz4760_ssi0_clk_b_pins[] = { 0x3c, }; 802 static int jz4760_ssi0_clk_d_pins[] = { 0x78, }; 803 static int jz4760_ssi0_clk_e_pins[] = { 0x8f, }; 804 static int jz4760_ssi0_gpc_b_pins[] = { 0x3e, }; 805 static int jz4760_ssi0_gpc_d_pins[] = { 0x76, }; 806 static int jz4760_ssi0_gpc_e_pins[] = { 0x93, }; 807 static int jz4760_ssi0_ce0_a_pins[] = { 0x13, }; 808 static int jz4760_ssi0_ce0_b_pins[] = { 0x3d, }; 809 static int jz4760_ssi0_ce0_d_pins[] = { 0x79, }; 810 static int jz4760_ssi0_ce0_e_pins[] = { 0x90, }; 811 static int jz4760_ssi0_ce1_b_pins[] = { 0x3f, }; 812 static int jz4760_ssi0_ce1_d_pins[] = { 0x77, }; 813 static int jz4760_ssi0_ce1_e_pins[] = { 0x92, }; 814 static int jz4760_ssi1_dt_b_9_pins[] = { 0x29, }; 815 static int jz4760_ssi1_dt_b_21_pins[] = { 0x35, }; 816 static int jz4760_ssi1_dt_d_12_pins[] = { 0x6c, }; 817 static int jz4760_ssi1_dt_d_21_pins[] = { 0x75, }; 818 static int jz4760_ssi1_dt_e_pins[] = { 0x91, }; 819 static int jz4760_ssi1_dt_f_pins[] = { 0xa3, }; 820 static int jz4760_ssi1_dr_b_6_pins[] = { 0x26, }; 821 static int jz4760_ssi1_dr_b_20_pins[] = { 0x34, }; 822 static int jz4760_ssi1_dr_d_13_pins[] = { 0x6d, }; 823 static int jz4760_ssi1_dr_d_20_pins[] = { 0x74, }; 824 static int jz4760_ssi1_dr_e_pins[] = { 0x8e, }; 825 static int jz4760_ssi1_dr_f_pins[] = { 0xa0, }; 826 static int jz4760_ssi1_clk_b_7_pins[] = { 0x27, }; 827 static int jz4760_ssi1_clk_b_28_pins[] = { 0x3c, }; 828 static int jz4760_ssi1_clk_d_pins[] = { 0x78, }; 829 static int jz4760_ssi1_clk_e_7_pins[] = { 0x87, }; 830 static int jz4760_ssi1_clk_e_15_pins[] = { 0x8f, }; 831 static int jz4760_ssi1_clk_f_pins[] = { 0xa2, }; 832 static int jz4760_ssi1_gpc_b_pins[] = { 0x3e, }; 833 static int jz4760_ssi1_gpc_d_pins[] = { 0x76, }; 834 static int jz4760_ssi1_gpc_e_pins[] = { 0x93, }; 835 static int jz4760_ssi1_ce0_b_8_pins[] = { 0x28, }; 836 static int jz4760_ssi1_ce0_b_29_pins[] = { 0x3d, }; 837 static int jz4760_ssi1_ce0_d_pins[] = { 0x79, }; 838 static int jz4760_ssi1_ce0_e_6_pins[] = { 0x86, }; 839 static int jz4760_ssi1_ce0_e_16_pins[] = { 0x90, }; 840 static int jz4760_ssi1_ce0_f_pins[] = { 0xa1, }; 841 static int jz4760_ssi1_ce1_b_pins[] = { 0x3f, }; 842 static int jz4760_ssi1_ce1_d_pins[] = { 0x77, }; 843 static int jz4760_ssi1_ce1_e_pins[] = { 0x92, }; 844 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 845 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 846 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 847 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 848 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 849 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 850 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 851 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 852 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 853 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 854 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 855 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 856 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 857 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 858 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 859 static int jz4760_nemc_8bit_data_pins[] = { 860 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 861 }; 862 static int jz4760_nemc_16bit_data_pins[] = { 863 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 864 }; 865 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 866 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 867 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; 868 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 869 static int jz4760_nemc_wait_pins[] = { 0x1b, }; 870 static int jz4760_nemc_cs1_pins[] = { 0x15, }; 871 static int jz4760_nemc_cs2_pins[] = { 0x16, }; 872 static int jz4760_nemc_cs3_pins[] = { 0x17, }; 873 static int jz4760_nemc_cs4_pins[] = { 0x18, }; 874 static int jz4760_nemc_cs5_pins[] = { 0x19, }; 875 static int jz4760_nemc_cs6_pins[] = { 0x1a, }; 876 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; 877 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; 878 static int jz4760_cim_pins[] = { 879 0x26, 0x27, 0x28, 0x29, 880 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 881 }; 882 static int jz4760_lcd_8bit_pins[] = { 883 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c, 884 0x4d, 0x52, 0x53, 885 }; 886 static int jz4760_lcd_16bit_pins[] = { 887 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 888 }; 889 static int jz4760_lcd_18bit_pins[] = { 890 0x5a, 0x5b, 891 }; 892 static int jz4760_lcd_24bit_pins[] = { 893 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, 894 }; 895 static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 896 static int jz4760_lcd_generic_pins[] = { 0x49, }; 897 static int jz4760_pwm_pwm0_pins[] = { 0x80, }; 898 static int jz4760_pwm_pwm1_pins[] = { 0x81, }; 899 static int jz4760_pwm_pwm2_pins[] = { 0x82, }; 900 static int jz4760_pwm_pwm3_pins[] = { 0x83, }; 901 static int jz4760_pwm_pwm4_pins[] = { 0x84, }; 902 static int jz4760_pwm_pwm5_pins[] = { 0x85, }; 903 static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; 904 static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; 905 static int jz4760_otg_pins[] = { 0x8a, }; 906 907 static u8 jz4760_uart3_data_funcs[] = { 0, 1, }; 908 static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 909 910 static const struct group_desc jz4760_groups[] = { 911 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0), 912 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0), 913 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0), 914 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0), 915 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0), 916 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0), 917 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data, 918 jz4760_uart3_data_funcs), 919 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0), 920 INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2), 921 INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1), 922 INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1), 923 INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0), 924 INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1), 925 INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1), 926 INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1), 927 INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0), 928 INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2), 929 INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1), 930 INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1), 931 INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0), 932 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1), 933 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1), 934 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0), 935 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2), 936 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1), 937 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1), 938 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0), 939 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1), 940 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1), 941 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0), 942 INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2), 943 INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2), 944 INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2), 945 INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2), 946 INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1), 947 INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2), 948 INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2), 949 INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2), 950 INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2), 951 INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2), 952 INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1), 953 INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2), 954 INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2), 955 INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2), 956 INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2), 957 INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2), 958 INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1), 959 INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2), 960 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2), 961 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2), 962 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1), 963 INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2), 964 INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2), 965 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2), 966 INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2), 967 INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1), 968 INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2), 969 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2), 970 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2), 971 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1), 972 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a, 973 jz4760_mmc0_1bit_a_funcs), 974 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1), 975 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0), 976 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0), 977 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0), 978 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0), 979 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0), 980 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1), 981 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1), 982 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1), 983 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0), 984 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0), 985 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2), 986 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2), 987 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2), 988 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0), 989 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0), 990 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0), 991 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0), 992 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0), 993 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0), 994 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0), 995 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0), 996 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0), 997 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0), 998 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0), 999 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0), 1000 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0), 1001 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0), 1002 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0), 1003 INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0), 1004 INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0), 1005 INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0), 1006 INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0), 1007 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0), 1008 INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1), 1009 INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0), 1010 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0), 1011 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0), 1012 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0), 1013 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0), 1014 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0), 1015 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0), 1016 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0), 1017 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0), 1018 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), 1019 }; 1020 1021 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1022 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1023 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1024 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 1025 static const char *jz4760_ssi0_groups[] = { 1026 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1027 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1028 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", 1029 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1030 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1031 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1032 }; 1033 static const char *jz4760_ssi1_groups[] = { 1034 "ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f", 1035 "ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f", 1036 "ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f", 1037 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1038 "ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f", 1039 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1040 }; 1041 static const char *jz4760_mmc0_groups[] = { 1042 "mmc0-1bit-a", "mmc0-4bit-a", 1043 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 1044 }; 1045 static const char *jz4760_mmc1_groups[] = { 1046 "mmc1-1bit-d", "mmc1-4bit-d", 1047 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 1048 }; 1049 static const char *jz4760_mmc2_groups[] = { 1050 "mmc2-1bit-b", "mmc2-4bit-b", 1051 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 1052 }; 1053 static const char *jz4760_nemc_groups[] = { 1054 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1055 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1056 }; 1057 static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; 1058 static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; 1059 static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; 1060 static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; 1061 static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; 1062 static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; 1063 static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; 1064 static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; 1065 static const char *jz4760_cim_groups[] = { "cim-data", }; 1066 static const char *jz4760_lcd_groups[] = { 1067 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1068 "lcd-special", "lcd-generic", 1069 }; 1070 static const char *jz4760_pwm0_groups[] = { "pwm0", }; 1071 static const char *jz4760_pwm1_groups[] = { "pwm1", }; 1072 static const char *jz4760_pwm2_groups[] = { "pwm2", }; 1073 static const char *jz4760_pwm3_groups[] = { "pwm3", }; 1074 static const char *jz4760_pwm4_groups[] = { "pwm4", }; 1075 static const char *jz4760_pwm5_groups[] = { "pwm5", }; 1076 static const char *jz4760_pwm6_groups[] = { "pwm6", }; 1077 static const char *jz4760_pwm7_groups[] = { "pwm7", }; 1078 static const char *jz4760_otg_groups[] = { "otg-vbus", }; 1079 1080 static const struct function_desc jz4760_functions[] = { 1081 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, 1082 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, 1083 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, 1084 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, 1085 { "ssi0", jz4760_ssi0_groups, ARRAY_SIZE(jz4760_ssi0_groups), }, 1086 { "ssi1", jz4760_ssi1_groups, ARRAY_SIZE(jz4760_ssi1_groups), }, 1087 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, 1088 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, 1089 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, 1090 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), }, 1091 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), }, 1092 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), }, 1093 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), }, 1094 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), }, 1095 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), }, 1096 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), }, 1097 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), }, 1098 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), }, 1099 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), }, 1100 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), }, 1101 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), }, 1102 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), }, 1103 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), }, 1104 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), }, 1105 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), }, 1106 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), }, 1107 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, 1108 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, 1109 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), }, 1110 }; 1111 1112 static const struct ingenic_chip_info jz4760_chip_info = { 1113 .num_chips = 6, 1114 .reg_offset = 0x100, 1115 .version = ID_JZ4760, 1116 .groups = jz4760_groups, 1117 .num_groups = ARRAY_SIZE(jz4760_groups), 1118 .functions = jz4760_functions, 1119 .num_functions = ARRAY_SIZE(jz4760_functions), 1120 .pull_ups = jz4760_pull_ups, 1121 .pull_downs = jz4760_pull_downs, 1122 }; 1123 1124 static const u32 jz4770_pull_ups[6] = { 1125 0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f, 1126 }; 1127 1128 static const u32 jz4770_pull_downs[6] = { 1129 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0, 1130 }; 1131 1132 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; 1133 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 1134 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, }; 1135 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 1136 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, }; 1137 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 1138 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; 1139 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; 1140 static int jz4770_ssi0_dt_a_pins[] = { 0x15, }; 1141 static int jz4770_ssi0_dt_b_pins[] = { 0x35, }; 1142 static int jz4770_ssi0_dt_d_pins[] = { 0x75, }; 1143 static int jz4770_ssi0_dt_e_pins[] = { 0x91, }; 1144 static int jz4770_ssi0_dr_a_pins[] = { 0x14, }; 1145 static int jz4770_ssi0_dr_b_pins[] = { 0x34, }; 1146 static int jz4770_ssi0_dr_d_pins[] = { 0x74, }; 1147 static int jz4770_ssi0_dr_e_pins[] = { 0x8e, }; 1148 static int jz4770_ssi0_clk_a_pins[] = { 0x12, }; 1149 static int jz4770_ssi0_clk_b_pins[] = { 0x3c, }; 1150 static int jz4770_ssi0_clk_d_pins[] = { 0x78, }; 1151 static int jz4770_ssi0_clk_e_pins[] = { 0x8f, }; 1152 static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, }; 1153 static int jz4770_ssi0_gpc_d_pins[] = { 0x76, }; 1154 static int jz4770_ssi0_gpc_e_pins[] = { 0x93, }; 1155 static int jz4770_ssi0_ce0_a_pins[] = { 0x13, }; 1156 static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, }; 1157 static int jz4770_ssi0_ce0_d_pins[] = { 0x79, }; 1158 static int jz4770_ssi0_ce0_e_pins[] = { 0x90, }; 1159 static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, }; 1160 static int jz4770_ssi0_ce1_d_pins[] = { 0x77, }; 1161 static int jz4770_ssi0_ce1_e_pins[] = { 0x92, }; 1162 static int jz4770_ssi1_dt_b_pins[] = { 0x35, }; 1163 static int jz4770_ssi1_dt_d_pins[] = { 0x75, }; 1164 static int jz4770_ssi1_dt_e_pins[] = { 0x91, }; 1165 static int jz4770_ssi1_dr_b_pins[] = { 0x34, }; 1166 static int jz4770_ssi1_dr_d_pins[] = { 0x74, }; 1167 static int jz4770_ssi1_dr_e_pins[] = { 0x8e, }; 1168 static int jz4770_ssi1_clk_b_pins[] = { 0x3c, }; 1169 static int jz4770_ssi1_clk_d_pins[] = { 0x78, }; 1170 static int jz4770_ssi1_clk_e_pins[] = { 0x8f, }; 1171 static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, }; 1172 static int jz4770_ssi1_gpc_d_pins[] = { 0x76, }; 1173 static int jz4770_ssi1_gpc_e_pins[] = { 0x93, }; 1174 static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, }; 1175 static int jz4770_ssi1_ce0_d_pins[] = { 0x79, }; 1176 static int jz4770_ssi1_ce0_e_pins[] = { 0x90, }; 1177 static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, }; 1178 static int jz4770_ssi1_ce1_d_pins[] = { 0x77, }; 1179 static int jz4770_ssi1_ce1_e_pins[] = { 0x92, }; 1180 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 1181 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 1182 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1183 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1184 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1185 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 1186 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 1187 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1188 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1189 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1190 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 1191 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 1192 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1193 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1194 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1195 static int jz4770_nemc_8bit_data_pins[] = { 1196 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1197 }; 1198 static int jz4770_nemc_16bit_data_pins[] = { 1199 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1200 }; 1201 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 1202 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 1203 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, }; 1204 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 1205 static int jz4770_nemc_wait_pins[] = { 0x1b, }; 1206 static int jz4770_nemc_cs1_pins[] = { 0x15, }; 1207 static int jz4770_nemc_cs2_pins[] = { 0x16, }; 1208 static int jz4770_nemc_cs3_pins[] = { 0x17, }; 1209 static int jz4770_nemc_cs4_pins[] = { 0x18, }; 1210 static int jz4770_nemc_cs5_pins[] = { 0x19, }; 1211 static int jz4770_nemc_cs6_pins[] = { 0x1a, }; 1212 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, }; 1213 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, }; 1214 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, }; 1215 static int jz4770_cim_8bit_pins[] = { 1216 0x26, 0x27, 0x28, 0x29, 1217 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 1218 }; 1219 static int jz4770_cim_12bit_pins[] = { 1220 0x32, 0x33, 0xb0, 0xb1, 1221 }; 1222 static int jz4770_lcd_8bit_pins[] = { 1223 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, 1224 0x48, 0x52, 0x53, 1225 }; 1226 static int jz4770_lcd_16bit_pins[] = { 1227 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 1228 }; 1229 static int jz4770_lcd_18bit_pins[] = { 1230 0x5a, 0x5b, 1231 }; 1232 static int jz4770_lcd_24bit_pins[] = { 1233 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 1234 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 1235 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 1236 0x58, 0x59, 0x5a, 0x5b, 1237 }; 1238 static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 1239 static int jz4770_lcd_generic_pins[] = { 0x49, }; 1240 static int jz4770_pwm_pwm0_pins[] = { 0x80, }; 1241 static int jz4770_pwm_pwm1_pins[] = { 0x81, }; 1242 static int jz4770_pwm_pwm2_pins[] = { 0x82, }; 1243 static int jz4770_pwm_pwm3_pins[] = { 0x83, }; 1244 static int jz4770_pwm_pwm4_pins[] = { 0x84, }; 1245 static int jz4770_pwm_pwm5_pins[] = { 0x85, }; 1246 static int jz4770_pwm_pwm6_pins[] = { 0x6a, }; 1247 static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; 1248 static int jz4770_mac_rmii_pins[] = { 1249 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 1250 }; 1251 static int jz4770_mac_mii_pins[] = { 1252 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, 1253 }; 1254 1255 static const struct group_desc jz4770_groups[] = { 1256 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 1257 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 1258 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 1259 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 1260 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0), 1261 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0), 1262 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 1263 jz4760_uart3_data_funcs), 1264 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 1265 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2), 1266 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1), 1267 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1), 1268 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 1269 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1), 1270 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1), 1271 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1), 1272 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 1273 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2), 1274 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1), 1275 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1), 1276 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 1277 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1), 1278 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1), 1279 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 1280 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2), 1281 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1), 1282 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1), 1283 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 1284 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1), 1285 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1), 1286 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 1287 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2), 1288 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2), 1289 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 1290 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2), 1291 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2), 1292 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 1293 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2), 1294 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2), 1295 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 1296 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2), 1297 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2), 1298 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 1299 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2), 1300 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2), 1301 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 1302 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2), 1303 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2), 1304 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 1305 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 1306 jz4760_mmc0_1bit_a_funcs), 1307 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 1308 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 1309 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 1310 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0), 1311 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 1312 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 1313 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 1314 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 1315 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1), 1316 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 1317 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 1318 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 1319 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 1320 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2), 1321 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0), 1322 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0), 1323 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 1324 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 1325 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 1326 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 1327 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 1328 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 1329 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 1330 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 1331 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 1332 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 1333 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 1334 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 1335 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 1336 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 1337 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0), 1338 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 1339 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), 1340 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), 1341 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), 1342 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 1343 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), 1344 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), 1345 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 1346 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 1347 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 1348 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 1349 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 1350 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 1351 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 1352 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 1353 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0), 1354 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0), 1355 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), 1356 }; 1357 1358 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1359 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1360 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1361 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 1362 static const char *jz4770_ssi0_groups[] = { 1363 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1364 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1365 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", 1366 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1367 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1368 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1369 }; 1370 static const char *jz4770_ssi1_groups[] = { 1371 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1372 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1373 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1374 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1375 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1376 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1377 }; 1378 static const char *jz4770_mmc0_groups[] = { 1379 "mmc0-1bit-a", "mmc0-4bit-a", 1380 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 1381 }; 1382 static const char *jz4770_mmc1_groups[] = { 1383 "mmc1-1bit-d", "mmc1-4bit-d", 1384 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 1385 }; 1386 static const char *jz4770_mmc2_groups[] = { 1387 "mmc2-1bit-b", "mmc2-4bit-b", 1388 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 1389 }; 1390 static const char *jz4770_nemc_groups[] = { 1391 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1392 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1393 }; 1394 static const char *jz4770_cs1_groups[] = { "nemc-cs1", }; 1395 static const char *jz4770_cs2_groups[] = { "nemc-cs2", }; 1396 static const char *jz4770_cs3_groups[] = { "nemc-cs3", }; 1397 static const char *jz4770_cs4_groups[] = { "nemc-cs4", }; 1398 static const char *jz4770_cs5_groups[] = { "nemc-cs5", }; 1399 static const char *jz4770_cs6_groups[] = { "nemc-cs6", }; 1400 static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; 1401 static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; 1402 static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; 1403 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 1404 static const char *jz4770_lcd_groups[] = { 1405 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1406 "lcd-special", "lcd-generic", 1407 }; 1408 static const char *jz4770_pwm0_groups[] = { "pwm0", }; 1409 static const char *jz4770_pwm1_groups[] = { "pwm1", }; 1410 static const char *jz4770_pwm2_groups[] = { "pwm2", }; 1411 static const char *jz4770_pwm3_groups[] = { "pwm3", }; 1412 static const char *jz4770_pwm4_groups[] = { "pwm4", }; 1413 static const char *jz4770_pwm5_groups[] = { "pwm5", }; 1414 static const char *jz4770_pwm6_groups[] = { "pwm6", }; 1415 static const char *jz4770_pwm7_groups[] = { "pwm7", }; 1416 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", }; 1417 1418 static const struct function_desc jz4770_functions[] = { 1419 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 1420 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 1421 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), }, 1422 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 1423 { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), }, 1424 { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), }, 1425 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), }, 1426 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), }, 1427 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), }, 1428 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), }, 1429 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1430 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1431 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1432 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1433 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1434 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1435 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1436 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1437 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1438 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), }, 1439 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1440 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1441 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1442 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1443 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1444 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1445 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1446 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1447 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1448 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), }, 1449 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), }, 1450 }; 1451 1452 static const struct ingenic_chip_info jz4770_chip_info = { 1453 .num_chips = 6, 1454 .reg_offset = 0x100, 1455 .version = ID_JZ4770, 1456 .groups = jz4770_groups, 1457 .num_groups = ARRAY_SIZE(jz4770_groups), 1458 .functions = jz4770_functions, 1459 .num_functions = ARRAY_SIZE(jz4770_functions), 1460 .pull_ups = jz4770_pull_ups, 1461 .pull_downs = jz4770_pull_downs, 1462 }; 1463 1464 static const u32 jz4775_pull_ups[7] = { 1465 0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0, 1466 }; 1467 1468 static const u32 jz4775_pull_downs[7] = { 1469 0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00, 1470 }; 1471 1472 static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, }; 1473 static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 1474 static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, }; 1475 static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 1476 static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, }; 1477 static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, }; 1478 static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, }; 1479 static int jz4775_ssi_dt_a_pins[] = { 0x13, }; 1480 static int jz4775_ssi_dt_d_pins[] = { 0x75, }; 1481 static int jz4775_ssi_dr_a_pins[] = { 0x14, }; 1482 static int jz4775_ssi_dr_d_pins[] = { 0x74, }; 1483 static int jz4775_ssi_clk_a_pins[] = { 0x12, }; 1484 static int jz4775_ssi_clk_d_pins[] = { 0x78, }; 1485 static int jz4775_ssi_gpc_pins[] = { 0x76, }; 1486 static int jz4775_ssi_ce0_a_pins[] = { 0x17, }; 1487 static int jz4775_ssi_ce0_d_pins[] = { 0x79, }; 1488 static int jz4775_ssi_ce1_pins[] = { 0x77, }; 1489 static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 1490 static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 1491 static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, }; 1492 static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1493 static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1494 static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 1495 static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 1496 static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1497 static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1498 static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 1499 static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 1500 static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1501 static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1502 static int jz4775_nemc_8bit_data_pins[] = { 1503 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1504 }; 1505 static int jz4775_nemc_16bit_data_pins[] = { 1506 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1, 1507 }; 1508 static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 1509 static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 1510 static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, }; 1511 static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 1512 static int jz4775_nemc_wait_pins[] = { 0x1b, }; 1513 static int jz4775_nemc_cs1_pins[] = { 0x15, }; 1514 static int jz4775_nemc_cs2_pins[] = { 0x16, }; 1515 static int jz4775_nemc_cs3_pins[] = { 0x17, }; 1516 static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, }; 1517 static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, }; 1518 static int jz4775_i2c2_pins[] = { 0x80, 0x83, }; 1519 static int jz4775_i2s_data_tx_pins[] = { 0xa3, }; 1520 static int jz4775_i2s_data_rx_pins[] = { 0xa2, }; 1521 static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, }; 1522 static int jz4775_i2s_sysclk_pins[] = { 0x83, }; 1523 static int jz4775_dmic_pins[] = { 0xaa, 0xab, }; 1524 static int jz4775_cim_pins[] = { 1525 0x26, 0x27, 0x28, 0x29, 1526 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 1527 }; 1528 static int jz4775_lcd_8bit_pins[] = { 1529 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, 1530 0x48, 0x52, 0x53, 1531 }; 1532 static int jz4775_lcd_16bit_pins[] = { 1533 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 1534 }; 1535 static int jz4775_lcd_18bit_pins[] = { 1536 0x5a, 0x5b, 1537 }; 1538 static int jz4775_lcd_24bit_pins[] = { 1539 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, 1540 }; 1541 static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 1542 static int jz4775_lcd_generic_pins[] = { 0x49, }; 1543 static int jz4775_pwm_pwm0_pins[] = { 0x80, }; 1544 static int jz4775_pwm_pwm1_pins[] = { 0x81, }; 1545 static int jz4775_pwm_pwm2_pins[] = { 0x82, }; 1546 static int jz4775_pwm_pwm3_pins[] = { 0x83, }; 1547 static int jz4775_mac_rmii_pins[] = { 1548 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 1549 }; 1550 static int jz4775_mac_mii_pins[] = { 1551 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, 1552 }; 1553 static int jz4775_mac_rgmii_pins[] = { 1554 0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4, 1555 0xad, 0xae, 0xa7, 0xa6, 1556 }; 1557 static int jz4775_mac_gmii_pins[] = { 1558 0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 1559 0xa8, 0x28, 0x24, 0xaf, 1560 }; 1561 static int jz4775_otg_pins[] = { 0x8a, }; 1562 1563 static u8 jz4775_uart3_data_funcs[] = { 0, 1, }; 1564 static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, }; 1565 static u8 jz4775_mac_rgmii_funcs[] = { 1566 0, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1567 0, 0, 0, 0, 1568 }; 1569 static u8 jz4775_mac_gmii_funcs[] = { 1570 1, 1, 1, 1, 1, 1, 1, 1, 1571 0, 1, 1, 0, 1572 }; 1573 1574 static const struct group_desc jz4775_groups[] = { 1575 INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0), 1576 INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0), 1577 INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0), 1578 INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0), 1579 INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2), 1580 INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1), 1581 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data, 1582 jz4775_uart3_data_funcs), 1583 INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2), 1584 INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1), 1585 INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2), 1586 INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1), 1587 INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2), 1588 INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1), 1589 INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1), 1590 INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2), 1591 INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1), 1592 INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1), 1593 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1), 1594 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1), 1595 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1), 1596 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0), 1597 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0), 1598 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0), 1599 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0), 1600 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1), 1601 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1), 1602 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0), 1603 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0), 1604 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2), 1605 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2), 1606 INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0), 1607 INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1), 1608 INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0), 1609 INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0), 1610 INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0), 1611 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0), 1612 INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0), 1613 INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0), 1614 INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0), 1615 INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0), 1616 INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0), 1617 INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0), 1618 INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1), 1619 INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1), 1620 INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1), 1621 INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1), 1622 INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2), 1623 INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1), 1624 INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0), 1625 INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0), 1626 INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0), 1627 INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0), 1628 INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0), 1629 INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0), 1630 INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1), 1631 INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0), 1632 INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0), 1633 INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0), 1634 INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0), 1635 INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0), 1636 INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii, 1637 jz4775_mac_mii_funcs), 1638 INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii, 1639 jz4775_mac_rgmii_funcs), 1640 INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii, 1641 jz4775_mac_gmii_funcs), 1642 INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0), 1643 }; 1644 1645 static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1646 static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1647 static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", }; 1648 static const char *jz4775_uart3_groups[] = { "uart3-data", }; 1649 static const char *jz4775_ssi_groups[] = { 1650 "ssi-dt-a", "ssi-dt-d", 1651 "ssi-dr-a", "ssi-dr-d", 1652 "ssi-clk-a", "ssi-clk-d", 1653 "ssi-gpc", 1654 "ssi-ce0-a", "ssi-ce0-d", 1655 "ssi-ce1", 1656 }; 1657 static const char *jz4775_mmc0_groups[] = { 1658 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1659 "mmc0-1bit-e", "mmc0-4bit-e", 1660 }; 1661 static const char *jz4775_mmc1_groups[] = { 1662 "mmc1-1bit-d", "mmc1-4bit-d", 1663 "mmc1-1bit-e", "mmc1-4bit-e", 1664 }; 1665 static const char *jz4775_mmc2_groups[] = { 1666 "mmc2-1bit-b", "mmc2-4bit-b", 1667 "mmc2-1bit-e", "mmc2-4bit-e", 1668 }; 1669 static const char *jz4775_nemc_groups[] = { 1670 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1671 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1672 }; 1673 static const char *jz4775_cs1_groups[] = { "nemc-cs1", }; 1674 static const char *jz4775_cs2_groups[] = { "nemc-cs2", }; 1675 static const char *jz4775_cs3_groups[] = { "nemc-cs3", }; 1676 static const char *jz4775_i2c0_groups[] = { "i2c0-data", }; 1677 static const char *jz4775_i2c1_groups[] = { "i2c1-data", }; 1678 static const char *jz4775_i2c2_groups[] = { "i2c2-data", }; 1679 static const char *jz4775_i2s_groups[] = { 1680 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 1681 }; 1682 static const char *jz4775_dmic_groups[] = { "dmic", }; 1683 static const char *jz4775_cim_groups[] = { "cim-data", }; 1684 static const char *jz4775_lcd_groups[] = { 1685 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1686 "lcd-special", "lcd-generic", 1687 }; 1688 static const char *jz4775_pwm0_groups[] = { "pwm0", }; 1689 static const char *jz4775_pwm1_groups[] = { "pwm1", }; 1690 static const char *jz4775_pwm2_groups[] = { "pwm2", }; 1691 static const char *jz4775_pwm3_groups[] = { "pwm3", }; 1692 static const char *jz4775_mac_groups[] = { 1693 "mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii", 1694 }; 1695 static const char *jz4775_otg_groups[] = { "otg-vbus", }; 1696 1697 static const struct function_desc jz4775_functions[] = { 1698 { "uart0", jz4775_uart0_groups, ARRAY_SIZE(jz4775_uart0_groups), }, 1699 { "uart1", jz4775_uart1_groups, ARRAY_SIZE(jz4775_uart1_groups), }, 1700 { "uart2", jz4775_uart2_groups, ARRAY_SIZE(jz4775_uart2_groups), }, 1701 { "uart3", jz4775_uart3_groups, ARRAY_SIZE(jz4775_uart3_groups), }, 1702 { "ssi", jz4775_ssi_groups, ARRAY_SIZE(jz4775_ssi_groups), }, 1703 { "mmc0", jz4775_mmc0_groups, ARRAY_SIZE(jz4775_mmc0_groups), }, 1704 { "mmc1", jz4775_mmc1_groups, ARRAY_SIZE(jz4775_mmc1_groups), }, 1705 { "mmc2", jz4775_mmc2_groups, ARRAY_SIZE(jz4775_mmc2_groups), }, 1706 { "nemc", jz4775_nemc_groups, ARRAY_SIZE(jz4775_nemc_groups), }, 1707 { "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), }, 1708 { "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), }, 1709 { "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), }, 1710 { "i2c0", jz4775_i2c0_groups, ARRAY_SIZE(jz4775_i2c0_groups), }, 1711 { "i2c1", jz4775_i2c1_groups, ARRAY_SIZE(jz4775_i2c1_groups), }, 1712 { "i2c2", jz4775_i2c2_groups, ARRAY_SIZE(jz4775_i2c2_groups), }, 1713 { "i2s", jz4775_i2s_groups, ARRAY_SIZE(jz4775_i2s_groups), }, 1714 { "dmic", jz4775_dmic_groups, ARRAY_SIZE(jz4775_dmic_groups), }, 1715 { "cim", jz4775_cim_groups, ARRAY_SIZE(jz4775_cim_groups), }, 1716 { "lcd", jz4775_lcd_groups, ARRAY_SIZE(jz4775_lcd_groups), }, 1717 { "pwm0", jz4775_pwm0_groups, ARRAY_SIZE(jz4775_pwm0_groups), }, 1718 { "pwm1", jz4775_pwm1_groups, ARRAY_SIZE(jz4775_pwm1_groups), }, 1719 { "pwm2", jz4775_pwm2_groups, ARRAY_SIZE(jz4775_pwm2_groups), }, 1720 { "pwm3", jz4775_pwm3_groups, ARRAY_SIZE(jz4775_pwm3_groups), }, 1721 { "mac", jz4775_mac_groups, ARRAY_SIZE(jz4775_mac_groups), }, 1722 { "otg", jz4775_otg_groups, ARRAY_SIZE(jz4775_otg_groups), }, 1723 }; 1724 1725 static const struct ingenic_chip_info jz4775_chip_info = { 1726 .num_chips = 7, 1727 .reg_offset = 0x100, 1728 .version = ID_JZ4775, 1729 .groups = jz4775_groups, 1730 .num_groups = ARRAY_SIZE(jz4775_groups), 1731 .functions = jz4775_functions, 1732 .num_functions = ARRAY_SIZE(jz4775_functions), 1733 .pull_ups = jz4775_pull_ups, 1734 .pull_downs = jz4775_pull_downs, 1735 }; 1736 1737 static const u32 jz4780_pull_ups[6] = { 1738 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f, 1739 }; 1740 1741 static const u32 jz4780_pull_downs[6] = { 1742 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 1743 }; 1744 1745 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; 1746 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; 1747 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; 1748 static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, }; 1749 static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, }; 1750 static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, }; 1751 static int jz4780_ssi0_dt_b_pins[] = { 0x3d, }; 1752 static int jz4780_ssi0_dt_d_pins[] = { 0x79, }; 1753 static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, }; 1754 static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, }; 1755 static int jz4780_ssi0_dr_b_pins[] = { 0x34, }; 1756 static int jz4780_ssi0_dr_d_pins[] = { 0x74, }; 1757 static int jz4780_ssi0_clk_a_pins[] = { 0x12, }; 1758 static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, }; 1759 static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, }; 1760 static int jz4780_ssi0_clk_d_pins[] = { 0x78, }; 1761 static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, }; 1762 static int jz4780_ssi0_gpc_d_pins[] = { 0x76, }; 1763 static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, }; 1764 static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, }; 1765 static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, }; 1766 static int jz4780_ssi0_ce0_d_pins[] = { 0x77, }; 1767 static int jz4780_ssi0_ce1_b_pins[] = { 0x35, }; 1768 static int jz4780_ssi0_ce1_d_pins[] = { 0x75, }; 1769 static int jz4780_ssi1_dt_b_pins[] = { 0x3d, }; 1770 static int jz4780_ssi1_dt_d_pins[] = { 0x79, }; 1771 static int jz4780_ssi1_dr_b_pins[] = { 0x34, }; 1772 static int jz4780_ssi1_dr_d_pins[] = { 0x74, }; 1773 static int jz4780_ssi1_clk_b_pins[] = { 0x3c, }; 1774 static int jz4780_ssi1_clk_d_pins[] = { 0x78, }; 1775 static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, }; 1776 static int jz4780_ssi1_gpc_d_pins[] = { 0x76, }; 1777 static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, }; 1778 static int jz4780_ssi1_ce0_d_pins[] = { 0x77, }; 1779 static int jz4780_ssi1_ce1_b_pins[] = { 0x35, }; 1780 static int jz4780_ssi1_ce1_d_pins[] = { 0x75, }; 1781 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; 1782 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; 1783 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; 1784 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; 1785 static int jz4780_i2s_data_tx_pins[] = { 0x87, }; 1786 static int jz4780_i2s_data_rx_pins[] = { 0x86, }; 1787 static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, }; 1788 static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, }; 1789 static int jz4780_i2s_sysclk_pins[] = { 0x85, }; 1790 static int jz4780_dmic_pins[] = { 0x32, 0x33, }; 1791 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; 1792 1793 static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, }; 1794 1795 static const struct group_desc jz4780_groups[] = { 1796 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 1797 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 1798 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 1799 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 1800 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1), 1801 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1), 1802 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 1803 jz4760_uart3_data_funcs), 1804 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 1805 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2), 1806 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2), 1807 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2), 1808 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2), 1809 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1), 1810 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1), 1811 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 1812 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2), 1813 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2), 1814 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1), 1815 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1), 1816 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 1817 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2), 1818 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1), 1819 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1), 1820 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1), 1821 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 1822 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1), 1823 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1), 1824 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 1825 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2), 1826 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2), 1827 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1), 1828 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1), 1829 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 1830 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1), 1831 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1), 1832 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 1833 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2), 1834 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2), 1835 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 1836 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2), 1837 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2), 1838 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 1839 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2), 1840 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2), 1841 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 1842 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2), 1843 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2), 1844 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 1845 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2), 1846 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2), 1847 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 1848 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2), 1849 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2), 1850 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 1851 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 1852 jz4760_mmc0_1bit_a_funcs), 1853 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 1854 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1), 1855 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 1856 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 1857 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 1858 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 1859 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 1860 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 1861 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 1862 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 1863 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 1864 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 1865 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0), 1866 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 1867 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 1868 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 1869 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 1870 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 1871 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 1872 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 1873 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 1874 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 1875 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 1876 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 1877 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 1878 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 1879 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 1880 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1), 1881 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1), 1882 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1), 1883 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0), 1884 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0), 1885 INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx, 1886 jz4780_i2s_clk_txrx_funcs), 1887 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1), 1888 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2), 1889 INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1), 1890 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0), 1891 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0), 1892 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 1893 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), 1894 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), 1895 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), 1896 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 1897 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), 1898 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), 1899 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 1900 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 1901 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 1902 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 1903 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 1904 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 1905 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 1906 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 1907 }; 1908 1909 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1910 static const char *jz4780_uart4_groups[] = { "uart4-data", }; 1911 static const char *jz4780_ssi0_groups[] = { 1912 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1913 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1914 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e", 1915 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1916 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1917 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1918 }; 1919 static const char *jz4780_ssi1_groups[] = { 1920 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1921 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1922 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1923 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1924 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1925 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1926 }; 1927 static const char *jz4780_mmc0_groups[] = { 1928 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1929 "mmc0-1bit-e", "mmc0-4bit-e", 1930 }; 1931 static const char *jz4780_mmc1_groups[] = { 1932 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e", 1933 }; 1934 static const char *jz4780_mmc2_groups[] = { 1935 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e", 1936 }; 1937 static const char *jz4780_nemc_groups[] = { 1938 "nemc-data", "nemc-cle-ale", "nemc-addr", 1939 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1940 }; 1941 static const char *jz4780_i2c3_groups[] = { "i2c3-data", }; 1942 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; 1943 static const char *jz4780_i2s_groups[] = { 1944 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 1945 }; 1946 static const char *jz4780_dmic_groups[] = { "dmic", }; 1947 static const char *jz4780_cim_groups[] = { "cim-data", }; 1948 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", }; 1949 1950 static const struct function_desc jz4780_functions[] = { 1951 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 1952 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 1953 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), }, 1954 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 1955 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), }, 1956 { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), }, 1957 { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), }, 1958 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), }, 1959 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), }, 1960 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), }, 1961 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), }, 1962 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1963 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1964 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1965 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1966 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1967 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1968 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1969 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1970 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1971 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), }, 1972 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), }, 1973 { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), }, 1974 { "dmic", jz4780_dmic_groups, ARRAY_SIZE(jz4780_dmic_groups), }, 1975 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), }, 1976 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1977 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1978 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1979 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1980 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1981 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1982 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1983 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1984 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1985 { "hdmi-ddc", jz4780_hdmi_ddc_groups, 1986 ARRAY_SIZE(jz4780_hdmi_ddc_groups), }, 1987 }; 1988 1989 static const struct ingenic_chip_info jz4780_chip_info = { 1990 .num_chips = 6, 1991 .reg_offset = 0x100, 1992 .version = ID_JZ4780, 1993 .groups = jz4780_groups, 1994 .num_groups = ARRAY_SIZE(jz4780_groups), 1995 .functions = jz4780_functions, 1996 .num_functions = ARRAY_SIZE(jz4780_functions), 1997 .pull_ups = jz4780_pull_ups, 1998 .pull_downs = jz4780_pull_downs, 1999 }; 2000 2001 static const u32 x1000_pull_ups[4] = { 2002 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, 2003 }; 2004 2005 static const u32 x1000_pull_downs[4] = { 2006 0x00000000, 0x02000000, 0x02000000, 0x00000000, 2007 }; 2008 2009 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; 2010 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 2011 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; 2012 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; 2013 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; 2014 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; 2015 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; 2016 static int x1000_sfc_data_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, }; 2017 static int x1000_sfc_clk_pins[] = { 0x1a, }; 2018 static int x1000_sfc_ce_pins[] = { 0x1b, }; 2019 static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; 2020 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; 2021 static int x1000_ssi_dt_d_pins[] = { 0x62, }; 2022 static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; 2023 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; 2024 static int x1000_ssi_dr_d_pins[] = { 0x63, }; 2025 static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; 2026 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; 2027 static int x1000_ssi_clk_d_pins[] = { 0x60, }; 2028 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; 2029 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; 2030 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; 2031 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; 2032 static int x1000_ssi_ce0_d_pins[] = { 0x61, }; 2033 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; 2034 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; 2035 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; 2036 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; 2037 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; 2038 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; 2039 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; 2040 static int x1000_emc_8bit_data_pins[] = { 2041 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2042 }; 2043 static int x1000_emc_16bit_data_pins[] = { 2044 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 2045 }; 2046 static int x1000_emc_addr_pins[] = { 2047 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2048 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 2049 }; 2050 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; 2051 static int x1000_emc_wait_pins[] = { 0x34, }; 2052 static int x1000_emc_cs1_pins[] = { 0x32, }; 2053 static int x1000_emc_cs2_pins[] = { 0x33, }; 2054 static int x1000_i2c0_pins[] = { 0x38, 0x37, }; 2055 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; 2056 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; 2057 static int x1000_i2c2_pins[] = { 0x61, 0x60, }; 2058 static int x1000_i2s_data_tx_pins[] = { 0x24, }; 2059 static int x1000_i2s_data_rx_pins[] = { 0x23, }; 2060 static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 2061 static int x1000_i2s_sysclk_pins[] = { 0x20, }; 2062 static int x1000_dmic_if0_pins[] = { 0x35, 0x36, }; 2063 static int x1000_dmic_if1_pins[] = { 0x25, }; 2064 static int x1000_cim_pins[] = { 2065 0x08, 0x09, 0x0a, 0x0b, 2066 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 2067 }; 2068 static int x1000_lcd_8bit_pins[] = { 2069 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2070 0x30, 0x31, 0x32, 0x33, 0x34, 2071 }; 2072 static int x1000_lcd_16bit_pins[] = { 2073 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 2074 }; 2075 static int x1000_pwm_pwm0_pins[] = { 0x59, }; 2076 static int x1000_pwm_pwm1_pins[] = { 0x5a, }; 2077 static int x1000_pwm_pwm2_pins[] = { 0x5b, }; 2078 static int x1000_pwm_pwm3_pins[] = { 0x26, }; 2079 static int x1000_pwm_pwm4_pins[] = { 0x58, }; 2080 static int x1000_mac_pins[] = { 2081 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, 2082 }; 2083 2084 static const struct group_desc x1000_groups[] = { 2085 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0), 2086 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0), 2087 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2), 2088 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1), 2089 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1), 2090 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2), 2091 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0), 2092 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1), 2093 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1), 2094 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1), 2095 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2), 2096 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2), 2097 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0), 2098 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2), 2099 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2), 2100 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0), 2101 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2), 2102 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2), 2103 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0), 2104 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2), 2105 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2), 2106 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2), 2107 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2), 2108 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0), 2109 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2), 2110 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2), 2111 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1), 2112 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1), 2113 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1), 2114 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0), 2115 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0), 2116 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0), 2117 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0), 2118 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0), 2119 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0), 2120 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0), 2121 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0), 2122 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0), 2123 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0), 2124 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2), 2125 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0), 2126 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1), 2127 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1), 2128 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1), 2129 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1), 2130 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1), 2131 INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0), 2132 INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1), 2133 INGENIC_PIN_GROUP("cim-data", x1000_cim, 2), 2134 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1), 2135 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1), 2136 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0), 2137 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1), 2138 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1), 2139 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2), 2140 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0), 2141 INGENIC_PIN_GROUP("mac", x1000_mac, 1), 2142 }; 2143 2144 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2145 static const char *x1000_uart1_groups[] = { 2146 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 2147 }; 2148 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 2149 static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", }; 2150 static const char *x1000_ssi_groups[] = { 2151 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", 2152 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", 2153 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d", 2154 "ssi-gpc-a-20", "ssi-gpc-a-31", 2155 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d", 2156 "ssi-ce1-a-21", "ssi-ce1-a-30", 2157 }; 2158 static const char *x1000_mmc0_groups[] = { 2159 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 2160 }; 2161 static const char *x1000_mmc1_groups[] = { 2162 "mmc1-1bit", "mmc1-4bit", 2163 }; 2164 static const char *x1000_emc_groups[] = { 2165 "emc-8bit-data", "emc-16bit-data", 2166 "emc-addr", "emc-rd-we", "emc-wait", 2167 }; 2168 static const char *x1000_cs1_groups[] = { "emc-cs1", }; 2169 static const char *x1000_cs2_groups[] = { "emc-cs2", }; 2170 static const char *x1000_i2c0_groups[] = { "i2c0-data", }; 2171 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 2172 static const char *x1000_i2c2_groups[] = { "i2c2-data", }; 2173 static const char *x1000_i2s_groups[] = { 2174 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 2175 }; 2176 static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", }; 2177 static const char *x1000_cim_groups[] = { "cim-data", }; 2178 static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", }; 2179 static const char *x1000_pwm0_groups[] = { "pwm0", }; 2180 static const char *x1000_pwm1_groups[] = { "pwm1", }; 2181 static const char *x1000_pwm2_groups[] = { "pwm2", }; 2182 static const char *x1000_pwm3_groups[] = { "pwm3", }; 2183 static const char *x1000_pwm4_groups[] = { "pwm4", }; 2184 static const char *x1000_mac_groups[] = { "mac", }; 2185 2186 static const struct function_desc x1000_functions[] = { 2187 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, 2188 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, 2189 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, 2190 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 2191 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), }, 2192 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, 2193 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, 2194 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, 2195 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, 2196 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, 2197 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, 2198 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, 2199 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, 2200 { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), }, 2201 { "dmic", x1000_dmic_groups, ARRAY_SIZE(x1000_dmic_groups), }, 2202 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, 2203 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, 2204 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, 2205 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), }, 2206 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), }, 2207 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), }, 2208 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), }, 2209 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, 2210 }; 2211 2212 static const struct regmap_range x1000_access_ranges[] = { 2213 regmap_reg_range(0x000, 0x400 - 4), 2214 regmap_reg_range(0x700, 0x800 - 4), 2215 }; 2216 2217 /* shared with X1500 */ 2218 static const struct regmap_access_table x1000_access_table = { 2219 .yes_ranges = x1000_access_ranges, 2220 .n_yes_ranges = ARRAY_SIZE(x1000_access_ranges), 2221 }; 2222 2223 static const struct ingenic_chip_info x1000_chip_info = { 2224 .num_chips = 4, 2225 .reg_offset = 0x100, 2226 .version = ID_X1000, 2227 .groups = x1000_groups, 2228 .num_groups = ARRAY_SIZE(x1000_groups), 2229 .functions = x1000_functions, 2230 .num_functions = ARRAY_SIZE(x1000_functions), 2231 .pull_ups = x1000_pull_ups, 2232 .pull_downs = x1000_pull_downs, 2233 .access_table = &x1000_access_table, 2234 }; 2235 2236 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; 2237 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 2238 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; 2239 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; 2240 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; 2241 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; 2242 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; 2243 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; 2244 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; 2245 static int x1500_i2c0_pins[] = { 0x38, 0x37, }; 2246 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; 2247 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; 2248 static int x1500_i2c2_pins[] = { 0x61, 0x60, }; 2249 static int x1500_i2s_data_tx_pins[] = { 0x24, }; 2250 static int x1500_i2s_data_rx_pins[] = { 0x23, }; 2251 static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 2252 static int x1500_i2s_sysclk_pins[] = { 0x20, }; 2253 static int x1500_dmic_if0_pins[] = { 0x35, 0x36, }; 2254 static int x1500_dmic_if1_pins[] = { 0x25, }; 2255 static int x1500_cim_pins[] = { 2256 0x08, 0x09, 0x0a, 0x0b, 2257 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 2258 }; 2259 static int x1500_pwm_pwm0_pins[] = { 0x59, }; 2260 static int x1500_pwm_pwm1_pins[] = { 0x5a, }; 2261 static int x1500_pwm_pwm2_pins[] = { 0x5b, }; 2262 static int x1500_pwm_pwm3_pins[] = { 0x26, }; 2263 static int x1500_pwm_pwm4_pins[] = { 0x58, }; 2264 2265 static const struct group_desc x1500_groups[] = { 2266 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0), 2267 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0), 2268 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2), 2269 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1), 2270 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1), 2271 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2), 2272 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0), 2273 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1), 2274 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1), 2275 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1), 2276 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1), 2277 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1), 2278 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0), 2279 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2), 2280 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0), 2281 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1), 2282 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1), 2283 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1), 2284 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1), 2285 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1), 2286 INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0), 2287 INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1), 2288 INGENIC_PIN_GROUP("cim-data", x1500_cim, 2), 2289 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0), 2290 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1), 2291 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1), 2292 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2), 2293 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0), 2294 }; 2295 2296 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2297 static const char *x1500_uart1_groups[] = { 2298 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 2299 }; 2300 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 2301 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 2302 static const char *x1500_i2c0_groups[] = { "i2c0-data", }; 2303 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 2304 static const char *x1500_i2c2_groups[] = { "i2c2-data", }; 2305 static const char *x1500_i2s_groups[] = { 2306 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 2307 }; 2308 static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", }; 2309 static const char *x1500_cim_groups[] = { "cim-data", }; 2310 static const char *x1500_pwm0_groups[] = { "pwm0", }; 2311 static const char *x1500_pwm1_groups[] = { "pwm1", }; 2312 static const char *x1500_pwm2_groups[] = { "pwm2", }; 2313 static const char *x1500_pwm3_groups[] = { "pwm3", }; 2314 static const char *x1500_pwm4_groups[] = { "pwm4", }; 2315 2316 static const struct function_desc x1500_functions[] = { 2317 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, 2318 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, 2319 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, 2320 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 2321 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, 2322 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, 2323 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, 2324 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, 2325 { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), }, 2326 { "dmic", x1500_dmic_groups, ARRAY_SIZE(x1500_dmic_groups), }, 2327 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, 2328 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, 2329 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, 2330 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, 2331 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), }, 2332 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), }, 2333 }; 2334 2335 static const struct ingenic_chip_info x1500_chip_info = { 2336 .num_chips = 4, 2337 .reg_offset = 0x100, 2338 .version = ID_X1500, 2339 .groups = x1500_groups, 2340 .num_groups = ARRAY_SIZE(x1500_groups), 2341 .functions = x1500_functions, 2342 .num_functions = ARRAY_SIZE(x1500_functions), 2343 .pull_ups = x1000_pull_ups, 2344 .pull_downs = x1000_pull_downs, 2345 .access_table = &x1000_access_table, 2346 }; 2347 2348 static const u32 x1830_pull_ups[4] = { 2349 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 2350 }; 2351 2352 static const u32 x1830_pull_downs[4] = { 2353 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 2354 }; 2355 2356 static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; 2357 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; 2358 static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; 2359 static int x1830_sfc_data_pins[] = { 0x17, 0x18, 0x1a, 0x19, }; 2360 static int x1830_sfc_clk_pins[] = { 0x1b, }; 2361 static int x1830_sfc_ce_pins[] = { 0x1c, }; 2362 static int x1830_ssi0_dt_pins[] = { 0x4c, }; 2363 static int x1830_ssi0_dr_pins[] = { 0x4b, }; 2364 static int x1830_ssi0_clk_pins[] = { 0x4f, }; 2365 static int x1830_ssi0_gpc_pins[] = { 0x4d, }; 2366 static int x1830_ssi0_ce0_pins[] = { 0x50, }; 2367 static int x1830_ssi0_ce1_pins[] = { 0x4e, }; 2368 static int x1830_ssi1_dt_c_pins[] = { 0x53, }; 2369 static int x1830_ssi1_dt_d_pins[] = { 0x62, }; 2370 static int x1830_ssi1_dr_c_pins[] = { 0x54, }; 2371 static int x1830_ssi1_dr_d_pins[] = { 0x63, }; 2372 static int x1830_ssi1_clk_c_pins[] = { 0x57, }; 2373 static int x1830_ssi1_clk_d_pins[] = { 0x66, }; 2374 static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; 2375 static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; 2376 static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; 2377 static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; 2378 static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; 2379 static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; 2380 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; 2381 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; 2382 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; 2383 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; 2384 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; 2385 static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; 2386 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; 2387 static int x1830_i2s_data_tx_pins[] = { 0x53, }; 2388 static int x1830_i2s_data_rx_pins[] = { 0x54, }; 2389 static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, }; 2390 static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, }; 2391 static int x1830_i2s_sysclk_pins[] = { 0x57, }; 2392 static int x1830_dmic_if0_pins[] = { 0x48, 0x59, }; 2393 static int x1830_dmic_if1_pins[] = { 0x5a, }; 2394 static int x1830_lcd_tft_8bit_pins[] = { 2395 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 2396 0x68, 0x73, 0x72, 0x69, 2397 }; 2398 static int x1830_lcd_tft_24bit_pins[] = { 2399 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 2400 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 2401 }; 2402 static int x1830_lcd_slcd_8bit_pins[] = { 2403 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d, 2404 0x69, 0x72, 0x73, 0x7b, 0x7a, 2405 }; 2406 static int x1830_lcd_slcd_16bit_pins[] = { 2407 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79, 2408 }; 2409 static int x1830_pwm_pwm0_b_pins[] = { 0x31, }; 2410 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, }; 2411 static int x1830_pwm_pwm1_b_pins[] = { 0x32, }; 2412 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, }; 2413 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, }; 2414 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, }; 2415 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, }; 2416 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, }; 2417 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, }; 2418 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, }; 2419 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, }; 2420 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, }; 2421 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, }; 2422 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, }; 2423 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, }; 2424 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, }; 2425 static int x1830_mac_pins[] = { 2426 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, 2427 }; 2428 2429 static const struct group_desc x1830_groups[] = { 2430 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0), 2431 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0), 2432 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0), 2433 INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1), 2434 INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1), 2435 INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1), 2436 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0), 2437 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0), 2438 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0), 2439 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0), 2440 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0), 2441 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0), 2442 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1), 2443 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1), 2444 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1), 2445 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1), 2446 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1), 2447 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1), 2448 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2), 2449 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2), 2450 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2), 2451 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2), 2452 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2), 2453 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2), 2454 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0), 2455 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0), 2456 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0), 2457 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0), 2458 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1), 2459 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0), 2460 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1), 2461 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0), 2462 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0), 2463 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0), 2464 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0), 2465 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0), 2466 INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2), 2467 INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2), 2468 INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0), 2469 INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0), 2470 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1), 2471 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1), 2472 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0), 2473 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1), 2474 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0), 2475 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1), 2476 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0), 2477 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1), 2478 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0), 2479 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1), 2480 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1), 2481 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0), 2482 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1), 2483 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0), 2484 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1), 2485 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0), 2486 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1), 2487 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0), 2488 INGENIC_PIN_GROUP("mac", x1830_mac, 0), 2489 }; 2490 2491 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2492 static const char *x1830_uart1_groups[] = { "uart1-data", }; 2493 static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", }; 2494 static const char *x1830_ssi0_groups[] = { 2495 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", 2496 }; 2497 static const char *x1830_ssi1_groups[] = { 2498 "ssi1-dt-c", "ssi1-dt-d", 2499 "ssi1-dr-c", "ssi1-dr-d", 2500 "ssi1-clk-c", "ssi1-clk-d", 2501 "ssi1-gpc-c", "ssi1-gpc-d", 2502 "ssi1-ce0-c", "ssi1-ce0-d", 2503 "ssi1-ce1-c", "ssi1-ce1-d", 2504 }; 2505 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 2506 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 2507 static const char *x1830_i2c0_groups[] = { "i2c0-data", }; 2508 static const char *x1830_i2c1_groups[] = { "i2c1-data", }; 2509 static const char *x1830_i2c2_groups[] = { "i2c2-data", }; 2510 static const char *x1830_i2s_groups[] = { 2511 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 2512 }; 2513 static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", }; 2514 static const char *x1830_lcd_groups[] = { 2515 "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit", 2516 }; 2517 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; 2518 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; 2519 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", }; 2520 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", }; 2521 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", }; 2522 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", }; 2523 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", }; 2524 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", }; 2525 static const char *x1830_mac_groups[] = { "mac", }; 2526 2527 static const struct function_desc x1830_functions[] = { 2528 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), }, 2529 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), }, 2530 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), }, 2531 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), }, 2532 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), }, 2533 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), }, 2534 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), }, 2535 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, 2536 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, 2537 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, 2538 { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), }, 2539 { "dmic", x1830_dmic_groups, ARRAY_SIZE(x1830_dmic_groups), }, 2540 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), }, 2541 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, 2542 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, 2543 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), }, 2544 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), }, 2545 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2546 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2547 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2548 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2549 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, 2550 }; 2551 2552 static const struct regmap_range x1830_access_ranges[] = { 2553 regmap_reg_range(0x0000, 0x4000 - 4), 2554 regmap_reg_range(0x7000, 0x8000 - 4), 2555 }; 2556 2557 static const struct regmap_access_table x1830_access_table = { 2558 .yes_ranges = x1830_access_ranges, 2559 .n_yes_ranges = ARRAY_SIZE(x1830_access_ranges), 2560 }; 2561 2562 static const struct ingenic_chip_info x1830_chip_info = { 2563 .num_chips = 4, 2564 .reg_offset = 0x1000, 2565 .version = ID_X1830, 2566 .groups = x1830_groups, 2567 .num_groups = ARRAY_SIZE(x1830_groups), 2568 .functions = x1830_functions, 2569 .num_functions = ARRAY_SIZE(x1830_functions), 2570 .pull_ups = x1830_pull_ups, 2571 .pull_downs = x1830_pull_downs, 2572 .access_table = &x1830_access_table, 2573 }; 2574 2575 static const u32 x2000_pull_ups[5] = { 2576 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f, 2577 }; 2578 2579 static const u32 x2000_pull_downs[5] = { 2580 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f, 2581 }; 2582 2583 static int x2000_uart0_data_pins[] = { 0x77, 0x78, }; 2584 static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, }; 2585 static int x2000_uart1_data_pins[] = { 0x57, 0x58, }; 2586 static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, }; 2587 static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, }; 2588 static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, }; 2589 static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, }; 2590 static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, }; 2591 static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, }; 2592 static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, }; 2593 static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, }; 2594 static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, }; 2595 static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, }; 2596 static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, }; 2597 static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, }; 2598 static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, }; 2599 static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, }; 2600 static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, }; 2601 static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, }; 2602 static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, }; 2603 static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, }; 2604 static int x2000_sfc_data_if0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, }; 2605 static int x2000_sfc_data_if0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, }; 2606 static int x2000_sfc_data_if1_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; 2607 static int x2000_sfc_clk_d_pins[] = { 0x71, }; 2608 static int x2000_sfc_clk_e_pins[] = { 0x90, }; 2609 static int x2000_sfc_ce_d_pins[] = { 0x72, }; 2610 static int x2000_sfc_ce_e_pins[] = { 0x91, }; 2611 static int x2000_ssi0_dt_b_pins[] = { 0x3e, }; 2612 static int x2000_ssi0_dt_d_pins[] = { 0x69, }; 2613 static int x2000_ssi0_dr_b_pins[] = { 0x3d, }; 2614 static int x2000_ssi0_dr_d_pins[] = { 0x6a, }; 2615 static int x2000_ssi0_clk_b_pins[] = { 0x3f, }; 2616 static int x2000_ssi0_clk_d_pins[] = { 0x68, }; 2617 static int x2000_ssi0_ce_b_pins[] = { 0x3c, }; 2618 static int x2000_ssi0_ce_d_pins[] = { 0x6d, }; 2619 static int x2000_ssi1_dt_c_pins[] = { 0x4b, }; 2620 static int x2000_ssi1_dt_d_pins[] = { 0x72, }; 2621 static int x2000_ssi1_dt_e_pins[] = { 0x91, }; 2622 static int x2000_ssi1_dr_c_pins[] = { 0x4a, }; 2623 static int x2000_ssi1_dr_d_pins[] = { 0x73, }; 2624 static int x2000_ssi1_dr_e_pins[] = { 0x92, }; 2625 static int x2000_ssi1_clk_c_pins[] = { 0x4c, }; 2626 static int x2000_ssi1_clk_d_pins[] = { 0x71, }; 2627 static int x2000_ssi1_clk_e_pins[] = { 0x90, }; 2628 static int x2000_ssi1_ce_c_pins[] = { 0x49, }; 2629 static int x2000_ssi1_ce_d_pins[] = { 0x76, }; 2630 static int x2000_ssi1_ce_e_pins[] = { 0x95, }; 2631 static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, }; 2632 static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, }; 2633 static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; 2634 static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, }; 2635 static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 2636 static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, }; 2637 static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, }; 2638 static int x2000_emc_8bit_data_pins[] = { 2639 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 2640 }; 2641 static int x2000_emc_16bit_data_pins[] = { 2642 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 2643 }; 2644 static int x2000_emc_addr_pins[] = { 2645 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2646 0x28, 0x29, 0x2a, 0x2b, 0x2c, 2647 }; 2648 static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, }; 2649 static int x2000_emc_wait_pins[] = { 0x2f, }; 2650 static int x2000_emc_cs1_pins[] = { 0x57, }; 2651 static int x2000_emc_cs2_pins[] = { 0x58, }; 2652 static int x2000_i2c0_pins[] = { 0x4e, 0x4d, }; 2653 static int x2000_i2c1_c_pins[] = { 0x58, 0x57, }; 2654 static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, }; 2655 static int x2000_i2c2_b_pins[] = { 0x37, 0x36, }; 2656 static int x2000_i2c2_d_pins[] = { 0x75, 0x74, }; 2657 static int x2000_i2c2_e_pins[] = { 0x94, 0x93, }; 2658 static int x2000_i2c3_a_pins[] = { 0x11, 0x10, }; 2659 static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, }; 2660 static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, }; 2661 static int x2000_i2c4_d_pins[] = { 0x61, 0x60, }; 2662 static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, }; 2663 static int x2000_i2c5_d_pins[] = { 0x65, 0x64, }; 2664 static int x2000_i2s1_data_tx_pins[] = { 0x47, }; 2665 static int x2000_i2s1_data_rx_pins[] = { 0x44, }; 2666 static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, }; 2667 static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, }; 2668 static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, }; 2669 static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, }; 2670 static int x2000_i2s2_data_rx0_pins[] = { 0x0a, }; 2671 static int x2000_i2s2_data_rx1_pins[] = { 0x0b, }; 2672 static int x2000_i2s2_data_rx2_pins[] = { 0x0c, }; 2673 static int x2000_i2s2_data_rx3_pins[] = { 0x0d, }; 2674 static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, }; 2675 static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, }; 2676 static int x2000_i2s3_data_tx0_pins[] = { 0x03, }; 2677 static int x2000_i2s3_data_tx1_pins[] = { 0x04, }; 2678 static int x2000_i2s3_data_tx2_pins[] = { 0x05, }; 2679 static int x2000_i2s3_data_tx3_pins[] = { 0x06, }; 2680 static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, }; 2681 static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, }; 2682 static int x2000_dmic_if0_pins[] = { 0x54, 0x55, }; 2683 static int x2000_dmic_if1_pins[] = { 0x56, }; 2684 static int x2000_dmic_if2_pins[] = { 0x57, }; 2685 static int x2000_dmic_if3_pins[] = { 0x58, }; 2686 static int x2000_cim_8bit_pins[] = { 2687 0x0e, 0x0c, 0x0d, 0x4f, 2688 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2689 }; 2690 static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, }; 2691 static int x2000_lcd_tft_8bit_pins[] = { 2692 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2693 0x38, 0x3a, 0x39, 0x3b, 2694 }; 2695 static int x2000_lcd_tft_16bit_pins[] = { 2696 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 2697 }; 2698 static int x2000_lcd_tft_18bit_pins[] = { 2699 0x30, 0x31, 2700 }; 2701 static int x2000_lcd_tft_24bit_pins[] = { 2702 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 2703 }; 2704 static int x2000_lcd_slcd_8bit_pins[] = { 2705 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2706 0x3a, 0x38, 0x3b, 0x30, 0x39, 2707 }; 2708 static int x2000_pwm_pwm0_c_pins[] = { 0x40, }; 2709 static int x2000_pwm_pwm0_d_pins[] = { 0x7e, }; 2710 static int x2000_pwm_pwm1_c_pins[] = { 0x41, }; 2711 static int x2000_pwm_pwm1_d_pins[] = { 0x7f, }; 2712 static int x2000_pwm_pwm2_c_pins[] = { 0x42, }; 2713 static int x2000_pwm_pwm2_e_pins[] = { 0x80, }; 2714 static int x2000_pwm_pwm3_c_pins[] = { 0x43, }; 2715 static int x2000_pwm_pwm3_e_pins[] = { 0x81, }; 2716 static int x2000_pwm_pwm4_c_pins[] = { 0x44, }; 2717 static int x2000_pwm_pwm4_e_pins[] = { 0x82, }; 2718 static int x2000_pwm_pwm5_c_pins[] = { 0x45, }; 2719 static int x2000_pwm_pwm5_e_pins[] = { 0x83, }; 2720 static int x2000_pwm_pwm6_c_pins[] = { 0x46, }; 2721 static int x2000_pwm_pwm6_e_pins[] = { 0x84, }; 2722 static int x2000_pwm_pwm7_c_pins[] = { 0x47, }; 2723 static int x2000_pwm_pwm7_e_pins[] = { 0x85, }; 2724 static int x2000_pwm_pwm8_pins[] = { 0x48, }; 2725 static int x2000_pwm_pwm9_pins[] = { 0x49, }; 2726 static int x2000_pwm_pwm10_pins[] = { 0x4a, }; 2727 static int x2000_pwm_pwm11_pins[] = { 0x4b, }; 2728 static int x2000_pwm_pwm12_pins[] = { 0x4c, }; 2729 static int x2000_pwm_pwm13_pins[] = { 0x4d, }; 2730 static int x2000_pwm_pwm14_pins[] = { 0x4e, }; 2731 static int x2000_pwm_pwm15_pins[] = { 0x4f, }; 2732 static int x2000_mac0_rmii_pins[] = { 2733 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41, 2734 }; 2735 static int x2000_mac0_rgmii_pins[] = { 2736 0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42, 2737 0x4c, 0x4d, 0x4f, 0x4e, 0x41, 2738 }; 2739 static int x2000_mac1_rmii_pins[] = { 2740 0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37, 2741 }; 2742 static int x2000_mac1_rgmii_pins[] = { 2743 0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28, 2744 0x33, 0x34, 0x36, 0x35, 0x37, 2745 }; 2746 static int x2000_otg_pins[] = { 0x96, }; 2747 2748 static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, }; 2749 2750 static const struct group_desc x2000_groups[] = { 2751 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2), 2752 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2), 2753 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1), 2754 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1), 2755 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0), 2756 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0), 2757 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1), 2758 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0), 2759 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1), 2760 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1), 2761 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3), 2762 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1), 2763 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3), 2764 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1), 2765 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3), 2766 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1), 2767 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3), 2768 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1), 2769 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3), 2770 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3), 2771 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3), 2772 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1), 2773 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0), 2774 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1), 2775 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1), 2776 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0), 2777 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1), 2778 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0), 2779 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1), 2780 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1), 2781 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1), 2782 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1), 2783 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1), 2784 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1), 2785 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1), 2786 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1), 2787 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2), 2788 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2), 2789 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1), 2790 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2), 2791 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2), 2792 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1), 2793 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2), 2794 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2), 2795 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1), 2796 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2), 2797 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2), 2798 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1), 2799 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0), 2800 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0), 2801 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0), 2802 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0), 2803 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0), 2804 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0), 2805 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0), 2806 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0), 2807 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0), 2808 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0), 2809 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0), 2810 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0), 2811 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3), 2812 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3), 2813 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3), 2814 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2), 2815 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1), 2816 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2), 2817 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2), 2818 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1), 2819 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0), 2820 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1), 2821 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1), 2822 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2), 2823 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1), 2824 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1), 2825 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2), 2826 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2), 2827 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2), 2828 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2), 2829 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2), 2830 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2), 2831 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2), 2832 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2), 2833 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2), 2834 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2), 2835 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2), 2836 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2), 2837 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2), 2838 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2), 2839 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2), 2840 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2), 2841 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2), 2842 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2), 2843 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0), 2844 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0), 2845 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0), 2846 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0), 2847 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit, 2848 x2000_cim_8bit_funcs), 2849 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0), 2850 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1), 2851 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1), 2852 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1), 2853 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1), 2854 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2), 2855 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2), 2856 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0), 2857 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2), 2858 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0), 2859 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2), 2860 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0), 2861 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1), 2862 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0), 2863 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1), 2864 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0), 2865 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1), 2866 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0), 2867 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1), 2868 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0), 2869 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1), 2870 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0), 2871 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1), 2872 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0), 2873 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0), 2874 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0), 2875 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0), 2876 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0), 2877 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0), 2878 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0), 2879 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0), 2880 INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1), 2881 INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1), 2882 INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3), 2883 INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3), 2884 INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0), 2885 }; 2886 2887 static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2888 static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 2889 static const char *x2000_uart2_groups[] = { "uart2-data", }; 2890 static const char *x2000_uart3_groups[] = { 2891 "uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d", 2892 }; 2893 static const char *x2000_uart4_groups[] = { 2894 "uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c", 2895 }; 2896 static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", }; 2897 static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", }; 2898 static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", }; 2899 static const char *x2000_uart8_groups[] = { "uart8-data", }; 2900 static const char *x2000_uart9_groups[] = { "uart9-data", }; 2901 static const char *x2000_sfc_groups[] = { 2902 "sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1", 2903 "sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e", 2904 }; 2905 static const char *x2000_ssi0_groups[] = { 2906 "ssi0-dt-b", "ssi0-dt-d", 2907 "ssi0-dr-b", "ssi0-dr-d", 2908 "ssi0-clk-b", "ssi0-clk-d", 2909 "ssi0-ce-b", "ssi0-ce-d", 2910 }; 2911 static const char *x2000_ssi1_groups[] = { 2912 "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e", 2913 "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e", 2914 "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e", 2915 "ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e", 2916 }; 2917 static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", }; 2918 static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 2919 static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", }; 2920 static const char *x2000_emc_groups[] = { 2921 "emc-8bit-data", "emc-16bit-data", 2922 "emc-addr", "emc-rd-we", "emc-wait", 2923 }; 2924 static const char *x2000_cs1_groups[] = { "emc-cs1", }; 2925 static const char *x2000_cs2_groups[] = { "emc-cs2", }; 2926 static const char *x2000_i2c0_groups[] = { "i2c0-data", }; 2927 static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", }; 2928 static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", }; 2929 static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", }; 2930 static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", }; 2931 static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", }; 2932 static const char *x2000_i2s1_groups[] = { 2933 "i2s1-data-tx", "i2s1-data-rx", 2934 "i2s1-clk-tx", "i2s1-clk-rx", 2935 "i2s1-sysclk-tx", "i2s1-sysclk-rx", 2936 }; 2937 static const char *x2000_i2s2_groups[] = { 2938 "i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3", 2939 "i2s2-clk-rx", "i2s2-sysclk-rx", 2940 }; 2941 static const char *x2000_i2s3_groups[] = { 2942 "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3", 2943 "i2s3-clk-tx", "i2s3-sysclk-tx", 2944 }; 2945 static const char *x2000_dmic_groups[] = { 2946 "dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3", 2947 }; 2948 static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 2949 static const char *x2000_lcd_groups[] = { 2950 "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit", 2951 "lcd-slcd-8bit", "lcd-slcd-16bit", 2952 }; 2953 static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", }; 2954 static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", }; 2955 static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", }; 2956 static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", }; 2957 static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", }; 2958 static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", }; 2959 static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", }; 2960 static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", }; 2961 static const char *x2000_pwm8_groups[] = { "pwm8", }; 2962 static const char *x2000_pwm9_groups[] = { "pwm9", }; 2963 static const char *x2000_pwm10_groups[] = { "pwm10", }; 2964 static const char *x2000_pwm11_groups[] = { "pwm11", }; 2965 static const char *x2000_pwm12_groups[] = { "pwm12", }; 2966 static const char *x2000_pwm13_groups[] = { "pwm13", }; 2967 static const char *x2000_pwm14_groups[] = { "pwm14", }; 2968 static const char *x2000_pwm15_groups[] = { "pwm15", }; 2969 static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", }; 2970 static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", }; 2971 static const char *x2000_otg_groups[] = { "otg-vbus", }; 2972 2973 static const struct function_desc x2000_functions[] = { 2974 { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), }, 2975 { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), }, 2976 { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), }, 2977 { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), }, 2978 { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), }, 2979 { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), }, 2980 { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), }, 2981 { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), }, 2982 { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), }, 2983 { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), }, 2984 { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), }, 2985 { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), }, 2986 { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), }, 2987 { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), }, 2988 { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), }, 2989 { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), }, 2990 { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), }, 2991 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), }, 2992 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), }, 2993 { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), }, 2994 { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), }, 2995 { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), }, 2996 { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), }, 2997 { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), }, 2998 { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), }, 2999 { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), }, 3000 { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), }, 3001 { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), }, 3002 { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), }, 3003 { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), }, 3004 { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), }, 3005 { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), }, 3006 { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), }, 3007 { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), }, 3008 { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), }, 3009 { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), }, 3010 { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), }, 3011 { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), }, 3012 { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), }, 3013 { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), }, 3014 { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), }, 3015 { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), }, 3016 { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), }, 3017 { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), }, 3018 { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), }, 3019 { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), }, 3020 { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), }, 3021 { "mac0", x2000_mac0_groups, ARRAY_SIZE(x2000_mac0_groups), }, 3022 { "mac1", x2000_mac1_groups, ARRAY_SIZE(x2000_mac1_groups), }, 3023 { "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), }, 3024 }; 3025 3026 static const struct regmap_range x2000_access_ranges[] = { 3027 regmap_reg_range(0x000, 0x500 - 4), 3028 regmap_reg_range(0x700, 0x800 - 4), 3029 }; 3030 3031 /* shared with X2100 */ 3032 static const struct regmap_access_table x2000_access_table = { 3033 .yes_ranges = x2000_access_ranges, 3034 .n_yes_ranges = ARRAY_SIZE(x2000_access_ranges), 3035 }; 3036 3037 static const struct ingenic_chip_info x2000_chip_info = { 3038 .num_chips = 5, 3039 .reg_offset = 0x100, 3040 .version = ID_X2000, 3041 .groups = x2000_groups, 3042 .num_groups = ARRAY_SIZE(x2000_groups), 3043 .functions = x2000_functions, 3044 .num_functions = ARRAY_SIZE(x2000_functions), 3045 .pull_ups = x2000_pull_ups, 3046 .pull_downs = x2000_pull_downs, 3047 .access_table = &x2000_access_table, 3048 }; 3049 3050 static const u32 x2100_pull_ups[5] = { 3051 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x0fbf003f, 3052 }; 3053 3054 static const u32 x2100_pull_downs[5] = { 3055 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x0fbf003f, 3056 }; 3057 3058 static int x2100_mac_pins[] = { 3059 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4f, 0x41, 3060 }; 3061 3062 static const struct group_desc x2100_groups[] = { 3063 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2), 3064 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2), 3065 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1), 3066 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1), 3067 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0), 3068 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0), 3069 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1), 3070 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0), 3071 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1), 3072 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1), 3073 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3), 3074 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1), 3075 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3), 3076 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1), 3077 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3), 3078 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1), 3079 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3), 3080 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1), 3081 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3), 3082 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3), 3083 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3), 3084 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1), 3085 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0), 3086 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1), 3087 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1), 3088 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0), 3089 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1), 3090 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0), 3091 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1), 3092 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1), 3093 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1), 3094 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1), 3095 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1), 3096 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1), 3097 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1), 3098 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1), 3099 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2), 3100 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2), 3101 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1), 3102 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2), 3103 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2), 3104 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1), 3105 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2), 3106 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2), 3107 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1), 3108 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2), 3109 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2), 3110 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1), 3111 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0), 3112 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0), 3113 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0), 3114 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0), 3115 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0), 3116 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0), 3117 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0), 3118 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0), 3119 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0), 3120 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0), 3121 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0), 3122 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0), 3123 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3), 3124 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3), 3125 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3), 3126 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2), 3127 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1), 3128 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2), 3129 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2), 3130 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1), 3131 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0), 3132 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1), 3133 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1), 3134 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2), 3135 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1), 3136 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1), 3137 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2), 3138 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2), 3139 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2), 3140 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2), 3141 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2), 3142 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2), 3143 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2), 3144 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2), 3145 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2), 3146 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2), 3147 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2), 3148 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2), 3149 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2), 3150 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2), 3151 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2), 3152 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2), 3153 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2), 3154 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2), 3155 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0), 3156 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0), 3157 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0), 3158 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0), 3159 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit, 3160 x2000_cim_8bit_funcs), 3161 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0), 3162 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1), 3163 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1), 3164 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1), 3165 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1), 3166 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2), 3167 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2), 3168 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0), 3169 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2), 3170 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0), 3171 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2), 3172 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0), 3173 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1), 3174 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0), 3175 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1), 3176 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0), 3177 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1), 3178 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0), 3179 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1), 3180 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0), 3181 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1), 3182 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0), 3183 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1), 3184 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0), 3185 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0), 3186 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0), 3187 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0), 3188 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0), 3189 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0), 3190 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0), 3191 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0), 3192 INGENIC_PIN_GROUP("mac", x2100_mac, 1), 3193 }; 3194 3195 static const char *x2100_mac_groups[] = { "mac", }; 3196 3197 static const struct function_desc x2100_functions[] = { 3198 { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), }, 3199 { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), }, 3200 { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), }, 3201 { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), }, 3202 { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), }, 3203 { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), }, 3204 { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), }, 3205 { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), }, 3206 { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), }, 3207 { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), }, 3208 { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), }, 3209 { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), }, 3210 { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), }, 3211 { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), }, 3212 { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), }, 3213 { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), }, 3214 { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), }, 3215 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), }, 3216 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), }, 3217 { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), }, 3218 { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), }, 3219 { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), }, 3220 { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), }, 3221 { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), }, 3222 { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), }, 3223 { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), }, 3224 { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), }, 3225 { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), }, 3226 { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), }, 3227 { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), }, 3228 { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), }, 3229 { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), }, 3230 { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), }, 3231 { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), }, 3232 { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), }, 3233 { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), }, 3234 { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), }, 3235 { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), }, 3236 { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), }, 3237 { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), }, 3238 { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), }, 3239 { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), }, 3240 { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), }, 3241 { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), }, 3242 { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), }, 3243 { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), }, 3244 { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), }, 3245 { "mac", x2100_mac_groups, ARRAY_SIZE(x2100_mac_groups), }, 3246 }; 3247 3248 static const struct ingenic_chip_info x2100_chip_info = { 3249 .num_chips = 5, 3250 .reg_offset = 0x100, 3251 .version = ID_X2100, 3252 .groups = x2100_groups, 3253 .num_groups = ARRAY_SIZE(x2100_groups), 3254 .functions = x2100_functions, 3255 .num_functions = ARRAY_SIZE(x2100_functions), 3256 .pull_ups = x2100_pull_ups, 3257 .pull_downs = x2100_pull_downs, 3258 .access_table = &x2000_access_table, 3259 }; 3260 3261 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) 3262 { 3263 unsigned int val; 3264 3265 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); 3266 3267 return (u32) val; 3268 } 3269 3270 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, 3271 u8 reg, u8 offset, bool set) 3272 { 3273 if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) { 3274 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, 3275 BIT(offset), set ? BIT(offset) : 0); 3276 return; 3277 } 3278 3279 if (set) 3280 reg = REG_SET(reg); 3281 else 3282 reg = REG_CLEAR(reg); 3283 3284 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); 3285 } 3286 3287 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, 3288 u8 reg, u8 offset, bool set) 3289 { 3290 if (set) 3291 reg = REG_SET(reg); 3292 else 3293 reg = REG_CLEAR(reg); 3294 3295 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( 3296 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); 3297 } 3298 3299 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) 3300 { 3301 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( 3302 jzgc->jzpc->info->reg_offset), 3303 jzgc->gc.base / PINS_PER_GPIO_CHIP); 3304 } 3305 3306 static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc, 3307 u8 reg_upper, u8 reg_lower, u8 offset, u8 value) 3308 { 3309 /* 3310 * JZ4730 function and IRQ registers support two-bits-per-pin 3311 * definitions, split into two groups of 16. 3312 */ 3313 u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; 3314 unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG; 3315 unsigned int mask = GENMASK(1, 0) << idx * 2; 3316 3317 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2)); 3318 } 3319 3320 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, 3321 u8 offset) 3322 { 3323 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); 3324 3325 return !!(val & BIT(offset)); 3326 } 3327 3328 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, 3329 u8 offset, int value) 3330 { 3331 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3332 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value); 3333 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3334 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); 3335 else 3336 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value); 3337 } 3338 3339 static void irq_set_type(struct ingenic_gpio_chip *jzgc, 3340 u8 offset, unsigned int type) 3341 { 3342 u8 reg1, reg2; 3343 bool val1, val2, val3; 3344 3345 switch (type) { 3346 case IRQ_TYPE_EDGE_BOTH: 3347 val1 = val2 = false; 3348 val3 = true; 3349 break; 3350 case IRQ_TYPE_EDGE_RISING: 3351 val1 = val2 = true; 3352 val3 = false; 3353 break; 3354 case IRQ_TYPE_EDGE_FALLING: 3355 val1 = val3 = false; 3356 val2 = true; 3357 break; 3358 case IRQ_TYPE_LEVEL_HIGH: 3359 val1 = true; 3360 val2 = val3 = false; 3361 break; 3362 case IRQ_TYPE_LEVEL_LOW: 3363 default: 3364 val1 = val2 = val3 = false; 3365 break; 3366 } 3367 3368 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) { 3369 reg1 = JZ4770_GPIO_PAT1; 3370 reg2 = JZ4770_GPIO_PAT0; 3371 } else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) { 3372 reg1 = JZ4740_GPIO_TRIG; 3373 reg2 = JZ4740_GPIO_DIR; 3374 } else { 3375 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false); 3376 jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR, 3377 JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1); 3378 return; 3379 } 3380 3381 if (is_soc_or_above(jzgc->jzpc, ID_X2000)) { 3382 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 3383 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 3384 ingenic_gpio_shadow_set_bit_load(jzgc); 3385 ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3); 3386 } else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) { 3387 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 3388 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 3389 ingenic_gpio_shadow_set_bit_load(jzgc); 3390 } else { 3391 ingenic_gpio_set_bit(jzgc, reg2, offset, val1); 3392 ingenic_gpio_set_bit(jzgc, reg1, offset, val2); 3393 } 3394 } 3395 3396 static void ingenic_gpio_irq_mask(struct irq_data *irqd) 3397 { 3398 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3399 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3400 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3401 3402 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3403 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true); 3404 else 3405 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true); 3406 } 3407 3408 static void ingenic_gpio_irq_unmask(struct irq_data *irqd) 3409 { 3410 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3411 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3412 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3413 3414 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3415 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false); 3416 else 3417 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false); 3418 } 3419 3420 static void ingenic_gpio_irq_enable(struct irq_data *irqd) 3421 { 3422 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3423 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3424 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3425 3426 gpiochip_enable_irq(gc, irq); 3427 3428 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3429 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); 3430 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3431 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); 3432 else 3433 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true); 3434 3435 ingenic_gpio_irq_unmask(irqd); 3436 } 3437 3438 static void ingenic_gpio_irq_disable(struct irq_data *irqd) 3439 { 3440 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3441 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3442 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3443 3444 ingenic_gpio_irq_mask(irqd); 3445 3446 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3447 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false); 3448 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3449 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); 3450 else 3451 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false); 3452 3453 gpiochip_disable_irq(gc, irq); 3454 } 3455 3456 static void ingenic_gpio_irq_ack(struct irq_data *irqd) 3457 { 3458 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3459 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3460 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3461 bool high; 3462 3463 if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) && 3464 !is_soc_or_above(jzgc->jzpc, ID_X2000)) { 3465 /* 3466 * Switch to an interrupt for the opposite edge to the one that 3467 * triggered the interrupt being ACKed. 3468 */ 3469 high = ingenic_gpio_get_value(jzgc, irq); 3470 if (high) 3471 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW); 3472 else 3473 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH); 3474 } 3475 3476 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3477 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false); 3478 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3479 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); 3480 else 3481 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false); 3482 } 3483 3484 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 3485 { 3486 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3487 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3488 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3489 3490 switch (type) { 3491 case IRQ_TYPE_EDGE_BOTH: 3492 case IRQ_TYPE_EDGE_RISING: 3493 case IRQ_TYPE_EDGE_FALLING: 3494 irq_set_handler_locked(irqd, handle_edge_irq); 3495 break; 3496 case IRQ_TYPE_LEVEL_HIGH: 3497 case IRQ_TYPE_LEVEL_LOW: 3498 irq_set_handler_locked(irqd, handle_level_irq); 3499 break; 3500 default: 3501 irq_set_handler_locked(irqd, handle_bad_irq); 3502 } 3503 3504 if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) { 3505 /* 3506 * The hardware does not support interrupts on both edges. The 3507 * best we can do is to set up a single-edge interrupt and then 3508 * switch to the opposing edge when ACKing the interrupt. 3509 */ 3510 bool high = ingenic_gpio_get_value(jzgc, irq); 3511 3512 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH; 3513 } 3514 3515 irq_set_type(jzgc, irq, type); 3516 return 0; 3517 } 3518 3519 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on) 3520 { 3521 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3522 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3523 3524 return irq_set_irq_wake(jzgc->irq, on); 3525 } 3526 3527 static void ingenic_gpio_irq_handler(struct irq_desc *desc) 3528 { 3529 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 3530 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3531 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); 3532 unsigned long flag, i; 3533 3534 chained_irq_enter(irq_chip, desc); 3535 3536 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3537 flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG); 3538 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3539 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); 3540 else 3541 flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR); 3542 3543 for_each_set_bit(i, &flag, 32) 3544 generic_handle_domain_irq(gc->irq.domain, i); 3545 chained_irq_exit(irq_chip, desc); 3546 } 3547 3548 static void ingenic_gpio_set(struct gpio_chip *gc, 3549 unsigned int offset, int value) 3550 { 3551 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3552 3553 ingenic_gpio_set_value(jzgc, offset, value); 3554 } 3555 3556 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) 3557 { 3558 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3559 3560 return (int) ingenic_gpio_get_value(jzgc, offset); 3561 } 3562 3563 static int ingenic_gpio_direction_output(struct gpio_chip *gc, 3564 unsigned int offset, int value) 3565 { 3566 ingenic_gpio_set(gc, offset, value); 3567 return pinctrl_gpio_direction_output(gc, offset); 3568 } 3569 3570 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, 3571 unsigned int pin, unsigned int reg, bool set) 3572 { 3573 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3574 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3575 3576 if (set) { 3577 if (is_soc_or_above(jzpc, ID_JZ4740)) 3578 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3579 REG_SET(reg), BIT(idx)); 3580 else 3581 regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset + 3582 reg, BIT(idx)); 3583 } else { 3584 if (is_soc_or_above(jzpc, ID_JZ4740)) 3585 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3586 REG_CLEAR(reg), BIT(idx)); 3587 else 3588 regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset + 3589 reg, BIT(idx)); 3590 } 3591 } 3592 3593 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, 3594 unsigned int pin, u8 reg, bool set) 3595 { 3596 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3597 3598 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + 3599 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 3600 } 3601 3602 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, 3603 unsigned int pin) 3604 { 3605 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), 3606 pin / PINS_PER_GPIO_CHIP); 3607 } 3608 3609 static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc, 3610 unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value) 3611 { 3612 /* 3613 * JZ4730 function and IRQ registers support two-bits-per-pin 3614 * definitions, split into two groups of 16. 3615 */ 3616 unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG; 3617 unsigned int mask = GENMASK(1, 0) << idx * 2; 3618 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3619 u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; 3620 3621 regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg, 3622 mask, value << (idx * 2)); 3623 } 3624 3625 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, 3626 unsigned int pin, unsigned int reg) 3627 { 3628 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3629 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3630 unsigned int val; 3631 3632 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); 3633 3634 return val & BIT(idx); 3635 } 3636 3637 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 3638 { 3639 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3640 struct ingenic_pinctrl *jzpc = jzgc->jzpc; 3641 unsigned int pin = gc->base + offset; 3642 3643 if (is_soc_or_above(jzpc, ID_JZ4770)) { 3644 if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) || 3645 ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1)) 3646 return GPIO_LINE_DIRECTION_IN; 3647 return GPIO_LINE_DIRECTION_OUT; 3648 } else if (!is_soc_or_above(jzpc, ID_JZ4740)) { 3649 if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR)) 3650 return GPIO_LINE_DIRECTION_IN; 3651 return GPIO_LINE_DIRECTION_OUT; 3652 } 3653 3654 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) 3655 return GPIO_LINE_DIRECTION_IN; 3656 3657 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR)) 3658 return GPIO_LINE_DIRECTION_OUT; 3659 3660 return GPIO_LINE_DIRECTION_IN; 3661 } 3662 3663 static const struct pinctrl_ops ingenic_pctlops = { 3664 .get_groups_count = pinctrl_generic_get_group_count, 3665 .get_group_name = pinctrl_generic_get_group_name, 3666 .get_group_pins = pinctrl_generic_get_group_pins, 3667 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 3668 .dt_free_map = pinconf_generic_dt_free_map, 3669 }; 3670 3671 static int ingenic_gpio_irq_request(struct irq_data *data) 3672 { 3673 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3674 irq_hw_number_t irq = irqd_to_hwirq(data); 3675 int ret; 3676 3677 ret = pinctrl_gpio_direction_input(gpio_chip, irq); 3678 if (ret) 3679 return ret; 3680 3681 return gpiochip_reqres_irq(gpio_chip, irq); 3682 } 3683 3684 static void ingenic_gpio_irq_release(struct irq_data *data) 3685 { 3686 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3687 irq_hw_number_t irq = irqd_to_hwirq(data); 3688 3689 return gpiochip_relres_irq(gpio_chip, irq); 3690 } 3691 3692 static void ingenic_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 3693 { 3694 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3695 3696 seq_printf(p, "%s", gpio_chip->label); 3697 } 3698 3699 static const struct irq_chip ingenic_gpio_irqchip = { 3700 .irq_enable = ingenic_gpio_irq_enable, 3701 .irq_disable = ingenic_gpio_irq_disable, 3702 .irq_unmask = ingenic_gpio_irq_unmask, 3703 .irq_mask = ingenic_gpio_irq_mask, 3704 .irq_ack = ingenic_gpio_irq_ack, 3705 .irq_set_type = ingenic_gpio_irq_set_type, 3706 .irq_set_wake = ingenic_gpio_irq_set_wake, 3707 .irq_request_resources = ingenic_gpio_irq_request, 3708 .irq_release_resources = ingenic_gpio_irq_release, 3709 .irq_print_chip = ingenic_gpio_irq_print_chip, 3710 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 3711 }; 3712 3713 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, 3714 int pin, int func) 3715 { 3716 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3717 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3718 3719 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 3720 'A' + offt, idx, func); 3721 3722 if (is_soc_or_above(jzpc, ID_X1000)) { 3723 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3724 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); 3725 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); 3726 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); 3727 ingenic_shadow_config_pin_load(jzpc, pin); 3728 } else if (is_soc_or_above(jzpc, ID_JZ4770)) { 3729 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3730 ingenic_config_pin(jzpc, pin, GPIO_MSK, false); 3731 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); 3732 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); 3733 } else if (is_soc_or_above(jzpc, ID_JZ4740)) { 3734 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); 3735 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); 3736 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1); 3737 } else { 3738 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); 3739 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func); 3740 } 3741 3742 return 0; 3743 } 3744 3745 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, 3746 unsigned int selector, unsigned int group) 3747 { 3748 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3749 struct function_desc *func; 3750 struct group_desc *grp; 3751 unsigned int i; 3752 uintptr_t mode; 3753 u8 *pin_modes; 3754 3755 func = pinmux_generic_get_function(pctldev, selector); 3756 if (!func) 3757 return -EINVAL; 3758 3759 grp = pinctrl_generic_get_group(pctldev, group); 3760 if (!grp) 3761 return -EINVAL; 3762 3763 dev_dbg(pctldev->dev, "enable function %s group %s\n", 3764 func->name, grp->name); 3765 3766 mode = (uintptr_t)grp->data; 3767 if (mode <= 3) { 3768 for (i = 0; i < grp->num_pins; i++) 3769 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode); 3770 } else { 3771 pin_modes = grp->data; 3772 3773 for (i = 0; i < grp->num_pins; i++) 3774 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); 3775 } 3776 3777 return 0; 3778 } 3779 3780 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 3781 struct pinctrl_gpio_range *range, 3782 unsigned int pin, bool input) 3783 { 3784 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3785 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3786 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3787 3788 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 3789 'A' + offt, idx, input ? "in" : "out"); 3790 3791 if (is_soc_or_above(jzpc, ID_X1000)) { 3792 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3793 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); 3794 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); 3795 ingenic_shadow_config_pin_load(jzpc, pin); 3796 } else if (is_soc_or_above(jzpc, ID_JZ4770)) { 3797 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3798 ingenic_config_pin(jzpc, pin, GPIO_MSK, true); 3799 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); 3800 } else if (is_soc_or_above(jzpc, ID_JZ4740)) { 3801 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); 3802 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); 3803 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); 3804 } else { 3805 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); 3806 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input); 3807 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0); 3808 } 3809 3810 return 0; 3811 } 3812 3813 static const struct pinmux_ops ingenic_pmxops = { 3814 .get_functions_count = pinmux_generic_get_function_count, 3815 .get_function_name = pinmux_generic_get_function_name, 3816 .get_function_groups = pinmux_generic_get_function_groups, 3817 .set_mux = ingenic_pinmux_set_mux, 3818 .gpio_set_direction = ingenic_pinmux_gpio_set_direction, 3819 }; 3820 3821 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, 3822 unsigned int pin, unsigned long *config) 3823 { 3824 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3825 enum pin_config_param param = pinconf_to_config_param(*config); 3826 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3827 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3828 unsigned int arg = 1; 3829 unsigned int bias, reg; 3830 bool pull, pullup, pulldown; 3831 3832 if (is_soc_or_above(jzpc, ID_X2000)) { 3833 pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && 3834 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && 3835 (jzpc->info->pull_ups[offt] & BIT(idx)); 3836 pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && 3837 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && 3838 (jzpc->info->pull_downs[offt] & BIT(idx)); 3839 3840 } else if (is_soc_or_above(jzpc, ID_X1830)) { 3841 unsigned int half = PINS_PER_GPIO_CHIP / 2; 3842 unsigned int idxh = (pin % half) * 2; 3843 3844 if (idx < half) 3845 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + 3846 X1830_GPIO_PEL, &bias); 3847 else 3848 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + 3849 X1830_GPIO_PEH, &bias); 3850 3851 bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN); 3852 3853 pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx)); 3854 pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx)); 3855 3856 } else { 3857 if (is_soc_or_above(jzpc, ID_JZ4770)) 3858 pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); 3859 else if (is_soc_or_above(jzpc, ID_JZ4740)) 3860 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); 3861 else 3862 pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR); 3863 3864 pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx)); 3865 pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx)); 3866 } 3867 3868 switch (param) { 3869 case PIN_CONFIG_BIAS_DISABLE: 3870 if (pullup || pulldown) 3871 return -EINVAL; 3872 3873 break; 3874 3875 case PIN_CONFIG_BIAS_PULL_UP: 3876 if (!pullup) 3877 return -EINVAL; 3878 3879 break; 3880 3881 case PIN_CONFIG_BIAS_PULL_DOWN: 3882 if (!pulldown) 3883 return -EINVAL; 3884 3885 break; 3886 3887 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3888 if (is_soc_or_above(jzpc, ID_X2000)) 3889 reg = X2000_GPIO_SMT; 3890 else if (is_soc_or_above(jzpc, ID_X1830)) 3891 reg = X1830_GPIO_SMT; 3892 else 3893 return -EINVAL; 3894 3895 arg = !!ingenic_get_pin_config(jzpc, pin, reg); 3896 break; 3897 3898 case PIN_CONFIG_SLEW_RATE: 3899 if (is_soc_or_above(jzpc, ID_X2000)) 3900 reg = X2000_GPIO_SR; 3901 else if (is_soc_or_above(jzpc, ID_X1830)) 3902 reg = X1830_GPIO_SR; 3903 else 3904 return -EINVAL; 3905 3906 arg = !!ingenic_get_pin_config(jzpc, pin, reg); 3907 break; 3908 3909 default: 3910 return -ENOTSUPP; 3911 } 3912 3913 *config = pinconf_to_config_packed(param, arg); 3914 return 0; 3915 } 3916 3917 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, 3918 unsigned int pin, unsigned int bias) 3919 { 3920 if (is_soc_or_above(jzpc, ID_X2000)) { 3921 switch (bias) { 3922 case GPIO_PULL_UP: 3923 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); 3924 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true); 3925 break; 3926 3927 case GPIO_PULL_DOWN: 3928 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); 3929 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true); 3930 break; 3931 3932 case GPIO_PULL_DIS: 3933 default: 3934 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); 3935 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); 3936 } 3937 3938 } else if (is_soc_or_above(jzpc, ID_X1830)) { 3939 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3940 unsigned int half = PINS_PER_GPIO_CHIP / 2; 3941 unsigned int idxh = (pin % half) * 2; 3942 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3943 3944 if (idx < half) { 3945 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3946 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); 3947 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3948 REG_SET(X1830_GPIO_PEL), bias << idxh); 3949 } else { 3950 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3951 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); 3952 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3953 REG_SET(X1830_GPIO_PEH), bias << idxh); 3954 } 3955 3956 } else if (is_soc_or_above(jzpc, ID_JZ4770)) { 3957 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias); 3958 } else if (is_soc_or_above(jzpc, ID_JZ4740)) { 3959 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); 3960 } else { 3961 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias); 3962 } 3963 } 3964 3965 static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc, 3966 unsigned int pin, bool enable) 3967 { 3968 if (is_soc_or_above(jzpc, ID_X2000)) 3969 ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable); 3970 else 3971 ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable); 3972 } 3973 3974 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, 3975 unsigned int pin, bool high) 3976 { 3977 if (is_soc_or_above(jzpc, ID_JZ4770)) 3978 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high); 3979 else if (is_soc_or_above(jzpc, ID_JZ4740)) 3980 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); 3981 else 3982 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high); 3983 } 3984 3985 static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc, 3986 unsigned int pin, unsigned int slew) 3987 { 3988 if (is_soc_or_above(jzpc, ID_X2000)) 3989 ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew); 3990 else 3991 ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew); 3992 } 3993 3994 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 3995 unsigned long *configs, unsigned int num_configs) 3996 { 3997 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3998 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3999 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 4000 unsigned int cfg, arg; 4001 int ret; 4002 4003 for (cfg = 0; cfg < num_configs; cfg++) { 4004 switch (pinconf_to_config_param(configs[cfg])) { 4005 case PIN_CONFIG_BIAS_DISABLE: 4006 case PIN_CONFIG_BIAS_PULL_UP: 4007 case PIN_CONFIG_BIAS_PULL_DOWN: 4008 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 4009 case PIN_CONFIG_OUTPUT: 4010 case PIN_CONFIG_SLEW_RATE: 4011 continue; 4012 default: 4013 return -ENOTSUPP; 4014 } 4015 } 4016 4017 for (cfg = 0; cfg < num_configs; cfg++) { 4018 arg = pinconf_to_config_argument(configs[cfg]); 4019 4020 switch (pinconf_to_config_param(configs[cfg])) { 4021 case PIN_CONFIG_BIAS_DISABLE: 4022 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 4023 'A' + offt, idx); 4024 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS); 4025 break; 4026 4027 case PIN_CONFIG_BIAS_PULL_UP: 4028 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) 4029 return -EINVAL; 4030 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 4031 'A' + offt, idx); 4032 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP); 4033 break; 4034 4035 case PIN_CONFIG_BIAS_PULL_DOWN: 4036 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) 4037 return -EINVAL; 4038 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 4039 'A' + offt, idx); 4040 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); 4041 break; 4042 4043 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 4044 if (!is_soc_or_above(jzpc, ID_X1830)) 4045 return -EINVAL; 4046 4047 ingenic_set_schmitt_trigger(jzpc, pin, arg); 4048 break; 4049 4050 case PIN_CONFIG_OUTPUT: 4051 ret = pinctrl_gpio_direction_output(jzpc->gc, 4052 pin - jzpc->gc->base); 4053 if (ret) 4054 return ret; 4055 4056 ingenic_set_output_level(jzpc, pin, arg); 4057 break; 4058 4059 case PIN_CONFIG_SLEW_RATE: 4060 if (!is_soc_or_above(jzpc, ID_X1830)) 4061 return -EINVAL; 4062 4063 ingenic_set_slew_rate(jzpc, pin, arg); 4064 break; 4065 4066 default: 4067 /* unreachable */ 4068 break; 4069 } 4070 } 4071 4072 return 0; 4073 } 4074 4075 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, 4076 unsigned int group, unsigned long *config) 4077 { 4078 const unsigned int *pins; 4079 unsigned int i, npins, old = 0; 4080 int ret; 4081 4082 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 4083 if (ret) 4084 return ret; 4085 4086 for (i = 0; i < npins; i++) { 4087 if (ingenic_pinconf_get(pctldev, pins[i], config)) 4088 return -ENOTSUPP; 4089 4090 /* configs do not match between two pins */ 4091 if (i && (old != *config)) 4092 return -ENOTSUPP; 4093 4094 old = *config; 4095 } 4096 4097 return 0; 4098 } 4099 4100 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, 4101 unsigned int group, unsigned long *configs, 4102 unsigned int num_configs) 4103 { 4104 const unsigned int *pins; 4105 unsigned int i, npins; 4106 int ret; 4107 4108 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 4109 if (ret) 4110 return ret; 4111 4112 for (i = 0; i < npins; i++) { 4113 ret = ingenic_pinconf_set(pctldev, 4114 pins[i], configs, num_configs); 4115 if (ret) 4116 return ret; 4117 } 4118 4119 return 0; 4120 } 4121 4122 static const struct pinconf_ops ingenic_confops = { 4123 .is_generic = true, 4124 .pin_config_get = ingenic_pinconf_get, 4125 .pin_config_set = ingenic_pinconf_set, 4126 .pin_config_group_get = ingenic_pinconf_group_get, 4127 .pin_config_group_set = ingenic_pinconf_group_set, 4128 }; 4129 4130 static const struct regmap_config ingenic_pinctrl_regmap_config = { 4131 .reg_bits = 32, 4132 .val_bits = 32, 4133 .reg_stride = 4, 4134 }; 4135 4136 static const struct of_device_id ingenic_gpio_of_matches[] __initconst = { 4137 { .compatible = "ingenic,jz4730-gpio" }, 4138 { .compatible = "ingenic,jz4740-gpio" }, 4139 { .compatible = "ingenic,jz4725b-gpio" }, 4140 { .compatible = "ingenic,jz4750-gpio" }, 4141 { .compatible = "ingenic,jz4755-gpio" }, 4142 { .compatible = "ingenic,jz4760-gpio" }, 4143 { .compatible = "ingenic,jz4770-gpio" }, 4144 { .compatible = "ingenic,jz4775-gpio" }, 4145 { .compatible = "ingenic,jz4780-gpio" }, 4146 { .compatible = "ingenic,x1000-gpio" }, 4147 { .compatible = "ingenic,x1830-gpio" }, 4148 { .compatible = "ingenic,x2000-gpio" }, 4149 { .compatible = "ingenic,x2100-gpio" }, 4150 {}, 4151 }; 4152 4153 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, 4154 struct fwnode_handle *fwnode) 4155 { 4156 struct ingenic_gpio_chip *jzgc; 4157 struct device *dev = jzpc->dev; 4158 struct gpio_irq_chip *girq; 4159 unsigned int bank; 4160 int err; 4161 4162 err = fwnode_property_read_u32(fwnode, "reg", &bank); 4163 if (err) { 4164 dev_err(dev, "Cannot read \"reg\" property: %i\n", err); 4165 return err; 4166 } 4167 4168 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL); 4169 if (!jzgc) 4170 return -ENOMEM; 4171 4172 jzpc->gc = &jzgc->gc; 4173 4174 jzgc->jzpc = jzpc; 4175 jzgc->reg_base = bank * jzpc->info->reg_offset; 4176 4177 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); 4178 if (!jzgc->gc.label) 4179 return -ENOMEM; 4180 4181 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY 4182 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN 4183 * <linux/gpio/consumer.h> INSTEAD. 4184 */ 4185 jzgc->gc.base = bank * 32; 4186 4187 jzgc->gc.ngpio = 32; 4188 jzgc->gc.parent = dev; 4189 jzgc->gc.fwnode = fwnode; 4190 jzgc->gc.owner = THIS_MODULE; 4191 4192 jzgc->gc.set = ingenic_gpio_set; 4193 jzgc->gc.get = ingenic_gpio_get; 4194 jzgc->gc.direction_input = pinctrl_gpio_direction_input; 4195 jzgc->gc.direction_output = ingenic_gpio_direction_output; 4196 jzgc->gc.get_direction = ingenic_gpio_get_direction; 4197 jzgc->gc.request = gpiochip_generic_request; 4198 jzgc->gc.free = gpiochip_generic_free; 4199 4200 err = fwnode_irq_get(fwnode, 0); 4201 if (err < 0) 4202 return err; 4203 if (!err) 4204 return -EINVAL; 4205 jzgc->irq = err; 4206 4207 girq = &jzgc->gc.irq; 4208 gpio_irq_chip_set_chip(girq, &ingenic_gpio_irqchip); 4209 girq->parent_handler = ingenic_gpio_irq_handler; 4210 girq->num_parents = 1; 4211 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 4212 GFP_KERNEL); 4213 if (!girq->parents) 4214 return -ENOMEM; 4215 4216 girq->parents[0] = jzgc->irq; 4217 girq->default_type = IRQ_TYPE_NONE; 4218 girq->handler = handle_level_irq; 4219 4220 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); 4221 if (err) 4222 return err; 4223 4224 return 0; 4225 } 4226 4227 static int __init ingenic_pinctrl_probe(struct platform_device *pdev) 4228 { 4229 struct device *dev = &pdev->dev; 4230 struct ingenic_pinctrl *jzpc; 4231 struct pinctrl_desc *pctl_desc; 4232 void __iomem *base; 4233 const struct ingenic_chip_info *chip_info; 4234 struct regmap_config regmap_config; 4235 struct fwnode_handle *fwnode; 4236 unsigned int i; 4237 int err; 4238 4239 chip_info = device_get_match_data(dev); 4240 if (!chip_info) { 4241 dev_err(dev, "Unsupported SoC\n"); 4242 return -EINVAL; 4243 } 4244 4245 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL); 4246 if (!jzpc) 4247 return -ENOMEM; 4248 4249 base = devm_platform_ioremap_resource(pdev, 0); 4250 if (IS_ERR(base)) 4251 return PTR_ERR(base); 4252 4253 regmap_config = ingenic_pinctrl_regmap_config; 4254 if (chip_info->access_table) { 4255 regmap_config.rd_table = chip_info->access_table; 4256 regmap_config.wr_table = chip_info->access_table; 4257 } else { 4258 regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4; 4259 } 4260 4261 jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config); 4262 if (IS_ERR(jzpc->map)) { 4263 dev_err(dev, "Failed to create regmap\n"); 4264 return PTR_ERR(jzpc->map); 4265 } 4266 4267 jzpc->dev = dev; 4268 jzpc->info = chip_info; 4269 4270 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 4271 if (!pctl_desc) 4272 return -ENOMEM; 4273 4274 /* fill in pinctrl_desc structure */ 4275 pctl_desc->name = dev_name(dev); 4276 pctl_desc->owner = THIS_MODULE; 4277 pctl_desc->pctlops = &ingenic_pctlops; 4278 pctl_desc->pmxops = &ingenic_pmxops; 4279 pctl_desc->confops = &ingenic_confops; 4280 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; 4281 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, 4282 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); 4283 if (!jzpc->pdesc) 4284 return -ENOMEM; 4285 4286 for (i = 0; i < pctl_desc->npins; i++) { 4287 jzpc->pdesc[i].number = i; 4288 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 4289 'A' + (i / PINS_PER_GPIO_CHIP), 4290 i % PINS_PER_GPIO_CHIP); 4291 } 4292 4293 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); 4294 if (IS_ERR(jzpc->pctl)) { 4295 dev_err(dev, "Failed to register pinctrl\n"); 4296 return PTR_ERR(jzpc->pctl); 4297 } 4298 4299 for (i = 0; i < chip_info->num_groups; i++) { 4300 const struct group_desc *group = &chip_info->groups[i]; 4301 4302 err = pinctrl_generic_add_group(jzpc->pctl, group->name, 4303 group->pins, group->num_pins, group->data); 4304 if (err < 0) { 4305 dev_err(dev, "Failed to register group %s\n", 4306 group->name); 4307 return err; 4308 } 4309 } 4310 4311 for (i = 0; i < chip_info->num_functions; i++) { 4312 const struct function_desc *func = &chip_info->functions[i]; 4313 4314 err = pinmux_generic_add_function(jzpc->pctl, func->name, 4315 func->group_names, func->num_group_names, 4316 func->data); 4317 if (err < 0) { 4318 dev_err(dev, "Failed to register function %s\n", 4319 func->name); 4320 return err; 4321 } 4322 } 4323 4324 dev_set_drvdata(dev, jzpc->map); 4325 4326 device_for_each_child_node(dev, fwnode) { 4327 if (of_match_node(ingenic_gpio_of_matches, to_of_node(fwnode))) { 4328 err = ingenic_gpio_probe(jzpc, fwnode); 4329 if (err) { 4330 fwnode_handle_put(fwnode); 4331 return err; 4332 } 4333 } 4334 } 4335 4336 return 0; 4337 } 4338 4339 #define IF_ENABLED(cfg, ptr) PTR_IF(IS_ENABLED(cfg), (ptr)) 4340 4341 static const struct of_device_id ingenic_pinctrl_of_matches[] = { 4342 { 4343 .compatible = "ingenic,jz4730-pinctrl", 4344 .data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info) 4345 }, 4346 { 4347 .compatible = "ingenic,jz4740-pinctrl", 4348 .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info) 4349 }, 4350 { 4351 .compatible = "ingenic,jz4725b-pinctrl", 4352 .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info) 4353 }, 4354 { 4355 .compatible = "ingenic,jz4750-pinctrl", 4356 .data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info) 4357 }, 4358 { 4359 .compatible = "ingenic,jz4755-pinctrl", 4360 .data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info) 4361 }, 4362 { 4363 .compatible = "ingenic,jz4760-pinctrl", 4364 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info) 4365 }, 4366 { 4367 .compatible = "ingenic,jz4760b-pinctrl", 4368 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info) 4369 }, 4370 { 4371 .compatible = "ingenic,jz4770-pinctrl", 4372 .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info) 4373 }, 4374 { 4375 .compatible = "ingenic,jz4775-pinctrl", 4376 .data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info) 4377 }, 4378 { 4379 .compatible = "ingenic,jz4780-pinctrl", 4380 .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info) 4381 }, 4382 { 4383 .compatible = "ingenic,x1000-pinctrl", 4384 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info) 4385 }, 4386 { 4387 .compatible = "ingenic,x1000e-pinctrl", 4388 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info) 4389 }, 4390 { 4391 .compatible = "ingenic,x1500-pinctrl", 4392 .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info) 4393 }, 4394 { 4395 .compatible = "ingenic,x1830-pinctrl", 4396 .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info) 4397 }, 4398 { 4399 .compatible = "ingenic,x2000-pinctrl", 4400 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) 4401 }, 4402 { 4403 .compatible = "ingenic,x2000e-pinctrl", 4404 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) 4405 }, 4406 { 4407 .compatible = "ingenic,x2100-pinctrl", 4408 .data = IF_ENABLED(CONFIG_MACH_X2100, &x2100_chip_info) 4409 }, 4410 { /* sentinel */ }, 4411 }; 4412 4413 static struct platform_driver ingenic_pinctrl_driver = { 4414 .driver = { 4415 .name = "pinctrl-ingenic", 4416 .of_match_table = ingenic_pinctrl_of_matches, 4417 }, 4418 }; 4419 4420 static int __init ingenic_pinctrl_drv_register(void) 4421 { 4422 return platform_driver_probe(&ingenic_pinctrl_driver, 4423 ingenic_pinctrl_probe); 4424 } 4425 subsys_initcall(ingenic_pinctrl_drv_register); 4426