1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ingenic SoCs pinctrl driver 4 * 5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> 6 * Copyright (c) 2017, 2019, 2020, 2023 Paul Boddie <paul@boddie.org.uk> 7 * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 8 */ 9 10 #include <linux/compiler.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/property.h> 19 #include <linux/regmap.h> 20 #include <linux/seq_file.h> 21 #include <linux/slab.h> 22 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinmux.h> 28 29 #include "core.h" 30 #include "pinconf.h" 31 #include "pinmux.h" 32 33 #define GPIO_PIN 0x00 34 #define GPIO_MSK 0x20 35 36 #define JZ4730_GPIO_DATA 0x00 37 #define JZ4730_GPIO_GPDIR 0x04 38 #define JZ4730_GPIO_GPPUR 0x0c 39 #define JZ4730_GPIO_GPALR 0x10 40 #define JZ4730_GPIO_GPAUR 0x14 41 #define JZ4730_GPIO_GPIDLR 0x18 42 #define JZ4730_GPIO_GPIDUR 0x1c 43 #define JZ4730_GPIO_GPIER 0x20 44 #define JZ4730_GPIO_GPIMR 0x24 45 #define JZ4730_GPIO_GPFR 0x28 46 47 #define JZ4740_GPIO_DATA 0x10 48 #define JZ4740_GPIO_PULL_DIS 0x30 49 #define JZ4740_GPIO_FUNC 0x40 50 #define JZ4740_GPIO_SELECT 0x50 51 #define JZ4740_GPIO_DIR 0x60 52 #define JZ4740_GPIO_TRIG 0x70 53 #define JZ4740_GPIO_FLAG 0x80 54 55 #define JZ4770_GPIO_INT 0x10 56 #define JZ4770_GPIO_PAT1 0x30 57 #define JZ4770_GPIO_PAT0 0x40 58 #define JZ4770_GPIO_FLAG 0x50 59 #define JZ4770_GPIO_PEN 0x70 60 61 #define X1600_GPIO_PU 0x80 62 63 #define X1830_GPIO_PEL 0x110 64 #define X1830_GPIO_PEH 0x120 65 #define X1830_GPIO_SR 0x150 66 #define X1830_GPIO_SMT 0x160 67 68 #define X2000_GPIO_EDG 0x70 69 #define X2000_GPIO_PEPU 0x80 70 #define X2000_GPIO_PEPD 0x90 71 #define X2000_GPIO_SR 0xd0 72 #define X2000_GPIO_SMT 0xe0 73 74 #define REG_SET(x) ((x) + 0x4) 75 #define REG_CLEAR(x) ((x) + 0x8) 76 77 #define REG_PZ_BASE(x) ((x) * 7) 78 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) 79 80 #define GPIO_PULL_DIS 0 81 #define GPIO_PULL_UP 1 82 #define GPIO_PULL_DOWN 2 83 84 #define PINS_PER_GPIO_CHIP 32 85 #define JZ4730_PINS_PER_PAIRED_REG 16 86 87 #define INGENIC_PIN_GROUP_FUNCS(_name_, id, funcs) \ 88 { \ 89 .grp = PINCTRL_PINGROUP(_name_, id##_pins, ARRAY_SIZE(id##_pins)), \ 90 .data = funcs, \ 91 } 92 93 #define INGENIC_PIN_GROUP(_name_, id, func) \ 94 { \ 95 .grp = PINCTRL_PINGROUP(_name_, id##_pins, ARRAY_SIZE(id##_pins)), \ 96 .data = (void *)func, \ 97 } 98 99 #define INGENIC_PIN_FUNCTION(_name_, id) \ 100 PINCTRL_PINFUNCTION(_name_, id##_groups, ARRAY_SIZE(id##_groups)) 101 102 enum jz_version { 103 ID_JZ4730, 104 ID_JZ4740, 105 ID_JZ4725B, 106 ID_JZ4750, 107 ID_JZ4755, 108 ID_JZ4760, 109 ID_JZ4770, 110 ID_JZ4775, 111 ID_JZ4780, 112 ID_X1000, 113 ID_X1500, 114 ID_X1600, 115 ID_X1830, 116 ID_X2000, 117 ID_X2100, 118 }; 119 120 struct ingenic_chip_info { 121 unsigned int num_chips; 122 unsigned int reg_offset; 123 enum jz_version version; 124 125 const struct group_desc *groups; 126 unsigned int num_groups; 127 128 const struct pinfunction *functions; 129 unsigned int num_functions; 130 131 const u32 *pull_ups, *pull_downs; 132 133 const struct regmap_access_table *access_table; 134 }; 135 136 struct ingenic_pinctrl { 137 struct device *dev; 138 struct regmap *map; 139 struct pinctrl_dev *pctl; 140 struct pinctrl_pin_desc *pdesc; 141 142 const struct ingenic_chip_info *info; 143 144 struct gpio_chip *gc; 145 }; 146 147 struct ingenic_gpio_chip { 148 struct ingenic_pinctrl *jzpc; 149 struct gpio_chip gc; 150 unsigned int irq, reg_base; 151 }; 152 153 static const unsigned long enabled_socs = 154 IS_ENABLED(CONFIG_MACH_JZ4730) << ID_JZ4730 | 155 IS_ENABLED(CONFIG_MACH_JZ4740) << ID_JZ4740 | 156 IS_ENABLED(CONFIG_MACH_JZ4725B) << ID_JZ4725B | 157 IS_ENABLED(CONFIG_MACH_JZ4750) << ID_JZ4750 | 158 IS_ENABLED(CONFIG_MACH_JZ4755) << ID_JZ4755 | 159 IS_ENABLED(CONFIG_MACH_JZ4760) << ID_JZ4760 | 160 IS_ENABLED(CONFIG_MACH_JZ4770) << ID_JZ4770 | 161 IS_ENABLED(CONFIG_MACH_JZ4775) << ID_JZ4775 | 162 IS_ENABLED(CONFIG_MACH_JZ4780) << ID_JZ4780 | 163 IS_ENABLED(CONFIG_MACH_X1000) << ID_X1000 | 164 IS_ENABLED(CONFIG_MACH_X1500) << ID_X1500 | 165 IS_ENABLED(CONFIG_MACH_X1600) << ID_X1600 | 166 IS_ENABLED(CONFIG_MACH_X1830) << ID_X1830 | 167 IS_ENABLED(CONFIG_MACH_X2000) << ID_X2000 | 168 IS_ENABLED(CONFIG_MACH_X2100) << ID_X2100; 169 170 static bool 171 is_soc_or_above(const struct ingenic_pinctrl *jzpc, enum jz_version version) 172 { 173 return (enabled_socs >> version) && 174 (!(enabled_socs & GENMASK(version - 1, 0)) 175 || jzpc->info->version >= version); 176 } 177 178 static const u32 jz4730_pull_ups[4] = { 179 0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff, 180 }; 181 182 static const u32 jz4730_pull_downs[4] = { 183 0x00000df0, 0x0dff0000, 0x00000000, 0x00000000, 184 }; 185 186 static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, }; 187 static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, }; 188 static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, }; 189 static int jz4730_uart1_data_pins[] = { 0x18, 0x19, }; 190 static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, }; 191 static int jz4730_uart3_data_pins[] = { 0x10, 0x15, }; 192 static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, }; 193 static int jz4730_lcd_8bit_pins[] = { 194 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 195 0x3a, 0x39, 0x38, 196 }; 197 static int jz4730_lcd_16bit_pins[] = { 198 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 199 }; 200 static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, }; 201 static int jz4730_lcd_generic_pins[] = { 0x3b, }; 202 static int jz4730_nand_cs1_pins[] = { 0x53, }; 203 static int jz4730_nand_cs2_pins[] = { 0x54, }; 204 static int jz4730_nand_cs3_pins[] = { 0x55, }; 205 static int jz4730_nand_cs4_pins[] = { 0x56, }; 206 static int jz4730_nand_cs5_pins[] = { 0x57, }; 207 static int jz4730_pwm_pwm0_pins[] = { 0x5e, }; 208 static int jz4730_pwm_pwm1_pins[] = { 0x5f, }; 209 210 static int jz4730_mii_pins[] = { 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 211 0x77, 0x78, 0x19, 0x7a, 0x1b, 0x7c, }; 212 213 static int jz4730_i2s_mclk_pins[] = { 0x44, }; 214 static int jz4730_i2s_acreset_pins[] = { 0x45, }; 215 static int jz4730_i2s_data_pins[] = { 0x46, 0x47, }; 216 static int jz4730_i2s_clock_pins[] = { 0x4d, 0x4e, }; 217 218 static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, }; 219 220 static const struct group_desc jz4730_groups[] = { 221 INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1), 222 INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1), 223 INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1), 224 INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1), 225 INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1), 226 INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1), 227 INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1), 228 INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs), 229 INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1), 230 INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1), 231 INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1), 232 INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1), 233 INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1), 234 INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1), 235 INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1), 236 INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1), 237 INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1), 238 INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1), 239 INGENIC_PIN_GROUP("mii", jz4730_mii, 1), 240 INGENIC_PIN_GROUP("i2s-mclk-out", jz4730_i2s_mclk, 1), 241 INGENIC_PIN_GROUP("i2s-acreset", jz4730_i2s_acreset, 1), 242 INGENIC_PIN_GROUP("i2s-data", jz4730_i2s_data, 1), 243 INGENIC_PIN_GROUP("i2s-master", jz4730_i2s_clock, 1), 244 INGENIC_PIN_GROUP("i2s-slave", jz4730_i2s_clock, 2), 245 }; 246 247 static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 248 static const char *jz4730_uart0_groups[] = { "uart0-data", }; 249 static const char *jz4730_uart1_groups[] = { "uart1-data", }; 250 static const char *jz4730_uart2_groups[] = { "uart2-data", }; 251 static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 252 static const char *jz4730_lcd_groups[] = { 253 "lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic", 254 }; 255 static const char *jz4730_nand_groups[] = { 256 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5", 257 }; 258 static const char *jz4730_pwm0_groups[] = { "pwm0", }; 259 static const char *jz4730_pwm1_groups[] = { "pwm1", }; 260 static const char *jz4730_mii_groups[] = { "mii", }; 261 static const char *jz4730_i2s_groups[] = { "i2s-data", "i2s-master", "i2s-slave", }; 262 263 static const struct pinfunction jz4730_functions[] = { 264 INGENIC_PIN_FUNCTION("mmc", jz4730_mmc), 265 INGENIC_PIN_FUNCTION("uart0", jz4730_uart0), 266 INGENIC_PIN_FUNCTION("uart1", jz4730_uart1), 267 INGENIC_PIN_FUNCTION("uart2", jz4730_uart2), 268 INGENIC_PIN_FUNCTION("uart3", jz4730_uart3), 269 INGENIC_PIN_FUNCTION("lcd", jz4730_lcd), 270 INGENIC_PIN_FUNCTION("nand", jz4730_nand), 271 INGENIC_PIN_FUNCTION("pwm0", jz4730_pwm0), 272 INGENIC_PIN_FUNCTION("pwm1", jz4730_pwm1), 273 INGENIC_PIN_FUNCTION("mii", jz4730_mii), 274 INGENIC_PIN_FUNCTION("i2s", jz4730_i2s), 275 }; 276 277 static const struct ingenic_chip_info jz4730_chip_info = { 278 .num_chips = 4, 279 .reg_offset = 0x30, 280 .version = ID_JZ4730, 281 .groups = jz4730_groups, 282 .num_groups = ARRAY_SIZE(jz4730_groups), 283 .functions = jz4730_functions, 284 .num_functions = ARRAY_SIZE(jz4730_functions), 285 .pull_ups = jz4730_pull_ups, 286 .pull_downs = jz4730_pull_downs, 287 }; 288 289 static const u32 jz4740_pull_ups[4] = { 290 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 291 }; 292 293 static const u32 jz4740_pull_downs[4] = { 294 0x00000000, 0x00000000, 0x00000000, 0x00000000, 295 }; 296 297 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, }; 298 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 299 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; 300 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 301 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; 302 static int jz4740_lcd_8bit_pins[] = { 303 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 304 0x52, 0x53, 0x54, 305 }; 306 static int jz4740_lcd_16bit_pins[] = { 307 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 308 }; 309 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; 310 static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, }; 311 static int jz4740_lcd_generic_pins[] = { 0x55, }; 312 static int jz4740_nand_cs1_pins[] = { 0x39, }; 313 static int jz4740_nand_cs2_pins[] = { 0x3a, }; 314 static int jz4740_nand_cs3_pins[] = { 0x3b, }; 315 static int jz4740_nand_cs4_pins[] = { 0x3c, }; 316 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 317 static int jz4740_pwm_pwm0_pins[] = { 0x77, }; 318 static int jz4740_pwm_pwm1_pins[] = { 0x78, }; 319 static int jz4740_pwm_pwm2_pins[] = { 0x79, }; 320 static int jz4740_pwm_pwm3_pins[] = { 0x7a, }; 321 static int jz4740_pwm_pwm4_pins[] = { 0x7b, }; 322 static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; 323 static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; 324 static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; 325 326 static const struct group_desc jz4740_groups[] = { 327 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0), 328 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0), 329 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1), 330 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1), 331 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2), 332 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0), 333 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0), 334 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0), 335 INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0), 336 INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0), 337 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0), 338 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0), 339 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0), 340 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0), 341 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0), 342 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0), 343 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0), 344 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0), 345 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0), 346 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0), 347 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0), 348 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0), 349 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0), 350 }; 351 352 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 353 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 354 static const char *jz4740_uart1_groups[] = { "uart1-data", }; 355 static const char *jz4740_lcd_groups[] = { 356 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic", 357 }; 358 static const char *jz4740_nand_groups[] = { 359 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 360 }; 361 static const char *jz4740_pwm0_groups[] = { "pwm0", }; 362 static const char *jz4740_pwm1_groups[] = { "pwm1", }; 363 static const char *jz4740_pwm2_groups[] = { "pwm2", }; 364 static const char *jz4740_pwm3_groups[] = { "pwm3", }; 365 static const char *jz4740_pwm4_groups[] = { "pwm4", }; 366 static const char *jz4740_pwm5_groups[] = { "pwm5", }; 367 static const char *jz4740_pwm6_groups[] = { "pwm6", }; 368 static const char *jz4740_pwm7_groups[] = { "pwm7", }; 369 370 static const struct pinfunction jz4740_functions[] = { 371 INGENIC_PIN_FUNCTION("mmc", jz4740_mmc), 372 INGENIC_PIN_FUNCTION("uart0", jz4740_uart0), 373 INGENIC_PIN_FUNCTION("uart1", jz4740_uart1), 374 INGENIC_PIN_FUNCTION("lcd", jz4740_lcd), 375 INGENIC_PIN_FUNCTION("nand", jz4740_nand), 376 INGENIC_PIN_FUNCTION("pwm0", jz4740_pwm0), 377 INGENIC_PIN_FUNCTION("pwm1", jz4740_pwm1), 378 INGENIC_PIN_FUNCTION("pwm2", jz4740_pwm2), 379 INGENIC_PIN_FUNCTION("pwm3", jz4740_pwm3), 380 INGENIC_PIN_FUNCTION("pwm4", jz4740_pwm4), 381 INGENIC_PIN_FUNCTION("pwm5", jz4740_pwm5), 382 INGENIC_PIN_FUNCTION("pwm6", jz4740_pwm6), 383 INGENIC_PIN_FUNCTION("pwm7", jz4740_pwm7), 384 }; 385 386 static const struct ingenic_chip_info jz4740_chip_info = { 387 .num_chips = 4, 388 .reg_offset = 0x100, 389 .version = ID_JZ4740, 390 .groups = jz4740_groups, 391 .num_groups = ARRAY_SIZE(jz4740_groups), 392 .functions = jz4740_functions, 393 .num_functions = ARRAY_SIZE(jz4740_functions), 394 .pull_ups = jz4740_pull_ups, 395 .pull_downs = jz4740_pull_downs, 396 }; 397 398 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, }; 399 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, }; 400 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, }; 401 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, }; 402 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, }; 403 static int jz4725b_lcd_8bit_pins[] = { 404 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 405 0x72, 0x73, 0x74, 406 }; 407 static int jz4725b_lcd_16bit_pins[] = { 408 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 409 }; 410 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; 411 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 412 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 413 static int jz4725b_lcd_generic_pins[] = { 0x75, }; 414 static int jz4725b_nand_cs1_pins[] = { 0x55, }; 415 static int jz4725b_nand_cs2_pins[] = { 0x56, }; 416 static int jz4725b_nand_cs3_pins[] = { 0x57, }; 417 static int jz4725b_nand_cs4_pins[] = { 0x58, }; 418 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 }; 419 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d }; 420 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, }; 421 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, }; 422 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, }; 423 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, }; 424 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, }; 425 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, }; 426 427 static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; 428 429 static const struct group_desc jz4725b_groups[] = { 430 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1), 431 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit, 432 jz4725b_mmc0_4bit_funcs), 433 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0), 434 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0), 435 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1), 436 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0), 437 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0), 438 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0), 439 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1), 440 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0), 441 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0), 442 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0), 443 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0), 444 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0), 445 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0), 446 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0), 447 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0), 448 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0), 449 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0), 450 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0), 451 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0), 452 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0), 453 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0), 454 }; 455 456 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 457 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 458 static const char *jz4725b_uart_groups[] = { "uart-data", }; 459 static const char *jz4725b_lcd_groups[] = { 460 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 461 "lcd-special", "lcd-generic", 462 }; 463 static const char *jz4725b_nand_groups[] = { 464 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 465 "nand-cle-ale", "nand-fre-fwe", 466 }; 467 static const char *jz4725b_pwm0_groups[] = { "pwm0", }; 468 static const char *jz4725b_pwm1_groups[] = { "pwm1", }; 469 static const char *jz4725b_pwm2_groups[] = { "pwm2", }; 470 static const char *jz4725b_pwm3_groups[] = { "pwm3", }; 471 static const char *jz4725b_pwm4_groups[] = { "pwm4", }; 472 static const char *jz4725b_pwm5_groups[] = { "pwm5", }; 473 474 static const struct pinfunction jz4725b_functions[] = { 475 INGENIC_PIN_FUNCTION("mmc0", jz4725b_mmc0), 476 INGENIC_PIN_FUNCTION("mmc1", jz4725b_mmc1), 477 INGENIC_PIN_FUNCTION("uart", jz4725b_uart), 478 INGENIC_PIN_FUNCTION("nand", jz4725b_nand), 479 INGENIC_PIN_FUNCTION("pwm0", jz4725b_pwm0), 480 INGENIC_PIN_FUNCTION("pwm1", jz4725b_pwm1), 481 INGENIC_PIN_FUNCTION("pwm2", jz4725b_pwm2), 482 INGENIC_PIN_FUNCTION("pwm3", jz4725b_pwm3), 483 INGENIC_PIN_FUNCTION("pwm4", jz4725b_pwm4), 484 INGENIC_PIN_FUNCTION("pwm5", jz4725b_pwm5), 485 INGENIC_PIN_FUNCTION("lcd", jz4725b_lcd), 486 }; 487 488 static const struct ingenic_chip_info jz4725b_chip_info = { 489 .num_chips = 4, 490 .reg_offset = 0x100, 491 .version = ID_JZ4725B, 492 .groups = jz4725b_groups, 493 .num_groups = ARRAY_SIZE(jz4725b_groups), 494 .functions = jz4725b_functions, 495 .num_functions = ARRAY_SIZE(jz4725b_functions), 496 .pull_ups = jz4740_pull_ups, 497 .pull_downs = jz4740_pull_downs, 498 }; 499 500 static const u32 jz4750_pull_ups[6] = { 501 0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff, 502 }; 503 504 static const u32 jz4750_pull_downs[6] = { 505 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 506 }; 507 508 static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, }; 509 static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, }; 510 static int jz4750_uart1_data_pins[] = { 0x90, 0x91, }; 511 static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, }; 512 static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, }; 513 static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, }; 514 static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, }; 515 static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, }; 516 static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, }; 517 static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, }; 518 static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, }; 519 static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, }; 520 static int jz4750_i2c_pins[] = { 0x8c, 0x8d, }; 521 static int jz4750_cim_pins[] = { 522 0x89, 0x8b, 0x8a, 0x88, 523 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 524 }; 525 static int jz4750_lcd_8bit_pins[] = { 526 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 527 0x72, 0x73, 0x74, 528 }; 529 static int jz4750_lcd_16bit_pins[] = { 530 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 531 }; 532 static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, }; 533 static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, }; 534 static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 535 static int jz4750_lcd_generic_pins[] = { 0x75, }; 536 static int jz4750_nand_cs1_pins[] = { 0x55, }; 537 static int jz4750_nand_cs2_pins[] = { 0x56, }; 538 static int jz4750_nand_cs3_pins[] = { 0x57, }; 539 static int jz4750_nand_cs4_pins[] = { 0x58, }; 540 static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 541 static int jz4750_pwm_pwm0_pins[] = { 0x94, }; 542 static int jz4750_pwm_pwm1_pins[] = { 0x95, }; 543 static int jz4750_pwm_pwm2_pins[] = { 0x96, }; 544 static int jz4750_pwm_pwm3_pins[] = { 0x97, }; 545 static int jz4750_pwm_pwm4_pins[] = { 0x98, }; 546 static int jz4750_pwm_pwm5_pins[] = { 0x99, }; 547 548 static const struct group_desc jz4750_groups[] = { 549 INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1), 550 INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1), 551 INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0), 552 INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0), 553 INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1), 554 INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0), 555 INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0), 556 INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0), 557 INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0), 558 INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0), 559 INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0), 560 INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0), 561 INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0), 562 INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0), 563 INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0), 564 INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0), 565 INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0), 566 INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1), 567 INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0), 568 INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0), 569 INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0), 570 INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0), 571 INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0), 572 INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0), 573 INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0), 574 INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0), 575 INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0), 576 INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0), 577 INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0), 578 INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0), 579 INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0), 580 }; 581 582 static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 583 static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 584 static const char *jz4750_uart2_groups[] = { "uart2-data", }; 585 static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 586 static const char *jz4750_mmc0_groups[] = { 587 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 588 }; 589 static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 590 static const char *jz4750_i2c_groups[] = { "i2c-data", }; 591 static const char *jz4750_cim_groups[] = { "cim-data", }; 592 static const char *jz4750_lcd_groups[] = { 593 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 594 "lcd-special", "lcd-generic", 595 }; 596 static const char *jz4750_nand_groups[] = { 597 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 598 }; 599 static const char *jz4750_pwm0_groups[] = { "pwm0", }; 600 static const char *jz4750_pwm1_groups[] = { "pwm1", }; 601 static const char *jz4750_pwm2_groups[] = { "pwm2", }; 602 static const char *jz4750_pwm3_groups[] = { "pwm3", }; 603 static const char *jz4750_pwm4_groups[] = { "pwm4", }; 604 static const char *jz4750_pwm5_groups[] = { "pwm5", }; 605 606 static const struct pinfunction jz4750_functions[] = { 607 INGENIC_PIN_FUNCTION("uart0", jz4750_uart0), 608 INGENIC_PIN_FUNCTION("uart1", jz4750_uart1), 609 INGENIC_PIN_FUNCTION("uart2", jz4750_uart2), 610 INGENIC_PIN_FUNCTION("uart3", jz4750_uart3), 611 INGENIC_PIN_FUNCTION("mmc0", jz4750_mmc0), 612 INGENIC_PIN_FUNCTION("mmc1", jz4750_mmc1), 613 INGENIC_PIN_FUNCTION("i2c", jz4750_i2c), 614 INGENIC_PIN_FUNCTION("cim", jz4750_cim), 615 INGENIC_PIN_FUNCTION("lcd", jz4750_lcd), 616 INGENIC_PIN_FUNCTION("nand", jz4750_nand), 617 INGENIC_PIN_FUNCTION("pwm0", jz4750_pwm0), 618 INGENIC_PIN_FUNCTION("pwm1", jz4750_pwm1), 619 INGENIC_PIN_FUNCTION("pwm2", jz4750_pwm2), 620 INGENIC_PIN_FUNCTION("pwm3", jz4750_pwm3), 621 INGENIC_PIN_FUNCTION("pwm4", jz4750_pwm4), 622 INGENIC_PIN_FUNCTION("pwm5", jz4750_pwm5), 623 }; 624 625 static const struct ingenic_chip_info jz4750_chip_info = { 626 .num_chips = 6, 627 .reg_offset = 0x100, 628 .version = ID_JZ4750, 629 .groups = jz4750_groups, 630 .num_groups = ARRAY_SIZE(jz4750_groups), 631 .functions = jz4750_functions, 632 .num_functions = ARRAY_SIZE(jz4750_functions), 633 .pull_ups = jz4750_pull_ups, 634 .pull_downs = jz4750_pull_downs, 635 }; 636 637 static const u32 jz4755_pull_ups[6] = { 638 0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00, 639 }; 640 641 static const u32 jz4755_pull_downs[6] = { 642 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 643 }; 644 645 static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, }; 646 static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 647 static int jz4755_uart1_data_pins[] = { 0x97, 0x99, }; 648 static int jz4755_uart2_data_pins[] = { 0x9f, }; 649 static int jz4755_ssi_dt_b_pins[] = { 0x3b, }; 650 static int jz4755_ssi_dt_f_pins[] = { 0xa1, }; 651 static int jz4755_ssi_dr_b_pins[] = { 0x3c, }; 652 static int jz4755_ssi_dr_f_pins[] = { 0xa2, }; 653 static int jz4755_ssi_clk_b_pins[] = { 0x3a, }; 654 static int jz4755_ssi_clk_f_pins[] = { 0xa0, }; 655 static int jz4755_ssi_gpc_b_pins[] = { 0x3e, }; 656 static int jz4755_ssi_gpc_f_pins[] = { 0xa4, }; 657 static int jz4755_ssi_ce0_b_pins[] = { 0x3d, }; 658 static int jz4755_ssi_ce0_f_pins[] = { 0xa3, }; 659 static int jz4755_ssi_ce1_b_pins[] = { 0x3f, }; 660 static int jz4755_ssi_ce1_f_pins[] = { 0xa5, }; 661 static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, }; 662 static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, }; 663 static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, }; 664 static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, }; 665 static int jz4755_i2c_pins[] = { 0x8c, 0x8d, }; 666 static int jz4755_cim_pins[] = { 667 0x89, 0x8b, 0x8a, 0x88, 668 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 669 }; 670 static int jz4755_lcd_8bit_pins[] = { 671 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 672 0x72, 0x73, 0x74, 673 }; 674 static int jz4755_lcd_16bit_pins[] = { 675 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 676 }; 677 static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, }; 678 static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, }; 679 static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 680 static int jz4755_lcd_generic_pins[] = { 0x75, }; 681 static int jz4755_nand_cs1_pins[] = { 0x55, }; 682 static int jz4755_nand_cs2_pins[] = { 0x56, }; 683 static int jz4755_nand_cs3_pins[] = { 0x57, }; 684 static int jz4755_nand_cs4_pins[] = { 0x58, }; 685 static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 686 static int jz4755_pwm_pwm0_pins[] = { 0x94, }; 687 static int jz4755_pwm_pwm1_pins[] = { 0xab, }; 688 static int jz4755_pwm_pwm2_pins[] = { 0x96, }; 689 static int jz4755_pwm_pwm3_pins[] = { 0x97, }; 690 static int jz4755_pwm_pwm4_pins[] = { 0x98, }; 691 static int jz4755_pwm_pwm5_pins[] = { 0x99, }; 692 693 static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, }; 694 static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, }; 695 static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, }; 696 697 static const struct group_desc jz4755_groups[] = { 698 INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0), 699 INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0), 700 INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1), 701 INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1), 702 INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0), 703 INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0), 704 INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0), 705 INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0), 706 INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0), 707 INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0), 708 INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0), 709 INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0), 710 INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0), 711 INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0), 712 INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0), 713 INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0), 714 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit, 715 jz4755_mmc0_1bit_funcs), 716 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit, 717 jz4755_mmc0_4bit_funcs), 718 INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1), 719 INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1), 720 INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0), 721 INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0), 722 INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0), 723 INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0), 724 INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0), 725 INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit, 726 jz4755_lcd_24bit_funcs), 727 INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0), 728 INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0), 729 INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0), 730 INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0), 731 INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0), 732 INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0), 733 INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0), 734 INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0), 735 INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1), 736 INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0), 737 INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0), 738 INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0), 739 INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0), 740 }; 741 742 static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 743 static const char *jz4755_uart1_groups[] = { "uart1-data", }; 744 static const char *jz4755_uart2_groups[] = { "uart2-data", }; 745 static const char *jz4755_ssi_groups[] = { 746 "ssi-dt-b", "ssi-dt-f", 747 "ssi-dr-b", "ssi-dr-f", 748 "ssi-clk-b", "ssi-clk-f", 749 "ssi-gpc-b", "ssi-gpc-f", 750 "ssi-ce0-b", "ssi-ce0-f", 751 "ssi-ce1-b", "ssi-ce1-f", 752 }; 753 static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 754 static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 755 static const char *jz4755_i2c_groups[] = { "i2c-data", }; 756 static const char *jz4755_cim_groups[] = { "cim-data", }; 757 static const char *jz4755_lcd_groups[] = { 758 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 759 "lcd-special", "lcd-generic", 760 }; 761 static const char *jz4755_nand_groups[] = { 762 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 763 }; 764 static const char *jz4755_pwm0_groups[] = { "pwm0", }; 765 static const char *jz4755_pwm1_groups[] = { "pwm1", }; 766 static const char *jz4755_pwm2_groups[] = { "pwm2", }; 767 static const char *jz4755_pwm3_groups[] = { "pwm3", }; 768 static const char *jz4755_pwm4_groups[] = { "pwm4", }; 769 static const char *jz4755_pwm5_groups[] = { "pwm5", }; 770 771 static const struct pinfunction jz4755_functions[] = { 772 INGENIC_PIN_FUNCTION("uart0", jz4755_uart0), 773 INGENIC_PIN_FUNCTION("uart1", jz4755_uart1), 774 INGENIC_PIN_FUNCTION("uart2", jz4755_uart2), 775 INGENIC_PIN_FUNCTION("ssi", jz4755_ssi), 776 INGENIC_PIN_FUNCTION("mmc0", jz4755_mmc0), 777 INGENIC_PIN_FUNCTION("mmc1", jz4755_mmc1), 778 INGENIC_PIN_FUNCTION("i2c", jz4755_i2c), 779 INGENIC_PIN_FUNCTION("cim", jz4755_cim), 780 INGENIC_PIN_FUNCTION("lcd", jz4755_lcd), 781 INGENIC_PIN_FUNCTION("nand", jz4755_nand), 782 INGENIC_PIN_FUNCTION("pwm0", jz4755_pwm0), 783 INGENIC_PIN_FUNCTION("pwm1", jz4755_pwm1), 784 INGENIC_PIN_FUNCTION("pwm2", jz4755_pwm2), 785 INGENIC_PIN_FUNCTION("pwm3", jz4755_pwm3), 786 INGENIC_PIN_FUNCTION("pwm4", jz4755_pwm4), 787 INGENIC_PIN_FUNCTION("pwm5", jz4755_pwm5), 788 }; 789 790 static const struct ingenic_chip_info jz4755_chip_info = { 791 .num_chips = 6, 792 .reg_offset = 0x100, 793 .version = ID_JZ4755, 794 .groups = jz4755_groups, 795 .num_groups = ARRAY_SIZE(jz4755_groups), 796 .functions = jz4755_functions, 797 .num_functions = ARRAY_SIZE(jz4755_functions), 798 .pull_ups = jz4755_pull_ups, 799 .pull_downs = jz4755_pull_downs, 800 }; 801 802 static const u32 jz4760_pull_ups[6] = { 803 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f, 804 }; 805 806 static const u32 jz4760_pull_downs[6] = { 807 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, 808 }; 809 810 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; 811 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 812 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; 813 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 814 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; 815 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 816 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; 817 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; 818 static int jz4760_ssi0_dt_a_pins[] = { 0x15, }; 819 static int jz4760_ssi0_dt_b_pins[] = { 0x35, }; 820 static int jz4760_ssi0_dt_d_pins[] = { 0x75, }; 821 static int jz4760_ssi0_dt_e_pins[] = { 0x91, }; 822 static int jz4760_ssi0_dr_a_pins[] = { 0x14, }; 823 static int jz4760_ssi0_dr_b_pins[] = { 0x34, }; 824 static int jz4760_ssi0_dr_d_pins[] = { 0x74, }; 825 static int jz4760_ssi0_dr_e_pins[] = { 0x8e, }; 826 static int jz4760_ssi0_clk_a_pins[] = { 0x12, }; 827 static int jz4760_ssi0_clk_b_pins[] = { 0x3c, }; 828 static int jz4760_ssi0_clk_d_pins[] = { 0x78, }; 829 static int jz4760_ssi0_clk_e_pins[] = { 0x8f, }; 830 static int jz4760_ssi0_gpc_b_pins[] = { 0x3e, }; 831 static int jz4760_ssi0_gpc_d_pins[] = { 0x76, }; 832 static int jz4760_ssi0_gpc_e_pins[] = { 0x93, }; 833 static int jz4760_ssi0_ce0_a_pins[] = { 0x13, }; 834 static int jz4760_ssi0_ce0_b_pins[] = { 0x3d, }; 835 static int jz4760_ssi0_ce0_d_pins[] = { 0x79, }; 836 static int jz4760_ssi0_ce0_e_pins[] = { 0x90, }; 837 static int jz4760_ssi0_ce1_b_pins[] = { 0x3f, }; 838 static int jz4760_ssi0_ce1_d_pins[] = { 0x77, }; 839 static int jz4760_ssi0_ce1_e_pins[] = { 0x92, }; 840 static int jz4760_ssi1_dt_b_9_pins[] = { 0x29, }; 841 static int jz4760_ssi1_dt_b_21_pins[] = { 0x35, }; 842 static int jz4760_ssi1_dt_d_12_pins[] = { 0x6c, }; 843 static int jz4760_ssi1_dt_d_21_pins[] = { 0x75, }; 844 static int jz4760_ssi1_dt_e_pins[] = { 0x91, }; 845 static int jz4760_ssi1_dt_f_pins[] = { 0xa3, }; 846 static int jz4760_ssi1_dr_b_6_pins[] = { 0x26, }; 847 static int jz4760_ssi1_dr_b_20_pins[] = { 0x34, }; 848 static int jz4760_ssi1_dr_d_13_pins[] = { 0x6d, }; 849 static int jz4760_ssi1_dr_d_20_pins[] = { 0x74, }; 850 static int jz4760_ssi1_dr_e_pins[] = { 0x8e, }; 851 static int jz4760_ssi1_dr_f_pins[] = { 0xa0, }; 852 static int jz4760_ssi1_clk_b_7_pins[] = { 0x27, }; 853 static int jz4760_ssi1_clk_b_28_pins[] = { 0x3c, }; 854 static int jz4760_ssi1_clk_d_pins[] = { 0x78, }; 855 static int jz4760_ssi1_clk_e_7_pins[] = { 0x87, }; 856 static int jz4760_ssi1_clk_e_15_pins[] = { 0x8f, }; 857 static int jz4760_ssi1_clk_f_pins[] = { 0xa2, }; 858 static int jz4760_ssi1_gpc_b_pins[] = { 0x3e, }; 859 static int jz4760_ssi1_gpc_d_pins[] = { 0x76, }; 860 static int jz4760_ssi1_gpc_e_pins[] = { 0x93, }; 861 static int jz4760_ssi1_ce0_b_8_pins[] = { 0x28, }; 862 static int jz4760_ssi1_ce0_b_29_pins[] = { 0x3d, }; 863 static int jz4760_ssi1_ce0_d_pins[] = { 0x79, }; 864 static int jz4760_ssi1_ce0_e_6_pins[] = { 0x86, }; 865 static int jz4760_ssi1_ce0_e_16_pins[] = { 0x90, }; 866 static int jz4760_ssi1_ce0_f_pins[] = { 0xa1, }; 867 static int jz4760_ssi1_ce1_b_pins[] = { 0x3f, }; 868 static int jz4760_ssi1_ce1_d_pins[] = { 0x77, }; 869 static int jz4760_ssi1_ce1_e_pins[] = { 0x92, }; 870 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 871 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 872 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 873 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 874 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 875 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 876 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 877 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 878 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 879 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 880 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 881 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 882 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 883 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 884 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 885 static int jz4760_nemc_8bit_data_pins[] = { 886 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 887 }; 888 static int jz4760_nemc_16bit_data_pins[] = { 889 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 890 }; 891 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 892 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 893 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; 894 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 895 static int jz4760_nemc_wait_pins[] = { 0x1b, }; 896 static int jz4760_nemc_cs1_pins[] = { 0x15, }; 897 static int jz4760_nemc_cs2_pins[] = { 0x16, }; 898 static int jz4760_nemc_cs3_pins[] = { 0x17, }; 899 static int jz4760_nemc_cs4_pins[] = { 0x18, }; 900 static int jz4760_nemc_cs5_pins[] = { 0x19, }; 901 static int jz4760_nemc_cs6_pins[] = { 0x1a, }; 902 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; 903 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; 904 static int jz4760_cim_pins[] = { 905 0x26, 0x27, 0x28, 0x29, 906 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 907 }; 908 static int jz4760_lcd_8bit_pins[] = { 909 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c, 910 0x4d, 0x52, 0x53, 911 }; 912 static int jz4760_lcd_16bit_pins[] = { 913 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 914 }; 915 static int jz4760_lcd_18bit_pins[] = { 916 0x5a, 0x5b, 917 }; 918 static int jz4760_lcd_24bit_pins[] = { 919 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, 920 }; 921 static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 922 static int jz4760_lcd_generic_pins[] = { 0x49, }; 923 static int jz4760_pwm_pwm0_pins[] = { 0x80, }; 924 static int jz4760_pwm_pwm1_pins[] = { 0x81, }; 925 static int jz4760_pwm_pwm2_pins[] = { 0x82, }; 926 static int jz4760_pwm_pwm3_pins[] = { 0x83, }; 927 static int jz4760_pwm_pwm4_pins[] = { 0x84, }; 928 static int jz4760_pwm_pwm5_pins[] = { 0x85, }; 929 static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; 930 static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; 931 static int jz4760_otg_pins[] = { 0x8a, }; 932 933 static u8 jz4760_uart3_data_funcs[] = { 0, 1, }; 934 static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 935 936 static const struct group_desc jz4760_groups[] = { 937 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0), 938 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0), 939 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0), 940 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0), 941 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0), 942 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0), 943 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data, 944 jz4760_uart3_data_funcs), 945 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0), 946 INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2), 947 INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1), 948 INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1), 949 INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0), 950 INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1), 951 INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1), 952 INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1), 953 INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0), 954 INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2), 955 INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1), 956 INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1), 957 INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0), 958 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1), 959 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1), 960 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0), 961 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2), 962 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1), 963 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1), 964 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0), 965 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1), 966 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1), 967 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0), 968 INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2), 969 INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2), 970 INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2), 971 INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2), 972 INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1), 973 INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2), 974 INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2), 975 INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2), 976 INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2), 977 INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2), 978 INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1), 979 INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2), 980 INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2), 981 INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2), 982 INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2), 983 INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2), 984 INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1), 985 INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2), 986 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2), 987 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2), 988 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1), 989 INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2), 990 INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2), 991 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2), 992 INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2), 993 INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1), 994 INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2), 995 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2), 996 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2), 997 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1), 998 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a, 999 jz4760_mmc0_1bit_a_funcs), 1000 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1), 1001 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0), 1002 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0), 1003 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0), 1004 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0), 1005 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0), 1006 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1), 1007 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1), 1008 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1), 1009 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0), 1010 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0), 1011 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2), 1012 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2), 1013 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2), 1014 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0), 1015 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0), 1016 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0), 1017 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0), 1018 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0), 1019 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0), 1020 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0), 1021 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0), 1022 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0), 1023 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0), 1024 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0), 1025 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0), 1026 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0), 1027 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0), 1028 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0), 1029 INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0), 1030 INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0), 1031 INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0), 1032 INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0), 1033 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0), 1034 INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1), 1035 INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0), 1036 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0), 1037 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0), 1038 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0), 1039 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0), 1040 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0), 1041 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0), 1042 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0), 1043 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0), 1044 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), 1045 }; 1046 1047 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1048 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1049 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1050 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 1051 static const char *jz4760_ssi0_groups[] = { 1052 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1053 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1054 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", 1055 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1056 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1057 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1058 }; 1059 static const char *jz4760_ssi1_groups[] = { 1060 "ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f", 1061 "ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f", 1062 "ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f", 1063 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1064 "ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f", 1065 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1066 }; 1067 static const char *jz4760_mmc0_groups[] = { 1068 "mmc0-1bit-a", "mmc0-4bit-a", 1069 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 1070 }; 1071 static const char *jz4760_mmc1_groups[] = { 1072 "mmc1-1bit-d", "mmc1-4bit-d", 1073 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 1074 }; 1075 static const char *jz4760_mmc2_groups[] = { 1076 "mmc2-1bit-b", "mmc2-4bit-b", 1077 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 1078 }; 1079 static const char *jz4760_nemc_groups[] = { 1080 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1081 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1082 }; 1083 static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; 1084 static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; 1085 static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; 1086 static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; 1087 static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; 1088 static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; 1089 static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; 1090 static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; 1091 static const char *jz4760_cim_groups[] = { "cim-data", }; 1092 static const char *jz4760_lcd_groups[] = { 1093 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1094 "lcd-special", "lcd-generic", 1095 }; 1096 static const char *jz4760_pwm0_groups[] = { "pwm0", }; 1097 static const char *jz4760_pwm1_groups[] = { "pwm1", }; 1098 static const char *jz4760_pwm2_groups[] = { "pwm2", }; 1099 static const char *jz4760_pwm3_groups[] = { "pwm3", }; 1100 static const char *jz4760_pwm4_groups[] = { "pwm4", }; 1101 static const char *jz4760_pwm5_groups[] = { "pwm5", }; 1102 static const char *jz4760_pwm6_groups[] = { "pwm6", }; 1103 static const char *jz4760_pwm7_groups[] = { "pwm7", }; 1104 static const char *jz4760_otg_groups[] = { "otg-vbus", }; 1105 1106 static const struct pinfunction jz4760_functions[] = { 1107 INGENIC_PIN_FUNCTION("uart0", jz4760_uart0), 1108 INGENIC_PIN_FUNCTION("uart1", jz4760_uart1), 1109 INGENIC_PIN_FUNCTION("uart2", jz4760_uart2), 1110 INGENIC_PIN_FUNCTION("uart3", jz4760_uart3), 1111 INGENIC_PIN_FUNCTION("ssi0", jz4760_ssi0), 1112 INGENIC_PIN_FUNCTION("ssi1", jz4760_ssi1), 1113 INGENIC_PIN_FUNCTION("mmc0", jz4760_mmc0), 1114 INGENIC_PIN_FUNCTION("mmc1", jz4760_mmc1), 1115 INGENIC_PIN_FUNCTION("mmc2", jz4760_mmc2), 1116 INGENIC_PIN_FUNCTION("nemc", jz4760_nemc), 1117 INGENIC_PIN_FUNCTION("nemc-cs1", jz4760_cs1), 1118 INGENIC_PIN_FUNCTION("nemc-cs2", jz4760_cs2), 1119 INGENIC_PIN_FUNCTION("nemc-cs3", jz4760_cs3), 1120 INGENIC_PIN_FUNCTION("nemc-cs4", jz4760_cs4), 1121 INGENIC_PIN_FUNCTION("nemc-cs5", jz4760_cs5), 1122 INGENIC_PIN_FUNCTION("nemc-cs6", jz4760_cs6), 1123 INGENIC_PIN_FUNCTION("i2c0", jz4760_i2c0), 1124 INGENIC_PIN_FUNCTION("i2c1", jz4760_i2c1), 1125 INGENIC_PIN_FUNCTION("cim", jz4760_cim), 1126 INGENIC_PIN_FUNCTION("lcd", jz4760_lcd), 1127 INGENIC_PIN_FUNCTION("pwm0", jz4760_pwm0), 1128 INGENIC_PIN_FUNCTION("pwm1", jz4760_pwm1), 1129 INGENIC_PIN_FUNCTION("pwm2", jz4760_pwm2), 1130 INGENIC_PIN_FUNCTION("pwm3", jz4760_pwm3), 1131 INGENIC_PIN_FUNCTION("pwm4", jz4760_pwm4), 1132 INGENIC_PIN_FUNCTION("pwm5", jz4760_pwm5), 1133 INGENIC_PIN_FUNCTION("pwm6", jz4760_pwm6), 1134 INGENIC_PIN_FUNCTION("pwm7", jz4760_pwm7), 1135 INGENIC_PIN_FUNCTION("otg", jz4760_otg), 1136 }; 1137 1138 static const struct ingenic_chip_info jz4760_chip_info = { 1139 .num_chips = 6, 1140 .reg_offset = 0x100, 1141 .version = ID_JZ4760, 1142 .groups = jz4760_groups, 1143 .num_groups = ARRAY_SIZE(jz4760_groups), 1144 .functions = jz4760_functions, 1145 .num_functions = ARRAY_SIZE(jz4760_functions), 1146 .pull_ups = jz4760_pull_ups, 1147 .pull_downs = jz4760_pull_downs, 1148 }; 1149 1150 static const u32 jz4770_pull_ups[6] = { 1151 0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f, 1152 }; 1153 1154 static const u32 jz4770_pull_downs[6] = { 1155 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0, 1156 }; 1157 1158 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; 1159 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 1160 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, }; 1161 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 1162 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, }; 1163 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 1164 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; 1165 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; 1166 static int jz4770_ssi0_dt_a_pins[] = { 0x15, }; 1167 static int jz4770_ssi0_dt_b_pins[] = { 0x35, }; 1168 static int jz4770_ssi0_dt_d_pins[] = { 0x75, }; 1169 static int jz4770_ssi0_dt_e_pins[] = { 0x91, }; 1170 static int jz4770_ssi0_dr_a_pins[] = { 0x14, }; 1171 static int jz4770_ssi0_dr_b_pins[] = { 0x34, }; 1172 static int jz4770_ssi0_dr_d_pins[] = { 0x74, }; 1173 static int jz4770_ssi0_dr_e_pins[] = { 0x8e, }; 1174 static int jz4770_ssi0_clk_a_pins[] = { 0x12, }; 1175 static int jz4770_ssi0_clk_b_pins[] = { 0x3c, }; 1176 static int jz4770_ssi0_clk_d_pins[] = { 0x78, }; 1177 static int jz4770_ssi0_clk_e_pins[] = { 0x8f, }; 1178 static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, }; 1179 static int jz4770_ssi0_gpc_d_pins[] = { 0x76, }; 1180 static int jz4770_ssi0_gpc_e_pins[] = { 0x93, }; 1181 static int jz4770_ssi0_ce0_a_pins[] = { 0x13, }; 1182 static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, }; 1183 static int jz4770_ssi0_ce0_d_pins[] = { 0x79, }; 1184 static int jz4770_ssi0_ce0_e_pins[] = { 0x90, }; 1185 static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, }; 1186 static int jz4770_ssi0_ce1_d_pins[] = { 0x77, }; 1187 static int jz4770_ssi0_ce1_e_pins[] = { 0x92, }; 1188 static int jz4770_ssi1_dt_b_pins[] = { 0x35, }; 1189 static int jz4770_ssi1_dt_d_pins[] = { 0x75, }; 1190 static int jz4770_ssi1_dt_e_pins[] = { 0x91, }; 1191 static int jz4770_ssi1_dr_b_pins[] = { 0x34, }; 1192 static int jz4770_ssi1_dr_d_pins[] = { 0x74, }; 1193 static int jz4770_ssi1_dr_e_pins[] = { 0x8e, }; 1194 static int jz4770_ssi1_clk_b_pins[] = { 0x3c, }; 1195 static int jz4770_ssi1_clk_d_pins[] = { 0x78, }; 1196 static int jz4770_ssi1_clk_e_pins[] = { 0x8f, }; 1197 static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, }; 1198 static int jz4770_ssi1_gpc_d_pins[] = { 0x76, }; 1199 static int jz4770_ssi1_gpc_e_pins[] = { 0x93, }; 1200 static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, }; 1201 static int jz4770_ssi1_ce0_d_pins[] = { 0x79, }; 1202 static int jz4770_ssi1_ce0_e_pins[] = { 0x90, }; 1203 static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, }; 1204 static int jz4770_ssi1_ce1_d_pins[] = { 0x77, }; 1205 static int jz4770_ssi1_ce1_e_pins[] = { 0x92, }; 1206 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 1207 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 1208 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1209 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1210 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1211 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 1212 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 1213 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1214 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1215 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1216 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 1217 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 1218 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1219 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1220 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1221 static int jz4770_nemc_8bit_data_pins[] = { 1222 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1223 }; 1224 static int jz4770_nemc_16bit_data_pins[] = { 1225 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1226 }; 1227 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 1228 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 1229 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, }; 1230 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 1231 static int jz4770_nemc_wait_pins[] = { 0x1b, }; 1232 static int jz4770_nemc_cs1_pins[] = { 0x15, }; 1233 static int jz4770_nemc_cs2_pins[] = { 0x16, }; 1234 static int jz4770_nemc_cs3_pins[] = { 0x17, }; 1235 static int jz4770_nemc_cs4_pins[] = { 0x18, }; 1236 static int jz4770_nemc_cs5_pins[] = { 0x19, }; 1237 static int jz4770_nemc_cs6_pins[] = { 0x1a, }; 1238 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, }; 1239 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, }; 1240 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, }; 1241 static int jz4770_cim_8bit_pins[] = { 1242 0x26, 0x27, 0x28, 0x29, 1243 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 1244 }; 1245 static int jz4770_cim_12bit_pins[] = { 1246 0x32, 0x33, 0xb0, 0xb1, 1247 }; 1248 static int jz4770_lcd_8bit_pins[] = { 1249 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, 1250 0x48, 0x52, 0x53, 1251 }; 1252 static int jz4770_lcd_16bit_pins[] = { 1253 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 1254 }; 1255 static int jz4770_lcd_18bit_pins[] = { 1256 0x5a, 0x5b, 1257 }; 1258 static int jz4770_lcd_24bit_pins[] = { 1259 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 1260 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 1261 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 1262 0x58, 0x59, 0x5a, 0x5b, 1263 }; 1264 static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 1265 static int jz4770_lcd_generic_pins[] = { 0x49, }; 1266 static int jz4770_pwm_pwm0_pins[] = { 0x80, }; 1267 static int jz4770_pwm_pwm1_pins[] = { 0x81, }; 1268 static int jz4770_pwm_pwm2_pins[] = { 0x82, }; 1269 static int jz4770_pwm_pwm3_pins[] = { 0x83, }; 1270 static int jz4770_pwm_pwm4_pins[] = { 0x84, }; 1271 static int jz4770_pwm_pwm5_pins[] = { 0x85, }; 1272 static int jz4770_pwm_pwm6_pins[] = { 0x6a, }; 1273 static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; 1274 static int jz4770_mac_rmii_pins[] = { 1275 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 1276 }; 1277 static int jz4770_mac_mii_pins[] = { 1278 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, 1279 }; 1280 1281 static const struct group_desc jz4770_groups[] = { 1282 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 1283 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 1284 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 1285 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 1286 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0), 1287 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0), 1288 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 1289 jz4760_uart3_data_funcs), 1290 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 1291 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2), 1292 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1), 1293 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1), 1294 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 1295 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1), 1296 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1), 1297 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1), 1298 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 1299 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2), 1300 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1), 1301 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1), 1302 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 1303 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1), 1304 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1), 1305 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 1306 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2), 1307 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1), 1308 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1), 1309 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 1310 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1), 1311 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1), 1312 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 1313 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2), 1314 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2), 1315 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 1316 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2), 1317 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2), 1318 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 1319 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2), 1320 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2), 1321 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 1322 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2), 1323 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2), 1324 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 1325 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2), 1326 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2), 1327 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 1328 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2), 1329 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2), 1330 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 1331 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 1332 jz4760_mmc0_1bit_a_funcs), 1333 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 1334 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 1335 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 1336 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0), 1337 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 1338 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 1339 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 1340 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 1341 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1), 1342 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 1343 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 1344 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 1345 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 1346 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2), 1347 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0), 1348 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0), 1349 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 1350 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 1351 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 1352 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 1353 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 1354 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 1355 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 1356 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 1357 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 1358 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 1359 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 1360 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 1361 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 1362 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 1363 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0), 1364 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 1365 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), 1366 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), 1367 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), 1368 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 1369 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), 1370 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), 1371 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 1372 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 1373 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 1374 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 1375 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 1376 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 1377 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 1378 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 1379 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0), 1380 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0), 1381 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), 1382 }; 1383 1384 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1385 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1386 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1387 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 1388 static const char *jz4770_ssi0_groups[] = { 1389 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1390 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1391 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", 1392 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1393 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1394 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1395 }; 1396 static const char *jz4770_ssi1_groups[] = { 1397 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1398 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1399 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1400 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1401 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1402 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1403 }; 1404 static const char *jz4770_mmc0_groups[] = { 1405 "mmc0-1bit-a", "mmc0-4bit-a", 1406 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 1407 }; 1408 static const char *jz4770_mmc1_groups[] = { 1409 "mmc1-1bit-d", "mmc1-4bit-d", 1410 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 1411 }; 1412 static const char *jz4770_mmc2_groups[] = { 1413 "mmc2-1bit-b", "mmc2-4bit-b", 1414 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 1415 }; 1416 static const char *jz4770_nemc_groups[] = { 1417 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1418 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1419 }; 1420 static const char *jz4770_cs1_groups[] = { "nemc-cs1", }; 1421 static const char *jz4770_cs2_groups[] = { "nemc-cs2", }; 1422 static const char *jz4770_cs3_groups[] = { "nemc-cs3", }; 1423 static const char *jz4770_cs4_groups[] = { "nemc-cs4", }; 1424 static const char *jz4770_cs5_groups[] = { "nemc-cs5", }; 1425 static const char *jz4770_cs6_groups[] = { "nemc-cs6", }; 1426 static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; 1427 static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; 1428 static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; 1429 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 1430 static const char *jz4770_lcd_groups[] = { 1431 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1432 "lcd-special", "lcd-generic", 1433 }; 1434 static const char *jz4770_pwm0_groups[] = { "pwm0", }; 1435 static const char *jz4770_pwm1_groups[] = { "pwm1", }; 1436 static const char *jz4770_pwm2_groups[] = { "pwm2", }; 1437 static const char *jz4770_pwm3_groups[] = { "pwm3", }; 1438 static const char *jz4770_pwm4_groups[] = { "pwm4", }; 1439 static const char *jz4770_pwm5_groups[] = { "pwm5", }; 1440 static const char *jz4770_pwm6_groups[] = { "pwm6", }; 1441 static const char *jz4770_pwm7_groups[] = { "pwm7", }; 1442 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", }; 1443 1444 static const struct pinfunction jz4770_functions[] = { 1445 INGENIC_PIN_FUNCTION("uart0", jz4770_uart0), 1446 INGENIC_PIN_FUNCTION("uart1", jz4770_uart1), 1447 INGENIC_PIN_FUNCTION("uart2", jz4770_uart2), 1448 INGENIC_PIN_FUNCTION("uart3", jz4770_uart3), 1449 INGENIC_PIN_FUNCTION("ssi0", jz4770_ssi0), 1450 INGENIC_PIN_FUNCTION("ssi1", jz4770_ssi1), 1451 INGENIC_PIN_FUNCTION("mmc0", jz4770_mmc0), 1452 INGENIC_PIN_FUNCTION("mmc1", jz4770_mmc1), 1453 INGENIC_PIN_FUNCTION("mmc2", jz4770_mmc2), 1454 INGENIC_PIN_FUNCTION("nemc", jz4770_nemc), 1455 INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1), 1456 INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2), 1457 INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3), 1458 INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4), 1459 INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5), 1460 INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6), 1461 INGENIC_PIN_FUNCTION("i2c0", jz4770_i2c0), 1462 INGENIC_PIN_FUNCTION("i2c1", jz4770_i2c1), 1463 INGENIC_PIN_FUNCTION("i2c2", jz4770_i2c2), 1464 INGENIC_PIN_FUNCTION("cim", jz4770_cim), 1465 INGENIC_PIN_FUNCTION("lcd", jz4770_lcd), 1466 INGENIC_PIN_FUNCTION("pwm0", jz4770_pwm0), 1467 INGENIC_PIN_FUNCTION("pwm1", jz4770_pwm1), 1468 INGENIC_PIN_FUNCTION("pwm2", jz4770_pwm2), 1469 INGENIC_PIN_FUNCTION("pwm3", jz4770_pwm3), 1470 INGENIC_PIN_FUNCTION("pwm4", jz4770_pwm4), 1471 INGENIC_PIN_FUNCTION("pwm5", jz4770_pwm5), 1472 INGENIC_PIN_FUNCTION("pwm6", jz4770_pwm6), 1473 INGENIC_PIN_FUNCTION("pwm7", jz4770_pwm7), 1474 INGENIC_PIN_FUNCTION("mac", jz4770_mac), 1475 INGENIC_PIN_FUNCTION("otg", jz4760_otg), 1476 }; 1477 1478 static const struct ingenic_chip_info jz4770_chip_info = { 1479 .num_chips = 6, 1480 .reg_offset = 0x100, 1481 .version = ID_JZ4770, 1482 .groups = jz4770_groups, 1483 .num_groups = ARRAY_SIZE(jz4770_groups), 1484 .functions = jz4770_functions, 1485 .num_functions = ARRAY_SIZE(jz4770_functions), 1486 .pull_ups = jz4770_pull_ups, 1487 .pull_downs = jz4770_pull_downs, 1488 }; 1489 1490 static const u32 jz4775_pull_ups[7] = { 1491 0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0, 1492 }; 1493 1494 static const u32 jz4775_pull_downs[7] = { 1495 0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00, 1496 }; 1497 1498 static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, }; 1499 static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 1500 static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, }; 1501 static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 1502 static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, }; 1503 static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, }; 1504 static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, }; 1505 static int jz4775_ssi_dt_a_pins[] = { 0x13, }; 1506 static int jz4775_ssi_dt_d_pins[] = { 0x75, }; 1507 static int jz4775_ssi_dr_a_pins[] = { 0x14, }; 1508 static int jz4775_ssi_dr_d_pins[] = { 0x74, }; 1509 static int jz4775_ssi_clk_a_pins[] = { 0x12, }; 1510 static int jz4775_ssi_clk_d_pins[] = { 0x78, }; 1511 static int jz4775_ssi_gpc_pins[] = { 0x76, }; 1512 static int jz4775_ssi_ce0_a_pins[] = { 0x17, }; 1513 static int jz4775_ssi_ce0_d_pins[] = { 0x79, }; 1514 static int jz4775_ssi_ce1_pins[] = { 0x77, }; 1515 static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 1516 static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 1517 static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, }; 1518 static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1519 static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1520 static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 1521 static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 1522 static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1523 static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1524 static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 1525 static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 1526 static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1527 static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1528 static int jz4775_nemc_8bit_data_pins[] = { 1529 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1530 }; 1531 static int jz4775_nemc_16bit_data_pins[] = { 1532 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1, 1533 }; 1534 static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 1535 static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 1536 static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, }; 1537 static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 1538 static int jz4775_nemc_wait_pins[] = { 0x1b, }; 1539 static int jz4775_nemc_cs1_pins[] = { 0x15, }; 1540 static int jz4775_nemc_cs2_pins[] = { 0x16, }; 1541 static int jz4775_nemc_cs3_pins[] = { 0x17, }; 1542 static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, }; 1543 static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, }; 1544 static int jz4775_i2c2_pins[] = { 0x80, 0x83, }; 1545 static int jz4775_i2s_data_tx_pins[] = { 0xa3, }; 1546 static int jz4775_i2s_data_rx_pins[] = { 0xa2, }; 1547 static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, }; 1548 static int jz4775_i2s_sysclk_pins[] = { 0x83, }; 1549 static int jz4775_dmic_pins[] = { 0xaa, 0xab, }; 1550 static int jz4775_cim_pins[] = { 1551 0x26, 0x27, 0x28, 0x29, 1552 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 1553 }; 1554 static int jz4775_lcd_8bit_pins[] = { 1555 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, 1556 0x48, 0x52, 0x53, 1557 }; 1558 static int jz4775_lcd_16bit_pins[] = { 1559 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 1560 }; 1561 static int jz4775_lcd_18bit_pins[] = { 1562 0x5a, 0x5b, 1563 }; 1564 static int jz4775_lcd_24bit_pins[] = { 1565 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, 1566 }; 1567 static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 1568 static int jz4775_lcd_generic_pins[] = { 0x49, }; 1569 static int jz4775_pwm_pwm0_pins[] = { 0x80, }; 1570 static int jz4775_pwm_pwm1_pins[] = { 0x81, }; 1571 static int jz4775_pwm_pwm2_pins[] = { 0x82, }; 1572 static int jz4775_pwm_pwm3_pins[] = { 0x83, }; 1573 static int jz4775_mac_rmii_pins[] = { 1574 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 1575 }; 1576 static int jz4775_mac_mii_pins[] = { 1577 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, 1578 }; 1579 static int jz4775_mac_rgmii_pins[] = { 1580 0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4, 1581 0xad, 0xae, 0xa7, 0xa6, 1582 }; 1583 static int jz4775_mac_gmii_pins[] = { 1584 0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 1585 0xa8, 0x28, 0x24, 0xaf, 1586 }; 1587 static int jz4775_otg_pins[] = { 0x8a, }; 1588 1589 static u8 jz4775_uart3_data_funcs[] = { 0, 1, }; 1590 static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, }; 1591 static u8 jz4775_mac_rgmii_funcs[] = { 1592 0, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1593 0, 0, 0, 0, 1594 }; 1595 static u8 jz4775_mac_gmii_funcs[] = { 1596 1, 1, 1, 1, 1, 1, 1, 1, 1597 0, 1, 1, 0, 1598 }; 1599 1600 static const struct group_desc jz4775_groups[] = { 1601 INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0), 1602 INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0), 1603 INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0), 1604 INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0), 1605 INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2), 1606 INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1), 1607 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data, 1608 jz4775_uart3_data_funcs), 1609 INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2), 1610 INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1), 1611 INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2), 1612 INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1), 1613 INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2), 1614 INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1), 1615 INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1), 1616 INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2), 1617 INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1), 1618 INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1), 1619 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1), 1620 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1), 1621 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1), 1622 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0), 1623 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0), 1624 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0), 1625 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0), 1626 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1), 1627 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1), 1628 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0), 1629 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0), 1630 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2), 1631 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2), 1632 INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0), 1633 INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1), 1634 INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0), 1635 INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0), 1636 INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0), 1637 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0), 1638 INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0), 1639 INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0), 1640 INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0), 1641 INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0), 1642 INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0), 1643 INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0), 1644 INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1), 1645 INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1), 1646 INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1), 1647 INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1), 1648 INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2), 1649 INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1), 1650 INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0), 1651 INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0), 1652 INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0), 1653 INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0), 1654 INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0), 1655 INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0), 1656 INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1), 1657 INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0), 1658 INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0), 1659 INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0), 1660 INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0), 1661 INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0), 1662 INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii, 1663 jz4775_mac_mii_funcs), 1664 INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii, 1665 jz4775_mac_rgmii_funcs), 1666 INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii, 1667 jz4775_mac_gmii_funcs), 1668 INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0), 1669 }; 1670 1671 static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1672 static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1673 static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", }; 1674 static const char *jz4775_uart3_groups[] = { "uart3-data", }; 1675 static const char *jz4775_ssi_groups[] = { 1676 "ssi-dt-a", "ssi-dt-d", 1677 "ssi-dr-a", "ssi-dr-d", 1678 "ssi-clk-a", "ssi-clk-d", 1679 "ssi-gpc", 1680 "ssi-ce0-a", "ssi-ce0-d", 1681 "ssi-ce1", 1682 }; 1683 static const char *jz4775_mmc0_groups[] = { 1684 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1685 "mmc0-1bit-e", "mmc0-4bit-e", 1686 }; 1687 static const char *jz4775_mmc1_groups[] = { 1688 "mmc1-1bit-d", "mmc1-4bit-d", 1689 "mmc1-1bit-e", "mmc1-4bit-e", 1690 }; 1691 static const char *jz4775_mmc2_groups[] = { 1692 "mmc2-1bit-b", "mmc2-4bit-b", 1693 "mmc2-1bit-e", "mmc2-4bit-e", 1694 }; 1695 static const char *jz4775_nemc_groups[] = { 1696 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1697 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1698 }; 1699 static const char *jz4775_cs1_groups[] = { "nemc-cs1", }; 1700 static const char *jz4775_cs2_groups[] = { "nemc-cs2", }; 1701 static const char *jz4775_cs3_groups[] = { "nemc-cs3", }; 1702 static const char *jz4775_i2c0_groups[] = { "i2c0-data", }; 1703 static const char *jz4775_i2c1_groups[] = { "i2c1-data", }; 1704 static const char *jz4775_i2c2_groups[] = { "i2c2-data", }; 1705 static const char *jz4775_i2s_groups[] = { 1706 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 1707 }; 1708 static const char *jz4775_dmic_groups[] = { "dmic", }; 1709 static const char *jz4775_cim_groups[] = { "cim-data", }; 1710 static const char *jz4775_lcd_groups[] = { 1711 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1712 "lcd-special", "lcd-generic", 1713 }; 1714 static const char *jz4775_pwm0_groups[] = { "pwm0", }; 1715 static const char *jz4775_pwm1_groups[] = { "pwm1", }; 1716 static const char *jz4775_pwm2_groups[] = { "pwm2", }; 1717 static const char *jz4775_pwm3_groups[] = { "pwm3", }; 1718 static const char *jz4775_mac_groups[] = { 1719 "mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii", 1720 }; 1721 static const char *jz4775_otg_groups[] = { "otg-vbus", }; 1722 1723 static const struct pinfunction jz4775_functions[] = { 1724 INGENIC_PIN_FUNCTION("uart0", jz4775_uart0), 1725 INGENIC_PIN_FUNCTION("uart1", jz4775_uart1), 1726 INGENIC_PIN_FUNCTION("uart2", jz4775_uart2), 1727 INGENIC_PIN_FUNCTION("uart3", jz4775_uart3), 1728 INGENIC_PIN_FUNCTION("ssi", jz4775_ssi), 1729 INGENIC_PIN_FUNCTION("mmc0", jz4775_mmc0), 1730 INGENIC_PIN_FUNCTION("mmc1", jz4775_mmc1), 1731 INGENIC_PIN_FUNCTION("mmc2", jz4775_mmc2), 1732 INGENIC_PIN_FUNCTION("nemc", jz4775_nemc), 1733 INGENIC_PIN_FUNCTION("nemc-cs1", jz4775_cs1), 1734 INGENIC_PIN_FUNCTION("nemc-cs2", jz4775_cs2), 1735 INGENIC_PIN_FUNCTION("nemc-cs3", jz4775_cs3), 1736 INGENIC_PIN_FUNCTION("i2c0", jz4775_i2c0), 1737 INGENIC_PIN_FUNCTION("i2c1", jz4775_i2c1), 1738 INGENIC_PIN_FUNCTION("i2c2", jz4775_i2c2), 1739 INGENIC_PIN_FUNCTION("i2s", jz4775_i2s), 1740 INGENIC_PIN_FUNCTION("dmic", jz4775_dmic), 1741 INGENIC_PIN_FUNCTION("cim", jz4775_cim), 1742 INGENIC_PIN_FUNCTION("lcd", jz4775_lcd), 1743 INGENIC_PIN_FUNCTION("pwm0", jz4775_pwm0), 1744 INGENIC_PIN_FUNCTION("pwm1", jz4775_pwm1), 1745 INGENIC_PIN_FUNCTION("pwm2", jz4775_pwm2), 1746 INGENIC_PIN_FUNCTION("pwm3", jz4775_pwm3), 1747 INGENIC_PIN_FUNCTION("mac", jz4775_mac), 1748 INGENIC_PIN_FUNCTION("otg", jz4775_otg), 1749 }; 1750 1751 static const struct ingenic_chip_info jz4775_chip_info = { 1752 .num_chips = 7, 1753 .reg_offset = 0x100, 1754 .version = ID_JZ4775, 1755 .groups = jz4775_groups, 1756 .num_groups = ARRAY_SIZE(jz4775_groups), 1757 .functions = jz4775_functions, 1758 .num_functions = ARRAY_SIZE(jz4775_functions), 1759 .pull_ups = jz4775_pull_ups, 1760 .pull_downs = jz4775_pull_downs, 1761 }; 1762 1763 static const u32 jz4780_pull_ups[6] = { 1764 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f, 1765 }; 1766 1767 static const u32 jz4780_pull_downs[6] = { 1768 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 1769 }; 1770 1771 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; 1772 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; 1773 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; 1774 static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, }; 1775 static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, }; 1776 static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, }; 1777 static int jz4780_ssi0_dt_b_pins[] = { 0x3d, }; 1778 static int jz4780_ssi0_dt_d_pins[] = { 0x79, }; 1779 static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, }; 1780 static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, }; 1781 static int jz4780_ssi0_dr_b_pins[] = { 0x34, }; 1782 static int jz4780_ssi0_dr_d_pins[] = { 0x74, }; 1783 static int jz4780_ssi0_clk_a_pins[] = { 0x12, }; 1784 static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, }; 1785 static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, }; 1786 static int jz4780_ssi0_clk_d_pins[] = { 0x78, }; 1787 static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, }; 1788 static int jz4780_ssi0_gpc_d_pins[] = { 0x76, }; 1789 static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, }; 1790 static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, }; 1791 static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, }; 1792 static int jz4780_ssi0_ce0_d_pins[] = { 0x77, }; 1793 static int jz4780_ssi0_ce1_b_pins[] = { 0x35, }; 1794 static int jz4780_ssi0_ce1_d_pins[] = { 0x75, }; 1795 static int jz4780_ssi1_dt_b_pins[] = { 0x3d, }; 1796 static int jz4780_ssi1_dt_d_pins[] = { 0x79, }; 1797 static int jz4780_ssi1_dr_b_pins[] = { 0x34, }; 1798 static int jz4780_ssi1_dr_d_pins[] = { 0x74, }; 1799 static int jz4780_ssi1_clk_b_pins[] = { 0x3c, }; 1800 static int jz4780_ssi1_clk_d_pins[] = { 0x78, }; 1801 static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, }; 1802 static int jz4780_ssi1_gpc_d_pins[] = { 0x76, }; 1803 static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, }; 1804 static int jz4780_ssi1_ce0_d_pins[] = { 0x77, }; 1805 static int jz4780_ssi1_ce1_b_pins[] = { 0x35, }; 1806 static int jz4780_ssi1_ce1_d_pins[] = { 0x75, }; 1807 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; 1808 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; 1809 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; 1810 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; 1811 static int jz4780_i2s_data_tx_pins[] = { 0x87, }; 1812 static int jz4780_i2s_data_rx_pins[] = { 0x86, }; 1813 static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, }; 1814 static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, }; 1815 static int jz4780_i2s_sysclk_pins[] = { 0x85, }; 1816 static int jz4780_dmic_pins[] = { 0x32, 0x33, }; 1817 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; 1818 1819 static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, }; 1820 1821 static const struct group_desc jz4780_groups[] = { 1822 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 1823 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 1824 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 1825 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 1826 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1), 1827 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1), 1828 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 1829 jz4760_uart3_data_funcs), 1830 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 1831 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2), 1832 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2), 1833 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2), 1834 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2), 1835 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1), 1836 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1), 1837 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 1838 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2), 1839 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2), 1840 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1), 1841 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1), 1842 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 1843 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2), 1844 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1), 1845 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1), 1846 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1), 1847 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 1848 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1), 1849 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1), 1850 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 1851 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2), 1852 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2), 1853 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1), 1854 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1), 1855 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 1856 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1), 1857 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1), 1858 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 1859 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2), 1860 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2), 1861 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 1862 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2), 1863 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2), 1864 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 1865 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2), 1866 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2), 1867 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 1868 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2), 1869 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2), 1870 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 1871 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2), 1872 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2), 1873 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 1874 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2), 1875 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2), 1876 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 1877 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 1878 jz4760_mmc0_1bit_a_funcs), 1879 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 1880 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1), 1881 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 1882 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 1883 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 1884 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 1885 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 1886 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 1887 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 1888 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 1889 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 1890 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 1891 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0), 1892 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 1893 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 1894 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 1895 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 1896 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 1897 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 1898 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 1899 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 1900 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 1901 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 1902 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 1903 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 1904 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 1905 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 1906 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1), 1907 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1), 1908 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1), 1909 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0), 1910 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0), 1911 INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx, 1912 jz4780_i2s_clk_txrx_funcs), 1913 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1), 1914 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2), 1915 INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1), 1916 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0), 1917 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0), 1918 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 1919 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), 1920 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), 1921 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), 1922 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 1923 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), 1924 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), 1925 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 1926 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 1927 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 1928 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 1929 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 1930 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 1931 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 1932 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 1933 }; 1934 1935 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1936 static const char *jz4780_uart4_groups[] = { "uart4-data", }; 1937 static const char *jz4780_ssi0_groups[] = { 1938 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1939 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1940 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e", 1941 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1942 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1943 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1944 }; 1945 static const char *jz4780_ssi1_groups[] = { 1946 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1947 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1948 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1949 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1950 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1951 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1952 }; 1953 static const char *jz4780_mmc0_groups[] = { 1954 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1955 "mmc0-1bit-e", "mmc0-4bit-e", 1956 }; 1957 static const char *jz4780_mmc1_groups[] = { 1958 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e", 1959 }; 1960 static const char *jz4780_mmc2_groups[] = { 1961 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e", 1962 }; 1963 static const char *jz4780_nemc_groups[] = { 1964 "nemc-data", "nemc-cle-ale", "nemc-addr", 1965 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1966 }; 1967 static const char *jz4780_i2c3_groups[] = { "i2c3-data", }; 1968 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; 1969 static const char *jz4780_i2s_groups[] = { 1970 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 1971 }; 1972 static const char *jz4780_dmic_groups[] = { "dmic", }; 1973 static const char *jz4780_cim_groups[] = { "cim-data", }; 1974 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", }; 1975 1976 static const struct pinfunction jz4780_functions[] = { 1977 INGENIC_PIN_FUNCTION("uart0", jz4770_uart0), 1978 INGENIC_PIN_FUNCTION("uart1", jz4770_uart1), 1979 INGENIC_PIN_FUNCTION("uart2", jz4780_uart2), 1980 INGENIC_PIN_FUNCTION("uart3", jz4770_uart3), 1981 INGENIC_PIN_FUNCTION("uart4", jz4780_uart4), 1982 INGENIC_PIN_FUNCTION("ssi0", jz4780_ssi0), 1983 INGENIC_PIN_FUNCTION("ssi1", jz4780_ssi1), 1984 INGENIC_PIN_FUNCTION("mmc0", jz4780_mmc0), 1985 INGENIC_PIN_FUNCTION("mmc1", jz4780_mmc1), 1986 INGENIC_PIN_FUNCTION("mmc2", jz4780_mmc2), 1987 INGENIC_PIN_FUNCTION("nemc", jz4780_nemc), 1988 INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1), 1989 INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2), 1990 INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3), 1991 INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4), 1992 INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5), 1993 INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6), 1994 INGENIC_PIN_FUNCTION("i2c0", jz4770_i2c0), 1995 INGENIC_PIN_FUNCTION("i2c1", jz4770_i2c1), 1996 INGENIC_PIN_FUNCTION("i2c2", jz4770_i2c2), 1997 INGENIC_PIN_FUNCTION("i2c3", jz4780_i2c3), 1998 INGENIC_PIN_FUNCTION("i2c4", jz4780_i2c4), 1999 INGENIC_PIN_FUNCTION("i2s", jz4780_i2s), 2000 INGENIC_PIN_FUNCTION("dmic", jz4780_dmic), 2001 INGENIC_PIN_FUNCTION("cim", jz4780_cim), 2002 INGENIC_PIN_FUNCTION("lcd", jz4770_lcd), 2003 INGENIC_PIN_FUNCTION("pwm0", jz4770_pwm0), 2004 INGENIC_PIN_FUNCTION("pwm1", jz4770_pwm1), 2005 INGENIC_PIN_FUNCTION("pwm2", jz4770_pwm2), 2006 INGENIC_PIN_FUNCTION("pwm3", jz4770_pwm3), 2007 INGENIC_PIN_FUNCTION("pwm4", jz4770_pwm4), 2008 INGENIC_PIN_FUNCTION("pwm5", jz4770_pwm5), 2009 INGENIC_PIN_FUNCTION("pwm6", jz4770_pwm6), 2010 INGENIC_PIN_FUNCTION("pwm7", jz4770_pwm7), 2011 INGENIC_PIN_FUNCTION("hdmi-ddc", jz4780_hdmi_ddc), 2012 }; 2013 2014 static const struct ingenic_chip_info jz4780_chip_info = { 2015 .num_chips = 6, 2016 .reg_offset = 0x100, 2017 .version = ID_JZ4780, 2018 .groups = jz4780_groups, 2019 .num_groups = ARRAY_SIZE(jz4780_groups), 2020 .functions = jz4780_functions, 2021 .num_functions = ARRAY_SIZE(jz4780_functions), 2022 .pull_ups = jz4780_pull_ups, 2023 .pull_downs = jz4780_pull_downs, 2024 }; 2025 2026 static const u32 x1000_pull_ups[4] = { 2027 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, 2028 }; 2029 2030 static const u32 x1000_pull_downs[4] = { 2031 0x00000000, 0x02000000, 0x02000000, 0x00000000, 2032 }; 2033 2034 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; 2035 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 2036 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; 2037 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; 2038 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; 2039 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; 2040 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; 2041 static int x1000_sfc_data_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, }; 2042 static int x1000_sfc_clk_pins[] = { 0x1a, }; 2043 static int x1000_sfc_ce_pins[] = { 0x1b, }; 2044 static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; 2045 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; 2046 static int x1000_ssi_dt_d_pins[] = { 0x62, }; 2047 static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; 2048 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; 2049 static int x1000_ssi_dr_d_pins[] = { 0x63, }; 2050 static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; 2051 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; 2052 static int x1000_ssi_clk_d_pins[] = { 0x60, }; 2053 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; 2054 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; 2055 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; 2056 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; 2057 static int x1000_ssi_ce0_d_pins[] = { 0x61, }; 2058 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; 2059 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; 2060 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; 2061 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; 2062 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; 2063 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; 2064 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; 2065 static int x1000_emc_8bit_data_pins[] = { 2066 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2067 }; 2068 static int x1000_emc_16bit_data_pins[] = { 2069 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 2070 }; 2071 static int x1000_emc_addr_pins[] = { 2072 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2073 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 2074 }; 2075 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; 2076 static int x1000_emc_wait_pins[] = { 0x34, }; 2077 static int x1000_emc_cs1_pins[] = { 0x32, }; 2078 static int x1000_emc_cs2_pins[] = { 0x33, }; 2079 static int x1000_i2c0_pins[] = { 0x38, 0x37, }; 2080 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; 2081 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; 2082 static int x1000_i2c2_pins[] = { 0x61, 0x60, }; 2083 static int x1000_i2s_data_tx_pins[] = { 0x24, }; 2084 static int x1000_i2s_data_rx_pins[] = { 0x23, }; 2085 static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 2086 static int x1000_i2s_sysclk_pins[] = { 0x20, }; 2087 static int x1000_dmic_if0_pins[] = { 0x35, 0x36, }; 2088 static int x1000_dmic_if1_pins[] = { 0x25, }; 2089 static int x1000_cim_pins[] = { 2090 0x08, 0x09, 0x0a, 0x0b, 2091 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 2092 }; 2093 static int x1000_lcd_8bit_pins[] = { 2094 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2095 0x30, 0x31, 0x32, 0x33, 0x34, 2096 }; 2097 static int x1000_lcd_16bit_pins[] = { 2098 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 2099 }; 2100 static int x1000_pwm_pwm0_pins[] = { 0x59, }; 2101 static int x1000_pwm_pwm1_pins[] = { 0x5a, }; 2102 static int x1000_pwm_pwm2_pins[] = { 0x5b, }; 2103 static int x1000_pwm_pwm3_pins[] = { 0x26, }; 2104 static int x1000_pwm_pwm4_pins[] = { 0x58, }; 2105 static int x1000_mac_pins[] = { 2106 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, 2107 }; 2108 2109 static const struct group_desc x1000_groups[] = { 2110 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0), 2111 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0), 2112 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2), 2113 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1), 2114 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1), 2115 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2), 2116 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0), 2117 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1), 2118 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1), 2119 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1), 2120 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2), 2121 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2), 2122 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0), 2123 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2), 2124 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2), 2125 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0), 2126 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2), 2127 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2), 2128 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0), 2129 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2), 2130 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2), 2131 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2), 2132 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2), 2133 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0), 2134 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2), 2135 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2), 2136 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1), 2137 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1), 2138 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1), 2139 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0), 2140 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0), 2141 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0), 2142 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0), 2143 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0), 2144 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0), 2145 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0), 2146 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0), 2147 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0), 2148 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0), 2149 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2), 2150 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0), 2151 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1), 2152 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1), 2153 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1), 2154 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1), 2155 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1), 2156 INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0), 2157 INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1), 2158 INGENIC_PIN_GROUP("cim-data", x1000_cim, 2), 2159 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1), 2160 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1), 2161 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0), 2162 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1), 2163 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1), 2164 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2), 2165 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0), 2166 INGENIC_PIN_GROUP("mac", x1000_mac, 1), 2167 }; 2168 2169 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2170 static const char *x1000_uart1_groups[] = { 2171 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 2172 }; 2173 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 2174 static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", }; 2175 static const char *x1000_ssi_groups[] = { 2176 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", 2177 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", 2178 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d", 2179 "ssi-gpc-a-20", "ssi-gpc-a-31", 2180 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d", 2181 "ssi-ce1-a-21", "ssi-ce1-a-30", 2182 }; 2183 static const char *x1000_mmc0_groups[] = { 2184 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 2185 }; 2186 static const char *x1000_mmc1_groups[] = { 2187 "mmc1-1bit", "mmc1-4bit", 2188 }; 2189 static const char *x1000_emc_groups[] = { 2190 "emc-8bit-data", "emc-16bit-data", 2191 "emc-addr", "emc-rd-we", "emc-wait", 2192 }; 2193 static const char *x1000_cs1_groups[] = { "emc-cs1", }; 2194 static const char *x1000_cs2_groups[] = { "emc-cs2", }; 2195 static const char *x1000_i2c0_groups[] = { "i2c0-data", }; 2196 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 2197 static const char *x1000_i2c2_groups[] = { "i2c2-data", }; 2198 static const char *x1000_i2s_groups[] = { 2199 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 2200 }; 2201 static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", }; 2202 static const char *x1000_cim_groups[] = { "cim-data", }; 2203 static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", }; 2204 static const char *x1000_pwm0_groups[] = { "pwm0", }; 2205 static const char *x1000_pwm1_groups[] = { "pwm1", }; 2206 static const char *x1000_pwm2_groups[] = { "pwm2", }; 2207 static const char *x1000_pwm3_groups[] = { "pwm3", }; 2208 static const char *x1000_pwm4_groups[] = { "pwm4", }; 2209 static const char *x1000_mac_groups[] = { "mac", }; 2210 2211 static const struct pinfunction x1000_functions[] = { 2212 INGENIC_PIN_FUNCTION("uart0", x1000_uart0), 2213 INGENIC_PIN_FUNCTION("uart1", x1000_uart1), 2214 INGENIC_PIN_FUNCTION("uart2", x1000_uart2), 2215 INGENIC_PIN_FUNCTION("sfc", x1000_sfc), 2216 INGENIC_PIN_FUNCTION("ssi", x1000_ssi), 2217 INGENIC_PIN_FUNCTION("mmc0", x1000_mmc0), 2218 INGENIC_PIN_FUNCTION("mmc1", x1000_mmc1), 2219 INGENIC_PIN_FUNCTION("emc", x1000_emc), 2220 INGENIC_PIN_FUNCTION("emc-cs1", x1000_cs1), 2221 INGENIC_PIN_FUNCTION("emc-cs2", x1000_cs2), 2222 INGENIC_PIN_FUNCTION("i2c0", x1000_i2c0), 2223 INGENIC_PIN_FUNCTION("i2c1", x1000_i2c1), 2224 INGENIC_PIN_FUNCTION("i2c2", x1000_i2c2), 2225 INGENIC_PIN_FUNCTION("i2s", x1000_i2s), 2226 INGENIC_PIN_FUNCTION("dmic", x1000_dmic), 2227 INGENIC_PIN_FUNCTION("cim", x1000_cim), 2228 INGENIC_PIN_FUNCTION("lcd", x1000_lcd), 2229 INGENIC_PIN_FUNCTION("pwm0", x1000_pwm0), 2230 INGENIC_PIN_FUNCTION("pwm1", x1000_pwm1), 2231 INGENIC_PIN_FUNCTION("pwm2", x1000_pwm2), 2232 INGENIC_PIN_FUNCTION("pwm3", x1000_pwm3), 2233 INGENIC_PIN_FUNCTION("pwm4", x1000_pwm4), 2234 INGENIC_PIN_FUNCTION("mac", x1000_mac), 2235 }; 2236 2237 static const struct regmap_range x1000_access_ranges[] = { 2238 regmap_reg_range(0x000, 0x400 - 4), 2239 regmap_reg_range(0x700, 0x800 - 4), 2240 }; 2241 2242 /* shared with X1500 */ 2243 static const struct regmap_access_table x1000_access_table = { 2244 .yes_ranges = x1000_access_ranges, 2245 .n_yes_ranges = ARRAY_SIZE(x1000_access_ranges), 2246 }; 2247 2248 static const struct ingenic_chip_info x1000_chip_info = { 2249 .num_chips = 4, 2250 .reg_offset = 0x100, 2251 .version = ID_X1000, 2252 .groups = x1000_groups, 2253 .num_groups = ARRAY_SIZE(x1000_groups), 2254 .functions = x1000_functions, 2255 .num_functions = ARRAY_SIZE(x1000_functions), 2256 .pull_ups = x1000_pull_ups, 2257 .pull_downs = x1000_pull_downs, 2258 .access_table = &x1000_access_table, 2259 }; 2260 2261 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; 2262 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 2263 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; 2264 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; 2265 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; 2266 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; 2267 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; 2268 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; 2269 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; 2270 static int x1500_i2c0_pins[] = { 0x38, 0x37, }; 2271 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; 2272 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; 2273 static int x1500_i2c2_pins[] = { 0x61, 0x60, }; 2274 static int x1500_i2s_data_tx_pins[] = { 0x24, }; 2275 static int x1500_i2s_data_rx_pins[] = { 0x23, }; 2276 static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 2277 static int x1500_i2s_sysclk_pins[] = { 0x20, }; 2278 static int x1500_dmic_if0_pins[] = { 0x35, 0x36, }; 2279 static int x1500_dmic_if1_pins[] = { 0x25, }; 2280 static int x1500_cim_pins[] = { 2281 0x08, 0x09, 0x0a, 0x0b, 2282 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 2283 }; 2284 static int x1500_pwm_pwm0_pins[] = { 0x59, }; 2285 static int x1500_pwm_pwm1_pins[] = { 0x5a, }; 2286 static int x1500_pwm_pwm2_pins[] = { 0x5b, }; 2287 static int x1500_pwm_pwm3_pins[] = { 0x26, }; 2288 static int x1500_pwm_pwm4_pins[] = { 0x58, }; 2289 2290 static const struct group_desc x1500_groups[] = { 2291 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0), 2292 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0), 2293 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2), 2294 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1), 2295 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1), 2296 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2), 2297 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0), 2298 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1), 2299 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1), 2300 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1), 2301 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1), 2302 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1), 2303 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0), 2304 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2), 2305 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0), 2306 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1), 2307 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1), 2308 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1), 2309 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1), 2310 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1), 2311 INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0), 2312 INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1), 2313 INGENIC_PIN_GROUP("cim-data", x1500_cim, 2), 2314 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0), 2315 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1), 2316 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1), 2317 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2), 2318 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0), 2319 }; 2320 2321 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2322 static const char *x1500_uart1_groups[] = { 2323 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 2324 }; 2325 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 2326 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 2327 static const char *x1500_i2c0_groups[] = { "i2c0-data", }; 2328 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 2329 static const char *x1500_i2c2_groups[] = { "i2c2-data", }; 2330 static const char *x1500_i2s_groups[] = { 2331 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 2332 }; 2333 static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", }; 2334 static const char *x1500_cim_groups[] = { "cim-data", }; 2335 static const char *x1500_pwm0_groups[] = { "pwm0", }; 2336 static const char *x1500_pwm1_groups[] = { "pwm1", }; 2337 static const char *x1500_pwm2_groups[] = { "pwm2", }; 2338 static const char *x1500_pwm3_groups[] = { "pwm3", }; 2339 static const char *x1500_pwm4_groups[] = { "pwm4", }; 2340 2341 static const struct pinfunction x1500_functions[] = { 2342 INGENIC_PIN_FUNCTION("uart0", x1500_uart0), 2343 INGENIC_PIN_FUNCTION("uart1", x1500_uart1), 2344 INGENIC_PIN_FUNCTION("uart2", x1500_uart2), 2345 INGENIC_PIN_FUNCTION("sfc", x1000_sfc), 2346 INGENIC_PIN_FUNCTION("mmc", x1500_mmc), 2347 INGENIC_PIN_FUNCTION("i2c0", x1500_i2c0), 2348 INGENIC_PIN_FUNCTION("i2c1", x1500_i2c1), 2349 INGENIC_PIN_FUNCTION("i2c2", x1500_i2c2), 2350 INGENIC_PIN_FUNCTION("i2s", x1500_i2s), 2351 INGENIC_PIN_FUNCTION("dmic", x1500_dmic), 2352 INGENIC_PIN_FUNCTION("cim", x1500_cim), 2353 INGENIC_PIN_FUNCTION("pwm0", x1500_pwm0), 2354 INGENIC_PIN_FUNCTION("pwm1", x1500_pwm1), 2355 INGENIC_PIN_FUNCTION("pwm2", x1500_pwm2), 2356 INGENIC_PIN_FUNCTION("pwm3", x1500_pwm3), 2357 INGENIC_PIN_FUNCTION("pwm4", x1500_pwm4), 2358 }; 2359 2360 static const struct ingenic_chip_info x1500_chip_info = { 2361 .num_chips = 4, 2362 .reg_offset = 0x100, 2363 .version = ID_X1500, 2364 .groups = x1500_groups, 2365 .num_groups = ARRAY_SIZE(x1500_groups), 2366 .functions = x1500_functions, 2367 .num_functions = ARRAY_SIZE(x1500_functions), 2368 .pull_ups = x1000_pull_ups, 2369 .pull_downs = x1000_pull_downs, 2370 .access_table = &x1000_access_table, 2371 }; 2372 2373 static const u32 x1600_pull_ups[4] = { 2374 0xffffffff, 0xdffbf7bf, 0x987e0000, 0x0000003f, 2375 }; 2376 2377 static const u32 x1600_pull_downs[4] = { 2378 0x00000000, 0x00000000, 0x07000007, 0x00000000, 2379 }; 2380 2381 static int x1600_uart0_data_pins[] = { 0x27, 0x28, }; 2382 static int x1600_uart0_hwflow_pins[] = { 0x29, 0x2a, }; 2383 static int x1600_uart1_data_pins[] = { 0x23, 0x22, }; 2384 static int x1600_uart1_hwflow_pins[] = { 0x25, 0x24, }; 2385 static int x1600_uart2_data_a_pins[] = { 0x1f, 0x1e, }; 2386 static int x1600_uart2_data_b_pins[] = { 0x21, 0x20, }; 2387 static int x1600_uart3_data_b_pins[] = { 0x25, 0x24, }; 2388 static int x1600_uart3_data_d_pins[] = { 0x65, 0x64, }; 2389 static int x1600_sfc_pins[] = { 0x53, 0x54, 0x55, 0x56, 0x51, 0x52, 0x24, }; 2390 static int x1600_ssi_dt_a_pins[] = { 0x1e, }; 2391 static int x1600_ssi_dt_b_pins[] = { 0x2d, }; 2392 static int x1600_ssi_dr_a_pins[] = { 0x1d, }; 2393 static int x1600_ssi_dr_b_pins[] = { 0x2e, }; 2394 static int x1600_ssi_clk_a_pins[] = { 0x1f, }; 2395 static int x1600_ssi_clk_b_pins[] = { 0x2c, }; 2396 static int x1600_ssi_ce0_a_pins[] = { 0x1c, }; 2397 static int x1600_ssi_ce0_b_pins[] = { 0x31, }; 2398 static int x1600_ssi_ce1_a_pins[] = { 0x22, }; 2399 static int x1600_ssi_ce1_b_pins[] = { 0x30, }; 2400 static int x1600_mmc0_1bit_b_pins[] = { 0x2c, 0x2d, 0x2e, }; 2401 static int x1600_mmc0_4bit_b_pins[] = { 0x2f, 0x30, 0x31, }; 2402 static int x1600_mmc0_1bit_c_pins[] = { 0x51, 0x53, 0x54, }; 2403 static int x1600_mmc0_4bit_c_pins[] = { 0x56, 0x55, 0x52, }; 2404 static int x1600_mmc1_1bit_pins[] = { 0x60, 0x61, 0x62, }; 2405 static int x1600_mmc1_4bit_pins[] = { 0x63, 0x64, 0x65, }; 2406 static int x1600_i2c0_a_pins[] = { 0x1d, 0x1c, }; 2407 static int x1600_i2c0_b_pins[] = { 0x3f, 0x3e, }; 2408 static int x1600_i2c1_b_15_pins[] = { 0x30, 0x2f, }; 2409 static int x1600_i2c1_b_19_pins[] = { 0x34, 0x33, }; 2410 static int x1600_i2s_data_tx_pins[] = { 0x39, }; 2411 static int x1600_i2s_data_rx_pins[] = { 0x35, }; 2412 static int x1600_i2s_clk_rx_pins[] = { 0x37, 0x38, }; 2413 static int x1600_i2s_clk_tx_pins[] = { 0x3b, 0x3c, }; 2414 static int x1600_i2s_sysclk_pins[] = { 0x36, 0x3a, }; 2415 2416 static int x1600_cim_pins[] = { 2417 0x14, 0x16, 0x15, 0x18, 0x13, 2418 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 2419 }; 2420 2421 static int x1600_slcd_8bit_pins[] = { 2422 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2423 0x17, 0x19, 0x1a, 0x1b, 2424 }; 2425 2426 static int x1600_slcd_16bit_pins[] = { 2427 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 2428 }; 2429 2430 static int x1600_lcd_16bit_pins[] = { 2431 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2432 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 2433 0x18, 0x19, 0x1a, 0x1b, 2434 }; 2435 2436 static int x1600_lcd_18bit_pins[] = { 2437 0x10, 0x11, 2438 }; 2439 2440 static int x1600_lcd_24bit_pins[] = { 2441 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 2442 }; 2443 2444 static int x1600_pwm_pwm0_pins[] = { 0x40, }; 2445 static int x1600_pwm_pwm1_pins[] = { 0x41, }; 2446 static int x1600_pwm_pwm2_pins[] = { 0x42, }; 2447 static int x1600_pwm_pwm3_pins[] = { 0x58, }; 2448 static int x1600_pwm_pwm4_pins[] = { 0x59, }; 2449 static int x1600_pwm_pwm5_b_pins[] = { 0x33, }; 2450 static int x1600_pwm_pwm5_c_pins[] = { 0x5a, }; 2451 static int x1600_pwm_pwm6_b9_pins[] = { 0x29, }; 2452 static int x1600_pwm_pwm6_b20_pins[] = { 0x34, }; 2453 static int x1600_pwm_pwm7_b10_pins[] = { 0x2a, }; 2454 static int x1600_pwm_pwm7_b21_pins[] = { 0x35, }; 2455 2456 static int x1600_mac_pins[] = { 2457 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 2458 }; 2459 2460 static int x1600_sfc_funcs[] = { 0, 0, 0, 0, 0, 0, 2, }; 2461 2462 static const struct group_desc x1600_groups[] = { 2463 INGENIC_PIN_GROUP("uart0-data", x1600_uart0_data, 0), 2464 INGENIC_PIN_GROUP("uart0-hwflow", x1600_uart0_hwflow, 0), 2465 INGENIC_PIN_GROUP("uart1-data", x1600_uart1_data, 1), 2466 INGENIC_PIN_GROUP("uart1-hwflow", x1600_uart1_hwflow, 1), 2467 INGENIC_PIN_GROUP("uart2-data-a", x1600_uart2_data_a, 2), 2468 INGENIC_PIN_GROUP("uart2-data-b", x1600_uart2_data_b, 1), 2469 INGENIC_PIN_GROUP("uart3-data-b", x1600_uart3_data_b, 0), 2470 INGENIC_PIN_GROUP("uart3-data-d", x1600_uart3_data_d, 2), 2471 INGENIC_PIN_GROUP_FUNCS("sfc", x1600_sfc, x1600_sfc_funcs), 2472 INGENIC_PIN_GROUP("ssi-dt-a", x1600_ssi_dt_a, 0), 2473 INGENIC_PIN_GROUP("ssi-dt-b", x1600_ssi_dt_b, 1), 2474 INGENIC_PIN_GROUP("ssi-dr-a", x1600_ssi_dr_a, 0), 2475 INGENIC_PIN_GROUP("ssi-dr-b", x1600_ssi_dr_b, 1), 2476 INGENIC_PIN_GROUP("ssi-clk-a", x1600_ssi_clk_a, 0), 2477 INGENIC_PIN_GROUP("ssi-clk-b", x1600_ssi_clk_b, 1), 2478 INGENIC_PIN_GROUP("ssi-ce0-a", x1600_ssi_ce0_a, 0), 2479 INGENIC_PIN_GROUP("ssi-ce0-b", x1600_ssi_ce0_b, 1), 2480 INGENIC_PIN_GROUP("ssi-ce1-a", x1600_ssi_ce1_a, 2), 2481 INGENIC_PIN_GROUP("ssi-ce1-b", x1600_ssi_ce1_b, 1), 2482 INGENIC_PIN_GROUP("mmc0-1bit-b", x1600_mmc0_1bit_b, 0), 2483 INGENIC_PIN_GROUP("mmc0-4bit-b", x1600_mmc0_4bit_b, 0), 2484 INGENIC_PIN_GROUP("mmc0-1bit-c", x1600_mmc0_1bit_c, 1), 2485 INGENIC_PIN_GROUP("mmc0-4bit-c", x1600_mmc0_4bit_c, 1), 2486 INGENIC_PIN_GROUP("mmc1-1bit", x1600_mmc1_1bit, 0), 2487 INGENIC_PIN_GROUP("mmc1-4bit", x1600_mmc1_4bit, 0), 2488 INGENIC_PIN_GROUP("i2c0-data-a", x1600_i2c0_a, 2), 2489 INGENIC_PIN_GROUP("i2c0-data-b", x1600_i2c0_b, 0), 2490 INGENIC_PIN_GROUP("i2c1-data-b-15", x1600_i2c1_b_15, 2), 2491 INGENIC_PIN_GROUP("i2c1-data-b-19", x1600_i2c1_b_19, 0), 2492 INGENIC_PIN_GROUP("i2s-data-tx", x1600_i2s_data_tx, 0), 2493 INGENIC_PIN_GROUP("i2s-data-rx", x1600_i2s_data_rx, 0), 2494 INGENIC_PIN_GROUP("i2s-clk-rx", x1600_i2s_clk_rx, 0), 2495 INGENIC_PIN_GROUP("i2s-clk-tx", x1600_i2s_clk_tx, 0), 2496 INGENIC_PIN_GROUP("i2s-sysclk", x1600_i2s_sysclk, 0), 2497 INGENIC_PIN_GROUP("cim-data", x1600_cim, 2), 2498 INGENIC_PIN_GROUP("slcd-8bit", x1600_slcd_8bit, 1), 2499 INGENIC_PIN_GROUP("slcd-16bit", x1600_slcd_16bit, 1), 2500 INGENIC_PIN_GROUP("lcd-16bit", x1600_lcd_16bit, 0), 2501 INGENIC_PIN_GROUP("lcd-18bit", x1600_lcd_18bit, 0), 2502 INGENIC_PIN_GROUP("lcd-24bit", x1600_lcd_24bit, 0), 2503 INGENIC_PIN_GROUP("pwm0", x1600_pwm_pwm0, 0), 2504 INGENIC_PIN_GROUP("pwm1", x1600_pwm_pwm1, 0), 2505 INGENIC_PIN_GROUP("pwm2", x1600_pwm_pwm2, 0), 2506 INGENIC_PIN_GROUP("pwm3", x1600_pwm_pwm3, 1), 2507 INGENIC_PIN_GROUP("pwm4", x1600_pwm_pwm4, 1), 2508 INGENIC_PIN_GROUP("pwm5-b", x1600_pwm_pwm5_b, 2), 2509 INGENIC_PIN_GROUP("pwm5-c", x1600_pwm_pwm5_c, 1), 2510 INGENIC_PIN_GROUP("pwm6-b9", x1600_pwm_pwm6_b9, 1), 2511 INGENIC_PIN_GROUP("pwm6-b20", x1600_pwm_pwm6_b20, 2), 2512 INGENIC_PIN_GROUP("pwm7-b10", x1600_pwm_pwm7_b10, 1), 2513 INGENIC_PIN_GROUP("pwm7-b21", x1600_pwm_pwm7_b21, 2), 2514 INGENIC_PIN_GROUP("mac", x1600_mac, 1), 2515 }; 2516 2517 static const char * const x1600_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2518 static const char * const x1600_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 2519 static const char * const x1600_uart2_groups[] = { "uart2-data-a", "uart2-data-b", }; 2520 static const char * const x1600_uart3_groups[] = { "uart3-data-b", "uart3-data-d", }; 2521 2522 static const char * const x1600_sfc_groups[] = { "sfc", }; 2523 2524 static const char * const x1600_ssi_groups[] = { 2525 "ssi-dt-a", "ssi-dt-b", 2526 "ssi-dr-a", "ssi-dr-b", 2527 "ssi-clk-a", "ssi-clk-b", 2528 "ssi-ce0-a", "ssi-ce0-b", 2529 "ssi-ce1-a", "ssi-ce1-b", 2530 }; 2531 2532 static const char * const x1600_mmc0_groups[] = { "mmc0-1bit-b", "mmc0-4bit-b", 2533 "mmc0-1bit-c", "mmc0-4bit-c", 2534 }; 2535 2536 static const char * const x1600_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 2537 2538 static const char * const x1600_i2c0_groups[] = { "i2c0-data-a", "i2c0-data-b", }; 2539 static const char * const x1600_i2c1_groups[] = { "i2c1-data-b-15", "i2c1-data-b-19", }; 2540 2541 static const char * const x1600_i2s_groups[] = { 2542 "i2s-data-tx", "i2s-data-rx", "i2s-clk-rx", "i2s-clk-tx", "i2s-sysclk", 2543 }; 2544 2545 static const char * const x1600_cim_groups[] = { "cim-data", }; 2546 2547 static const char * const x1600_lcd_groups[] = { "slcd-8bit", "slcd-16bit", 2548 "lcd-16bit", "lcd-18bit", "lcd-24bit", "lcd-no-pins", 2549 }; 2550 2551 static const char * const x1600_pwm0_groups[] = { "pwm0", }; 2552 static const char * const x1600_pwm1_groups[] = { "pwm1", }; 2553 static const char * const x1600_pwm2_groups[] = { "pwm2", }; 2554 static const char * const x1600_pwm3_groups[] = { "pwm3", }; 2555 static const char * const x1600_pwm4_groups[] = { "pwm4", }; 2556 static const char * const x1600_pwm5_groups[] = { "pwm5-b", "pwm5-c", }; 2557 static const char * const x1600_pwm6_groups[] = { "pwm6-b9", "pwm6-b20", }; 2558 static const char * const x1600_pwm7_groups[] = { "pwm7-b10", "pwm7-b21", }; 2559 2560 static const char * const x1600_mac_groups[] = { "mac", }; 2561 2562 static const struct pinfunction x1600_functions[] = { 2563 INGENIC_PIN_FUNCTION("uart0", x1600_uart0), 2564 INGENIC_PIN_FUNCTION("uart1", x1600_uart1), 2565 INGENIC_PIN_FUNCTION("uart2", x1600_uart2), 2566 INGENIC_PIN_FUNCTION("uart3", x1600_uart3), 2567 INGENIC_PIN_FUNCTION("sfc", x1600_sfc), 2568 INGENIC_PIN_FUNCTION("ssi", x1600_ssi), 2569 INGENIC_PIN_FUNCTION("mmc0", x1600_mmc0), 2570 INGENIC_PIN_FUNCTION("mmc1", x1600_mmc1), 2571 INGENIC_PIN_FUNCTION("i2c0", x1600_i2c0), 2572 INGENIC_PIN_FUNCTION("i2c1", x1600_i2c1), 2573 INGENIC_PIN_FUNCTION("i2s", x1600_i2s), 2574 INGENIC_PIN_FUNCTION("cim", x1600_cim), 2575 INGENIC_PIN_FUNCTION("lcd", x1600_lcd), 2576 INGENIC_PIN_FUNCTION("pwm0", x1600_pwm0), 2577 INGENIC_PIN_FUNCTION("pwm1", x1600_pwm1), 2578 INGENIC_PIN_FUNCTION("pwm2", x1600_pwm2), 2579 INGENIC_PIN_FUNCTION("pwm3", x1600_pwm3), 2580 INGENIC_PIN_FUNCTION("pwm4", x1600_pwm4), 2581 INGENIC_PIN_FUNCTION("pwm5", x1600_pwm5), 2582 INGENIC_PIN_FUNCTION("pwm6", x1600_pwm6), 2583 INGENIC_PIN_FUNCTION("pwm7", x1600_pwm7), 2584 INGENIC_PIN_FUNCTION("mac", x1600_mac), 2585 }; 2586 2587 static const struct ingenic_chip_info x1600_chip_info = { 2588 .num_chips = 4, 2589 .reg_offset = 0x100, 2590 .version = ID_X1600, 2591 .groups = x1600_groups, 2592 .num_groups = ARRAY_SIZE(x1600_groups), 2593 .functions = x1600_functions, 2594 .num_functions = ARRAY_SIZE(x1600_functions), 2595 .pull_ups = x1600_pull_ups, 2596 .pull_downs = x1600_pull_downs, 2597 .access_table = &x1000_access_table, 2598 }; 2599 2600 static const u32 x1830_pull_ups[4] = { 2601 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 2602 }; 2603 2604 static const u32 x1830_pull_downs[4] = { 2605 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 2606 }; 2607 2608 static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; 2609 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; 2610 static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; 2611 static int x1830_sfc_data_pins[] = { 0x17, 0x18, 0x1a, 0x19, }; 2612 static int x1830_sfc_clk_pins[] = { 0x1b, }; 2613 static int x1830_sfc_ce_pins[] = { 0x1c, }; 2614 static int x1830_ssi0_dt_pins[] = { 0x4c, }; 2615 static int x1830_ssi0_dr_pins[] = { 0x4b, }; 2616 static int x1830_ssi0_clk_pins[] = { 0x4f, }; 2617 static int x1830_ssi0_gpc_pins[] = { 0x4d, }; 2618 static int x1830_ssi0_ce0_pins[] = { 0x50, }; 2619 static int x1830_ssi0_ce1_pins[] = { 0x4e, }; 2620 static int x1830_ssi1_dt_c_pins[] = { 0x53, }; 2621 static int x1830_ssi1_dt_d_pins[] = { 0x62, }; 2622 static int x1830_ssi1_dr_c_pins[] = { 0x54, }; 2623 static int x1830_ssi1_dr_d_pins[] = { 0x63, }; 2624 static int x1830_ssi1_clk_c_pins[] = { 0x57, }; 2625 static int x1830_ssi1_clk_d_pins[] = { 0x66, }; 2626 static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; 2627 static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; 2628 static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; 2629 static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; 2630 static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; 2631 static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; 2632 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; 2633 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; 2634 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; 2635 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; 2636 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; 2637 static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; 2638 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; 2639 static int x1830_i2s_data_tx_pins[] = { 0x53, }; 2640 static int x1830_i2s_data_rx_pins[] = { 0x54, }; 2641 static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, }; 2642 static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, }; 2643 static int x1830_i2s_sysclk_pins[] = { 0x57, }; 2644 static int x1830_dmic_if0_pins[] = { 0x48, 0x59, }; 2645 static int x1830_dmic_if1_pins[] = { 0x5a, }; 2646 static int x1830_lcd_tft_8bit_pins[] = { 2647 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 2648 0x68, 0x73, 0x72, 0x69, 2649 }; 2650 static int x1830_lcd_tft_24bit_pins[] = { 2651 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 2652 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 2653 }; 2654 static int x1830_lcd_slcd_8bit_pins[] = { 2655 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d, 2656 0x69, 0x72, 0x73, 0x7b, 0x7a, 2657 }; 2658 static int x1830_lcd_slcd_16bit_pins[] = { 2659 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79, 2660 }; 2661 static int x1830_pwm_pwm0_b_pins[] = { 0x31, }; 2662 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, }; 2663 static int x1830_pwm_pwm1_b_pins[] = { 0x32, }; 2664 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, }; 2665 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, }; 2666 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, }; 2667 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, }; 2668 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, }; 2669 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, }; 2670 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, }; 2671 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, }; 2672 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, }; 2673 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, }; 2674 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, }; 2675 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, }; 2676 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, }; 2677 static int x1830_mac_pins[] = { 2678 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, 2679 }; 2680 2681 static const struct group_desc x1830_groups[] = { 2682 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0), 2683 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0), 2684 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0), 2685 INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1), 2686 INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1), 2687 INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1), 2688 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0), 2689 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0), 2690 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0), 2691 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0), 2692 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0), 2693 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0), 2694 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1), 2695 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1), 2696 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1), 2697 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1), 2698 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1), 2699 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1), 2700 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2), 2701 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2), 2702 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2), 2703 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2), 2704 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2), 2705 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2), 2706 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0), 2707 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0), 2708 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0), 2709 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0), 2710 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1), 2711 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0), 2712 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1), 2713 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0), 2714 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0), 2715 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0), 2716 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0), 2717 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0), 2718 INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2), 2719 INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2), 2720 INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0), 2721 INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0), 2722 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1), 2723 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1), 2724 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0), 2725 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1), 2726 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0), 2727 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1), 2728 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0), 2729 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1), 2730 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0), 2731 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1), 2732 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1), 2733 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0), 2734 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1), 2735 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0), 2736 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1), 2737 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0), 2738 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1), 2739 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0), 2740 INGENIC_PIN_GROUP("mac", x1830_mac, 0), 2741 }; 2742 2743 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2744 static const char *x1830_uart1_groups[] = { "uart1-data", }; 2745 static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", }; 2746 static const char *x1830_ssi0_groups[] = { 2747 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", 2748 }; 2749 static const char *x1830_ssi1_groups[] = { 2750 "ssi1-dt-c", "ssi1-dt-d", 2751 "ssi1-dr-c", "ssi1-dr-d", 2752 "ssi1-clk-c", "ssi1-clk-d", 2753 "ssi1-gpc-c", "ssi1-gpc-d", 2754 "ssi1-ce0-c", "ssi1-ce0-d", 2755 "ssi1-ce1-c", "ssi1-ce1-d", 2756 }; 2757 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 2758 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 2759 static const char *x1830_i2c0_groups[] = { "i2c0-data", }; 2760 static const char *x1830_i2c1_groups[] = { "i2c1-data", }; 2761 static const char *x1830_i2c2_groups[] = { "i2c2-data", }; 2762 static const char *x1830_i2s_groups[] = { 2763 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 2764 }; 2765 static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", }; 2766 static const char *x1830_lcd_groups[] = { 2767 "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit", 2768 }; 2769 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; 2770 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; 2771 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", }; 2772 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", }; 2773 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", }; 2774 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", }; 2775 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", }; 2776 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", }; 2777 static const char *x1830_mac_groups[] = { "mac", }; 2778 2779 static const struct pinfunction x1830_functions[] = { 2780 INGENIC_PIN_FUNCTION("uart0", x1830_uart0), 2781 INGENIC_PIN_FUNCTION("uart1", x1830_uart1), 2782 INGENIC_PIN_FUNCTION("sfc", x1830_sfc), 2783 INGENIC_PIN_FUNCTION("ssi0", x1830_ssi0), 2784 INGENIC_PIN_FUNCTION("ssi1", x1830_ssi1), 2785 INGENIC_PIN_FUNCTION("mmc0", x1830_mmc0), 2786 INGENIC_PIN_FUNCTION("mmc1", x1830_mmc1), 2787 INGENIC_PIN_FUNCTION("i2c0", x1830_i2c0), 2788 INGENIC_PIN_FUNCTION("i2c1", x1830_i2c1), 2789 INGENIC_PIN_FUNCTION("i2c2", x1830_i2c2), 2790 INGENIC_PIN_FUNCTION("i2s", x1830_i2s), 2791 INGENIC_PIN_FUNCTION("dmic", x1830_dmic), 2792 INGENIC_PIN_FUNCTION("lcd", x1830_lcd), 2793 INGENIC_PIN_FUNCTION("pwm0", x1830_pwm0), 2794 INGENIC_PIN_FUNCTION("pwm1", x1830_pwm1), 2795 INGENIC_PIN_FUNCTION("pwm2", x1830_pwm2), 2796 INGENIC_PIN_FUNCTION("pwm3", x1830_pwm3), 2797 INGENIC_PIN_FUNCTION("pwm4", x1830_pwm4), 2798 INGENIC_PIN_FUNCTION("pwm5", x1830_pwm5), 2799 INGENIC_PIN_FUNCTION("pwm6", x1830_pwm6), 2800 INGENIC_PIN_FUNCTION("pwm7", x1830_pwm7), 2801 INGENIC_PIN_FUNCTION("mac", x1830_mac), 2802 }; 2803 2804 static const struct regmap_range x1830_access_ranges[] = { 2805 regmap_reg_range(0x0000, 0x4000 - 4), 2806 regmap_reg_range(0x7000, 0x8000 - 4), 2807 }; 2808 2809 static const struct regmap_access_table x1830_access_table = { 2810 .yes_ranges = x1830_access_ranges, 2811 .n_yes_ranges = ARRAY_SIZE(x1830_access_ranges), 2812 }; 2813 2814 static const struct ingenic_chip_info x1830_chip_info = { 2815 .num_chips = 4, 2816 .reg_offset = 0x1000, 2817 .version = ID_X1830, 2818 .groups = x1830_groups, 2819 .num_groups = ARRAY_SIZE(x1830_groups), 2820 .functions = x1830_functions, 2821 .num_functions = ARRAY_SIZE(x1830_functions), 2822 .pull_ups = x1830_pull_ups, 2823 .pull_downs = x1830_pull_downs, 2824 .access_table = &x1830_access_table, 2825 }; 2826 2827 static const u32 x2000_pull_ups[5] = { 2828 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f, 2829 }; 2830 2831 static const u32 x2000_pull_downs[5] = { 2832 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f, 2833 }; 2834 2835 static int x2000_uart0_data_pins[] = { 0x77, 0x78, }; 2836 static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, }; 2837 static int x2000_uart1_data_pins[] = { 0x57, 0x58, }; 2838 static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, }; 2839 static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, }; 2840 static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, }; 2841 static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, }; 2842 static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, }; 2843 static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, }; 2844 static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, }; 2845 static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, }; 2846 static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, }; 2847 static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, }; 2848 static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, }; 2849 static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, }; 2850 static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, }; 2851 static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, }; 2852 static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, }; 2853 static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, }; 2854 static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, }; 2855 static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, }; 2856 static int x2000_sfc_data_if0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, }; 2857 static int x2000_sfc_data_if0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, }; 2858 static int x2000_sfc_data_if1_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; 2859 static int x2000_sfc_clk_d_pins[] = { 0x71, }; 2860 static int x2000_sfc_clk_e_pins[] = { 0x90, }; 2861 static int x2000_sfc_ce_d_pins[] = { 0x72, }; 2862 static int x2000_sfc_ce_e_pins[] = { 0x91, }; 2863 static int x2000_ssi0_dt_b_pins[] = { 0x3e, }; 2864 static int x2000_ssi0_dt_d_pins[] = { 0x69, }; 2865 static int x2000_ssi0_dr_b_pins[] = { 0x3d, }; 2866 static int x2000_ssi0_dr_d_pins[] = { 0x6a, }; 2867 static int x2000_ssi0_clk_b_pins[] = { 0x3f, }; 2868 static int x2000_ssi0_clk_d_pins[] = { 0x68, }; 2869 static int x2000_ssi0_ce_b_pins[] = { 0x3c, }; 2870 static int x2000_ssi0_ce_d_pins[] = { 0x6d, }; 2871 static int x2000_ssi1_dt_c_pins[] = { 0x4b, }; 2872 static int x2000_ssi1_dt_d_pins[] = { 0x72, }; 2873 static int x2000_ssi1_dt_e_pins[] = { 0x91, }; 2874 static int x2000_ssi1_dr_c_pins[] = { 0x4a, }; 2875 static int x2000_ssi1_dr_d_pins[] = { 0x73, }; 2876 static int x2000_ssi1_dr_e_pins[] = { 0x92, }; 2877 static int x2000_ssi1_clk_c_pins[] = { 0x4c, }; 2878 static int x2000_ssi1_clk_d_pins[] = { 0x71, }; 2879 static int x2000_ssi1_clk_e_pins[] = { 0x90, }; 2880 static int x2000_ssi1_ce_c_pins[] = { 0x49, }; 2881 static int x2000_ssi1_ce_d_pins[] = { 0x76, }; 2882 static int x2000_ssi1_ce_e_pins[] = { 0x95, }; 2883 static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, }; 2884 static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, }; 2885 static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; 2886 static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, }; 2887 static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 2888 static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, }; 2889 static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, }; 2890 static int x2000_emc_8bit_data_pins[] = { 2891 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 2892 }; 2893 static int x2000_emc_16bit_data_pins[] = { 2894 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 2895 }; 2896 static int x2000_emc_addr_pins[] = { 2897 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2898 0x28, 0x29, 0x2a, 0x2b, 0x2c, 2899 }; 2900 static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, }; 2901 static int x2000_emc_wait_pins[] = { 0x2f, }; 2902 static int x2000_emc_cs1_pins[] = { 0x57, }; 2903 static int x2000_emc_cs2_pins[] = { 0x58, }; 2904 static int x2000_i2c0_pins[] = { 0x4e, 0x4d, }; 2905 static int x2000_i2c1_c_pins[] = { 0x58, 0x57, }; 2906 static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, }; 2907 static int x2000_i2c2_b_pins[] = { 0x37, 0x36, }; 2908 static int x2000_i2c2_d_pins[] = { 0x75, 0x74, }; 2909 static int x2000_i2c2_e_pins[] = { 0x94, 0x93, }; 2910 static int x2000_i2c3_a_pins[] = { 0x11, 0x10, }; 2911 static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, }; 2912 static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, }; 2913 static int x2000_i2c4_d_pins[] = { 0x61, 0x60, }; 2914 static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, }; 2915 static int x2000_i2c5_d_pins[] = { 0x65, 0x64, }; 2916 static int x2000_i2s1_data_tx_pins[] = { 0x47, }; 2917 static int x2000_i2s1_data_rx_pins[] = { 0x44, }; 2918 static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, }; 2919 static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, }; 2920 static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, }; 2921 static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, }; 2922 static int x2000_i2s2_data_rx0_pins[] = { 0x0a, }; 2923 static int x2000_i2s2_data_rx1_pins[] = { 0x0b, }; 2924 static int x2000_i2s2_data_rx2_pins[] = { 0x0c, }; 2925 static int x2000_i2s2_data_rx3_pins[] = { 0x0d, }; 2926 static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, }; 2927 static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, }; 2928 static int x2000_i2s3_data_tx0_pins[] = { 0x03, }; 2929 static int x2000_i2s3_data_tx1_pins[] = { 0x04, }; 2930 static int x2000_i2s3_data_tx2_pins[] = { 0x05, }; 2931 static int x2000_i2s3_data_tx3_pins[] = { 0x06, }; 2932 static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, }; 2933 static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, }; 2934 static int x2000_dmic_if0_pins[] = { 0x54, 0x55, }; 2935 static int x2000_dmic_if1_pins[] = { 0x56, }; 2936 static int x2000_dmic_if2_pins[] = { 0x57, }; 2937 static int x2000_dmic_if3_pins[] = { 0x58, }; 2938 static int x2000_cim_8bit_pins[] = { 2939 0x0e, 0x0c, 0x0d, 0x4f, 2940 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2941 }; 2942 static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, }; 2943 static int x2000_lcd_tft_8bit_pins[] = { 2944 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2945 0x38, 0x3a, 0x39, 0x3b, 2946 }; 2947 static int x2000_lcd_tft_16bit_pins[] = { 2948 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 2949 }; 2950 static int x2000_lcd_tft_18bit_pins[] = { 2951 0x30, 0x31, 2952 }; 2953 static int x2000_lcd_tft_24bit_pins[] = { 2954 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 2955 }; 2956 static int x2000_lcd_slcd_8bit_pins[] = { 2957 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2958 0x3a, 0x38, 0x3b, 0x30, 0x39, 2959 }; 2960 static int x2000_pwm_pwm0_c_pins[] = { 0x40, }; 2961 static int x2000_pwm_pwm0_d_pins[] = { 0x7e, }; 2962 static int x2000_pwm_pwm1_c_pins[] = { 0x41, }; 2963 static int x2000_pwm_pwm1_d_pins[] = { 0x7f, }; 2964 static int x2000_pwm_pwm2_c_pins[] = { 0x42, }; 2965 static int x2000_pwm_pwm2_e_pins[] = { 0x80, }; 2966 static int x2000_pwm_pwm3_c_pins[] = { 0x43, }; 2967 static int x2000_pwm_pwm3_e_pins[] = { 0x81, }; 2968 static int x2000_pwm_pwm4_c_pins[] = { 0x44, }; 2969 static int x2000_pwm_pwm4_e_pins[] = { 0x82, }; 2970 static int x2000_pwm_pwm5_c_pins[] = { 0x45, }; 2971 static int x2000_pwm_pwm5_e_pins[] = { 0x83, }; 2972 static int x2000_pwm_pwm6_c_pins[] = { 0x46, }; 2973 static int x2000_pwm_pwm6_e_pins[] = { 0x84, }; 2974 static int x2000_pwm_pwm7_c_pins[] = { 0x47, }; 2975 static int x2000_pwm_pwm7_e_pins[] = { 0x85, }; 2976 static int x2000_pwm_pwm8_pins[] = { 0x48, }; 2977 static int x2000_pwm_pwm9_pins[] = { 0x49, }; 2978 static int x2000_pwm_pwm10_pins[] = { 0x4a, }; 2979 static int x2000_pwm_pwm11_pins[] = { 0x4b, }; 2980 static int x2000_pwm_pwm12_pins[] = { 0x4c, }; 2981 static int x2000_pwm_pwm13_pins[] = { 0x4d, }; 2982 static int x2000_pwm_pwm14_pins[] = { 0x4e, }; 2983 static int x2000_pwm_pwm15_pins[] = { 0x4f, }; 2984 static int x2000_mac0_rmii_pins[] = { 2985 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41, 2986 }; 2987 static int x2000_mac0_rgmii_pins[] = { 2988 0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42, 2989 0x4c, 0x4d, 0x4f, 0x4e, 0x41, 2990 }; 2991 static int x2000_mac1_rmii_pins[] = { 2992 0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37, 2993 }; 2994 static int x2000_mac1_rgmii_pins[] = { 2995 0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28, 2996 0x33, 0x34, 0x36, 0x35, 0x37, 2997 }; 2998 static int x2000_otg_pins[] = { 0x96, }; 2999 3000 static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, }; 3001 3002 static const struct group_desc x2000_groups[] = { 3003 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2), 3004 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2), 3005 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1), 3006 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1), 3007 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0), 3008 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0), 3009 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1), 3010 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0), 3011 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1), 3012 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1), 3013 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3), 3014 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1), 3015 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3), 3016 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1), 3017 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3), 3018 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1), 3019 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3), 3020 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1), 3021 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3), 3022 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3), 3023 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3), 3024 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1), 3025 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0), 3026 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1), 3027 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1), 3028 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0), 3029 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1), 3030 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0), 3031 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1), 3032 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1), 3033 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1), 3034 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1), 3035 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1), 3036 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1), 3037 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1), 3038 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1), 3039 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2), 3040 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2), 3041 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1), 3042 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2), 3043 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2), 3044 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1), 3045 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2), 3046 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2), 3047 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1), 3048 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2), 3049 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2), 3050 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1), 3051 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0), 3052 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0), 3053 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0), 3054 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0), 3055 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0), 3056 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0), 3057 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0), 3058 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0), 3059 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0), 3060 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0), 3061 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0), 3062 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0), 3063 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3), 3064 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3), 3065 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3), 3066 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2), 3067 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1), 3068 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2), 3069 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2), 3070 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1), 3071 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0), 3072 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1), 3073 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1), 3074 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2), 3075 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1), 3076 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1), 3077 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2), 3078 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2), 3079 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2), 3080 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2), 3081 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2), 3082 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2), 3083 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2), 3084 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2), 3085 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2), 3086 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2), 3087 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2), 3088 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2), 3089 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2), 3090 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2), 3091 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2), 3092 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2), 3093 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2), 3094 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2), 3095 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0), 3096 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0), 3097 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0), 3098 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0), 3099 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit, 3100 x2000_cim_8bit_funcs), 3101 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0), 3102 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1), 3103 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1), 3104 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1), 3105 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1), 3106 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2), 3107 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2), 3108 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0), 3109 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2), 3110 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0), 3111 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2), 3112 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0), 3113 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1), 3114 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0), 3115 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1), 3116 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0), 3117 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1), 3118 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0), 3119 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1), 3120 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0), 3121 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1), 3122 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0), 3123 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1), 3124 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0), 3125 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0), 3126 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0), 3127 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0), 3128 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0), 3129 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0), 3130 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0), 3131 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0), 3132 INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1), 3133 INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1), 3134 INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3), 3135 INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3), 3136 INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0), 3137 }; 3138 3139 static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 3140 static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 3141 static const char *x2000_uart2_groups[] = { "uart2-data", }; 3142 static const char *x2000_uart3_groups[] = { 3143 "uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d", 3144 }; 3145 static const char *x2000_uart4_groups[] = { 3146 "uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c", 3147 }; 3148 static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", }; 3149 static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", }; 3150 static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", }; 3151 static const char *x2000_uart8_groups[] = { "uart8-data", }; 3152 static const char *x2000_uart9_groups[] = { "uart9-data", }; 3153 static const char *x2000_sfc_groups[] = { 3154 "sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1", 3155 "sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e", 3156 }; 3157 static const char *x2000_ssi0_groups[] = { 3158 "ssi0-dt-b", "ssi0-dt-d", 3159 "ssi0-dr-b", "ssi0-dr-d", 3160 "ssi0-clk-b", "ssi0-clk-d", 3161 "ssi0-ce-b", "ssi0-ce-d", 3162 }; 3163 static const char *x2000_ssi1_groups[] = { 3164 "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e", 3165 "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e", 3166 "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e", 3167 "ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e", 3168 }; 3169 static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", }; 3170 static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 3171 static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", }; 3172 static const char *x2000_emc_groups[] = { 3173 "emc-8bit-data", "emc-16bit-data", 3174 "emc-addr", "emc-rd-we", "emc-wait", 3175 }; 3176 static const char *x2000_cs1_groups[] = { "emc-cs1", }; 3177 static const char *x2000_cs2_groups[] = { "emc-cs2", }; 3178 static const char *x2000_i2c0_groups[] = { "i2c0-data", }; 3179 static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", }; 3180 static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", }; 3181 static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", }; 3182 static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", }; 3183 static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", }; 3184 static const char *x2000_i2s1_groups[] = { 3185 "i2s1-data-tx", "i2s1-data-rx", 3186 "i2s1-clk-tx", "i2s1-clk-rx", 3187 "i2s1-sysclk-tx", "i2s1-sysclk-rx", 3188 }; 3189 static const char *x2000_i2s2_groups[] = { 3190 "i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3", 3191 "i2s2-clk-rx", "i2s2-sysclk-rx", 3192 }; 3193 static const char *x2000_i2s3_groups[] = { 3194 "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3", 3195 "i2s3-clk-tx", "i2s3-sysclk-tx", 3196 }; 3197 static const char *x2000_dmic_groups[] = { 3198 "dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3", 3199 }; 3200 static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 3201 static const char *x2000_lcd_groups[] = { 3202 "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit", 3203 "lcd-slcd-8bit", "lcd-slcd-16bit", 3204 }; 3205 static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", }; 3206 static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", }; 3207 static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", }; 3208 static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", }; 3209 static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", }; 3210 static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", }; 3211 static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", }; 3212 static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", }; 3213 static const char *x2000_pwm8_groups[] = { "pwm8", }; 3214 static const char *x2000_pwm9_groups[] = { "pwm9", }; 3215 static const char *x2000_pwm10_groups[] = { "pwm10", }; 3216 static const char *x2000_pwm11_groups[] = { "pwm11", }; 3217 static const char *x2000_pwm12_groups[] = { "pwm12", }; 3218 static const char *x2000_pwm13_groups[] = { "pwm13", }; 3219 static const char *x2000_pwm14_groups[] = { "pwm14", }; 3220 static const char *x2000_pwm15_groups[] = { "pwm15", }; 3221 static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", }; 3222 static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", }; 3223 static const char *x2000_otg_groups[] = { "otg-vbus", }; 3224 3225 static const struct pinfunction x2000_functions[] = { 3226 INGENIC_PIN_FUNCTION("uart0", x2000_uart0), 3227 INGENIC_PIN_FUNCTION("uart1", x2000_uart1), 3228 INGENIC_PIN_FUNCTION("uart2", x2000_uart2), 3229 INGENIC_PIN_FUNCTION("uart3", x2000_uart3), 3230 INGENIC_PIN_FUNCTION("uart4", x2000_uart4), 3231 INGENIC_PIN_FUNCTION("uart5", x2000_uart5), 3232 INGENIC_PIN_FUNCTION("uart6", x2000_uart6), 3233 INGENIC_PIN_FUNCTION("uart7", x2000_uart7), 3234 INGENIC_PIN_FUNCTION("uart8", x2000_uart8), 3235 INGENIC_PIN_FUNCTION("uart9", x2000_uart9), 3236 INGENIC_PIN_FUNCTION("sfc", x2000_sfc), 3237 INGENIC_PIN_FUNCTION("ssi0", x2000_ssi0), 3238 INGENIC_PIN_FUNCTION("ssi1", x2000_ssi1), 3239 INGENIC_PIN_FUNCTION("mmc0", x2000_mmc0), 3240 INGENIC_PIN_FUNCTION("mmc1", x2000_mmc1), 3241 INGENIC_PIN_FUNCTION("mmc2", x2000_mmc2), 3242 INGENIC_PIN_FUNCTION("emc", x2000_emc), 3243 INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1), 3244 INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2), 3245 INGENIC_PIN_FUNCTION("i2c0", x2000_i2c0), 3246 INGENIC_PIN_FUNCTION("i2c1", x2000_i2c1), 3247 INGENIC_PIN_FUNCTION("i2c2", x2000_i2c2), 3248 INGENIC_PIN_FUNCTION("i2c3", x2000_i2c3), 3249 INGENIC_PIN_FUNCTION("i2c4", x2000_i2c4), 3250 INGENIC_PIN_FUNCTION("i2c5", x2000_i2c5), 3251 INGENIC_PIN_FUNCTION("i2s1", x2000_i2s1), 3252 INGENIC_PIN_FUNCTION("i2s2", x2000_i2s2), 3253 INGENIC_PIN_FUNCTION("i2s3", x2000_i2s3), 3254 INGENIC_PIN_FUNCTION("dmic", x2000_dmic), 3255 INGENIC_PIN_FUNCTION("cim", x2000_cim), 3256 INGENIC_PIN_FUNCTION("lcd", x2000_lcd), 3257 INGENIC_PIN_FUNCTION("pwm0", x2000_pwm0), 3258 INGENIC_PIN_FUNCTION("pwm1", x2000_pwm1), 3259 INGENIC_PIN_FUNCTION("pwm2", x2000_pwm2), 3260 INGENIC_PIN_FUNCTION("pwm3", x2000_pwm3), 3261 INGENIC_PIN_FUNCTION("pwm4", x2000_pwm4), 3262 INGENIC_PIN_FUNCTION("pwm5", x2000_pwm5), 3263 INGENIC_PIN_FUNCTION("pwm6", x2000_pwm6), 3264 INGENIC_PIN_FUNCTION("pwm7", x2000_pwm7), 3265 INGENIC_PIN_FUNCTION("pwm8", x2000_pwm8), 3266 INGENIC_PIN_FUNCTION("pwm9", x2000_pwm9), 3267 INGENIC_PIN_FUNCTION("pwm10", x2000_pwm10), 3268 INGENIC_PIN_FUNCTION("pwm11", x2000_pwm11), 3269 INGENIC_PIN_FUNCTION("pwm12", x2000_pwm12), 3270 INGENIC_PIN_FUNCTION("pwm13", x2000_pwm13), 3271 INGENIC_PIN_FUNCTION("pwm14", x2000_pwm14), 3272 INGENIC_PIN_FUNCTION("pwm15", x2000_pwm15), 3273 INGENIC_PIN_FUNCTION("mac0", x2000_mac0), 3274 INGENIC_PIN_FUNCTION("mac1", x2000_mac1), 3275 INGENIC_PIN_FUNCTION("otg", x2000_otg), 3276 }; 3277 3278 static const struct regmap_range x2000_access_ranges[] = { 3279 regmap_reg_range(0x000, 0x500 - 4), 3280 regmap_reg_range(0x700, 0x800 - 4), 3281 }; 3282 3283 /* shared with X2100 */ 3284 static const struct regmap_access_table x2000_access_table = { 3285 .yes_ranges = x2000_access_ranges, 3286 .n_yes_ranges = ARRAY_SIZE(x2000_access_ranges), 3287 }; 3288 3289 static const struct ingenic_chip_info x2000_chip_info = { 3290 .num_chips = 5, 3291 .reg_offset = 0x100, 3292 .version = ID_X2000, 3293 .groups = x2000_groups, 3294 .num_groups = ARRAY_SIZE(x2000_groups), 3295 .functions = x2000_functions, 3296 .num_functions = ARRAY_SIZE(x2000_functions), 3297 .pull_ups = x2000_pull_ups, 3298 .pull_downs = x2000_pull_downs, 3299 .access_table = &x2000_access_table, 3300 }; 3301 3302 static const u32 x2100_pull_ups[5] = { 3303 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x0fbf003f, 3304 }; 3305 3306 static const u32 x2100_pull_downs[5] = { 3307 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x0fbf003f, 3308 }; 3309 3310 static int x2100_mac_pins[] = { 3311 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4f, 0x41, 3312 }; 3313 3314 static const struct group_desc x2100_groups[] = { 3315 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2), 3316 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2), 3317 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1), 3318 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1), 3319 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0), 3320 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0), 3321 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1), 3322 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0), 3323 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1), 3324 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1), 3325 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3), 3326 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1), 3327 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3), 3328 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1), 3329 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3), 3330 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1), 3331 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3), 3332 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1), 3333 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3), 3334 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3), 3335 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3), 3336 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1), 3337 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0), 3338 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1), 3339 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1), 3340 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0), 3341 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1), 3342 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0), 3343 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1), 3344 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1), 3345 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1), 3346 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1), 3347 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1), 3348 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1), 3349 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1), 3350 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1), 3351 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2), 3352 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2), 3353 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1), 3354 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2), 3355 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2), 3356 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1), 3357 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2), 3358 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2), 3359 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1), 3360 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2), 3361 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2), 3362 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1), 3363 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0), 3364 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0), 3365 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0), 3366 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0), 3367 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0), 3368 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0), 3369 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0), 3370 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0), 3371 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0), 3372 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0), 3373 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0), 3374 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0), 3375 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3), 3376 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3), 3377 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3), 3378 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2), 3379 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1), 3380 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2), 3381 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2), 3382 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1), 3383 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0), 3384 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1), 3385 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1), 3386 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2), 3387 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1), 3388 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1), 3389 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2), 3390 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2), 3391 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2), 3392 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2), 3393 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2), 3394 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2), 3395 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2), 3396 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2), 3397 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2), 3398 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2), 3399 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2), 3400 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2), 3401 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2), 3402 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2), 3403 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2), 3404 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2), 3405 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2), 3406 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2), 3407 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0), 3408 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0), 3409 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0), 3410 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0), 3411 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit, 3412 x2000_cim_8bit_funcs), 3413 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0), 3414 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1), 3415 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1), 3416 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1), 3417 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1), 3418 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2), 3419 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2), 3420 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0), 3421 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2), 3422 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0), 3423 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2), 3424 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0), 3425 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1), 3426 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0), 3427 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1), 3428 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0), 3429 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1), 3430 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0), 3431 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1), 3432 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0), 3433 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1), 3434 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0), 3435 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1), 3436 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0), 3437 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0), 3438 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0), 3439 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0), 3440 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0), 3441 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0), 3442 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0), 3443 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0), 3444 INGENIC_PIN_GROUP("mac", x2100_mac, 1), 3445 }; 3446 3447 static const char *x2100_mac_groups[] = { "mac", }; 3448 3449 static const struct pinfunction x2100_functions[] = { 3450 INGENIC_PIN_FUNCTION("uart0", x2000_uart0), 3451 INGENIC_PIN_FUNCTION("uart1", x2000_uart1), 3452 INGENIC_PIN_FUNCTION("uart2", x2000_uart2), 3453 INGENIC_PIN_FUNCTION("uart3", x2000_uart3), 3454 INGENIC_PIN_FUNCTION("uart4", x2000_uart4), 3455 INGENIC_PIN_FUNCTION("uart5", x2000_uart5), 3456 INGENIC_PIN_FUNCTION("uart6", x2000_uart6), 3457 INGENIC_PIN_FUNCTION("uart7", x2000_uart7), 3458 INGENIC_PIN_FUNCTION("uart8", x2000_uart8), 3459 INGENIC_PIN_FUNCTION("uart9", x2000_uart9), 3460 INGENIC_PIN_FUNCTION("sfc", x2000_sfc), 3461 INGENIC_PIN_FUNCTION("ssi0", x2000_ssi0), 3462 INGENIC_PIN_FUNCTION("ssi1", x2000_ssi1), 3463 INGENIC_PIN_FUNCTION("mmc0", x2000_mmc0), 3464 INGENIC_PIN_FUNCTION("mmc1", x2000_mmc1), 3465 INGENIC_PIN_FUNCTION("mmc2", x2000_mmc2), 3466 INGENIC_PIN_FUNCTION("emc", x2000_emc), 3467 INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1), 3468 INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2), 3469 INGENIC_PIN_FUNCTION("i2c0", x2000_i2c0), 3470 INGENIC_PIN_FUNCTION("i2c1", x2000_i2c1), 3471 INGENIC_PIN_FUNCTION("i2c2", x2000_i2c2), 3472 INGENIC_PIN_FUNCTION("i2c3", x2000_i2c3), 3473 INGENIC_PIN_FUNCTION("i2c4", x2000_i2c4), 3474 INGENIC_PIN_FUNCTION("i2c5", x2000_i2c5), 3475 INGENIC_PIN_FUNCTION("i2s1", x2000_i2s1), 3476 INGENIC_PIN_FUNCTION("i2s2", x2000_i2s2), 3477 INGENIC_PIN_FUNCTION("i2s3", x2000_i2s3), 3478 INGENIC_PIN_FUNCTION("dmic", x2000_dmic), 3479 INGENIC_PIN_FUNCTION("cim", x2000_cim), 3480 INGENIC_PIN_FUNCTION("lcd", x2000_lcd), 3481 INGENIC_PIN_FUNCTION("pwm0", x2000_pwm0), 3482 INGENIC_PIN_FUNCTION("pwm1", x2000_pwm1), 3483 INGENIC_PIN_FUNCTION("pwm2", x2000_pwm2), 3484 INGENIC_PIN_FUNCTION("pwm3", x2000_pwm3), 3485 INGENIC_PIN_FUNCTION("pwm4", x2000_pwm4), 3486 INGENIC_PIN_FUNCTION("pwm5", x2000_pwm5), 3487 INGENIC_PIN_FUNCTION("pwm6", x2000_pwm6), 3488 INGENIC_PIN_FUNCTION("pwm7", x2000_pwm7), 3489 INGENIC_PIN_FUNCTION("pwm8", x2000_pwm8), 3490 INGENIC_PIN_FUNCTION("pwm9", x2000_pwm9), 3491 INGENIC_PIN_FUNCTION("pwm10", x2000_pwm10), 3492 INGENIC_PIN_FUNCTION("pwm11", x2000_pwm11), 3493 INGENIC_PIN_FUNCTION("pwm12", x2000_pwm12), 3494 INGENIC_PIN_FUNCTION("pwm13", x2000_pwm13), 3495 INGENIC_PIN_FUNCTION("pwm14", x2000_pwm14), 3496 INGENIC_PIN_FUNCTION("pwm15", x2000_pwm15), 3497 INGENIC_PIN_FUNCTION("mac", x2100_mac), 3498 }; 3499 3500 static const struct ingenic_chip_info x2100_chip_info = { 3501 .num_chips = 5, 3502 .reg_offset = 0x100, 3503 .version = ID_X2100, 3504 .groups = x2100_groups, 3505 .num_groups = ARRAY_SIZE(x2100_groups), 3506 .functions = x2100_functions, 3507 .num_functions = ARRAY_SIZE(x2100_functions), 3508 .pull_ups = x2100_pull_ups, 3509 .pull_downs = x2100_pull_downs, 3510 .access_table = &x2000_access_table, 3511 }; 3512 3513 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) 3514 { 3515 unsigned int val; 3516 3517 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); 3518 3519 return (u32) val; 3520 } 3521 3522 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, 3523 u8 reg, u8 offset, bool set) 3524 { 3525 if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) { 3526 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, 3527 BIT(offset), set ? BIT(offset) : 0); 3528 return; 3529 } 3530 3531 if (set) 3532 reg = REG_SET(reg); 3533 else 3534 reg = REG_CLEAR(reg); 3535 3536 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); 3537 } 3538 3539 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, 3540 u8 reg, u8 offset, bool set) 3541 { 3542 if (set) 3543 reg = REG_SET(reg); 3544 else 3545 reg = REG_CLEAR(reg); 3546 3547 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( 3548 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); 3549 } 3550 3551 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) 3552 { 3553 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( 3554 jzgc->jzpc->info->reg_offset), 3555 jzgc->gc.base / PINS_PER_GPIO_CHIP); 3556 } 3557 3558 static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc, 3559 u8 reg_upper, u8 reg_lower, u8 offset, u8 value) 3560 { 3561 /* 3562 * JZ4730 function and IRQ registers support two-bits-per-pin 3563 * definitions, split into two groups of 16. 3564 */ 3565 u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; 3566 unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG; 3567 unsigned int mask = GENMASK(1, 0) << idx * 2; 3568 3569 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2)); 3570 } 3571 3572 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, 3573 u8 offset) 3574 { 3575 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); 3576 3577 return !!(val & BIT(offset)); 3578 } 3579 3580 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, 3581 u8 offset, int value) 3582 { 3583 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3584 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value); 3585 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3586 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); 3587 else 3588 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value); 3589 } 3590 3591 static void irq_set_type(struct ingenic_gpio_chip *jzgc, 3592 u8 offset, unsigned int type) 3593 { 3594 u8 reg1, reg2; 3595 bool val1, val2, val3; 3596 3597 switch (type) { 3598 case IRQ_TYPE_EDGE_BOTH: 3599 val1 = val2 = false; 3600 val3 = true; 3601 break; 3602 case IRQ_TYPE_EDGE_RISING: 3603 val1 = val2 = true; 3604 val3 = false; 3605 break; 3606 case IRQ_TYPE_EDGE_FALLING: 3607 val1 = val3 = false; 3608 val2 = true; 3609 break; 3610 case IRQ_TYPE_LEVEL_HIGH: 3611 val1 = true; 3612 val2 = val3 = false; 3613 break; 3614 case IRQ_TYPE_LEVEL_LOW: 3615 default: 3616 val1 = val2 = val3 = false; 3617 break; 3618 } 3619 3620 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) { 3621 reg1 = JZ4770_GPIO_PAT1; 3622 reg2 = JZ4770_GPIO_PAT0; 3623 } else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) { 3624 reg1 = JZ4740_GPIO_TRIG; 3625 reg2 = JZ4740_GPIO_DIR; 3626 } else { 3627 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false); 3628 jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR, 3629 JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1); 3630 return; 3631 } 3632 3633 if (is_soc_or_above(jzgc->jzpc, ID_X2000)) { 3634 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 3635 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 3636 ingenic_gpio_shadow_set_bit_load(jzgc); 3637 ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3); 3638 } else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) { 3639 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 3640 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 3641 ingenic_gpio_shadow_set_bit_load(jzgc); 3642 } else { 3643 ingenic_gpio_set_bit(jzgc, reg2, offset, val1); 3644 ingenic_gpio_set_bit(jzgc, reg1, offset, val2); 3645 } 3646 } 3647 3648 static void ingenic_gpio_irq_mask(struct irq_data *irqd) 3649 { 3650 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3651 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3652 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3653 3654 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3655 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true); 3656 else 3657 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true); 3658 } 3659 3660 static void ingenic_gpio_irq_unmask(struct irq_data *irqd) 3661 { 3662 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3663 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3664 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3665 3666 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3667 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false); 3668 else 3669 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false); 3670 } 3671 3672 static void ingenic_gpio_irq_enable(struct irq_data *irqd) 3673 { 3674 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3675 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3676 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3677 3678 gpiochip_enable_irq(gc, irq); 3679 3680 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3681 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); 3682 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3683 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); 3684 else 3685 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true); 3686 3687 ingenic_gpio_irq_unmask(irqd); 3688 } 3689 3690 static void ingenic_gpio_irq_disable(struct irq_data *irqd) 3691 { 3692 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3693 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3694 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3695 3696 ingenic_gpio_irq_mask(irqd); 3697 3698 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3699 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false); 3700 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3701 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); 3702 else 3703 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false); 3704 3705 gpiochip_disable_irq(gc, irq); 3706 } 3707 3708 static void ingenic_gpio_irq_ack(struct irq_data *irqd) 3709 { 3710 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3711 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3712 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3713 bool high; 3714 3715 if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) && 3716 !is_soc_or_above(jzgc->jzpc, ID_X2000)) { 3717 /* 3718 * Switch to an interrupt for the opposite edge to the one that 3719 * triggered the interrupt being ACKed. 3720 */ 3721 high = ingenic_gpio_get_value(jzgc, irq); 3722 if (high) 3723 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW); 3724 else 3725 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH); 3726 } 3727 3728 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3729 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false); 3730 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3731 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); 3732 else 3733 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false); 3734 } 3735 3736 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 3737 { 3738 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3739 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3740 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3741 3742 switch (type) { 3743 case IRQ_TYPE_EDGE_BOTH: 3744 case IRQ_TYPE_EDGE_RISING: 3745 case IRQ_TYPE_EDGE_FALLING: 3746 irq_set_handler_locked(irqd, handle_edge_irq); 3747 break; 3748 case IRQ_TYPE_LEVEL_HIGH: 3749 case IRQ_TYPE_LEVEL_LOW: 3750 irq_set_handler_locked(irqd, handle_level_irq); 3751 break; 3752 default: 3753 irq_set_handler_locked(irqd, handle_bad_irq); 3754 } 3755 3756 if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) { 3757 /* 3758 * The hardware does not support interrupts on both edges. The 3759 * best we can do is to set up a single-edge interrupt and then 3760 * switch to the opposing edge when ACKing the interrupt. 3761 */ 3762 bool high = ingenic_gpio_get_value(jzgc, irq); 3763 3764 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH; 3765 } 3766 3767 irq_set_type(jzgc, irq, type); 3768 return 0; 3769 } 3770 3771 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on) 3772 { 3773 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3774 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3775 3776 return irq_set_irq_wake(jzgc->irq, on); 3777 } 3778 3779 static void ingenic_gpio_irq_handler(struct irq_desc *desc) 3780 { 3781 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 3782 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3783 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); 3784 unsigned long flag, i; 3785 3786 chained_irq_enter(irq_chip, desc); 3787 3788 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3789 flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG); 3790 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3791 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); 3792 else 3793 flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR); 3794 3795 for_each_set_bit(i, &flag, 32) 3796 generic_handle_domain_irq(gc->irq.domain, i); 3797 chained_irq_exit(irq_chip, desc); 3798 } 3799 3800 static int ingenic_gpio_set(struct gpio_chip *gc, unsigned int offset, 3801 int value) 3802 { 3803 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3804 3805 ingenic_gpio_set_value(jzgc, offset, value); 3806 3807 return 0; 3808 } 3809 3810 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) 3811 { 3812 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3813 3814 return (int) ingenic_gpio_get_value(jzgc, offset); 3815 } 3816 3817 static int ingenic_gpio_direction_output(struct gpio_chip *gc, 3818 unsigned int offset, int value) 3819 { 3820 ingenic_gpio_set(gc, offset, value); 3821 return pinctrl_gpio_direction_output(gc, offset); 3822 } 3823 3824 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, 3825 unsigned int pin, unsigned int reg, bool set) 3826 { 3827 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3828 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3829 3830 if (set) { 3831 if (is_soc_or_above(jzpc, ID_JZ4740)) 3832 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3833 REG_SET(reg), BIT(idx)); 3834 else 3835 regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset + 3836 reg, BIT(idx)); 3837 } else { 3838 if (is_soc_or_above(jzpc, ID_JZ4740)) 3839 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3840 REG_CLEAR(reg), BIT(idx)); 3841 else 3842 regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset + 3843 reg, BIT(idx)); 3844 } 3845 } 3846 3847 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, 3848 unsigned int pin, u8 reg, bool set) 3849 { 3850 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3851 3852 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + 3853 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 3854 } 3855 3856 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, 3857 unsigned int pin) 3858 { 3859 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), 3860 pin / PINS_PER_GPIO_CHIP); 3861 } 3862 3863 static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc, 3864 unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value) 3865 { 3866 /* 3867 * JZ4730 function and IRQ registers support two-bits-per-pin 3868 * definitions, split into two groups of 16. 3869 */ 3870 unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG; 3871 unsigned int mask = GENMASK(1, 0) << idx * 2; 3872 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3873 u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; 3874 3875 regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg, 3876 mask, value << (idx * 2)); 3877 } 3878 3879 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, 3880 unsigned int pin, unsigned int reg) 3881 { 3882 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3883 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3884 unsigned int val; 3885 3886 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); 3887 3888 return val & BIT(idx); 3889 } 3890 3891 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 3892 { 3893 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3894 struct ingenic_pinctrl *jzpc = jzgc->jzpc; 3895 unsigned int pin = gc->base + offset; 3896 3897 if (is_soc_or_above(jzpc, ID_JZ4770)) { 3898 if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) || 3899 ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1)) 3900 return GPIO_LINE_DIRECTION_IN; 3901 return GPIO_LINE_DIRECTION_OUT; 3902 } else if (!is_soc_or_above(jzpc, ID_JZ4740)) { 3903 if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR)) 3904 return GPIO_LINE_DIRECTION_IN; 3905 return GPIO_LINE_DIRECTION_OUT; 3906 } 3907 3908 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) 3909 return GPIO_LINE_DIRECTION_IN; 3910 3911 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR)) 3912 return GPIO_LINE_DIRECTION_OUT; 3913 3914 return GPIO_LINE_DIRECTION_IN; 3915 } 3916 3917 static const struct pinctrl_ops ingenic_pctlops = { 3918 .get_groups_count = pinctrl_generic_get_group_count, 3919 .get_group_name = pinctrl_generic_get_group_name, 3920 .get_group_pins = pinctrl_generic_get_group_pins, 3921 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 3922 .dt_free_map = pinconf_generic_dt_free_map, 3923 }; 3924 3925 static int ingenic_gpio_irq_request(struct irq_data *data) 3926 { 3927 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3928 irq_hw_number_t irq = irqd_to_hwirq(data); 3929 int ret; 3930 3931 ret = pinctrl_gpio_direction_input(gpio_chip, irq); 3932 if (ret) 3933 return ret; 3934 3935 return gpiochip_reqres_irq(gpio_chip, irq); 3936 } 3937 3938 static void ingenic_gpio_irq_release(struct irq_data *data) 3939 { 3940 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3941 irq_hw_number_t irq = irqd_to_hwirq(data); 3942 3943 return gpiochip_relres_irq(gpio_chip, irq); 3944 } 3945 3946 static void ingenic_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 3947 { 3948 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3949 3950 seq_puts(p, gpio_chip->label); 3951 } 3952 3953 static const struct irq_chip ingenic_gpio_irqchip = { 3954 .irq_enable = ingenic_gpio_irq_enable, 3955 .irq_disable = ingenic_gpio_irq_disable, 3956 .irq_unmask = ingenic_gpio_irq_unmask, 3957 .irq_mask = ingenic_gpio_irq_mask, 3958 .irq_ack = ingenic_gpio_irq_ack, 3959 .irq_set_type = ingenic_gpio_irq_set_type, 3960 .irq_set_wake = ingenic_gpio_irq_set_wake, 3961 .irq_request_resources = ingenic_gpio_irq_request, 3962 .irq_release_resources = ingenic_gpio_irq_release, 3963 .irq_print_chip = ingenic_gpio_irq_print_chip, 3964 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 3965 }; 3966 3967 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, 3968 int pin, int func) 3969 { 3970 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3971 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3972 3973 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 3974 'A' + offt, idx, func); 3975 3976 if (is_soc_or_above(jzpc, ID_X1000)) { 3977 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3978 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); 3979 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); 3980 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); 3981 ingenic_shadow_config_pin_load(jzpc, pin); 3982 } else if (is_soc_or_above(jzpc, ID_JZ4770)) { 3983 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3984 ingenic_config_pin(jzpc, pin, GPIO_MSK, false); 3985 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); 3986 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); 3987 } else if (is_soc_or_above(jzpc, ID_JZ4740)) { 3988 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); 3989 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); 3990 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1); 3991 } else { 3992 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); 3993 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func); 3994 } 3995 3996 return 0; 3997 } 3998 3999 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, 4000 unsigned int selector, unsigned int group) 4001 { 4002 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 4003 const struct function_desc *func; 4004 struct group_desc *grp; 4005 unsigned int i; 4006 uintptr_t mode; 4007 u8 *pin_modes; 4008 4009 func = pinmux_generic_get_function(pctldev, selector); 4010 if (!func) 4011 return -EINVAL; 4012 4013 grp = pinctrl_generic_get_group(pctldev, group); 4014 if (!grp) 4015 return -EINVAL; 4016 4017 dev_dbg(pctldev->dev, "enable function %s group %s\n", 4018 func->func->name, grp->grp.name); 4019 4020 mode = (uintptr_t)grp->data; 4021 if (mode <= 3) { 4022 for (i = 0; i < grp->grp.npins; i++) 4023 ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], mode); 4024 } else { 4025 pin_modes = grp->data; 4026 4027 for (i = 0; i < grp->grp.npins; i++) 4028 ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], pin_modes[i]); 4029 } 4030 4031 return 0; 4032 } 4033 4034 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 4035 struct pinctrl_gpio_range *range, 4036 unsigned int pin, bool input) 4037 { 4038 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 4039 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 4040 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 4041 4042 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 4043 'A' + offt, idx, input ? "in" : "out"); 4044 4045 if (is_soc_or_above(jzpc, ID_X1000)) { 4046 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 4047 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); 4048 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); 4049 ingenic_shadow_config_pin_load(jzpc, pin); 4050 } else if (is_soc_or_above(jzpc, ID_JZ4770)) { 4051 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 4052 ingenic_config_pin(jzpc, pin, GPIO_MSK, true); 4053 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); 4054 } else if (is_soc_or_above(jzpc, ID_JZ4740)) { 4055 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); 4056 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); 4057 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); 4058 } else { 4059 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); 4060 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input); 4061 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0); 4062 } 4063 4064 return 0; 4065 } 4066 4067 static const struct pinmux_ops ingenic_pmxops = { 4068 .get_functions_count = pinmux_generic_get_function_count, 4069 .get_function_name = pinmux_generic_get_function_name, 4070 .get_function_groups = pinmux_generic_get_function_groups, 4071 .set_mux = ingenic_pinmux_set_mux, 4072 .gpio_set_direction = ingenic_pinmux_gpio_set_direction, 4073 }; 4074 4075 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, 4076 unsigned int pin, unsigned long *config) 4077 { 4078 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 4079 enum pin_config_param param = pinconf_to_config_param(*config); 4080 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 4081 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 4082 unsigned int arg = 1; 4083 unsigned int bias, reg; 4084 bool pull, pullup, pulldown; 4085 4086 if (is_soc_or_above(jzpc, ID_X2000)) { 4087 pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && 4088 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && 4089 (jzpc->info->pull_ups[offt] & BIT(idx)); 4090 pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && 4091 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && 4092 (jzpc->info->pull_downs[offt] & BIT(idx)); 4093 4094 } else if (is_soc_or_above(jzpc, ID_X1830)) { 4095 unsigned int half = PINS_PER_GPIO_CHIP / 2; 4096 unsigned int idxh = (pin % half) * 2; 4097 4098 if (idx < half) 4099 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + 4100 X1830_GPIO_PEL, &bias); 4101 else 4102 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + 4103 X1830_GPIO_PEH, &bias); 4104 4105 bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN); 4106 4107 pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx)); 4108 pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx)); 4109 4110 } else { 4111 if (is_soc_or_above(jzpc, ID_X1600)) 4112 pull = ingenic_get_pin_config(jzpc, pin, X1600_GPIO_PU); 4113 else if (is_soc_or_above(jzpc, ID_JZ4770)) 4114 pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); 4115 else if (is_soc_or_above(jzpc, ID_JZ4740)) 4116 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); 4117 else 4118 pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR); 4119 4120 pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx)); 4121 pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx)); 4122 } 4123 4124 switch (param) { 4125 case PIN_CONFIG_BIAS_DISABLE: 4126 if (pullup || pulldown) 4127 return -EINVAL; 4128 4129 break; 4130 4131 case PIN_CONFIG_BIAS_PULL_UP: 4132 if (!pullup) 4133 return -EINVAL; 4134 4135 break; 4136 4137 case PIN_CONFIG_BIAS_PULL_DOWN: 4138 if (!pulldown) 4139 return -EINVAL; 4140 4141 break; 4142 4143 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 4144 if (is_soc_or_above(jzpc, ID_X2000)) 4145 reg = X2000_GPIO_SMT; 4146 else if (is_soc_or_above(jzpc, ID_X1830)) 4147 reg = X1830_GPIO_SMT; 4148 else 4149 return -EINVAL; 4150 4151 arg = !!ingenic_get_pin_config(jzpc, pin, reg); 4152 break; 4153 4154 case PIN_CONFIG_SLEW_RATE: 4155 if (is_soc_or_above(jzpc, ID_X2000)) 4156 reg = X2000_GPIO_SR; 4157 else if (is_soc_or_above(jzpc, ID_X1830)) 4158 reg = X1830_GPIO_SR; 4159 else 4160 return -EINVAL; 4161 4162 arg = !!ingenic_get_pin_config(jzpc, pin, reg); 4163 break; 4164 4165 default: 4166 return -ENOTSUPP; 4167 } 4168 4169 *config = pinconf_to_config_packed(param, arg); 4170 return 0; 4171 } 4172 4173 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, 4174 unsigned int pin, unsigned int bias) 4175 { 4176 if (is_soc_or_above(jzpc, ID_X2000)) { 4177 switch (bias) { 4178 case GPIO_PULL_UP: 4179 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); 4180 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true); 4181 break; 4182 4183 case GPIO_PULL_DOWN: 4184 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); 4185 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true); 4186 break; 4187 4188 case GPIO_PULL_DIS: 4189 default: 4190 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); 4191 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); 4192 } 4193 4194 } else if (is_soc_or_above(jzpc, ID_X1830)) { 4195 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 4196 unsigned int half = PINS_PER_GPIO_CHIP / 2; 4197 unsigned int idxh = (pin % half) * 2; 4198 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 4199 4200 if (idx < half) { 4201 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 4202 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); 4203 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 4204 REG_SET(X1830_GPIO_PEL), bias << idxh); 4205 } else { 4206 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 4207 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); 4208 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 4209 REG_SET(X1830_GPIO_PEH), bias << idxh); 4210 } 4211 4212 } else if (is_soc_or_above(jzpc, ID_X1600)) { 4213 ingenic_config_pin(jzpc, pin, X1600_GPIO_PU, bias); 4214 } else if (is_soc_or_above(jzpc, ID_JZ4770)) { 4215 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias); 4216 } else if (is_soc_or_above(jzpc, ID_JZ4740)) { 4217 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); 4218 } else { 4219 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias); 4220 } 4221 } 4222 4223 static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc, 4224 unsigned int pin, bool enable) 4225 { 4226 if (is_soc_or_above(jzpc, ID_X2000)) 4227 ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable); 4228 else 4229 ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable); 4230 } 4231 4232 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, 4233 unsigned int pin, bool high) 4234 { 4235 if (is_soc_or_above(jzpc, ID_JZ4770)) 4236 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high); 4237 else if (is_soc_or_above(jzpc, ID_JZ4740)) 4238 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); 4239 else 4240 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high); 4241 } 4242 4243 static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc, 4244 unsigned int pin, unsigned int slew) 4245 { 4246 if (is_soc_or_above(jzpc, ID_X2000)) 4247 ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew); 4248 else 4249 ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew); 4250 } 4251 4252 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 4253 unsigned long *configs, unsigned int num_configs) 4254 { 4255 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 4256 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 4257 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 4258 unsigned int cfg, arg; 4259 int ret; 4260 4261 for (cfg = 0; cfg < num_configs; cfg++) { 4262 switch (pinconf_to_config_param(configs[cfg])) { 4263 case PIN_CONFIG_BIAS_DISABLE: 4264 case PIN_CONFIG_BIAS_PULL_UP: 4265 case PIN_CONFIG_BIAS_PULL_DOWN: 4266 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 4267 case PIN_CONFIG_LEVEL: 4268 case PIN_CONFIG_SLEW_RATE: 4269 continue; 4270 default: 4271 return -ENOTSUPP; 4272 } 4273 } 4274 4275 for (cfg = 0; cfg < num_configs; cfg++) { 4276 arg = pinconf_to_config_argument(configs[cfg]); 4277 4278 switch (pinconf_to_config_param(configs[cfg])) { 4279 case PIN_CONFIG_BIAS_DISABLE: 4280 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 4281 'A' + offt, idx); 4282 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS); 4283 break; 4284 4285 case PIN_CONFIG_BIAS_PULL_UP: 4286 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) 4287 return -EINVAL; 4288 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 4289 'A' + offt, idx); 4290 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP); 4291 break; 4292 4293 case PIN_CONFIG_BIAS_PULL_DOWN: 4294 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) 4295 return -EINVAL; 4296 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 4297 'A' + offt, idx); 4298 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); 4299 break; 4300 4301 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 4302 if (!is_soc_or_above(jzpc, ID_X1830)) 4303 return -EINVAL; 4304 4305 ingenic_set_schmitt_trigger(jzpc, pin, arg); 4306 break; 4307 4308 case PIN_CONFIG_LEVEL: 4309 ret = pinctrl_gpio_direction_output(jzpc->gc, 4310 pin - jzpc->gc->base); 4311 if (ret) 4312 return ret; 4313 4314 ingenic_set_output_level(jzpc, pin, arg); 4315 break; 4316 4317 case PIN_CONFIG_SLEW_RATE: 4318 if (!is_soc_or_above(jzpc, ID_X1830)) 4319 return -EINVAL; 4320 4321 ingenic_set_slew_rate(jzpc, pin, arg); 4322 break; 4323 4324 default: 4325 /* unreachable */ 4326 break; 4327 } 4328 } 4329 4330 return 0; 4331 } 4332 4333 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, 4334 unsigned int group, unsigned long *config) 4335 { 4336 const unsigned int *pins; 4337 unsigned int i, npins, old = 0; 4338 int ret; 4339 4340 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 4341 if (ret) 4342 return ret; 4343 4344 for (i = 0; i < npins; i++) { 4345 if (ingenic_pinconf_get(pctldev, pins[i], config)) 4346 return -ENOTSUPP; 4347 4348 /* configs do not match between two pins */ 4349 if (i && (old != *config)) 4350 return -ENOTSUPP; 4351 4352 old = *config; 4353 } 4354 4355 return 0; 4356 } 4357 4358 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, 4359 unsigned int group, unsigned long *configs, 4360 unsigned int num_configs) 4361 { 4362 const unsigned int *pins; 4363 unsigned int i, npins; 4364 int ret; 4365 4366 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 4367 if (ret) 4368 return ret; 4369 4370 for (i = 0; i < npins; i++) { 4371 ret = ingenic_pinconf_set(pctldev, 4372 pins[i], configs, num_configs); 4373 if (ret) 4374 return ret; 4375 } 4376 4377 return 0; 4378 } 4379 4380 static const struct pinconf_ops ingenic_confops = { 4381 .is_generic = true, 4382 .pin_config_get = ingenic_pinconf_get, 4383 .pin_config_set = ingenic_pinconf_set, 4384 .pin_config_group_get = ingenic_pinconf_group_get, 4385 .pin_config_group_set = ingenic_pinconf_group_set, 4386 }; 4387 4388 static const struct regmap_config ingenic_pinctrl_regmap_config = { 4389 .reg_bits = 32, 4390 .val_bits = 32, 4391 .reg_stride = 4, 4392 }; 4393 4394 static const struct of_device_id ingenic_gpio_of_matches[] __initconst = { 4395 { .compatible = "ingenic,jz4730-gpio" }, 4396 { .compatible = "ingenic,jz4740-gpio" }, 4397 { .compatible = "ingenic,jz4725b-gpio" }, 4398 { .compatible = "ingenic,jz4750-gpio" }, 4399 { .compatible = "ingenic,jz4755-gpio" }, 4400 { .compatible = "ingenic,jz4760-gpio" }, 4401 { .compatible = "ingenic,jz4770-gpio" }, 4402 { .compatible = "ingenic,jz4775-gpio" }, 4403 { .compatible = "ingenic,jz4780-gpio" }, 4404 { .compatible = "ingenic,x1000-gpio" }, 4405 { .compatible = "ingenic,x1600-gpio" }, 4406 { .compatible = "ingenic,x1830-gpio" }, 4407 { .compatible = "ingenic,x2000-gpio" }, 4408 { .compatible = "ingenic,x2100-gpio" }, 4409 {}, 4410 }; 4411 4412 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, 4413 struct fwnode_handle *fwnode) 4414 { 4415 struct ingenic_gpio_chip *jzgc; 4416 struct device *dev = jzpc->dev; 4417 struct gpio_irq_chip *girq; 4418 unsigned int bank; 4419 int err; 4420 4421 err = fwnode_property_read_u32(fwnode, "reg", &bank); 4422 if (err) { 4423 dev_err(dev, "Cannot read \"reg\" property: %i\n", err); 4424 return err; 4425 } 4426 4427 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL); 4428 if (!jzgc) 4429 return -ENOMEM; 4430 4431 jzpc->gc = &jzgc->gc; 4432 4433 jzgc->jzpc = jzpc; 4434 jzgc->reg_base = bank * jzpc->info->reg_offset; 4435 4436 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); 4437 if (!jzgc->gc.label) 4438 return -ENOMEM; 4439 4440 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY 4441 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN 4442 * <linux/gpio/consumer.h> INSTEAD. 4443 */ 4444 jzgc->gc.base = bank * 32; 4445 4446 jzgc->gc.ngpio = 32; 4447 jzgc->gc.parent = dev; 4448 jzgc->gc.fwnode = fwnode; 4449 jzgc->gc.owner = THIS_MODULE; 4450 4451 jzgc->gc.set = ingenic_gpio_set; 4452 jzgc->gc.get = ingenic_gpio_get; 4453 jzgc->gc.direction_input = pinctrl_gpio_direction_input; 4454 jzgc->gc.direction_output = ingenic_gpio_direction_output; 4455 jzgc->gc.get_direction = ingenic_gpio_get_direction; 4456 jzgc->gc.request = gpiochip_generic_request; 4457 jzgc->gc.free = gpiochip_generic_free; 4458 4459 err = fwnode_irq_get(fwnode, 0); 4460 if (err < 0) 4461 return err; 4462 if (!err) 4463 return -EINVAL; 4464 jzgc->irq = err; 4465 4466 girq = &jzgc->gc.irq; 4467 gpio_irq_chip_set_chip(girq, &ingenic_gpio_irqchip); 4468 girq->parent_handler = ingenic_gpio_irq_handler; 4469 girq->num_parents = 1; 4470 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 4471 GFP_KERNEL); 4472 if (!girq->parents) 4473 return -ENOMEM; 4474 4475 girq->parents[0] = jzgc->irq; 4476 girq->default_type = IRQ_TYPE_NONE; 4477 girq->handler = handle_level_irq; 4478 4479 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); 4480 if (err) 4481 return err; 4482 4483 return 0; 4484 } 4485 4486 static int __init ingenic_pinctrl_probe(struct platform_device *pdev) 4487 { 4488 struct device *dev = &pdev->dev; 4489 struct ingenic_pinctrl *jzpc; 4490 struct pinctrl_desc *pctl_desc; 4491 void __iomem *base; 4492 const struct ingenic_chip_info *chip_info; 4493 struct regmap_config regmap_config; 4494 struct fwnode_handle *fwnode; 4495 unsigned int i; 4496 int err; 4497 4498 chip_info = device_get_match_data(dev); 4499 if (!chip_info) { 4500 dev_err(dev, "Unsupported SoC\n"); 4501 return -EINVAL; 4502 } 4503 4504 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL); 4505 if (!jzpc) 4506 return -ENOMEM; 4507 4508 base = devm_platform_ioremap_resource(pdev, 0); 4509 if (IS_ERR(base)) 4510 return PTR_ERR(base); 4511 4512 regmap_config = ingenic_pinctrl_regmap_config; 4513 if (chip_info->access_table) { 4514 regmap_config.rd_table = chip_info->access_table; 4515 regmap_config.wr_table = chip_info->access_table; 4516 } else { 4517 regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4; 4518 } 4519 4520 jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config); 4521 if (IS_ERR(jzpc->map)) { 4522 dev_err(dev, "Failed to create regmap\n"); 4523 return PTR_ERR(jzpc->map); 4524 } 4525 4526 jzpc->dev = dev; 4527 jzpc->info = chip_info; 4528 4529 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 4530 if (!pctl_desc) 4531 return -ENOMEM; 4532 4533 /* fill in pinctrl_desc structure */ 4534 pctl_desc->name = dev_name(dev); 4535 pctl_desc->owner = THIS_MODULE; 4536 pctl_desc->pctlops = &ingenic_pctlops; 4537 pctl_desc->pmxops = &ingenic_pmxops; 4538 pctl_desc->confops = &ingenic_confops; 4539 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; 4540 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, 4541 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); 4542 if (!jzpc->pdesc) 4543 return -ENOMEM; 4544 4545 for (i = 0; i < pctl_desc->npins; i++) { 4546 jzpc->pdesc[i].number = i; 4547 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 4548 'A' + (i / PINS_PER_GPIO_CHIP), 4549 i % PINS_PER_GPIO_CHIP); 4550 } 4551 4552 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); 4553 if (IS_ERR(jzpc->pctl)) { 4554 dev_err(dev, "Failed to register pinctrl\n"); 4555 return PTR_ERR(jzpc->pctl); 4556 } 4557 4558 for (i = 0; i < chip_info->num_groups; i++) { 4559 const struct group_desc *group = &chip_info->groups[i]; 4560 const struct pingroup *grp = &group->grp; 4561 4562 err = pinctrl_generic_add_group(jzpc->pctl, grp->name, grp->pins, grp->npins, 4563 group->data); 4564 if (err < 0) { 4565 dev_err(dev, "Failed to register group %s\n", grp->name); 4566 return err; 4567 } 4568 } 4569 4570 for (i = 0; i < chip_info->num_functions; i++) { 4571 const struct pinfunction *func = &chip_info->functions[i]; 4572 4573 err = pinmux_generic_add_pinfunction(jzpc->pctl, func, NULL); 4574 if (err < 0) { 4575 dev_err(dev, "Failed to register function %s\n", func->name); 4576 return err; 4577 } 4578 } 4579 4580 dev_set_drvdata(dev, jzpc->map); 4581 4582 device_for_each_child_node(dev, fwnode) { 4583 if (of_match_node(ingenic_gpio_of_matches, to_of_node(fwnode))) { 4584 err = ingenic_gpio_probe(jzpc, fwnode); 4585 if (err) { 4586 fwnode_handle_put(fwnode); 4587 return err; 4588 } 4589 } 4590 } 4591 4592 return 0; 4593 } 4594 4595 #define IF_ENABLED(cfg, ptr) PTR_IF(IS_ENABLED(cfg), (ptr)) 4596 4597 static const struct of_device_id ingenic_pinctrl_of_matches[] = { 4598 { 4599 .compatible = "ingenic,jz4730-pinctrl", 4600 .data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info) 4601 }, 4602 { 4603 .compatible = "ingenic,jz4740-pinctrl", 4604 .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info) 4605 }, 4606 { 4607 .compatible = "ingenic,jz4725b-pinctrl", 4608 .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info) 4609 }, 4610 { 4611 .compatible = "ingenic,jz4750-pinctrl", 4612 .data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info) 4613 }, 4614 { 4615 .compatible = "ingenic,jz4755-pinctrl", 4616 .data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info) 4617 }, 4618 { 4619 .compatible = "ingenic,jz4760-pinctrl", 4620 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info) 4621 }, 4622 { 4623 .compatible = "ingenic,jz4760b-pinctrl", 4624 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info) 4625 }, 4626 { 4627 .compatible = "ingenic,jz4770-pinctrl", 4628 .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info) 4629 }, 4630 { 4631 .compatible = "ingenic,jz4775-pinctrl", 4632 .data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info) 4633 }, 4634 { 4635 .compatible = "ingenic,jz4780-pinctrl", 4636 .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info) 4637 }, 4638 { 4639 .compatible = "ingenic,x1000-pinctrl", 4640 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info) 4641 }, 4642 { 4643 .compatible = "ingenic,x1000e-pinctrl", 4644 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info) 4645 }, 4646 { 4647 .compatible = "ingenic,x1500-pinctrl", 4648 .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info) 4649 }, 4650 { 4651 .compatible = "ingenic,x1600-pinctrl", 4652 .data = IF_ENABLED(CONFIG_MACH_X1600, &x1600_chip_info) 4653 }, 4654 { 4655 .compatible = "ingenic,x1830-pinctrl", 4656 .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info) 4657 }, 4658 { 4659 .compatible = "ingenic,x2000-pinctrl", 4660 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) 4661 }, 4662 { 4663 .compatible = "ingenic,x2000e-pinctrl", 4664 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) 4665 }, 4666 { 4667 .compatible = "ingenic,x2100-pinctrl", 4668 .data = IF_ENABLED(CONFIG_MACH_X2100, &x2100_chip_info) 4669 }, 4670 { /* sentinel */ }, 4671 }; 4672 4673 static struct platform_driver ingenic_pinctrl_driver = { 4674 .driver = { 4675 .name = "pinctrl-ingenic", 4676 .of_match_table = ingenic_pinctrl_of_matches, 4677 }, 4678 }; 4679 4680 static int __init ingenic_pinctrl_drv_register(void) 4681 { 4682 return platform_driver_probe(&ingenic_pinctrl_driver, 4683 ingenic_pinctrl_probe); 4684 } 4685 subsys_initcall(ingenic_pinctrl_drv_register); 4686