1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ingenic SoCs pinctrl driver 4 * 5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> 6 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 7 */ 8 9 #include <linux/compiler.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/slab.h> 23 24 #include "core.h" 25 #include "pinconf.h" 26 #include "pinmux.h" 27 28 #define GPIO_PIN 0x00 29 #define GPIO_MSK 0x20 30 31 #define JZ4740_GPIO_DATA 0x10 32 #define JZ4740_GPIO_PULL_DIS 0x30 33 #define JZ4740_GPIO_FUNC 0x40 34 #define JZ4740_GPIO_SELECT 0x50 35 #define JZ4740_GPIO_DIR 0x60 36 #define JZ4740_GPIO_TRIG 0x70 37 #define JZ4740_GPIO_FLAG 0x80 38 39 #define JZ4760_GPIO_INT 0x10 40 #define JZ4760_GPIO_PAT1 0x30 41 #define JZ4760_GPIO_PAT0 0x40 42 #define JZ4760_GPIO_FLAG 0x50 43 #define JZ4760_GPIO_PEN 0x70 44 45 #define X1830_GPIO_PEL 0x110 46 #define X1830_GPIO_PEH 0x120 47 48 #define REG_SET(x) ((x) + 0x4) 49 #define REG_CLEAR(x) ((x) + 0x8) 50 51 #define REG_PZ_BASE(x) ((x) * 7) 52 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) 53 54 #define GPIO_PULL_DIS 0 55 #define GPIO_PULL_UP 1 56 #define GPIO_PULL_DOWN 2 57 58 #define PINS_PER_GPIO_CHIP 32 59 60 enum jz_version { 61 ID_JZ4740, 62 ID_JZ4725B, 63 ID_JZ4760, 64 ID_JZ4760B, 65 ID_JZ4770, 66 ID_JZ4780, 67 ID_X1000, 68 ID_X1000E, 69 ID_X1500, 70 ID_X1830, 71 }; 72 73 struct ingenic_chip_info { 74 unsigned int num_chips; 75 unsigned int reg_offset; 76 77 const struct group_desc *groups; 78 unsigned int num_groups; 79 80 const struct function_desc *functions; 81 unsigned int num_functions; 82 83 const u32 *pull_ups, *pull_downs; 84 }; 85 86 struct ingenic_pinctrl { 87 struct device *dev; 88 struct regmap *map; 89 struct pinctrl_dev *pctl; 90 struct pinctrl_pin_desc *pdesc; 91 enum jz_version version; 92 93 const struct ingenic_chip_info *info; 94 }; 95 96 struct ingenic_gpio_chip { 97 struct ingenic_pinctrl *jzpc; 98 struct gpio_chip gc; 99 struct irq_chip irq_chip; 100 unsigned int irq, reg_base; 101 }; 102 103 static const u32 jz4740_pull_ups[4] = { 104 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 105 }; 106 107 static const u32 jz4740_pull_downs[4] = { 108 0x00000000, 0x00000000, 0x00000000, 0x00000000, 109 }; 110 111 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, }; 112 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 113 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; 114 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 115 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; 116 static int jz4740_lcd_8bit_pins[] = { 117 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54, 118 }; 119 static int jz4740_lcd_16bit_pins[] = { 120 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55, 121 }; 122 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; 123 static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, }; 124 static int jz4740_nand_cs1_pins[] = { 0x39, }; 125 static int jz4740_nand_cs2_pins[] = { 0x3a, }; 126 static int jz4740_nand_cs3_pins[] = { 0x3b, }; 127 static int jz4740_nand_cs4_pins[] = { 0x3c, }; 128 static int jz4740_pwm_pwm0_pins[] = { 0x77, }; 129 static int jz4740_pwm_pwm1_pins[] = { 0x78, }; 130 static int jz4740_pwm_pwm2_pins[] = { 0x79, }; 131 static int jz4740_pwm_pwm3_pins[] = { 0x7a, }; 132 static int jz4740_pwm_pwm4_pins[] = { 0x7b, }; 133 static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; 134 static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; 135 static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; 136 137 static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, }; 138 static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, }; 139 static int jz4740_uart0_data_funcs[] = { 1, 1, }; 140 static int jz4740_uart0_hwflow_funcs[] = { 1, 1, }; 141 static int jz4740_uart1_data_funcs[] = { 2, 2, }; 142 static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 143 static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 144 static int jz4740_lcd_18bit_funcs[] = { 0, 0, }; 145 static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, }; 146 static int jz4740_nand_cs1_funcs[] = { 0, }; 147 static int jz4740_nand_cs2_funcs[] = { 0, }; 148 static int jz4740_nand_cs3_funcs[] = { 0, }; 149 static int jz4740_nand_cs4_funcs[] = { 0, }; 150 static int jz4740_pwm_pwm0_funcs[] = { 0, }; 151 static int jz4740_pwm_pwm1_funcs[] = { 0, }; 152 static int jz4740_pwm_pwm2_funcs[] = { 0, }; 153 static int jz4740_pwm_pwm3_funcs[] = { 0, }; 154 static int jz4740_pwm_pwm4_funcs[] = { 0, }; 155 static int jz4740_pwm_pwm5_funcs[] = { 0, }; 156 static int jz4740_pwm_pwm6_funcs[] = { 0, }; 157 static int jz4740_pwm_pwm7_funcs[] = { 0, }; 158 159 #define INGENIC_PIN_GROUP(name, id) \ 160 { \ 161 name, \ 162 id##_pins, \ 163 ARRAY_SIZE(id##_pins), \ 164 id##_funcs, \ 165 } 166 167 static const struct group_desc jz4740_groups[] = { 168 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit), 169 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit), 170 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data), 171 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow), 172 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data), 173 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit), 174 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit), 175 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit), 176 INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft), 177 { "lcd-no-pins", }, 178 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1), 179 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2), 180 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3), 181 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4), 182 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0), 183 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1), 184 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2), 185 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3), 186 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4), 187 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5), 188 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6), 189 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7), 190 }; 191 192 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 193 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 194 static const char *jz4740_uart1_groups[] = { "uart1-data", }; 195 static const char *jz4740_lcd_groups[] = { 196 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins", 197 }; 198 static const char *jz4740_nand_groups[] = { 199 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 200 }; 201 static const char *jz4740_pwm0_groups[] = { "pwm0", }; 202 static const char *jz4740_pwm1_groups[] = { "pwm1", }; 203 static const char *jz4740_pwm2_groups[] = { "pwm2", }; 204 static const char *jz4740_pwm3_groups[] = { "pwm3", }; 205 static const char *jz4740_pwm4_groups[] = { "pwm4", }; 206 static const char *jz4740_pwm5_groups[] = { "pwm5", }; 207 static const char *jz4740_pwm6_groups[] = { "pwm6", }; 208 static const char *jz4740_pwm7_groups[] = { "pwm7", }; 209 210 static const struct function_desc jz4740_functions[] = { 211 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), }, 212 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), }, 213 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), }, 214 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), }, 215 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), }, 216 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), }, 217 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), }, 218 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), }, 219 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), }, 220 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), }, 221 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), }, 222 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), }, 223 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), }, 224 }; 225 226 static const struct ingenic_chip_info jz4740_chip_info = { 227 .num_chips = 4, 228 .reg_offset = 0x100, 229 .groups = jz4740_groups, 230 .num_groups = ARRAY_SIZE(jz4740_groups), 231 .functions = jz4740_functions, 232 .num_functions = ARRAY_SIZE(jz4740_functions), 233 .pull_ups = jz4740_pull_ups, 234 .pull_downs = jz4740_pull_downs, 235 }; 236 237 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, }; 238 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, }; 239 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, }; 240 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, }; 241 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, }; 242 static int jz4725b_nand_cs1_pins[] = { 0x55, }; 243 static int jz4725b_nand_cs2_pins[] = { 0x56, }; 244 static int jz4725b_nand_cs3_pins[] = { 0x57, }; 245 static int jz4725b_nand_cs4_pins[] = { 0x58, }; 246 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 }; 247 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d }; 248 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, }; 249 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, }; 250 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, }; 251 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, }; 252 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, }; 253 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, }; 254 static int jz4725b_lcd_8bit_pins[] = { 255 0x72, 0x73, 0x74, 256 0x60, 0x61, 0x62, 0x63, 257 0x64, 0x65, 0x66, 0x67, 258 }; 259 static int jz4725b_lcd_16bit_pins[] = { 260 0x68, 0x69, 0x6a, 0x6b, 261 0x6c, 0x6d, 0x6e, 0x6f, 262 }; 263 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; 264 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 265 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 266 static int jz4725b_lcd_generic_pins[] = { 0x75, }; 267 268 static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, }; 269 static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; 270 static int jz4725b_mmc1_1bit_funcs[] = { 0, 0, 0, }; 271 static int jz4725b_mmc1_4bit_funcs[] = { 0, 0, 0, }; 272 static int jz4725b_uart_data_funcs[] = { 1, 1, }; 273 static int jz4725b_nand_cs1_funcs[] = { 0, }; 274 static int jz4725b_nand_cs2_funcs[] = { 0, }; 275 static int jz4725b_nand_cs3_funcs[] = { 0, }; 276 static int jz4725b_nand_cs4_funcs[] = { 0, }; 277 static int jz4725b_nand_cle_ale_funcs[] = { 0, 0, }; 278 static int jz4725b_nand_fre_fwe_funcs[] = { 0, 0, }; 279 static int jz4725b_pwm_pwm0_funcs[] = { 0, }; 280 static int jz4725b_pwm_pwm1_funcs[] = { 0, }; 281 static int jz4725b_pwm_pwm2_funcs[] = { 0, }; 282 static int jz4725b_pwm_pwm3_funcs[] = { 0, }; 283 static int jz4725b_pwm_pwm4_funcs[] = { 0, }; 284 static int jz4725b_pwm_pwm5_funcs[] = { 0, }; 285 static int jz4725b_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 286 static int jz4725b_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 287 static int jz4725b_lcd_18bit_funcs[] = { 0, 0, }; 288 static int jz4725b_lcd_24bit_funcs[] = { 1, 1, 1, 1, }; 289 static int jz4725b_lcd_special_funcs[] = { 0, 0, 0, 0, }; 290 static int jz4725b_lcd_generic_funcs[] = { 0, }; 291 292 static const struct group_desc jz4725b_groups[] = { 293 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit), 294 INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit), 295 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit), 296 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit), 297 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data), 298 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1), 299 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2), 300 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3), 301 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4), 302 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale), 303 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe), 304 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0), 305 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1), 306 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2), 307 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3), 308 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4), 309 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5), 310 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit), 311 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit), 312 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit), 313 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit), 314 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special), 315 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic), 316 }; 317 318 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 319 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 320 static const char *jz4725b_uart_groups[] = { "uart-data", }; 321 static const char *jz4725b_nand_groups[] = { 322 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 323 "nand-cle-ale", "nand-fre-fwe", 324 }; 325 static const char *jz4725b_pwm0_groups[] = { "pwm0", }; 326 static const char *jz4725b_pwm1_groups[] = { "pwm1", }; 327 static const char *jz4725b_pwm2_groups[] = { "pwm2", }; 328 static const char *jz4725b_pwm3_groups[] = { "pwm3", }; 329 static const char *jz4725b_pwm4_groups[] = { "pwm4", }; 330 static const char *jz4725b_pwm5_groups[] = { "pwm5", }; 331 static const char *jz4725b_lcd_groups[] = { 332 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 333 "lcd-special", "lcd-generic", 334 }; 335 336 static const struct function_desc jz4725b_functions[] = { 337 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), }, 338 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), }, 339 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), }, 340 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), }, 341 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), }, 342 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), }, 343 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), }, 344 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), }, 345 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), }, 346 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), }, 347 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), }, 348 }; 349 350 static const struct ingenic_chip_info jz4725b_chip_info = { 351 .num_chips = 4, 352 .reg_offset = 0x100, 353 .groups = jz4725b_groups, 354 .num_groups = ARRAY_SIZE(jz4725b_groups), 355 .functions = jz4725b_functions, 356 .num_functions = ARRAY_SIZE(jz4725b_functions), 357 .pull_ups = jz4740_pull_ups, 358 .pull_downs = jz4740_pull_downs, 359 }; 360 361 static const u32 jz4760_pull_ups[6] = { 362 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f, 363 }; 364 365 static const u32 jz4760_pull_downs[6] = { 366 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, 367 }; 368 369 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; 370 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 371 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; 372 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 373 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; 374 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 375 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; 376 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; 377 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 378 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 379 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 380 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 381 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 382 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 383 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 384 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 385 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 386 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 387 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 388 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 389 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 390 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 391 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 392 static int jz4760_nemc_8bit_data_pins[] = { 393 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 394 }; 395 static int jz4760_nemc_16bit_data_pins[] = { 396 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 397 }; 398 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 399 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 400 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; 401 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 402 static int jz4760_nemc_wait_pins[] = { 0x1b, }; 403 static int jz4760_nemc_cs1_pins[] = { 0x15, }; 404 static int jz4760_nemc_cs2_pins[] = { 0x16, }; 405 static int jz4760_nemc_cs3_pins[] = { 0x17, }; 406 static int jz4760_nemc_cs4_pins[] = { 0x18, }; 407 static int jz4760_nemc_cs5_pins[] = { 0x19, }; 408 static int jz4760_nemc_cs6_pins[] = { 0x1a, }; 409 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; 410 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; 411 static int jz4760_cim_pins[] = { 412 0x26, 0x27, 0x28, 0x29, 413 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 414 }; 415 static int jz4760_lcd_24bit_pins[] = { 416 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 417 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 418 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 419 0x58, 0x59, 0x5a, 0x5b, 420 }; 421 static int jz4760_pwm_pwm0_pins[] = { 0x80, }; 422 static int jz4760_pwm_pwm1_pins[] = { 0x81, }; 423 static int jz4760_pwm_pwm2_pins[] = { 0x82, }; 424 static int jz4760_pwm_pwm3_pins[] = { 0x83, }; 425 static int jz4760_pwm_pwm4_pins[] = { 0x84, }; 426 static int jz4760_pwm_pwm5_pins[] = { 0x85, }; 427 static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; 428 static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; 429 430 static int jz4760_uart0_data_funcs[] = { 0, 0, }; 431 static int jz4760_uart0_hwflow_funcs[] = { 0, 0, }; 432 static int jz4760_uart1_data_funcs[] = { 0, 0, }; 433 static int jz4760_uart1_hwflow_funcs[] = { 0, 0, }; 434 static int jz4760_uart2_data_funcs[] = { 0, 0, }; 435 static int jz4760_uart2_hwflow_funcs[] = { 0, 0, }; 436 static int jz4760_uart3_data_funcs[] = { 0, 1, }; 437 static int jz4760_uart3_hwflow_funcs[] = { 0, 0, }; 438 static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 439 static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; 440 static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; 441 static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; 442 static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; 443 static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; 444 static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; 445 static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; 446 static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; 447 static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; 448 static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; 449 static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; 450 static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; 451 static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; 452 static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; 453 static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 454 static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 455 static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, }; 456 static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, }; 457 static int jz4760_nemc_rd_we_funcs[] = { 0, 0, }; 458 static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, }; 459 static int jz4760_nemc_wait_funcs[] = { 0, }; 460 static int jz4760_nemc_cs1_funcs[] = { 0, }; 461 static int jz4760_nemc_cs2_funcs[] = { 0, }; 462 static int jz4760_nemc_cs3_funcs[] = { 0, }; 463 static int jz4760_nemc_cs4_funcs[] = { 0, }; 464 static int jz4760_nemc_cs5_funcs[] = { 0, }; 465 static int jz4760_nemc_cs6_funcs[] = { 0, }; 466 static int jz4760_i2c0_funcs[] = { 0, 0, }; 467 static int jz4760_i2c1_funcs[] = { 0, 0, }; 468 static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 469 static int jz4760_lcd_24bit_funcs[] = { 470 0, 0, 0, 0, 0, 0, 0, 0, 471 0, 0, 0, 0, 0, 0, 0, 0, 472 0, 0, 0, 0, 0, 0, 0, 0, 473 0, 0, 0, 0, 474 }; 475 static int jz4760_pwm_pwm0_funcs[] = { 0, }; 476 static int jz4760_pwm_pwm1_funcs[] = { 0, }; 477 static int jz4760_pwm_pwm2_funcs[] = { 0, }; 478 static int jz4760_pwm_pwm3_funcs[] = { 0, }; 479 static int jz4760_pwm_pwm4_funcs[] = { 0, }; 480 static int jz4760_pwm_pwm5_funcs[] = { 0, }; 481 static int jz4760_pwm_pwm6_funcs[] = { 0, }; 482 static int jz4760_pwm_pwm7_funcs[] = { 0, }; 483 484 static const struct group_desc jz4760_groups[] = { 485 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data), 486 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow), 487 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data), 488 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow), 489 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data), 490 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow), 491 INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data), 492 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow), 493 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a), 494 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a), 495 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e), 496 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e), 497 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e), 498 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d), 499 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d), 500 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e), 501 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e), 502 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e), 503 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b), 504 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b), 505 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e), 506 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e), 507 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e), 508 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data), 509 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data), 510 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale), 511 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr), 512 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we), 513 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe), 514 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait), 515 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1), 516 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2), 517 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3), 518 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4), 519 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5), 520 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6), 521 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0), 522 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1), 523 INGENIC_PIN_GROUP("cim-data", jz4760_cim), 524 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit), 525 { "lcd-no-pins", }, 526 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0), 527 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1), 528 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2), 529 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3), 530 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4), 531 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5), 532 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6), 533 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7), 534 }; 535 536 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 537 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 538 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 539 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 540 static const char *jz4760_mmc0_groups[] = { 541 "mmc0-1bit-a", "mmc0-4bit-a", 542 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 543 }; 544 static const char *jz4760_mmc1_groups[] = { 545 "mmc1-1bit-d", "mmc1-4bit-d", 546 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 547 }; 548 static const char *jz4760_mmc2_groups[] = { 549 "mmc2-1bit-b", "mmc2-4bit-b", 550 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 551 }; 552 static const char *jz4760_nemc_groups[] = { 553 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 554 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 555 }; 556 static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; 557 static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; 558 static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; 559 static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; 560 static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; 561 static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; 562 static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; 563 static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; 564 static const char *jz4760_cim_groups[] = { "cim-data", }; 565 static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; 566 static const char *jz4760_pwm0_groups[] = { "pwm0", }; 567 static const char *jz4760_pwm1_groups[] = { "pwm1", }; 568 static const char *jz4760_pwm2_groups[] = { "pwm2", }; 569 static const char *jz4760_pwm3_groups[] = { "pwm3", }; 570 static const char *jz4760_pwm4_groups[] = { "pwm4", }; 571 static const char *jz4760_pwm5_groups[] = { "pwm5", }; 572 static const char *jz4760_pwm6_groups[] = { "pwm6", }; 573 static const char *jz4760_pwm7_groups[] = { "pwm7", }; 574 575 static const struct function_desc jz4760_functions[] = { 576 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, 577 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, 578 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, 579 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, 580 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, 581 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, 582 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, 583 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), }, 584 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), }, 585 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), }, 586 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), }, 587 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), }, 588 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), }, 589 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), }, 590 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), }, 591 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), }, 592 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), }, 593 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), }, 594 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), }, 595 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), }, 596 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), }, 597 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), }, 598 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), }, 599 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), }, 600 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, 601 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, 602 }; 603 604 static const struct ingenic_chip_info jz4760_chip_info = { 605 .num_chips = 6, 606 .reg_offset = 0x100, 607 .groups = jz4760_groups, 608 .num_groups = ARRAY_SIZE(jz4760_groups), 609 .functions = jz4760_functions, 610 .num_functions = ARRAY_SIZE(jz4760_functions), 611 .pull_ups = jz4760_pull_ups, 612 .pull_downs = jz4760_pull_downs, 613 }; 614 615 static const struct ingenic_chip_info jz4760b_chip_info = { 616 .num_chips = 6, 617 .reg_offset = 0x100, 618 .groups = jz4760_groups, 619 .num_groups = ARRAY_SIZE(jz4760_groups), 620 .functions = jz4760_functions, 621 .num_functions = ARRAY_SIZE(jz4760_functions), 622 .pull_ups = jz4760_pull_ups, 623 .pull_downs = jz4760_pull_downs, 624 }; 625 626 static const u32 jz4770_pull_ups[6] = { 627 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f, 628 }; 629 630 static const u32 jz4770_pull_downs[6] = { 631 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 632 }; 633 634 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; 635 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 636 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, }; 637 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 638 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, }; 639 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 640 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; 641 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; 642 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 643 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 644 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 645 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 646 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 647 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 648 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 649 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 650 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 651 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 652 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 653 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 654 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 655 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 656 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 657 static int jz4770_nemc_8bit_data_pins[] = { 658 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 659 }; 660 static int jz4770_nemc_16bit_data_pins[] = { 661 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 662 }; 663 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 664 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 665 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, }; 666 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 667 static int jz4770_nemc_wait_pins[] = { 0x1b, }; 668 static int jz4770_nemc_cs1_pins[] = { 0x15, }; 669 static int jz4770_nemc_cs2_pins[] = { 0x16, }; 670 static int jz4770_nemc_cs3_pins[] = { 0x17, }; 671 static int jz4770_nemc_cs4_pins[] = { 0x18, }; 672 static int jz4770_nemc_cs5_pins[] = { 0x19, }; 673 static int jz4770_nemc_cs6_pins[] = { 0x1a, }; 674 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, }; 675 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, }; 676 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, }; 677 static int jz4770_cim_8bit_pins[] = { 678 0x26, 0x27, 0x28, 0x29, 679 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 680 }; 681 static int jz4770_cim_12bit_pins[] = { 682 0x32, 0x33, 0xb0, 0xb1, 683 }; 684 static int jz4770_lcd_24bit_pins[] = { 685 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 686 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 687 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 688 0x58, 0x59, 0x5a, 0x5b, 689 }; 690 static int jz4770_pwm_pwm0_pins[] = { 0x80, }; 691 static int jz4770_pwm_pwm1_pins[] = { 0x81, }; 692 static int jz4770_pwm_pwm2_pins[] = { 0x82, }; 693 static int jz4770_pwm_pwm3_pins[] = { 0x83, }; 694 static int jz4770_pwm_pwm4_pins[] = { 0x84, }; 695 static int jz4770_pwm_pwm5_pins[] = { 0x85, }; 696 static int jz4770_pwm_pwm6_pins[] = { 0x6a, }; 697 static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; 698 static int jz4770_mac_rmii_pins[] = { 699 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 700 }; 701 static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, }; 702 static int jz4770_otg_pins[] = { 0x8a, }; 703 704 static int jz4770_uart0_data_funcs[] = { 0, 0, }; 705 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, }; 706 static int jz4770_uart1_data_funcs[] = { 0, 0, }; 707 static int jz4770_uart1_hwflow_funcs[] = { 0, 0, }; 708 static int jz4770_uart2_data_funcs[] = { 0, 0, }; 709 static int jz4770_uart2_hwflow_funcs[] = { 0, 0, }; 710 static int jz4770_uart3_data_funcs[] = { 0, 1, }; 711 static int jz4770_uart3_hwflow_funcs[] = { 0, 0, }; 712 static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 713 static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; 714 static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; 715 static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; 716 static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; 717 static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; 718 static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; 719 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; 720 static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; 721 static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; 722 static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; 723 static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; 724 static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; 725 static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; 726 static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; 727 static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 728 static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 729 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, }; 730 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, }; 731 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, }; 732 static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, }; 733 static int jz4770_nemc_wait_funcs[] = { 0, }; 734 static int jz4770_nemc_cs1_funcs[] = { 0, }; 735 static int jz4770_nemc_cs2_funcs[] = { 0, }; 736 static int jz4770_nemc_cs3_funcs[] = { 0, }; 737 static int jz4770_nemc_cs4_funcs[] = { 0, }; 738 static int jz4770_nemc_cs5_funcs[] = { 0, }; 739 static int jz4770_nemc_cs6_funcs[] = { 0, }; 740 static int jz4770_i2c0_funcs[] = { 0, 0, }; 741 static int jz4770_i2c1_funcs[] = { 0, 0, }; 742 static int jz4770_i2c2_funcs[] = { 2, 2, }; 743 static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 744 static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, }; 745 static int jz4770_lcd_24bit_funcs[] = { 746 0, 0, 0, 0, 0, 0, 0, 0, 747 0, 0, 0, 0, 0, 0, 0, 0, 748 0, 0, 0, 0, 0, 0, 0, 0, 749 0, 0, 0, 0, 750 }; 751 static int jz4770_pwm_pwm0_funcs[] = { 0, }; 752 static int jz4770_pwm_pwm1_funcs[] = { 0, }; 753 static int jz4770_pwm_pwm2_funcs[] = { 0, }; 754 static int jz4770_pwm_pwm3_funcs[] = { 0, }; 755 static int jz4770_pwm_pwm4_funcs[] = { 0, }; 756 static int jz4770_pwm_pwm5_funcs[] = { 0, }; 757 static int jz4770_pwm_pwm6_funcs[] = { 0, }; 758 static int jz4770_pwm_pwm7_funcs[] = { 0, }; 759 static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 760 static int jz4770_mac_mii_funcs[] = { 0, 0, }; 761 static int jz4770_otg_funcs[] = { 0, }; 762 763 static const struct group_desc jz4770_groups[] = { 764 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data), 765 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow), 766 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data), 767 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow), 768 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data), 769 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow), 770 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), 771 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), 772 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), 773 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), 774 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), 775 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e), 776 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e), 777 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d), 778 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d), 779 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e), 780 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e), 781 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e), 782 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b), 783 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b), 784 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e), 785 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e), 786 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e), 787 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data), 788 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data), 789 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale), 790 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr), 791 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we), 792 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe), 793 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait), 794 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1), 795 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2), 796 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3), 797 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4), 798 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5), 799 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6), 800 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0), 801 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1), 802 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2), 803 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit), 804 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit), 805 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit), 806 { "lcd-no-pins", }, 807 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0), 808 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1), 809 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2), 810 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3), 811 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4), 812 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5), 813 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6), 814 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7), 815 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii), 816 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii), 817 INGENIC_PIN_GROUP("otg-vbus", jz4770_otg), 818 }; 819 820 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 821 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 822 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 823 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 824 static const char *jz4770_mmc0_groups[] = { 825 "mmc0-1bit-a", "mmc0-4bit-a", 826 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 827 }; 828 static const char *jz4770_mmc1_groups[] = { 829 "mmc1-1bit-d", "mmc1-4bit-d", 830 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 831 }; 832 static const char *jz4770_mmc2_groups[] = { 833 "mmc2-1bit-b", "mmc2-4bit-b", 834 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 835 }; 836 static const char *jz4770_nemc_groups[] = { 837 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 838 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 839 }; 840 static const char *jz4770_cs1_groups[] = { "nemc-cs1", }; 841 static const char *jz4770_cs2_groups[] = { "nemc-cs2", }; 842 static const char *jz4770_cs3_groups[] = { "nemc-cs3", }; 843 static const char *jz4770_cs4_groups[] = { "nemc-cs4", }; 844 static const char *jz4770_cs5_groups[] = { "nemc-cs5", }; 845 static const char *jz4770_cs6_groups[] = { "nemc-cs6", }; 846 static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; 847 static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; 848 static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; 849 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 850 static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; 851 static const char *jz4770_pwm0_groups[] = { "pwm0", }; 852 static const char *jz4770_pwm1_groups[] = { "pwm1", }; 853 static const char *jz4770_pwm2_groups[] = { "pwm2", }; 854 static const char *jz4770_pwm3_groups[] = { "pwm3", }; 855 static const char *jz4770_pwm4_groups[] = { "pwm4", }; 856 static const char *jz4770_pwm5_groups[] = { "pwm5", }; 857 static const char *jz4770_pwm6_groups[] = { "pwm6", }; 858 static const char *jz4770_pwm7_groups[] = { "pwm7", }; 859 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", }; 860 static const char *jz4770_otg_groups[] = { "otg-vbus", }; 861 862 static const struct function_desc jz4770_functions[] = { 863 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 864 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 865 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), }, 866 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 867 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), }, 868 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), }, 869 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), }, 870 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), }, 871 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 872 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 873 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 874 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 875 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 876 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 877 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 878 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 879 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 880 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), }, 881 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 882 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 883 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 884 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 885 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 886 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 887 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 888 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 889 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 890 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), }, 891 { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), }, 892 }; 893 894 static const struct ingenic_chip_info jz4770_chip_info = { 895 .num_chips = 6, 896 .reg_offset = 0x100, 897 .groups = jz4770_groups, 898 .num_groups = ARRAY_SIZE(jz4770_groups), 899 .functions = jz4770_functions, 900 .num_functions = ARRAY_SIZE(jz4770_functions), 901 .pull_ups = jz4770_pull_ups, 902 .pull_downs = jz4770_pull_downs, 903 }; 904 905 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; 906 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; 907 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; 908 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; 909 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; 910 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; 911 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; 912 913 static int jz4780_uart2_data_funcs[] = { 1, 1, }; 914 static int jz4780_uart2_hwflow_funcs[] = { 1, 1, }; 915 static int jz4780_uart4_data_funcs[] = { 2, 2, }; 916 static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, }; 917 static int jz4780_i2c3_funcs[] = { 1, 1, }; 918 static int jz4780_i2c4_e_funcs[] = { 1, 1, }; 919 static int jz4780_i2c4_f_funcs[] = { 1, 1, }; 920 921 static const struct group_desc jz4780_groups[] = { 922 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data), 923 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow), 924 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data), 925 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow), 926 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data), 927 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow), 928 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), 929 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), 930 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data), 931 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), 932 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), 933 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a), 934 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), 935 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e), 936 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d), 937 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d), 938 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e), 939 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e), 940 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b), 941 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b), 942 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e), 943 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e), 944 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data), 945 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale), 946 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr), 947 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we), 948 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe), 949 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait), 950 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1), 951 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2), 952 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3), 953 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4), 954 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5), 955 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6), 956 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0), 957 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1), 958 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2), 959 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3), 960 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e), 961 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f), 962 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit), 963 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit), 964 { "lcd-no-pins", }, 965 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0), 966 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1), 967 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2), 968 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3), 969 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4), 970 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5), 971 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6), 972 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7), 973 }; 974 975 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 976 static const char *jz4780_uart4_groups[] = { "uart4-data", }; 977 static const char *jz4780_mmc0_groups[] = { 978 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 979 "mmc0-1bit-e", "mmc0-4bit-e", 980 }; 981 static const char *jz4780_mmc1_groups[] = { 982 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e", 983 }; 984 static const char *jz4780_mmc2_groups[] = { 985 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e", 986 }; 987 static const char *jz4780_nemc_groups[] = { 988 "nemc-data", "nemc-cle-ale", "nemc-addr", 989 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 990 }; 991 static const char *jz4780_i2c3_groups[] = { "i2c3-data", }; 992 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; 993 static const char *jz4780_cim_groups[] = { "cim-data", }; 994 995 static const struct function_desc jz4780_functions[] = { 996 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 997 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 998 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), }, 999 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 1000 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), }, 1001 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), }, 1002 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), }, 1003 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), }, 1004 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), }, 1005 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1006 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1007 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1008 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1009 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1010 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1011 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1012 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1013 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1014 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), }, 1015 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), }, 1016 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), }, 1017 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1018 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1019 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1020 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1021 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1022 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1023 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1024 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1025 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1026 }; 1027 1028 static const struct ingenic_chip_info jz4780_chip_info = { 1029 .num_chips = 6, 1030 .reg_offset = 0x100, 1031 .groups = jz4780_groups, 1032 .num_groups = ARRAY_SIZE(jz4780_groups), 1033 .functions = jz4780_functions, 1034 .num_functions = ARRAY_SIZE(jz4780_functions), 1035 .pull_ups = jz4770_pull_ups, 1036 .pull_downs = jz4770_pull_downs, 1037 }; 1038 1039 static const u32 x1000_pull_ups[4] = { 1040 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, 1041 }; 1042 1043 static const u32 x1000_pull_downs[4] = { 1044 0x00000000, 0x02000000, 0x02000000, 0x00000000, 1045 }; 1046 1047 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; 1048 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1049 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; 1050 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; 1051 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1052 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; 1053 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; 1054 static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, }; 1055 static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; 1056 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; 1057 static int x1000_ssi_dt_d_pins[] = { 0x62, }; 1058 static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; 1059 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; 1060 static int x1000_ssi_dr_d_pins[] = { 0x63, }; 1061 static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; 1062 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; 1063 static int x1000_ssi_clk_d_pins[] = { 0x60, }; 1064 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; 1065 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; 1066 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; 1067 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; 1068 static int x1000_ssi_ce0_d_pins[] = { 0x61, }; 1069 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; 1070 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; 1071 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1072 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1073 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; 1074 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; 1075 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; 1076 static int x1000_emc_8bit_data_pins[] = { 1077 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1078 }; 1079 static int x1000_emc_16bit_data_pins[] = { 1080 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1081 }; 1082 static int x1000_emc_addr_pins[] = { 1083 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 1084 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 1085 }; 1086 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; 1087 static int x1000_emc_wait_pins[] = { 0x34, }; 1088 static int x1000_emc_cs1_pins[] = { 0x32, }; 1089 static int x1000_emc_cs2_pins[] = { 0x33, }; 1090 static int x1000_i2c0_pins[] = { 0x38, 0x37, }; 1091 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; 1092 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1093 static int x1000_i2c2_pins[] = { 0x61, 0x60, }; 1094 static int x1000_cim_pins[] = { 1095 0x08, 0x09, 0x0a, 0x0b, 1096 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1097 }; 1098 static int x1000_lcd_8bit_pins[] = { 1099 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1100 0x30, 0x31, 0x32, 0x33, 0x34, 1101 }; 1102 static int x1000_lcd_16bit_pins[] = { 1103 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1104 }; 1105 static int x1000_pwm_pwm0_pins[] = { 0x59, }; 1106 static int x1000_pwm_pwm1_pins[] = { 0x5a, }; 1107 static int x1000_pwm_pwm2_pins[] = { 0x5b, }; 1108 static int x1000_pwm_pwm3_pins[] = { 0x26, }; 1109 static int x1000_pwm_pwm4_pins[] = { 0x58, }; 1110 static int x1000_mac_pins[] = { 1111 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, 1112 }; 1113 1114 static int x1000_uart0_data_funcs[] = { 0, 0, }; 1115 static int x1000_uart0_hwflow_funcs[] = { 0, 0, }; 1116 static int x1000_uart1_data_a_funcs[] = { 2, 2, }; 1117 static int x1000_uart1_data_d_funcs[] = { 1, 1, }; 1118 static int x1000_uart1_hwflow_funcs[] = { 1, 1, }; 1119 static int x1000_uart2_data_a_funcs[] = { 2, 2, }; 1120 static int x1000_uart2_data_d_funcs[] = { 0, 0, }; 1121 static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; 1122 static int x1000_ssi_dt_a_22_funcs[] = { 2, }; 1123 static int x1000_ssi_dt_a_29_funcs[] = { 2, }; 1124 static int x1000_ssi_dt_d_funcs[] = { 0, }; 1125 static int x1000_ssi_dr_a_23_funcs[] = { 2, }; 1126 static int x1000_ssi_dr_a_28_funcs[] = { 2, }; 1127 static int x1000_ssi_dr_d_funcs[] = { 0, }; 1128 static int x1000_ssi_clk_a_24_funcs[] = { 2, }; 1129 static int x1000_ssi_clk_a_26_funcs[] = { 2, }; 1130 static int x1000_ssi_clk_d_funcs[] = { 0, }; 1131 static int x1000_ssi_gpc_a_20_funcs[] = { 2, }; 1132 static int x1000_ssi_gpc_a_31_funcs[] = { 2, }; 1133 static int x1000_ssi_ce0_a_25_funcs[] = { 2, }; 1134 static int x1000_ssi_ce0_a_27_funcs[] = { 2, }; 1135 static int x1000_ssi_ce0_d_funcs[] = { 0, }; 1136 static int x1000_ssi_ce1_a_21_funcs[] = { 2, }; 1137 static int x1000_ssi_ce1_a_30_funcs[] = { 2, }; 1138 static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, }; 1139 static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, }; 1140 static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, }; 1141 static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, }; 1142 static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, }; 1143 static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 1144 static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 1145 static int x1000_emc_addr_funcs[] = { 1146 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1147 }; 1148 static int x1000_emc_rd_we_funcs[] = { 0, 0, }; 1149 static int x1000_emc_wait_funcs[] = { 0, }; 1150 static int x1000_emc_cs1_funcs[] = { 0, }; 1151 static int x1000_emc_cs2_funcs[] = { 0, }; 1152 static int x1000_i2c0_funcs[] = { 0, 0, }; 1153 static int x1000_i2c1_a_funcs[] = { 2, 2, }; 1154 static int x1000_i2c1_c_funcs[] = { 0, 0, }; 1155 static int x1000_i2c2_funcs[] = { 1, 1, }; 1156 static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; 1157 static int x1000_lcd_8bit_funcs[] = { 1158 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1159 }; 1160 static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; 1161 static int x1000_pwm_pwm0_funcs[] = { 0, }; 1162 static int x1000_pwm_pwm1_funcs[] = { 1, }; 1163 static int x1000_pwm_pwm2_funcs[] = { 1, }; 1164 static int x1000_pwm_pwm3_funcs[] = { 2, }; 1165 static int x1000_pwm_pwm4_funcs[] = { 0, }; 1166 static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; 1167 1168 static const struct group_desc x1000_groups[] = { 1169 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data), 1170 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow), 1171 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a), 1172 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d), 1173 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow), 1174 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a), 1175 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d), 1176 INGENIC_PIN_GROUP("sfc", x1000_sfc), 1177 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22), 1178 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29), 1179 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d), 1180 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23), 1181 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28), 1182 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d), 1183 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24), 1184 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26), 1185 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d), 1186 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20), 1187 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31), 1188 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25), 1189 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27), 1190 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d), 1191 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21), 1192 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30), 1193 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit), 1194 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit), 1195 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit), 1196 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit), 1197 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit), 1198 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data), 1199 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data), 1200 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr), 1201 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we), 1202 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait), 1203 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1), 1204 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2), 1205 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0), 1206 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a), 1207 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c), 1208 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2), 1209 INGENIC_PIN_GROUP("cim-data", x1000_cim), 1210 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit), 1211 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit), 1212 { "lcd-no-pins", }, 1213 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0), 1214 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1), 1215 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2), 1216 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3), 1217 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4), 1218 INGENIC_PIN_GROUP("mac", x1000_mac), 1219 }; 1220 1221 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1222 static const char *x1000_uart1_groups[] = { 1223 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1224 }; 1225 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1226 static const char *x1000_sfc_groups[] = { "sfc", }; 1227 static const char *x1000_ssi_groups[] = { 1228 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", 1229 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", 1230 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d", 1231 "ssi-gpc-a-20", "ssi-gpc-a-31", 1232 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d", 1233 "ssi-ce1-a-21", "ssi-ce1-a-30", 1234 }; 1235 static const char *x1000_mmc0_groups[] = { 1236 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 1237 }; 1238 static const char *x1000_mmc1_groups[] = { 1239 "mmc1-1bit", "mmc1-4bit", 1240 }; 1241 static const char *x1000_emc_groups[] = { 1242 "emc-8bit-data", "emc-16bit-data", 1243 "emc-addr", "emc-rd-we", "emc-wait", 1244 }; 1245 static const char *x1000_cs1_groups[] = { "emc-cs1", }; 1246 static const char *x1000_cs2_groups[] = { "emc-cs2", }; 1247 static const char *x1000_i2c0_groups[] = { "i2c0-data", }; 1248 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1249 static const char *x1000_i2c2_groups[] = { "i2c2-data", }; 1250 static const char *x1000_cim_groups[] = { "cim-data", }; 1251 static const char *x1000_lcd_groups[] = { 1252 "lcd-8bit", "lcd-16bit", "lcd-no-pins", 1253 }; 1254 static const char *x1000_pwm0_groups[] = { "pwm0", }; 1255 static const char *x1000_pwm1_groups[] = { "pwm1", }; 1256 static const char *x1000_pwm2_groups[] = { "pwm2", }; 1257 static const char *x1000_pwm3_groups[] = { "pwm3", }; 1258 static const char *x1000_pwm4_groups[] = { "pwm4", }; 1259 static const char *x1000_mac_groups[] = { "mac", }; 1260 1261 static const struct function_desc x1000_functions[] = { 1262 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, 1263 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, 1264 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, 1265 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 1266 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), }, 1267 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, 1268 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, 1269 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, 1270 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, 1271 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, 1272 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, 1273 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, 1274 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, 1275 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, 1276 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, 1277 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, 1278 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), }, 1279 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), }, 1280 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), }, 1281 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), }, 1282 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, 1283 }; 1284 1285 static const struct ingenic_chip_info x1000_chip_info = { 1286 .num_chips = 4, 1287 .reg_offset = 0x100, 1288 .groups = x1000_groups, 1289 .num_groups = ARRAY_SIZE(x1000_groups), 1290 .functions = x1000_functions, 1291 .num_functions = ARRAY_SIZE(x1000_functions), 1292 .pull_ups = x1000_pull_ups, 1293 .pull_downs = x1000_pull_downs, 1294 }; 1295 1296 static const struct ingenic_chip_info x1000e_chip_info = { 1297 .num_chips = 4, 1298 .reg_offset = 0x100, 1299 .groups = x1000_groups, 1300 .num_groups = ARRAY_SIZE(x1000_groups), 1301 .functions = x1000_functions, 1302 .num_functions = ARRAY_SIZE(x1000_functions), 1303 .pull_ups = x1000_pull_ups, 1304 .pull_downs = x1000_pull_downs, 1305 }; 1306 1307 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; 1308 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1309 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; 1310 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; 1311 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1312 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; 1313 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; 1314 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1315 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1316 static int x1500_i2c0_pins[] = { 0x38, 0x37, }; 1317 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; 1318 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1319 static int x1500_i2c2_pins[] = { 0x61, 0x60, }; 1320 static int x1500_cim_pins[] = { 1321 0x08, 0x09, 0x0a, 0x0b, 1322 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1323 }; 1324 static int x1500_pwm_pwm0_pins[] = { 0x59, }; 1325 static int x1500_pwm_pwm1_pins[] = { 0x5a, }; 1326 static int x1500_pwm_pwm2_pins[] = { 0x5b, }; 1327 static int x1500_pwm_pwm3_pins[] = { 0x26, }; 1328 static int x1500_pwm_pwm4_pins[] = { 0x58, }; 1329 1330 static int x1500_uart0_data_funcs[] = { 0, 0, }; 1331 static int x1500_uart0_hwflow_funcs[] = { 0, 0, }; 1332 static int x1500_uart1_data_a_funcs[] = { 2, 2, }; 1333 static int x1500_uart1_data_d_funcs[] = { 1, 1, }; 1334 static int x1500_uart1_hwflow_funcs[] = { 1, 1, }; 1335 static int x1500_uart2_data_a_funcs[] = { 2, 2, }; 1336 static int x1500_uart2_data_d_funcs[] = { 0, 0, }; 1337 static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, }; 1338 static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, }; 1339 static int x1500_i2c0_funcs[] = { 0, 0, }; 1340 static int x1500_i2c1_a_funcs[] = { 2, 2, }; 1341 static int x1500_i2c1_c_funcs[] = { 0, 0, }; 1342 static int x1500_i2c2_funcs[] = { 1, 1, }; 1343 static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; 1344 static int x1500_pwm_pwm0_funcs[] = { 0, }; 1345 static int x1500_pwm_pwm1_funcs[] = { 1, }; 1346 static int x1500_pwm_pwm2_funcs[] = { 1, }; 1347 static int x1500_pwm_pwm3_funcs[] = { 2, }; 1348 static int x1500_pwm_pwm4_funcs[] = { 0, }; 1349 1350 static const struct group_desc x1500_groups[] = { 1351 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data), 1352 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow), 1353 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a), 1354 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d), 1355 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow), 1356 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a), 1357 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d), 1358 INGENIC_PIN_GROUP("sfc", x1000_sfc), 1359 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit), 1360 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit), 1361 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0), 1362 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a), 1363 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c), 1364 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2), 1365 INGENIC_PIN_GROUP("cim-data", x1500_cim), 1366 { "lcd-no-pins", }, 1367 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0), 1368 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1), 1369 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2), 1370 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3), 1371 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4), 1372 }; 1373 1374 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1375 static const char *x1500_uart1_groups[] = { 1376 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1377 }; 1378 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1379 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 1380 static const char *x1500_i2c0_groups[] = { "i2c0-data", }; 1381 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1382 static const char *x1500_i2c2_groups[] = { "i2c2-data", }; 1383 static const char *x1500_cim_groups[] = { "cim-data", }; 1384 static const char *x1500_lcd_groups[] = { "lcd-no-pins", }; 1385 static const char *x1500_pwm0_groups[] = { "pwm0", }; 1386 static const char *x1500_pwm1_groups[] = { "pwm1", }; 1387 static const char *x1500_pwm2_groups[] = { "pwm2", }; 1388 static const char *x1500_pwm3_groups[] = { "pwm3", }; 1389 static const char *x1500_pwm4_groups[] = { "pwm4", }; 1390 1391 static const struct function_desc x1500_functions[] = { 1392 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, 1393 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, 1394 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, 1395 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 1396 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, 1397 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, 1398 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, 1399 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, 1400 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, 1401 { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), }, 1402 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, 1403 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, 1404 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, 1405 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), }, 1406 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), }, 1407 }; 1408 1409 static const struct ingenic_chip_info x1500_chip_info = { 1410 .num_chips = 4, 1411 .reg_offset = 0x100, 1412 .groups = x1500_groups, 1413 .num_groups = ARRAY_SIZE(x1500_groups), 1414 .functions = x1500_functions, 1415 .num_functions = ARRAY_SIZE(x1500_functions), 1416 .pull_ups = x1000_pull_ups, 1417 .pull_downs = x1000_pull_downs, 1418 }; 1419 1420 static const u32 x1830_pull_ups[4] = { 1421 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 1422 }; 1423 1424 static const u32 x1830_pull_downs[4] = { 1425 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 1426 }; 1427 1428 static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; 1429 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; 1430 static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; 1431 static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, }; 1432 static int x1830_ssi0_dt_pins[] = { 0x4c, }; 1433 static int x1830_ssi0_dr_pins[] = { 0x4b, }; 1434 static int x1830_ssi0_clk_pins[] = { 0x4f, }; 1435 static int x1830_ssi0_gpc_pins[] = { 0x4d, }; 1436 static int x1830_ssi0_ce0_pins[] = { 0x50, }; 1437 static int x1830_ssi0_ce1_pins[] = { 0x4e, }; 1438 static int x1830_ssi1_dt_c_pins[] = { 0x53, }; 1439 static int x1830_ssi1_dr_c_pins[] = { 0x54, }; 1440 static int x1830_ssi1_clk_c_pins[] = { 0x57, }; 1441 static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; 1442 static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; 1443 static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; 1444 static int x1830_ssi1_dt_d_pins[] = { 0x62, }; 1445 static int x1830_ssi1_dr_d_pins[] = { 0x63, }; 1446 static int x1830_ssi1_clk_d_pins[] = { 0x66, }; 1447 static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; 1448 static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; 1449 static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; 1450 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; 1451 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; 1452 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; 1453 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; 1454 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; 1455 static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; 1456 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; 1457 static int x1830_pwm_pwm0_b_pins[] = { 0x31, }; 1458 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, }; 1459 static int x1830_pwm_pwm1_b_pins[] = { 0x32, }; 1460 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, }; 1461 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, }; 1462 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, }; 1463 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, }; 1464 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, }; 1465 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, }; 1466 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, }; 1467 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, }; 1468 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, }; 1469 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, }; 1470 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, }; 1471 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, }; 1472 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, }; 1473 static int x1830_mac_pins[] = { 1474 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, 1475 }; 1476 1477 static int x1830_uart0_data_funcs[] = { 0, 0, }; 1478 static int x1830_uart0_hwflow_funcs[] = { 0, 0, }; 1479 static int x1830_uart1_data_funcs[] = { 0, 0, }; 1480 static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; 1481 static int x1830_ssi0_dt_funcs[] = { 0, }; 1482 static int x1830_ssi0_dr_funcs[] = { 0, }; 1483 static int x1830_ssi0_clk_funcs[] = { 0, }; 1484 static int x1830_ssi0_gpc_funcs[] = { 0, }; 1485 static int x1830_ssi0_ce0_funcs[] = { 0, }; 1486 static int x1830_ssi0_ce1_funcs[] = { 0, }; 1487 static int x1830_ssi1_dt_c_funcs[] = { 1, }; 1488 static int x1830_ssi1_dr_c_funcs[] = { 1, }; 1489 static int x1830_ssi1_clk_c_funcs[] = { 1, }; 1490 static int x1830_ssi1_gpc_c_funcs[] = { 1, }; 1491 static int x1830_ssi1_ce0_c_funcs[] = { 1, }; 1492 static int x1830_ssi1_ce1_c_funcs[] = { 1, }; 1493 static int x1830_ssi1_dt_d_funcs[] = { 2, }; 1494 static int x1830_ssi1_dr_d_funcs[] = { 2, }; 1495 static int x1830_ssi1_clk_d_funcs[] = { 2, }; 1496 static int x1830_ssi1_gpc_d_funcs[] = { 2, }; 1497 static int x1830_ssi1_ce0_d_funcs[] = { 2, }; 1498 static int x1830_ssi1_ce1_d_funcs[] = { 2, }; 1499 static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, }; 1500 static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, }; 1501 static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, }; 1502 static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, }; 1503 static int x1830_i2c0_funcs[] = { 1, 1, }; 1504 static int x1830_i2c1_funcs[] = { 0, 0, }; 1505 static int x1830_i2c2_funcs[] = { 1, 1, }; 1506 static int x1830_pwm_pwm0_b_funcs[] = { 0, }; 1507 static int x1830_pwm_pwm0_c_funcs[] = { 1, }; 1508 static int x1830_pwm_pwm1_b_funcs[] = { 0, }; 1509 static int x1830_pwm_pwm1_c_funcs[] = { 1, }; 1510 static int x1830_pwm_pwm2_c_8_funcs[] = { 0, }; 1511 static int x1830_pwm_pwm2_c_13_funcs[] = { 1, }; 1512 static int x1830_pwm_pwm3_c_9_funcs[] = { 0, }; 1513 static int x1830_pwm_pwm3_c_14_funcs[] = { 1, }; 1514 static int x1830_pwm_pwm4_c_15_funcs[] = { 1, }; 1515 static int x1830_pwm_pwm4_c_25_funcs[] = { 0, }; 1516 static int x1830_pwm_pwm5_c_16_funcs[] = { 1, }; 1517 static int x1830_pwm_pwm5_c_26_funcs[] = { 0, }; 1518 static int x1830_pwm_pwm6_c_17_funcs[] = { 1, }; 1519 static int x1830_pwm_pwm6_c_27_funcs[] = { 0, }; 1520 static int x1830_pwm_pwm7_c_18_funcs[] = { 1, }; 1521 static int x1830_pwm_pwm7_c_28_funcs[] = { 0, }; 1522 static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 1523 1524 static const struct group_desc x1830_groups[] = { 1525 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data), 1526 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow), 1527 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data), 1528 INGENIC_PIN_GROUP("sfc", x1830_sfc), 1529 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt), 1530 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr), 1531 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk), 1532 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc), 1533 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0), 1534 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1), 1535 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c), 1536 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c), 1537 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c), 1538 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c), 1539 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c), 1540 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c), 1541 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d), 1542 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d), 1543 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d), 1544 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d), 1545 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d), 1546 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d), 1547 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit), 1548 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit), 1549 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit), 1550 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit), 1551 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0), 1552 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1), 1553 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2), 1554 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b), 1555 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c), 1556 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b), 1557 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c), 1558 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8), 1559 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13), 1560 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9), 1561 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14), 1562 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15), 1563 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25), 1564 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16), 1565 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26), 1566 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17), 1567 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27), 1568 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18), 1569 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28), 1570 INGENIC_PIN_GROUP("mac", x1830_mac), 1571 }; 1572 1573 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1574 static const char *x1830_uart1_groups[] = { "uart1-data", }; 1575 static const char *x1830_sfc_groups[] = { "sfc", }; 1576 static const char *x1830_ssi0_groups[] = { 1577 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", 1578 }; 1579 static const char *x1830_ssi1_groups[] = { 1580 "ssi1-dt-c", "ssi1-dt-d", 1581 "ssi1-dr-c", "ssi1-dr-d", 1582 "ssi1-clk-c", "ssi1-clk-d", 1583 "ssi1-gpc-c", "ssi1-gpc-d", 1584 "ssi1-ce0-c", "ssi1-ce0-d", 1585 "ssi1-ce1-c", "ssi1-ce1-d", 1586 }; 1587 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 1588 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 1589 static const char *x1830_i2c0_groups[] = { "i2c0-data", }; 1590 static const char *x1830_i2c1_groups[] = { "i2c1-data", }; 1591 static const char *x1830_i2c2_groups[] = { "i2c2-data", }; 1592 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; 1593 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; 1594 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", }; 1595 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", }; 1596 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", }; 1597 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", }; 1598 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", }; 1599 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", }; 1600 static const char *x1830_mac_groups[] = { "mac", }; 1601 1602 static const struct function_desc x1830_functions[] = { 1603 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), }, 1604 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), }, 1605 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), }, 1606 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), }, 1607 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), }, 1608 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), }, 1609 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), }, 1610 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, 1611 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, 1612 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, 1613 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, 1614 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, 1615 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), }, 1616 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), }, 1617 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1618 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1619 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1620 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1621 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, 1622 }; 1623 1624 static const struct ingenic_chip_info x1830_chip_info = { 1625 .num_chips = 4, 1626 .reg_offset = 0x1000, 1627 .groups = x1830_groups, 1628 .num_groups = ARRAY_SIZE(x1830_groups), 1629 .functions = x1830_functions, 1630 .num_functions = ARRAY_SIZE(x1830_functions), 1631 .pull_ups = x1830_pull_ups, 1632 .pull_downs = x1830_pull_downs, 1633 }; 1634 1635 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) 1636 { 1637 unsigned int val; 1638 1639 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); 1640 1641 return (u32) val; 1642 } 1643 1644 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, 1645 u8 reg, u8 offset, bool set) 1646 { 1647 if (set) 1648 reg = REG_SET(reg); 1649 else 1650 reg = REG_CLEAR(reg); 1651 1652 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); 1653 } 1654 1655 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, 1656 u8 reg, u8 offset, bool set) 1657 { 1658 if (set) 1659 reg = REG_SET(reg); 1660 else 1661 reg = REG_CLEAR(reg); 1662 1663 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( 1664 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); 1665 } 1666 1667 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) 1668 { 1669 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( 1670 jzgc->jzpc->info->reg_offset), 1671 jzgc->gc.base / PINS_PER_GPIO_CHIP); 1672 } 1673 1674 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, 1675 u8 offset) 1676 { 1677 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); 1678 1679 return !!(val & BIT(offset)); 1680 } 1681 1682 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, 1683 u8 offset, int value) 1684 { 1685 if (jzgc->jzpc->version >= ID_JZ4760) 1686 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value); 1687 else 1688 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); 1689 } 1690 1691 static void irq_set_type(struct ingenic_gpio_chip *jzgc, 1692 u8 offset, unsigned int type) 1693 { 1694 u8 reg1, reg2; 1695 1696 if (jzgc->jzpc->version >= ID_JZ4760) { 1697 reg1 = JZ4760_GPIO_PAT1; 1698 reg2 = JZ4760_GPIO_PAT0; 1699 } else { 1700 reg1 = JZ4740_GPIO_TRIG; 1701 reg2 = JZ4740_GPIO_DIR; 1702 } 1703 1704 switch (type) { 1705 case IRQ_TYPE_EDGE_RISING: 1706 if (jzgc->jzpc->version >= ID_X1000) { 1707 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); 1708 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); 1709 ingenic_gpio_shadow_set_bit_load(jzgc); 1710 } else { 1711 ingenic_gpio_set_bit(jzgc, reg2, offset, true); 1712 ingenic_gpio_set_bit(jzgc, reg1, offset, true); 1713 } 1714 break; 1715 case IRQ_TYPE_EDGE_FALLING: 1716 if (jzgc->jzpc->version >= ID_X1000) { 1717 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); 1718 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); 1719 ingenic_gpio_shadow_set_bit_load(jzgc); 1720 } else { 1721 ingenic_gpio_set_bit(jzgc, reg2, offset, false); 1722 ingenic_gpio_set_bit(jzgc, reg1, offset, true); 1723 } 1724 break; 1725 case IRQ_TYPE_LEVEL_HIGH: 1726 if (jzgc->jzpc->version >= ID_X1000) { 1727 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); 1728 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); 1729 ingenic_gpio_shadow_set_bit_load(jzgc); 1730 } else { 1731 ingenic_gpio_set_bit(jzgc, reg2, offset, true); 1732 ingenic_gpio_set_bit(jzgc, reg1, offset, false); 1733 } 1734 break; 1735 case IRQ_TYPE_LEVEL_LOW: 1736 default: 1737 if (jzgc->jzpc->version >= ID_X1000) { 1738 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); 1739 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); 1740 ingenic_gpio_shadow_set_bit_load(jzgc); 1741 } else { 1742 ingenic_gpio_set_bit(jzgc, reg2, offset, false); 1743 ingenic_gpio_set_bit(jzgc, reg1, offset, false); 1744 } 1745 break; 1746 } 1747 } 1748 1749 static void ingenic_gpio_irq_mask(struct irq_data *irqd) 1750 { 1751 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1752 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1753 1754 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true); 1755 } 1756 1757 static void ingenic_gpio_irq_unmask(struct irq_data *irqd) 1758 { 1759 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1760 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1761 1762 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false); 1763 } 1764 1765 static void ingenic_gpio_irq_enable(struct irq_data *irqd) 1766 { 1767 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1768 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1769 int irq = irqd->hwirq; 1770 1771 if (jzgc->jzpc->version >= ID_JZ4760) 1772 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true); 1773 else 1774 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); 1775 1776 ingenic_gpio_irq_unmask(irqd); 1777 } 1778 1779 static void ingenic_gpio_irq_disable(struct irq_data *irqd) 1780 { 1781 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1782 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1783 int irq = irqd->hwirq; 1784 1785 ingenic_gpio_irq_mask(irqd); 1786 1787 if (jzgc->jzpc->version >= ID_JZ4760) 1788 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false); 1789 else 1790 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); 1791 } 1792 1793 static void ingenic_gpio_irq_ack(struct irq_data *irqd) 1794 { 1795 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1796 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1797 int irq = irqd->hwirq; 1798 bool high; 1799 1800 if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) { 1801 /* 1802 * Switch to an interrupt for the opposite edge to the one that 1803 * triggered the interrupt being ACKed. 1804 */ 1805 high = ingenic_gpio_get_value(jzgc, irq); 1806 if (high) 1807 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_FALLING); 1808 else 1809 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING); 1810 } 1811 1812 if (jzgc->jzpc->version >= ID_JZ4760) 1813 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false); 1814 else 1815 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); 1816 } 1817 1818 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 1819 { 1820 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1821 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1822 1823 switch (type) { 1824 case IRQ_TYPE_EDGE_BOTH: 1825 case IRQ_TYPE_EDGE_RISING: 1826 case IRQ_TYPE_EDGE_FALLING: 1827 irq_set_handler_locked(irqd, handle_edge_irq); 1828 break; 1829 case IRQ_TYPE_LEVEL_HIGH: 1830 case IRQ_TYPE_LEVEL_LOW: 1831 irq_set_handler_locked(irqd, handle_level_irq); 1832 break; 1833 default: 1834 irq_set_handler_locked(irqd, handle_bad_irq); 1835 } 1836 1837 if (type == IRQ_TYPE_EDGE_BOTH) { 1838 /* 1839 * The hardware does not support interrupts on both edges. The 1840 * best we can do is to set up a single-edge interrupt and then 1841 * switch to the opposing edge when ACKing the interrupt. 1842 */ 1843 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq); 1844 1845 type = high ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING; 1846 } 1847 1848 irq_set_type(jzgc, irqd->hwirq, type); 1849 return 0; 1850 } 1851 1852 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on) 1853 { 1854 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1855 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1856 1857 return irq_set_irq_wake(jzgc->irq, on); 1858 } 1859 1860 static void ingenic_gpio_irq_handler(struct irq_desc *desc) 1861 { 1862 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1863 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1864 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); 1865 unsigned long flag, i; 1866 1867 chained_irq_enter(irq_chip, desc); 1868 1869 if (jzgc->jzpc->version >= ID_JZ4760) 1870 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG); 1871 else 1872 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); 1873 1874 for_each_set_bit(i, &flag, 32) 1875 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i)); 1876 chained_irq_exit(irq_chip, desc); 1877 } 1878 1879 static void ingenic_gpio_set(struct gpio_chip *gc, 1880 unsigned int offset, int value) 1881 { 1882 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1883 1884 ingenic_gpio_set_value(jzgc, offset, value); 1885 } 1886 1887 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) 1888 { 1889 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1890 1891 return (int) ingenic_gpio_get_value(jzgc, offset); 1892 } 1893 1894 static int ingenic_gpio_direction_input(struct gpio_chip *gc, 1895 unsigned int offset) 1896 { 1897 return pinctrl_gpio_direction_input(gc->base + offset); 1898 } 1899 1900 static int ingenic_gpio_direction_output(struct gpio_chip *gc, 1901 unsigned int offset, int value) 1902 { 1903 ingenic_gpio_set(gc, offset, value); 1904 return pinctrl_gpio_direction_output(gc->base + offset); 1905 } 1906 1907 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, 1908 unsigned int pin, u8 reg, bool set) 1909 { 1910 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1911 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 1912 1913 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 1914 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 1915 } 1916 1917 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, 1918 unsigned int pin, u8 reg, bool set) 1919 { 1920 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1921 1922 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + 1923 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 1924 } 1925 1926 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, 1927 unsigned int pin) 1928 { 1929 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), 1930 pin / PINS_PER_GPIO_CHIP); 1931 } 1932 1933 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, 1934 unsigned int pin, u8 reg) 1935 { 1936 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1937 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 1938 unsigned int val; 1939 1940 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); 1941 1942 return val & BIT(idx); 1943 } 1944 1945 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1946 { 1947 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1948 struct ingenic_pinctrl *jzpc = jzgc->jzpc; 1949 unsigned int pin = gc->base + offset; 1950 1951 if (jzpc->version >= ID_JZ4760) 1952 return ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1); 1953 1954 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) 1955 return true; 1956 1957 return !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR); 1958 } 1959 1960 static const struct pinctrl_ops ingenic_pctlops = { 1961 .get_groups_count = pinctrl_generic_get_group_count, 1962 .get_group_name = pinctrl_generic_get_group_name, 1963 .get_group_pins = pinctrl_generic_get_group_pins, 1964 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 1965 .dt_free_map = pinconf_generic_dt_free_map, 1966 }; 1967 1968 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, 1969 int pin, int func) 1970 { 1971 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1972 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 1973 1974 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 1975 'A' + offt, idx, func); 1976 1977 if (jzpc->version >= ID_X1000) { 1978 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 1979 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); 1980 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); 1981 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); 1982 ingenic_shadow_config_pin_load(jzpc, pin); 1983 } else if (jzpc->version >= ID_JZ4760) { 1984 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 1985 ingenic_config_pin(jzpc, pin, GPIO_MSK, false); 1986 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); 1987 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); 1988 } else { 1989 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); 1990 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); 1991 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0); 1992 } 1993 1994 return 0; 1995 } 1996 1997 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, 1998 unsigned int selector, unsigned int group) 1999 { 2000 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2001 struct function_desc *func; 2002 struct group_desc *grp; 2003 unsigned int i; 2004 2005 func = pinmux_generic_get_function(pctldev, selector); 2006 if (!func) 2007 return -EINVAL; 2008 2009 grp = pinctrl_generic_get_group(pctldev, group); 2010 if (!grp) 2011 return -EINVAL; 2012 2013 dev_dbg(pctldev->dev, "enable function %s group %s\n", 2014 func->name, grp->name); 2015 2016 for (i = 0; i < grp->num_pins; i++) { 2017 int *pin_modes = grp->data; 2018 2019 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); 2020 } 2021 2022 return 0; 2023 } 2024 2025 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 2026 struct pinctrl_gpio_range *range, 2027 unsigned int pin, bool input) 2028 { 2029 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2030 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2031 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2032 2033 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 2034 'A' + offt, idx, input ? "in" : "out"); 2035 2036 if (jzpc->version >= ID_X1000) { 2037 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2038 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); 2039 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); 2040 ingenic_shadow_config_pin_load(jzpc, pin); 2041 } else if (jzpc->version >= ID_JZ4760) { 2042 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2043 ingenic_config_pin(jzpc, pin, GPIO_MSK, true); 2044 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); 2045 } else { 2046 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); 2047 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); 2048 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); 2049 } 2050 2051 return 0; 2052 } 2053 2054 static const struct pinmux_ops ingenic_pmxops = { 2055 .get_functions_count = pinmux_generic_get_function_count, 2056 .get_function_name = pinmux_generic_get_function_name, 2057 .get_function_groups = pinmux_generic_get_function_groups, 2058 .set_mux = ingenic_pinmux_set_mux, 2059 .gpio_set_direction = ingenic_pinmux_gpio_set_direction, 2060 }; 2061 2062 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, 2063 unsigned int pin, unsigned long *config) 2064 { 2065 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2066 enum pin_config_param param = pinconf_to_config_param(*config); 2067 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2068 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2069 bool pull; 2070 2071 if (jzpc->version >= ID_JZ4760) 2072 pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN); 2073 else 2074 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); 2075 2076 switch (param) { 2077 case PIN_CONFIG_BIAS_DISABLE: 2078 if (pull) 2079 return -EINVAL; 2080 break; 2081 2082 case PIN_CONFIG_BIAS_PULL_UP: 2083 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx))) 2084 return -EINVAL; 2085 break; 2086 2087 case PIN_CONFIG_BIAS_PULL_DOWN: 2088 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx))) 2089 return -EINVAL; 2090 break; 2091 2092 default: 2093 return -ENOTSUPP; 2094 } 2095 2096 *config = pinconf_to_config_packed(param, 1); 2097 return 0; 2098 } 2099 2100 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, 2101 unsigned int pin, unsigned int bias) 2102 { 2103 if (jzpc->version >= ID_X1830) { 2104 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2105 unsigned int half = PINS_PER_GPIO_CHIP / 2; 2106 unsigned int idxh = pin % half * 2; 2107 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2108 2109 if (idx < half) { 2110 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2111 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); 2112 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2113 REG_SET(X1830_GPIO_PEL), bias << idxh); 2114 } else { 2115 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2116 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); 2117 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2118 REG_SET(X1830_GPIO_PEH), bias << idxh); 2119 } 2120 2121 } else if (jzpc->version >= ID_JZ4760) { 2122 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias); 2123 } else { 2124 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); 2125 } 2126 } 2127 2128 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, 2129 unsigned int pin, bool high) 2130 { 2131 if (jzpc->version >= ID_JZ4760) 2132 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high); 2133 else 2134 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); 2135 } 2136 2137 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2138 unsigned long *configs, unsigned int num_configs) 2139 { 2140 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2141 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2142 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2143 unsigned int cfg, arg; 2144 int ret; 2145 2146 for (cfg = 0; cfg < num_configs; cfg++) { 2147 switch (pinconf_to_config_param(configs[cfg])) { 2148 case PIN_CONFIG_BIAS_DISABLE: 2149 case PIN_CONFIG_BIAS_PULL_UP: 2150 case PIN_CONFIG_BIAS_PULL_DOWN: 2151 case PIN_CONFIG_OUTPUT: 2152 continue; 2153 default: 2154 return -ENOTSUPP; 2155 } 2156 } 2157 2158 for (cfg = 0; cfg < num_configs; cfg++) { 2159 arg = pinconf_to_config_argument(configs[cfg]); 2160 2161 switch (pinconf_to_config_param(configs[cfg])) { 2162 case PIN_CONFIG_BIAS_DISABLE: 2163 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 2164 'A' + offt, idx); 2165 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS); 2166 break; 2167 2168 case PIN_CONFIG_BIAS_PULL_UP: 2169 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) 2170 return -EINVAL; 2171 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 2172 'A' + offt, idx); 2173 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP); 2174 break; 2175 2176 case PIN_CONFIG_BIAS_PULL_DOWN: 2177 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) 2178 return -EINVAL; 2179 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 2180 'A' + offt, idx); 2181 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); 2182 break; 2183 2184 case PIN_CONFIG_OUTPUT: 2185 ret = pinctrl_gpio_direction_output(pin); 2186 if (ret) 2187 return ret; 2188 2189 ingenic_set_output_level(jzpc, pin, arg); 2190 break; 2191 2192 default: 2193 unreachable(); 2194 } 2195 } 2196 2197 return 0; 2198 } 2199 2200 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, 2201 unsigned int group, unsigned long *config) 2202 { 2203 const unsigned int *pins; 2204 unsigned int i, npins, old = 0; 2205 int ret; 2206 2207 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 2208 if (ret) 2209 return ret; 2210 2211 for (i = 0; i < npins; i++) { 2212 if (ingenic_pinconf_get(pctldev, pins[i], config)) 2213 return -ENOTSUPP; 2214 2215 /* configs do not match between two pins */ 2216 if (i && (old != *config)) 2217 return -ENOTSUPP; 2218 2219 old = *config; 2220 } 2221 2222 return 0; 2223 } 2224 2225 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, 2226 unsigned int group, unsigned long *configs, 2227 unsigned int num_configs) 2228 { 2229 const unsigned int *pins; 2230 unsigned int i, npins; 2231 int ret; 2232 2233 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 2234 if (ret) 2235 return ret; 2236 2237 for (i = 0; i < npins; i++) { 2238 ret = ingenic_pinconf_set(pctldev, 2239 pins[i], configs, num_configs); 2240 if (ret) 2241 return ret; 2242 } 2243 2244 return 0; 2245 } 2246 2247 static const struct pinconf_ops ingenic_confops = { 2248 .is_generic = true, 2249 .pin_config_get = ingenic_pinconf_get, 2250 .pin_config_set = ingenic_pinconf_set, 2251 .pin_config_group_get = ingenic_pinconf_group_get, 2252 .pin_config_group_set = ingenic_pinconf_group_set, 2253 }; 2254 2255 static const struct regmap_config ingenic_pinctrl_regmap_config = { 2256 .reg_bits = 32, 2257 .val_bits = 32, 2258 .reg_stride = 4, 2259 }; 2260 2261 static const struct of_device_id ingenic_pinctrl_of_match[] = { 2262 { .compatible = "ingenic,jz4740-pinctrl", .data = (void *) ID_JZ4740 }, 2263 { .compatible = "ingenic,jz4725b-pinctrl", .data = (void *)ID_JZ4725B }, 2264 { .compatible = "ingenic,jz4760-pinctrl", .data = (void *) ID_JZ4760 }, 2265 { .compatible = "ingenic,jz4760b-pinctrl", .data = (void *) ID_JZ4760B }, 2266 { .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 }, 2267 { .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 }, 2268 { .compatible = "ingenic,x1000-pinctrl", .data = (void *) ID_X1000 }, 2269 { .compatible = "ingenic,x1000e-pinctrl", .data = (void *) ID_X1000E }, 2270 { .compatible = "ingenic,x1500-pinctrl", .data = (void *) ID_X1500 }, 2271 { .compatible = "ingenic,x1830-pinctrl", .data = (void *) ID_X1830 }, 2272 {}, 2273 }; 2274 2275 static const struct of_device_id ingenic_gpio_of_match[] __initconst = { 2276 { .compatible = "ingenic,jz4740-gpio", }, 2277 { .compatible = "ingenic,jz4760-gpio", }, 2278 { .compatible = "ingenic,jz4770-gpio", }, 2279 { .compatible = "ingenic,jz4780-gpio", }, 2280 { .compatible = "ingenic,x1000-gpio", }, 2281 { .compatible = "ingenic,x1830-gpio", }, 2282 {}, 2283 }; 2284 2285 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, 2286 struct device_node *node) 2287 { 2288 struct ingenic_gpio_chip *jzgc; 2289 struct device *dev = jzpc->dev; 2290 struct gpio_irq_chip *girq; 2291 unsigned int bank; 2292 int err; 2293 2294 err = of_property_read_u32(node, "reg", &bank); 2295 if (err) { 2296 dev_err(dev, "Cannot read \"reg\" property: %i\n", err); 2297 return err; 2298 } 2299 2300 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL); 2301 if (!jzgc) 2302 return -ENOMEM; 2303 2304 jzgc->jzpc = jzpc; 2305 jzgc->reg_base = bank * jzpc->info->reg_offset; 2306 2307 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); 2308 if (!jzgc->gc.label) 2309 return -ENOMEM; 2310 2311 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY 2312 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN 2313 * <linux/gpio/consumer.h> INSTEAD. 2314 */ 2315 jzgc->gc.base = bank * 32; 2316 2317 jzgc->gc.ngpio = 32; 2318 jzgc->gc.parent = dev; 2319 jzgc->gc.of_node = node; 2320 jzgc->gc.owner = THIS_MODULE; 2321 2322 jzgc->gc.set = ingenic_gpio_set; 2323 jzgc->gc.get = ingenic_gpio_get; 2324 jzgc->gc.direction_input = ingenic_gpio_direction_input; 2325 jzgc->gc.direction_output = ingenic_gpio_direction_output; 2326 jzgc->gc.get_direction = ingenic_gpio_get_direction; 2327 2328 if (of_property_read_bool(node, "gpio-ranges")) { 2329 jzgc->gc.request = gpiochip_generic_request; 2330 jzgc->gc.free = gpiochip_generic_free; 2331 } 2332 2333 jzgc->irq = irq_of_parse_and_map(node, 0); 2334 if (!jzgc->irq) 2335 return -EINVAL; 2336 2337 jzgc->irq_chip.name = jzgc->gc.label; 2338 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable; 2339 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable; 2340 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask; 2341 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask; 2342 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; 2343 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; 2344 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; 2345 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; 2346 2347 girq = &jzgc->gc.irq; 2348 girq->chip = &jzgc->irq_chip; 2349 girq->parent_handler = ingenic_gpio_irq_handler; 2350 girq->num_parents = 1; 2351 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 2352 GFP_KERNEL); 2353 if (!girq->parents) 2354 return -ENOMEM; 2355 girq->parents[0] = jzgc->irq; 2356 girq->default_type = IRQ_TYPE_NONE; 2357 girq->handler = handle_level_irq; 2358 2359 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); 2360 if (err) 2361 return err; 2362 2363 return 0; 2364 } 2365 2366 static int __init ingenic_pinctrl_probe(struct platform_device *pdev) 2367 { 2368 struct device *dev = &pdev->dev; 2369 struct ingenic_pinctrl *jzpc; 2370 struct pinctrl_desc *pctl_desc; 2371 void __iomem *base; 2372 const struct platform_device_id *id = platform_get_device_id(pdev); 2373 const struct of_device_id *of_id = of_match_device( 2374 ingenic_pinctrl_of_match, dev); 2375 const struct ingenic_chip_info *chip_info; 2376 struct device_node *node; 2377 unsigned int i; 2378 int err; 2379 2380 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL); 2381 if (!jzpc) 2382 return -ENOMEM; 2383 2384 base = devm_ioremap_resource(dev, 2385 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 2386 if (IS_ERR(base)) 2387 return PTR_ERR(base); 2388 2389 jzpc->map = devm_regmap_init_mmio(dev, base, 2390 &ingenic_pinctrl_regmap_config); 2391 if (IS_ERR(jzpc->map)) { 2392 dev_err(dev, "Failed to create regmap\n"); 2393 return PTR_ERR(jzpc->map); 2394 } 2395 2396 jzpc->dev = dev; 2397 2398 if (of_id) 2399 jzpc->version = (enum jz_version)of_id->data; 2400 else 2401 jzpc->version = (enum jz_version)id->driver_data; 2402 2403 if (jzpc->version >= ID_X1830) 2404 chip_info = &x1830_chip_info; 2405 else if (jzpc->version >= ID_X1500) 2406 chip_info = &x1500_chip_info; 2407 else if (jzpc->version >= ID_X1000E) 2408 chip_info = &x1000e_chip_info; 2409 else if (jzpc->version >= ID_X1000) 2410 chip_info = &x1000_chip_info; 2411 else if (jzpc->version >= ID_JZ4780) 2412 chip_info = &jz4780_chip_info; 2413 else if (jzpc->version >= ID_JZ4770) 2414 chip_info = &jz4770_chip_info; 2415 else if (jzpc->version >= ID_JZ4760B) 2416 chip_info = &jz4760b_chip_info; 2417 else if (jzpc->version >= ID_JZ4760) 2418 chip_info = &jz4760_chip_info; 2419 else if (jzpc->version >= ID_JZ4725B) 2420 chip_info = &jz4725b_chip_info; 2421 else 2422 chip_info = &jz4740_chip_info; 2423 jzpc->info = chip_info; 2424 2425 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 2426 if (!pctl_desc) 2427 return -ENOMEM; 2428 2429 /* fill in pinctrl_desc structure */ 2430 pctl_desc->name = dev_name(dev); 2431 pctl_desc->owner = THIS_MODULE; 2432 pctl_desc->pctlops = &ingenic_pctlops; 2433 pctl_desc->pmxops = &ingenic_pmxops; 2434 pctl_desc->confops = &ingenic_confops; 2435 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; 2436 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, 2437 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); 2438 if (!jzpc->pdesc) 2439 return -ENOMEM; 2440 2441 for (i = 0; i < pctl_desc->npins; i++) { 2442 jzpc->pdesc[i].number = i; 2443 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 2444 'A' + (i / PINS_PER_GPIO_CHIP), 2445 i % PINS_PER_GPIO_CHIP); 2446 } 2447 2448 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); 2449 if (IS_ERR(jzpc->pctl)) { 2450 dev_err(dev, "Failed to register pinctrl\n"); 2451 return PTR_ERR(jzpc->pctl); 2452 } 2453 2454 for (i = 0; i < chip_info->num_groups; i++) { 2455 const struct group_desc *group = &chip_info->groups[i]; 2456 2457 err = pinctrl_generic_add_group(jzpc->pctl, group->name, 2458 group->pins, group->num_pins, group->data); 2459 if (err < 0) { 2460 dev_err(dev, "Failed to register group %s\n", 2461 group->name); 2462 return err; 2463 } 2464 } 2465 2466 for (i = 0; i < chip_info->num_functions; i++) { 2467 const struct function_desc *func = &chip_info->functions[i]; 2468 2469 err = pinmux_generic_add_function(jzpc->pctl, func->name, 2470 func->group_names, func->num_group_names, 2471 func->data); 2472 if (err < 0) { 2473 dev_err(dev, "Failed to register function %s\n", 2474 func->name); 2475 return err; 2476 } 2477 } 2478 2479 dev_set_drvdata(dev, jzpc->map); 2480 2481 for_each_child_of_node(dev->of_node, node) { 2482 if (of_match_node(ingenic_gpio_of_match, node)) { 2483 err = ingenic_gpio_probe(jzpc, node); 2484 if (err) 2485 return err; 2486 } 2487 } 2488 2489 return 0; 2490 } 2491 2492 static const struct platform_device_id ingenic_pinctrl_ids[] = { 2493 { "jz4740-pinctrl", ID_JZ4740 }, 2494 { "jz4725b-pinctrl", ID_JZ4725B }, 2495 { "jz4760-pinctrl", ID_JZ4760 }, 2496 { "jz4760b-pinctrl", ID_JZ4760B }, 2497 { "jz4770-pinctrl", ID_JZ4770 }, 2498 { "jz4780-pinctrl", ID_JZ4780 }, 2499 { "x1000-pinctrl", ID_X1000 }, 2500 { "x1000e-pinctrl", ID_X1000E }, 2501 { "x1500-pinctrl", ID_X1500 }, 2502 { "x1830-pinctrl", ID_X1830 }, 2503 {}, 2504 }; 2505 2506 static struct platform_driver ingenic_pinctrl_driver = { 2507 .driver = { 2508 .name = "pinctrl-ingenic", 2509 .of_match_table = of_match_ptr(ingenic_pinctrl_of_match), 2510 }, 2511 .id_table = ingenic_pinctrl_ids, 2512 }; 2513 2514 static int __init ingenic_pinctrl_drv_register(void) 2515 { 2516 return platform_driver_probe(&ingenic_pinctrl_driver, 2517 ingenic_pinctrl_probe); 2518 } 2519 subsys_initcall(ingenic_pinctrl_drv_register); 2520