1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ingenic SoCs pinctrl driver 4 * 5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> 6 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk> 7 * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 8 */ 9 10 #include <linux/compiler.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/property.h> 19 #include <linux/regmap.h> 20 #include <linux/seq_file.h> 21 #include <linux/slab.h> 22 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinmux.h> 28 29 #include "core.h" 30 #include "pinconf.h" 31 #include "pinmux.h" 32 33 #define GPIO_PIN 0x00 34 #define GPIO_MSK 0x20 35 36 #define JZ4730_GPIO_DATA 0x00 37 #define JZ4730_GPIO_GPDIR 0x04 38 #define JZ4730_GPIO_GPPUR 0x0c 39 #define JZ4730_GPIO_GPALR 0x10 40 #define JZ4730_GPIO_GPAUR 0x14 41 #define JZ4730_GPIO_GPIDLR 0x18 42 #define JZ4730_GPIO_GPIDUR 0x1c 43 #define JZ4730_GPIO_GPIER 0x20 44 #define JZ4730_GPIO_GPIMR 0x24 45 #define JZ4730_GPIO_GPFR 0x28 46 47 #define JZ4740_GPIO_DATA 0x10 48 #define JZ4740_GPIO_PULL_DIS 0x30 49 #define JZ4740_GPIO_FUNC 0x40 50 #define JZ4740_GPIO_SELECT 0x50 51 #define JZ4740_GPIO_DIR 0x60 52 #define JZ4740_GPIO_TRIG 0x70 53 #define JZ4740_GPIO_FLAG 0x80 54 55 #define JZ4770_GPIO_INT 0x10 56 #define JZ4770_GPIO_PAT1 0x30 57 #define JZ4770_GPIO_PAT0 0x40 58 #define JZ4770_GPIO_FLAG 0x50 59 #define JZ4770_GPIO_PEN 0x70 60 61 #define X1830_GPIO_PEL 0x110 62 #define X1830_GPIO_PEH 0x120 63 #define X1830_GPIO_SR 0x150 64 #define X1830_GPIO_SMT 0x160 65 66 #define X2000_GPIO_EDG 0x70 67 #define X2000_GPIO_PEPU 0x80 68 #define X2000_GPIO_PEPD 0x90 69 #define X2000_GPIO_SR 0xd0 70 #define X2000_GPIO_SMT 0xe0 71 72 #define REG_SET(x) ((x) + 0x4) 73 #define REG_CLEAR(x) ((x) + 0x8) 74 75 #define REG_PZ_BASE(x) ((x) * 7) 76 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) 77 78 #define GPIO_PULL_DIS 0 79 #define GPIO_PULL_UP 1 80 #define GPIO_PULL_DOWN 2 81 82 #define PINS_PER_GPIO_CHIP 32 83 #define JZ4730_PINS_PER_PAIRED_REG 16 84 85 #define INGENIC_PIN_GROUP_FUNCS(_name_, id, funcs) \ 86 { \ 87 .grp = PINCTRL_PINGROUP(_name_, id##_pins, ARRAY_SIZE(id##_pins)), \ 88 .data = funcs, \ 89 } 90 91 #define INGENIC_PIN_GROUP(_name_, id, func) \ 92 { \ 93 .grp = PINCTRL_PINGROUP(_name_, id##_pins, ARRAY_SIZE(id##_pins)), \ 94 .data = (void *)func, \ 95 } 96 97 enum jz_version { 98 ID_JZ4730, 99 ID_JZ4740, 100 ID_JZ4725B, 101 ID_JZ4750, 102 ID_JZ4755, 103 ID_JZ4760, 104 ID_JZ4770, 105 ID_JZ4775, 106 ID_JZ4780, 107 ID_X1000, 108 ID_X1500, 109 ID_X1830, 110 ID_X2000, 111 ID_X2100, 112 }; 113 114 struct ingenic_chip_info { 115 unsigned int num_chips; 116 unsigned int reg_offset; 117 enum jz_version version; 118 119 const struct group_desc *groups; 120 unsigned int num_groups; 121 122 const struct function_desc *functions; 123 unsigned int num_functions; 124 125 const u32 *pull_ups, *pull_downs; 126 127 const struct regmap_access_table *access_table; 128 }; 129 130 struct ingenic_pinctrl { 131 struct device *dev; 132 struct regmap *map; 133 struct pinctrl_dev *pctl; 134 struct pinctrl_pin_desc *pdesc; 135 136 const struct ingenic_chip_info *info; 137 138 struct gpio_chip *gc; 139 }; 140 141 struct ingenic_gpio_chip { 142 struct ingenic_pinctrl *jzpc; 143 struct gpio_chip gc; 144 unsigned int irq, reg_base; 145 }; 146 147 static const unsigned long enabled_socs = 148 IS_ENABLED(CONFIG_MACH_JZ4730) << ID_JZ4730 | 149 IS_ENABLED(CONFIG_MACH_JZ4740) << ID_JZ4740 | 150 IS_ENABLED(CONFIG_MACH_JZ4725B) << ID_JZ4725B | 151 IS_ENABLED(CONFIG_MACH_JZ4750) << ID_JZ4750 | 152 IS_ENABLED(CONFIG_MACH_JZ4755) << ID_JZ4755 | 153 IS_ENABLED(CONFIG_MACH_JZ4760) << ID_JZ4760 | 154 IS_ENABLED(CONFIG_MACH_JZ4770) << ID_JZ4770 | 155 IS_ENABLED(CONFIG_MACH_JZ4775) << ID_JZ4775 | 156 IS_ENABLED(CONFIG_MACH_JZ4780) << ID_JZ4780 | 157 IS_ENABLED(CONFIG_MACH_X1000) << ID_X1000 | 158 IS_ENABLED(CONFIG_MACH_X1500) << ID_X1500 | 159 IS_ENABLED(CONFIG_MACH_X1830) << ID_X1830 | 160 IS_ENABLED(CONFIG_MACH_X2000) << ID_X2000 | 161 IS_ENABLED(CONFIG_MACH_X2100) << ID_X2100; 162 163 static bool 164 is_soc_or_above(const struct ingenic_pinctrl *jzpc, enum jz_version version) 165 { 166 return (enabled_socs >> version) && 167 (!(enabled_socs & GENMASK(version - 1, 0)) 168 || jzpc->info->version >= version); 169 } 170 171 static const u32 jz4730_pull_ups[4] = { 172 0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff, 173 }; 174 175 static const u32 jz4730_pull_downs[4] = { 176 0x00000df0, 0x0dff0000, 0x00000000, 0x00000000, 177 }; 178 179 static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, }; 180 static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, }; 181 static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, }; 182 static int jz4730_uart1_data_pins[] = { 0x18, 0x19, }; 183 static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, }; 184 static int jz4730_uart3_data_pins[] = { 0x10, 0x15, }; 185 static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, }; 186 static int jz4730_lcd_8bit_pins[] = { 187 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 188 0x3a, 0x39, 0x38, 189 }; 190 static int jz4730_lcd_16bit_pins[] = { 191 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 192 }; 193 static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, }; 194 static int jz4730_lcd_generic_pins[] = { 0x3b, }; 195 static int jz4730_nand_cs1_pins[] = { 0x53, }; 196 static int jz4730_nand_cs2_pins[] = { 0x54, }; 197 static int jz4730_nand_cs3_pins[] = { 0x55, }; 198 static int jz4730_nand_cs4_pins[] = { 0x56, }; 199 static int jz4730_nand_cs5_pins[] = { 0x57, }; 200 static int jz4730_pwm_pwm0_pins[] = { 0x5e, }; 201 static int jz4730_pwm_pwm1_pins[] = { 0x5f, }; 202 203 static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, }; 204 205 static const struct group_desc jz4730_groups[] = { 206 INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1), 207 INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1), 208 INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1), 209 INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1), 210 INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1), 211 INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1), 212 INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1), 213 INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs), 214 INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1), 215 INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1), 216 INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1), 217 INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1), 218 INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1), 219 INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1), 220 INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1), 221 INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1), 222 INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1), 223 INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1), 224 }; 225 226 static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 227 static const char *jz4730_uart0_groups[] = { "uart0-data", }; 228 static const char *jz4730_uart1_groups[] = { "uart1-data", }; 229 static const char *jz4730_uart2_groups[] = { "uart2-data", }; 230 static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 231 static const char *jz4730_lcd_groups[] = { 232 "lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic", 233 }; 234 static const char *jz4730_nand_groups[] = { 235 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5", 236 }; 237 static const char *jz4730_pwm0_groups[] = { "pwm0", }; 238 static const char *jz4730_pwm1_groups[] = { "pwm1", }; 239 240 static const struct function_desc jz4730_functions[] = { 241 { "mmc", jz4730_mmc_groups, ARRAY_SIZE(jz4730_mmc_groups), }, 242 { "uart0", jz4730_uart0_groups, ARRAY_SIZE(jz4730_uart0_groups), }, 243 { "uart1", jz4730_uart1_groups, ARRAY_SIZE(jz4730_uart1_groups), }, 244 { "uart2", jz4730_uart2_groups, ARRAY_SIZE(jz4730_uart2_groups), }, 245 { "uart3", jz4730_uart3_groups, ARRAY_SIZE(jz4730_uart3_groups), }, 246 { "lcd", jz4730_lcd_groups, ARRAY_SIZE(jz4730_lcd_groups), }, 247 { "nand", jz4730_nand_groups, ARRAY_SIZE(jz4730_nand_groups), }, 248 { "pwm0", jz4730_pwm0_groups, ARRAY_SIZE(jz4730_pwm0_groups), }, 249 { "pwm1", jz4730_pwm1_groups, ARRAY_SIZE(jz4730_pwm1_groups), }, 250 }; 251 252 static const struct ingenic_chip_info jz4730_chip_info = { 253 .num_chips = 4, 254 .reg_offset = 0x30, 255 .version = ID_JZ4730, 256 .groups = jz4730_groups, 257 .num_groups = ARRAY_SIZE(jz4730_groups), 258 .functions = jz4730_functions, 259 .num_functions = ARRAY_SIZE(jz4730_functions), 260 .pull_ups = jz4730_pull_ups, 261 .pull_downs = jz4730_pull_downs, 262 }; 263 264 static const u32 jz4740_pull_ups[4] = { 265 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 266 }; 267 268 static const u32 jz4740_pull_downs[4] = { 269 0x00000000, 0x00000000, 0x00000000, 0x00000000, 270 }; 271 272 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, }; 273 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 274 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; 275 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 276 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; 277 static int jz4740_lcd_8bit_pins[] = { 278 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 279 0x52, 0x53, 0x54, 280 }; 281 static int jz4740_lcd_16bit_pins[] = { 282 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 283 }; 284 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; 285 static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, }; 286 static int jz4740_lcd_generic_pins[] = { 0x55, }; 287 static int jz4740_nand_cs1_pins[] = { 0x39, }; 288 static int jz4740_nand_cs2_pins[] = { 0x3a, }; 289 static int jz4740_nand_cs3_pins[] = { 0x3b, }; 290 static int jz4740_nand_cs4_pins[] = { 0x3c, }; 291 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 292 static int jz4740_pwm_pwm0_pins[] = { 0x77, }; 293 static int jz4740_pwm_pwm1_pins[] = { 0x78, }; 294 static int jz4740_pwm_pwm2_pins[] = { 0x79, }; 295 static int jz4740_pwm_pwm3_pins[] = { 0x7a, }; 296 static int jz4740_pwm_pwm4_pins[] = { 0x7b, }; 297 static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; 298 static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; 299 static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; 300 301 static const struct group_desc jz4740_groups[] = { 302 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0), 303 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0), 304 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1), 305 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1), 306 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2), 307 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0), 308 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0), 309 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0), 310 INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0), 311 INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0), 312 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0), 313 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0), 314 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0), 315 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0), 316 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0), 317 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0), 318 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0), 319 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0), 320 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0), 321 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0), 322 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0), 323 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0), 324 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0), 325 }; 326 327 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 328 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 329 static const char *jz4740_uart1_groups[] = { "uart1-data", }; 330 static const char *jz4740_lcd_groups[] = { 331 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic", 332 }; 333 static const char *jz4740_nand_groups[] = { 334 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 335 }; 336 static const char *jz4740_pwm0_groups[] = { "pwm0", }; 337 static const char *jz4740_pwm1_groups[] = { "pwm1", }; 338 static const char *jz4740_pwm2_groups[] = { "pwm2", }; 339 static const char *jz4740_pwm3_groups[] = { "pwm3", }; 340 static const char *jz4740_pwm4_groups[] = { "pwm4", }; 341 static const char *jz4740_pwm5_groups[] = { "pwm5", }; 342 static const char *jz4740_pwm6_groups[] = { "pwm6", }; 343 static const char *jz4740_pwm7_groups[] = { "pwm7", }; 344 345 static const struct function_desc jz4740_functions[] = { 346 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), }, 347 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), }, 348 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), }, 349 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), }, 350 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), }, 351 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), }, 352 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), }, 353 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), }, 354 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), }, 355 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), }, 356 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), }, 357 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), }, 358 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), }, 359 }; 360 361 static const struct ingenic_chip_info jz4740_chip_info = { 362 .num_chips = 4, 363 .reg_offset = 0x100, 364 .version = ID_JZ4740, 365 .groups = jz4740_groups, 366 .num_groups = ARRAY_SIZE(jz4740_groups), 367 .functions = jz4740_functions, 368 .num_functions = ARRAY_SIZE(jz4740_functions), 369 .pull_ups = jz4740_pull_ups, 370 .pull_downs = jz4740_pull_downs, 371 }; 372 373 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, }; 374 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, }; 375 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, }; 376 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, }; 377 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, }; 378 static int jz4725b_lcd_8bit_pins[] = { 379 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 380 0x72, 0x73, 0x74, 381 }; 382 static int jz4725b_lcd_16bit_pins[] = { 383 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 384 }; 385 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; 386 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 387 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 388 static int jz4725b_lcd_generic_pins[] = { 0x75, }; 389 static int jz4725b_nand_cs1_pins[] = { 0x55, }; 390 static int jz4725b_nand_cs2_pins[] = { 0x56, }; 391 static int jz4725b_nand_cs3_pins[] = { 0x57, }; 392 static int jz4725b_nand_cs4_pins[] = { 0x58, }; 393 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 }; 394 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d }; 395 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, }; 396 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, }; 397 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, }; 398 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, }; 399 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, }; 400 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, }; 401 402 static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; 403 404 static const struct group_desc jz4725b_groups[] = { 405 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1), 406 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit, 407 jz4725b_mmc0_4bit_funcs), 408 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0), 409 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0), 410 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1), 411 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0), 412 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0), 413 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0), 414 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1), 415 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0), 416 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0), 417 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0), 418 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0), 419 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0), 420 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0), 421 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0), 422 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0), 423 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0), 424 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0), 425 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0), 426 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0), 427 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0), 428 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0), 429 }; 430 431 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 432 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 433 static const char *jz4725b_uart_groups[] = { "uart-data", }; 434 static const char *jz4725b_lcd_groups[] = { 435 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 436 "lcd-special", "lcd-generic", 437 }; 438 static const char *jz4725b_nand_groups[] = { 439 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 440 "nand-cle-ale", "nand-fre-fwe", 441 }; 442 static const char *jz4725b_pwm0_groups[] = { "pwm0", }; 443 static const char *jz4725b_pwm1_groups[] = { "pwm1", }; 444 static const char *jz4725b_pwm2_groups[] = { "pwm2", }; 445 static const char *jz4725b_pwm3_groups[] = { "pwm3", }; 446 static const char *jz4725b_pwm4_groups[] = { "pwm4", }; 447 static const char *jz4725b_pwm5_groups[] = { "pwm5", }; 448 449 static const struct function_desc jz4725b_functions[] = { 450 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), }, 451 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), }, 452 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), }, 453 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), }, 454 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), }, 455 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), }, 456 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), }, 457 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), }, 458 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), }, 459 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), }, 460 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), }, 461 }; 462 463 static const struct ingenic_chip_info jz4725b_chip_info = { 464 .num_chips = 4, 465 .reg_offset = 0x100, 466 .version = ID_JZ4725B, 467 .groups = jz4725b_groups, 468 .num_groups = ARRAY_SIZE(jz4725b_groups), 469 .functions = jz4725b_functions, 470 .num_functions = ARRAY_SIZE(jz4725b_functions), 471 .pull_ups = jz4740_pull_ups, 472 .pull_downs = jz4740_pull_downs, 473 }; 474 475 static const u32 jz4750_pull_ups[6] = { 476 0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff, 477 }; 478 479 static const u32 jz4750_pull_downs[6] = { 480 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 481 }; 482 483 static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, }; 484 static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, }; 485 static int jz4750_uart1_data_pins[] = { 0x90, 0x91, }; 486 static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, }; 487 static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, }; 488 static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, }; 489 static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, }; 490 static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, }; 491 static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, }; 492 static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, }; 493 static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, }; 494 static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, }; 495 static int jz4750_i2c_pins[] = { 0x8c, 0x8d, }; 496 static int jz4750_cim_pins[] = { 497 0x89, 0x8b, 0x8a, 0x88, 498 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 499 }; 500 static int jz4750_lcd_8bit_pins[] = { 501 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 502 0x72, 0x73, 0x74, 503 }; 504 static int jz4750_lcd_16bit_pins[] = { 505 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 506 }; 507 static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, }; 508 static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, }; 509 static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 510 static int jz4750_lcd_generic_pins[] = { 0x75, }; 511 static int jz4750_nand_cs1_pins[] = { 0x55, }; 512 static int jz4750_nand_cs2_pins[] = { 0x56, }; 513 static int jz4750_nand_cs3_pins[] = { 0x57, }; 514 static int jz4750_nand_cs4_pins[] = { 0x58, }; 515 static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 516 static int jz4750_pwm_pwm0_pins[] = { 0x94, }; 517 static int jz4750_pwm_pwm1_pins[] = { 0x95, }; 518 static int jz4750_pwm_pwm2_pins[] = { 0x96, }; 519 static int jz4750_pwm_pwm3_pins[] = { 0x97, }; 520 static int jz4750_pwm_pwm4_pins[] = { 0x98, }; 521 static int jz4750_pwm_pwm5_pins[] = { 0x99, }; 522 523 static const struct group_desc jz4750_groups[] = { 524 INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1), 525 INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1), 526 INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0), 527 INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0), 528 INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1), 529 INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0), 530 INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0), 531 INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0), 532 INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0), 533 INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0), 534 INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0), 535 INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0), 536 INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0), 537 INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0), 538 INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0), 539 INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0), 540 INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0), 541 INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1), 542 INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0), 543 INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0), 544 INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0), 545 INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0), 546 INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0), 547 INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0), 548 INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0), 549 INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0), 550 INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0), 551 INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0), 552 INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0), 553 INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0), 554 INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0), 555 }; 556 557 static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 558 static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 559 static const char *jz4750_uart2_groups[] = { "uart2-data", }; 560 static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 561 static const char *jz4750_mmc0_groups[] = { 562 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 563 }; 564 static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 565 static const char *jz4750_i2c_groups[] = { "i2c-data", }; 566 static const char *jz4750_cim_groups[] = { "cim-data", }; 567 static const char *jz4750_lcd_groups[] = { 568 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 569 "lcd-special", "lcd-generic", 570 }; 571 static const char *jz4750_nand_groups[] = { 572 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 573 }; 574 static const char *jz4750_pwm0_groups[] = { "pwm0", }; 575 static const char *jz4750_pwm1_groups[] = { "pwm1", }; 576 static const char *jz4750_pwm2_groups[] = { "pwm2", }; 577 static const char *jz4750_pwm3_groups[] = { "pwm3", }; 578 static const char *jz4750_pwm4_groups[] = { "pwm4", }; 579 static const char *jz4750_pwm5_groups[] = { "pwm5", }; 580 581 static const struct function_desc jz4750_functions[] = { 582 { "uart0", jz4750_uart0_groups, ARRAY_SIZE(jz4750_uart0_groups), }, 583 { "uart1", jz4750_uart1_groups, ARRAY_SIZE(jz4750_uart1_groups), }, 584 { "uart2", jz4750_uart2_groups, ARRAY_SIZE(jz4750_uart2_groups), }, 585 { "uart3", jz4750_uart3_groups, ARRAY_SIZE(jz4750_uart3_groups), }, 586 { "mmc0", jz4750_mmc0_groups, ARRAY_SIZE(jz4750_mmc0_groups), }, 587 { "mmc1", jz4750_mmc1_groups, ARRAY_SIZE(jz4750_mmc1_groups), }, 588 { "i2c", jz4750_i2c_groups, ARRAY_SIZE(jz4750_i2c_groups), }, 589 { "cim", jz4750_cim_groups, ARRAY_SIZE(jz4750_cim_groups), }, 590 { "lcd", jz4750_lcd_groups, ARRAY_SIZE(jz4750_lcd_groups), }, 591 { "nand", jz4750_nand_groups, ARRAY_SIZE(jz4750_nand_groups), }, 592 { "pwm0", jz4750_pwm0_groups, ARRAY_SIZE(jz4750_pwm0_groups), }, 593 { "pwm1", jz4750_pwm1_groups, ARRAY_SIZE(jz4750_pwm1_groups), }, 594 { "pwm2", jz4750_pwm2_groups, ARRAY_SIZE(jz4750_pwm2_groups), }, 595 { "pwm3", jz4750_pwm3_groups, ARRAY_SIZE(jz4750_pwm3_groups), }, 596 { "pwm4", jz4750_pwm4_groups, ARRAY_SIZE(jz4750_pwm4_groups), }, 597 { "pwm5", jz4750_pwm5_groups, ARRAY_SIZE(jz4750_pwm5_groups), }, 598 }; 599 600 static const struct ingenic_chip_info jz4750_chip_info = { 601 .num_chips = 6, 602 .reg_offset = 0x100, 603 .version = ID_JZ4750, 604 .groups = jz4750_groups, 605 .num_groups = ARRAY_SIZE(jz4750_groups), 606 .functions = jz4750_functions, 607 .num_functions = ARRAY_SIZE(jz4750_functions), 608 .pull_ups = jz4750_pull_ups, 609 .pull_downs = jz4750_pull_downs, 610 }; 611 612 static const u32 jz4755_pull_ups[6] = { 613 0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00, 614 }; 615 616 static const u32 jz4755_pull_downs[6] = { 617 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 618 }; 619 620 static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, }; 621 static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 622 static int jz4755_uart1_data_pins[] = { 0x97, 0x99, }; 623 static int jz4755_uart2_data_pins[] = { 0x9f, }; 624 static int jz4755_ssi_dt_b_pins[] = { 0x3b, }; 625 static int jz4755_ssi_dt_f_pins[] = { 0xa1, }; 626 static int jz4755_ssi_dr_b_pins[] = { 0x3c, }; 627 static int jz4755_ssi_dr_f_pins[] = { 0xa2, }; 628 static int jz4755_ssi_clk_b_pins[] = { 0x3a, }; 629 static int jz4755_ssi_clk_f_pins[] = { 0xa0, }; 630 static int jz4755_ssi_gpc_b_pins[] = { 0x3e, }; 631 static int jz4755_ssi_gpc_f_pins[] = { 0xa4, }; 632 static int jz4755_ssi_ce0_b_pins[] = { 0x3d, }; 633 static int jz4755_ssi_ce0_f_pins[] = { 0xa3, }; 634 static int jz4755_ssi_ce1_b_pins[] = { 0x3f, }; 635 static int jz4755_ssi_ce1_f_pins[] = { 0xa5, }; 636 static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, }; 637 static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, }; 638 static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, }; 639 static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, }; 640 static int jz4755_i2c_pins[] = { 0x8c, 0x8d, }; 641 static int jz4755_cim_pins[] = { 642 0x89, 0x8b, 0x8a, 0x88, 643 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 644 }; 645 static int jz4755_lcd_8bit_pins[] = { 646 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 647 0x72, 0x73, 0x74, 648 }; 649 static int jz4755_lcd_16bit_pins[] = { 650 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 651 }; 652 static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, }; 653 static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, }; 654 static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 655 static int jz4755_lcd_generic_pins[] = { 0x75, }; 656 static int jz4755_nand_cs1_pins[] = { 0x55, }; 657 static int jz4755_nand_cs2_pins[] = { 0x56, }; 658 static int jz4755_nand_cs3_pins[] = { 0x57, }; 659 static int jz4755_nand_cs4_pins[] = { 0x58, }; 660 static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; 661 static int jz4755_pwm_pwm0_pins[] = { 0x94, }; 662 static int jz4755_pwm_pwm1_pins[] = { 0xab, }; 663 static int jz4755_pwm_pwm2_pins[] = { 0x96, }; 664 static int jz4755_pwm_pwm3_pins[] = { 0x97, }; 665 static int jz4755_pwm_pwm4_pins[] = { 0x98, }; 666 static int jz4755_pwm_pwm5_pins[] = { 0x99, }; 667 668 static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, }; 669 static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, }; 670 static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, }; 671 672 static const struct group_desc jz4755_groups[] = { 673 INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0), 674 INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0), 675 INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1), 676 INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1), 677 INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0), 678 INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0), 679 INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0), 680 INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0), 681 INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0), 682 INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0), 683 INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0), 684 INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0), 685 INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0), 686 INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0), 687 INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0), 688 INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0), 689 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit, 690 jz4755_mmc0_1bit_funcs), 691 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit, 692 jz4755_mmc0_4bit_funcs), 693 INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1), 694 INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1), 695 INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0), 696 INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0), 697 INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0), 698 INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0), 699 INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0), 700 INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit, 701 jz4755_lcd_24bit_funcs), 702 INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0), 703 INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0), 704 INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0), 705 INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0), 706 INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0), 707 INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0), 708 INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0), 709 INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0), 710 INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1), 711 INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0), 712 INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0), 713 INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0), 714 INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0), 715 }; 716 717 static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 718 static const char *jz4755_uart1_groups[] = { "uart1-data", }; 719 static const char *jz4755_uart2_groups[] = { "uart2-data", }; 720 static const char *jz4755_ssi_groups[] = { 721 "ssi-dt-b", "ssi-dt-f", 722 "ssi-dr-b", "ssi-dr-f", 723 "ssi-clk-b", "ssi-clk-f", 724 "ssi-gpc-b", "ssi-gpc-f", 725 "ssi-ce0-b", "ssi-ce0-f", 726 "ssi-ce1-b", "ssi-ce1-f", 727 }; 728 static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 729 static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 730 static const char *jz4755_i2c_groups[] = { "i2c-data", }; 731 static const char *jz4755_cim_groups[] = { "cim-data", }; 732 static const char *jz4755_lcd_groups[] = { 733 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 734 "lcd-special", "lcd-generic", 735 }; 736 static const char *jz4755_nand_groups[] = { 737 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", 738 }; 739 static const char *jz4755_pwm0_groups[] = { "pwm0", }; 740 static const char *jz4755_pwm1_groups[] = { "pwm1", }; 741 static const char *jz4755_pwm2_groups[] = { "pwm2", }; 742 static const char *jz4755_pwm3_groups[] = { "pwm3", }; 743 static const char *jz4755_pwm4_groups[] = { "pwm4", }; 744 static const char *jz4755_pwm5_groups[] = { "pwm5", }; 745 746 static const struct function_desc jz4755_functions[] = { 747 { "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), }, 748 { "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), }, 749 { "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), }, 750 { "ssi", jz4755_ssi_groups, ARRAY_SIZE(jz4755_ssi_groups), }, 751 { "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), }, 752 { "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), }, 753 { "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), }, 754 { "cim", jz4755_cim_groups, ARRAY_SIZE(jz4755_cim_groups), }, 755 { "lcd", jz4755_lcd_groups, ARRAY_SIZE(jz4755_lcd_groups), }, 756 { "nand", jz4755_nand_groups, ARRAY_SIZE(jz4755_nand_groups), }, 757 { "pwm0", jz4755_pwm0_groups, ARRAY_SIZE(jz4755_pwm0_groups), }, 758 { "pwm1", jz4755_pwm1_groups, ARRAY_SIZE(jz4755_pwm1_groups), }, 759 { "pwm2", jz4755_pwm2_groups, ARRAY_SIZE(jz4755_pwm2_groups), }, 760 { "pwm3", jz4755_pwm3_groups, ARRAY_SIZE(jz4755_pwm3_groups), }, 761 { "pwm4", jz4755_pwm4_groups, ARRAY_SIZE(jz4755_pwm4_groups), }, 762 { "pwm5", jz4755_pwm5_groups, ARRAY_SIZE(jz4755_pwm5_groups), }, 763 }; 764 765 static const struct ingenic_chip_info jz4755_chip_info = { 766 .num_chips = 6, 767 .reg_offset = 0x100, 768 .version = ID_JZ4755, 769 .groups = jz4755_groups, 770 .num_groups = ARRAY_SIZE(jz4755_groups), 771 .functions = jz4755_functions, 772 .num_functions = ARRAY_SIZE(jz4755_functions), 773 .pull_ups = jz4755_pull_ups, 774 .pull_downs = jz4755_pull_downs, 775 }; 776 777 static const u32 jz4760_pull_ups[6] = { 778 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f, 779 }; 780 781 static const u32 jz4760_pull_downs[6] = { 782 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, 783 }; 784 785 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; 786 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 787 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; 788 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 789 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; 790 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 791 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; 792 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; 793 static int jz4760_ssi0_dt_a_pins[] = { 0x15, }; 794 static int jz4760_ssi0_dt_b_pins[] = { 0x35, }; 795 static int jz4760_ssi0_dt_d_pins[] = { 0x75, }; 796 static int jz4760_ssi0_dt_e_pins[] = { 0x91, }; 797 static int jz4760_ssi0_dr_a_pins[] = { 0x14, }; 798 static int jz4760_ssi0_dr_b_pins[] = { 0x34, }; 799 static int jz4760_ssi0_dr_d_pins[] = { 0x74, }; 800 static int jz4760_ssi0_dr_e_pins[] = { 0x8e, }; 801 static int jz4760_ssi0_clk_a_pins[] = { 0x12, }; 802 static int jz4760_ssi0_clk_b_pins[] = { 0x3c, }; 803 static int jz4760_ssi0_clk_d_pins[] = { 0x78, }; 804 static int jz4760_ssi0_clk_e_pins[] = { 0x8f, }; 805 static int jz4760_ssi0_gpc_b_pins[] = { 0x3e, }; 806 static int jz4760_ssi0_gpc_d_pins[] = { 0x76, }; 807 static int jz4760_ssi0_gpc_e_pins[] = { 0x93, }; 808 static int jz4760_ssi0_ce0_a_pins[] = { 0x13, }; 809 static int jz4760_ssi0_ce0_b_pins[] = { 0x3d, }; 810 static int jz4760_ssi0_ce0_d_pins[] = { 0x79, }; 811 static int jz4760_ssi0_ce0_e_pins[] = { 0x90, }; 812 static int jz4760_ssi0_ce1_b_pins[] = { 0x3f, }; 813 static int jz4760_ssi0_ce1_d_pins[] = { 0x77, }; 814 static int jz4760_ssi0_ce1_e_pins[] = { 0x92, }; 815 static int jz4760_ssi1_dt_b_9_pins[] = { 0x29, }; 816 static int jz4760_ssi1_dt_b_21_pins[] = { 0x35, }; 817 static int jz4760_ssi1_dt_d_12_pins[] = { 0x6c, }; 818 static int jz4760_ssi1_dt_d_21_pins[] = { 0x75, }; 819 static int jz4760_ssi1_dt_e_pins[] = { 0x91, }; 820 static int jz4760_ssi1_dt_f_pins[] = { 0xa3, }; 821 static int jz4760_ssi1_dr_b_6_pins[] = { 0x26, }; 822 static int jz4760_ssi1_dr_b_20_pins[] = { 0x34, }; 823 static int jz4760_ssi1_dr_d_13_pins[] = { 0x6d, }; 824 static int jz4760_ssi1_dr_d_20_pins[] = { 0x74, }; 825 static int jz4760_ssi1_dr_e_pins[] = { 0x8e, }; 826 static int jz4760_ssi1_dr_f_pins[] = { 0xa0, }; 827 static int jz4760_ssi1_clk_b_7_pins[] = { 0x27, }; 828 static int jz4760_ssi1_clk_b_28_pins[] = { 0x3c, }; 829 static int jz4760_ssi1_clk_d_pins[] = { 0x78, }; 830 static int jz4760_ssi1_clk_e_7_pins[] = { 0x87, }; 831 static int jz4760_ssi1_clk_e_15_pins[] = { 0x8f, }; 832 static int jz4760_ssi1_clk_f_pins[] = { 0xa2, }; 833 static int jz4760_ssi1_gpc_b_pins[] = { 0x3e, }; 834 static int jz4760_ssi1_gpc_d_pins[] = { 0x76, }; 835 static int jz4760_ssi1_gpc_e_pins[] = { 0x93, }; 836 static int jz4760_ssi1_ce0_b_8_pins[] = { 0x28, }; 837 static int jz4760_ssi1_ce0_b_29_pins[] = { 0x3d, }; 838 static int jz4760_ssi1_ce0_d_pins[] = { 0x79, }; 839 static int jz4760_ssi1_ce0_e_6_pins[] = { 0x86, }; 840 static int jz4760_ssi1_ce0_e_16_pins[] = { 0x90, }; 841 static int jz4760_ssi1_ce0_f_pins[] = { 0xa1, }; 842 static int jz4760_ssi1_ce1_b_pins[] = { 0x3f, }; 843 static int jz4760_ssi1_ce1_d_pins[] = { 0x77, }; 844 static int jz4760_ssi1_ce1_e_pins[] = { 0x92, }; 845 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 846 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 847 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 848 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 849 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 850 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 851 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 852 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 853 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 854 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 855 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 856 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 857 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 858 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 859 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 860 static int jz4760_nemc_8bit_data_pins[] = { 861 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 862 }; 863 static int jz4760_nemc_16bit_data_pins[] = { 864 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 865 }; 866 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 867 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 868 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; 869 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 870 static int jz4760_nemc_wait_pins[] = { 0x1b, }; 871 static int jz4760_nemc_cs1_pins[] = { 0x15, }; 872 static int jz4760_nemc_cs2_pins[] = { 0x16, }; 873 static int jz4760_nemc_cs3_pins[] = { 0x17, }; 874 static int jz4760_nemc_cs4_pins[] = { 0x18, }; 875 static int jz4760_nemc_cs5_pins[] = { 0x19, }; 876 static int jz4760_nemc_cs6_pins[] = { 0x1a, }; 877 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; 878 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; 879 static int jz4760_cim_pins[] = { 880 0x26, 0x27, 0x28, 0x29, 881 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 882 }; 883 static int jz4760_lcd_8bit_pins[] = { 884 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c, 885 0x4d, 0x52, 0x53, 886 }; 887 static int jz4760_lcd_16bit_pins[] = { 888 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 889 }; 890 static int jz4760_lcd_18bit_pins[] = { 891 0x5a, 0x5b, 892 }; 893 static int jz4760_lcd_24bit_pins[] = { 894 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, 895 }; 896 static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 897 static int jz4760_lcd_generic_pins[] = { 0x49, }; 898 static int jz4760_pwm_pwm0_pins[] = { 0x80, }; 899 static int jz4760_pwm_pwm1_pins[] = { 0x81, }; 900 static int jz4760_pwm_pwm2_pins[] = { 0x82, }; 901 static int jz4760_pwm_pwm3_pins[] = { 0x83, }; 902 static int jz4760_pwm_pwm4_pins[] = { 0x84, }; 903 static int jz4760_pwm_pwm5_pins[] = { 0x85, }; 904 static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; 905 static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; 906 static int jz4760_otg_pins[] = { 0x8a, }; 907 908 static u8 jz4760_uart3_data_funcs[] = { 0, 1, }; 909 static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 910 911 static const struct group_desc jz4760_groups[] = { 912 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0), 913 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0), 914 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0), 915 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0), 916 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0), 917 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0), 918 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data, 919 jz4760_uart3_data_funcs), 920 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0), 921 INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2), 922 INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1), 923 INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1), 924 INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0), 925 INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1), 926 INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1), 927 INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1), 928 INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0), 929 INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2), 930 INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1), 931 INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1), 932 INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0), 933 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1), 934 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1), 935 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0), 936 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2), 937 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1), 938 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1), 939 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0), 940 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1), 941 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1), 942 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0), 943 INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2), 944 INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2), 945 INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2), 946 INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2), 947 INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1), 948 INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2), 949 INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2), 950 INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2), 951 INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2), 952 INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2), 953 INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1), 954 INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2), 955 INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2), 956 INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2), 957 INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2), 958 INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2), 959 INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1), 960 INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2), 961 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2), 962 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2), 963 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1), 964 INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2), 965 INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2), 966 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2), 967 INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2), 968 INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1), 969 INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2), 970 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2), 971 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2), 972 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1), 973 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a, 974 jz4760_mmc0_1bit_a_funcs), 975 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1), 976 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0), 977 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0), 978 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0), 979 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0), 980 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0), 981 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1), 982 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1), 983 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1), 984 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0), 985 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0), 986 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2), 987 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2), 988 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2), 989 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0), 990 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0), 991 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0), 992 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0), 993 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0), 994 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0), 995 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0), 996 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0), 997 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0), 998 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0), 999 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0), 1000 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0), 1001 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0), 1002 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0), 1003 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0), 1004 INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0), 1005 INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0), 1006 INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0), 1007 INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0), 1008 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0), 1009 INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1), 1010 INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0), 1011 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0), 1012 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0), 1013 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0), 1014 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0), 1015 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0), 1016 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0), 1017 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0), 1018 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0), 1019 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), 1020 }; 1021 1022 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1023 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1024 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1025 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 1026 static const char *jz4760_ssi0_groups[] = { 1027 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1028 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1029 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", 1030 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1031 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1032 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1033 }; 1034 static const char *jz4760_ssi1_groups[] = { 1035 "ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f", 1036 "ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f", 1037 "ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f", 1038 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1039 "ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f", 1040 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1041 }; 1042 static const char *jz4760_mmc0_groups[] = { 1043 "mmc0-1bit-a", "mmc0-4bit-a", 1044 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 1045 }; 1046 static const char *jz4760_mmc1_groups[] = { 1047 "mmc1-1bit-d", "mmc1-4bit-d", 1048 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 1049 }; 1050 static const char *jz4760_mmc2_groups[] = { 1051 "mmc2-1bit-b", "mmc2-4bit-b", 1052 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 1053 }; 1054 static const char *jz4760_nemc_groups[] = { 1055 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1056 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1057 }; 1058 static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; 1059 static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; 1060 static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; 1061 static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; 1062 static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; 1063 static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; 1064 static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; 1065 static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; 1066 static const char *jz4760_cim_groups[] = { "cim-data", }; 1067 static const char *jz4760_lcd_groups[] = { 1068 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1069 "lcd-special", "lcd-generic", 1070 }; 1071 static const char *jz4760_pwm0_groups[] = { "pwm0", }; 1072 static const char *jz4760_pwm1_groups[] = { "pwm1", }; 1073 static const char *jz4760_pwm2_groups[] = { "pwm2", }; 1074 static const char *jz4760_pwm3_groups[] = { "pwm3", }; 1075 static const char *jz4760_pwm4_groups[] = { "pwm4", }; 1076 static const char *jz4760_pwm5_groups[] = { "pwm5", }; 1077 static const char *jz4760_pwm6_groups[] = { "pwm6", }; 1078 static const char *jz4760_pwm7_groups[] = { "pwm7", }; 1079 static const char *jz4760_otg_groups[] = { "otg-vbus", }; 1080 1081 static const struct function_desc jz4760_functions[] = { 1082 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, 1083 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, 1084 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, 1085 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, 1086 { "ssi0", jz4760_ssi0_groups, ARRAY_SIZE(jz4760_ssi0_groups), }, 1087 { "ssi1", jz4760_ssi1_groups, ARRAY_SIZE(jz4760_ssi1_groups), }, 1088 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, 1089 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, 1090 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, 1091 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), }, 1092 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), }, 1093 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), }, 1094 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), }, 1095 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), }, 1096 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), }, 1097 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), }, 1098 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), }, 1099 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), }, 1100 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), }, 1101 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), }, 1102 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), }, 1103 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), }, 1104 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), }, 1105 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), }, 1106 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), }, 1107 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), }, 1108 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, 1109 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, 1110 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), }, 1111 }; 1112 1113 static const struct ingenic_chip_info jz4760_chip_info = { 1114 .num_chips = 6, 1115 .reg_offset = 0x100, 1116 .version = ID_JZ4760, 1117 .groups = jz4760_groups, 1118 .num_groups = ARRAY_SIZE(jz4760_groups), 1119 .functions = jz4760_functions, 1120 .num_functions = ARRAY_SIZE(jz4760_functions), 1121 .pull_ups = jz4760_pull_ups, 1122 .pull_downs = jz4760_pull_downs, 1123 }; 1124 1125 static const u32 jz4770_pull_ups[6] = { 1126 0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f, 1127 }; 1128 1129 static const u32 jz4770_pull_downs[6] = { 1130 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0, 1131 }; 1132 1133 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; 1134 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 1135 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, }; 1136 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 1137 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, }; 1138 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 1139 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; 1140 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; 1141 static int jz4770_ssi0_dt_a_pins[] = { 0x15, }; 1142 static int jz4770_ssi0_dt_b_pins[] = { 0x35, }; 1143 static int jz4770_ssi0_dt_d_pins[] = { 0x75, }; 1144 static int jz4770_ssi0_dt_e_pins[] = { 0x91, }; 1145 static int jz4770_ssi0_dr_a_pins[] = { 0x14, }; 1146 static int jz4770_ssi0_dr_b_pins[] = { 0x34, }; 1147 static int jz4770_ssi0_dr_d_pins[] = { 0x74, }; 1148 static int jz4770_ssi0_dr_e_pins[] = { 0x8e, }; 1149 static int jz4770_ssi0_clk_a_pins[] = { 0x12, }; 1150 static int jz4770_ssi0_clk_b_pins[] = { 0x3c, }; 1151 static int jz4770_ssi0_clk_d_pins[] = { 0x78, }; 1152 static int jz4770_ssi0_clk_e_pins[] = { 0x8f, }; 1153 static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, }; 1154 static int jz4770_ssi0_gpc_d_pins[] = { 0x76, }; 1155 static int jz4770_ssi0_gpc_e_pins[] = { 0x93, }; 1156 static int jz4770_ssi0_ce0_a_pins[] = { 0x13, }; 1157 static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, }; 1158 static int jz4770_ssi0_ce0_d_pins[] = { 0x79, }; 1159 static int jz4770_ssi0_ce0_e_pins[] = { 0x90, }; 1160 static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, }; 1161 static int jz4770_ssi0_ce1_d_pins[] = { 0x77, }; 1162 static int jz4770_ssi0_ce1_e_pins[] = { 0x92, }; 1163 static int jz4770_ssi1_dt_b_pins[] = { 0x35, }; 1164 static int jz4770_ssi1_dt_d_pins[] = { 0x75, }; 1165 static int jz4770_ssi1_dt_e_pins[] = { 0x91, }; 1166 static int jz4770_ssi1_dr_b_pins[] = { 0x34, }; 1167 static int jz4770_ssi1_dr_d_pins[] = { 0x74, }; 1168 static int jz4770_ssi1_dr_e_pins[] = { 0x8e, }; 1169 static int jz4770_ssi1_clk_b_pins[] = { 0x3c, }; 1170 static int jz4770_ssi1_clk_d_pins[] = { 0x78, }; 1171 static int jz4770_ssi1_clk_e_pins[] = { 0x8f, }; 1172 static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, }; 1173 static int jz4770_ssi1_gpc_d_pins[] = { 0x76, }; 1174 static int jz4770_ssi1_gpc_e_pins[] = { 0x93, }; 1175 static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, }; 1176 static int jz4770_ssi1_ce0_d_pins[] = { 0x79, }; 1177 static int jz4770_ssi1_ce0_e_pins[] = { 0x90, }; 1178 static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, }; 1179 static int jz4770_ssi1_ce1_d_pins[] = { 0x77, }; 1180 static int jz4770_ssi1_ce1_e_pins[] = { 0x92, }; 1181 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 1182 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 1183 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1184 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1185 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1186 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 1187 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 1188 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1189 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1190 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1191 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 1192 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 1193 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1194 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1195 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 1196 static int jz4770_nemc_8bit_data_pins[] = { 1197 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1198 }; 1199 static int jz4770_nemc_16bit_data_pins[] = { 1200 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1201 }; 1202 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 1203 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 1204 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, }; 1205 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 1206 static int jz4770_nemc_wait_pins[] = { 0x1b, }; 1207 static int jz4770_nemc_cs1_pins[] = { 0x15, }; 1208 static int jz4770_nemc_cs2_pins[] = { 0x16, }; 1209 static int jz4770_nemc_cs3_pins[] = { 0x17, }; 1210 static int jz4770_nemc_cs4_pins[] = { 0x18, }; 1211 static int jz4770_nemc_cs5_pins[] = { 0x19, }; 1212 static int jz4770_nemc_cs6_pins[] = { 0x1a, }; 1213 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, }; 1214 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, }; 1215 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, }; 1216 static int jz4770_cim_8bit_pins[] = { 1217 0x26, 0x27, 0x28, 0x29, 1218 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 1219 }; 1220 static int jz4770_cim_12bit_pins[] = { 1221 0x32, 0x33, 0xb0, 0xb1, 1222 }; 1223 static int jz4770_lcd_8bit_pins[] = { 1224 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, 1225 0x48, 0x52, 0x53, 1226 }; 1227 static int jz4770_lcd_16bit_pins[] = { 1228 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 1229 }; 1230 static int jz4770_lcd_18bit_pins[] = { 1231 0x5a, 0x5b, 1232 }; 1233 static int jz4770_lcd_24bit_pins[] = { 1234 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 1235 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 1236 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 1237 0x58, 0x59, 0x5a, 0x5b, 1238 }; 1239 static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 1240 static int jz4770_lcd_generic_pins[] = { 0x49, }; 1241 static int jz4770_pwm_pwm0_pins[] = { 0x80, }; 1242 static int jz4770_pwm_pwm1_pins[] = { 0x81, }; 1243 static int jz4770_pwm_pwm2_pins[] = { 0x82, }; 1244 static int jz4770_pwm_pwm3_pins[] = { 0x83, }; 1245 static int jz4770_pwm_pwm4_pins[] = { 0x84, }; 1246 static int jz4770_pwm_pwm5_pins[] = { 0x85, }; 1247 static int jz4770_pwm_pwm6_pins[] = { 0x6a, }; 1248 static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; 1249 static int jz4770_mac_rmii_pins[] = { 1250 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 1251 }; 1252 static int jz4770_mac_mii_pins[] = { 1253 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, 1254 }; 1255 1256 static const struct group_desc jz4770_groups[] = { 1257 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 1258 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 1259 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 1260 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 1261 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0), 1262 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0), 1263 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 1264 jz4760_uart3_data_funcs), 1265 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 1266 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2), 1267 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1), 1268 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1), 1269 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 1270 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1), 1271 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1), 1272 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1), 1273 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 1274 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2), 1275 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1), 1276 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1), 1277 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 1278 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1), 1279 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1), 1280 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 1281 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2), 1282 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1), 1283 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1), 1284 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 1285 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1), 1286 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1), 1287 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 1288 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2), 1289 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2), 1290 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 1291 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2), 1292 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2), 1293 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 1294 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2), 1295 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2), 1296 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 1297 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2), 1298 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2), 1299 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 1300 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2), 1301 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2), 1302 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 1303 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2), 1304 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2), 1305 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 1306 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 1307 jz4760_mmc0_1bit_a_funcs), 1308 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 1309 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 1310 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 1311 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0), 1312 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 1313 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 1314 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 1315 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 1316 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1), 1317 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 1318 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 1319 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 1320 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 1321 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2), 1322 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0), 1323 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0), 1324 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 1325 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 1326 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 1327 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 1328 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 1329 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 1330 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 1331 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 1332 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 1333 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 1334 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 1335 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 1336 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 1337 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 1338 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0), 1339 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 1340 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), 1341 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), 1342 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), 1343 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 1344 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), 1345 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), 1346 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 1347 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 1348 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 1349 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 1350 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 1351 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 1352 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 1353 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 1354 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0), 1355 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0), 1356 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), 1357 }; 1358 1359 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1360 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1361 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1362 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 1363 static const char *jz4770_ssi0_groups[] = { 1364 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1365 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1366 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", 1367 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1368 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1369 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1370 }; 1371 static const char *jz4770_ssi1_groups[] = { 1372 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1373 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1374 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1375 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1376 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1377 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1378 }; 1379 static const char *jz4770_mmc0_groups[] = { 1380 "mmc0-1bit-a", "mmc0-4bit-a", 1381 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 1382 }; 1383 static const char *jz4770_mmc1_groups[] = { 1384 "mmc1-1bit-d", "mmc1-4bit-d", 1385 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 1386 }; 1387 static const char *jz4770_mmc2_groups[] = { 1388 "mmc2-1bit-b", "mmc2-4bit-b", 1389 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 1390 }; 1391 static const char *jz4770_nemc_groups[] = { 1392 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1393 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1394 }; 1395 static const char *jz4770_cs1_groups[] = { "nemc-cs1", }; 1396 static const char *jz4770_cs2_groups[] = { "nemc-cs2", }; 1397 static const char *jz4770_cs3_groups[] = { "nemc-cs3", }; 1398 static const char *jz4770_cs4_groups[] = { "nemc-cs4", }; 1399 static const char *jz4770_cs5_groups[] = { "nemc-cs5", }; 1400 static const char *jz4770_cs6_groups[] = { "nemc-cs6", }; 1401 static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; 1402 static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; 1403 static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; 1404 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 1405 static const char *jz4770_lcd_groups[] = { 1406 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1407 "lcd-special", "lcd-generic", 1408 }; 1409 static const char *jz4770_pwm0_groups[] = { "pwm0", }; 1410 static const char *jz4770_pwm1_groups[] = { "pwm1", }; 1411 static const char *jz4770_pwm2_groups[] = { "pwm2", }; 1412 static const char *jz4770_pwm3_groups[] = { "pwm3", }; 1413 static const char *jz4770_pwm4_groups[] = { "pwm4", }; 1414 static const char *jz4770_pwm5_groups[] = { "pwm5", }; 1415 static const char *jz4770_pwm6_groups[] = { "pwm6", }; 1416 static const char *jz4770_pwm7_groups[] = { "pwm7", }; 1417 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", }; 1418 1419 static const struct function_desc jz4770_functions[] = { 1420 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 1421 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 1422 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), }, 1423 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 1424 { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), }, 1425 { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), }, 1426 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), }, 1427 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), }, 1428 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), }, 1429 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), }, 1430 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1431 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1432 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1433 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1434 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1435 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1436 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1437 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1438 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1439 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), }, 1440 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1441 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1442 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1443 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1444 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1445 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1446 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1447 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1448 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1449 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), }, 1450 { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), }, 1451 }; 1452 1453 static const struct ingenic_chip_info jz4770_chip_info = { 1454 .num_chips = 6, 1455 .reg_offset = 0x100, 1456 .version = ID_JZ4770, 1457 .groups = jz4770_groups, 1458 .num_groups = ARRAY_SIZE(jz4770_groups), 1459 .functions = jz4770_functions, 1460 .num_functions = ARRAY_SIZE(jz4770_functions), 1461 .pull_ups = jz4770_pull_ups, 1462 .pull_downs = jz4770_pull_downs, 1463 }; 1464 1465 static const u32 jz4775_pull_ups[7] = { 1466 0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0, 1467 }; 1468 1469 static const u32 jz4775_pull_downs[7] = { 1470 0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00, 1471 }; 1472 1473 static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, }; 1474 static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 1475 static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, }; 1476 static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 1477 static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, }; 1478 static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, }; 1479 static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, }; 1480 static int jz4775_ssi_dt_a_pins[] = { 0x13, }; 1481 static int jz4775_ssi_dt_d_pins[] = { 0x75, }; 1482 static int jz4775_ssi_dr_a_pins[] = { 0x14, }; 1483 static int jz4775_ssi_dr_d_pins[] = { 0x74, }; 1484 static int jz4775_ssi_clk_a_pins[] = { 0x12, }; 1485 static int jz4775_ssi_clk_d_pins[] = { 0x78, }; 1486 static int jz4775_ssi_gpc_pins[] = { 0x76, }; 1487 static int jz4775_ssi_ce0_a_pins[] = { 0x17, }; 1488 static int jz4775_ssi_ce0_d_pins[] = { 0x79, }; 1489 static int jz4775_ssi_ce1_pins[] = { 0x77, }; 1490 static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 1491 static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 1492 static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, }; 1493 static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1494 static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1495 static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 1496 static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 1497 static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1498 static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1499 static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 1500 static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 1501 static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 1502 static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 1503 static int jz4775_nemc_8bit_data_pins[] = { 1504 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1505 }; 1506 static int jz4775_nemc_16bit_data_pins[] = { 1507 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1, 1508 }; 1509 static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 1510 static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 1511 static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, }; 1512 static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 1513 static int jz4775_nemc_wait_pins[] = { 0x1b, }; 1514 static int jz4775_nemc_cs1_pins[] = { 0x15, }; 1515 static int jz4775_nemc_cs2_pins[] = { 0x16, }; 1516 static int jz4775_nemc_cs3_pins[] = { 0x17, }; 1517 static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, }; 1518 static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, }; 1519 static int jz4775_i2c2_pins[] = { 0x80, 0x83, }; 1520 static int jz4775_i2s_data_tx_pins[] = { 0xa3, }; 1521 static int jz4775_i2s_data_rx_pins[] = { 0xa2, }; 1522 static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, }; 1523 static int jz4775_i2s_sysclk_pins[] = { 0x83, }; 1524 static int jz4775_dmic_pins[] = { 0xaa, 0xab, }; 1525 static int jz4775_cim_pins[] = { 1526 0x26, 0x27, 0x28, 0x29, 1527 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 1528 }; 1529 static int jz4775_lcd_8bit_pins[] = { 1530 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, 1531 0x48, 0x52, 0x53, 1532 }; 1533 static int jz4775_lcd_16bit_pins[] = { 1534 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, 1535 }; 1536 static int jz4775_lcd_18bit_pins[] = { 1537 0x5a, 0x5b, 1538 }; 1539 static int jz4775_lcd_24bit_pins[] = { 1540 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, 1541 }; 1542 static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; 1543 static int jz4775_lcd_generic_pins[] = { 0x49, }; 1544 static int jz4775_pwm_pwm0_pins[] = { 0x80, }; 1545 static int jz4775_pwm_pwm1_pins[] = { 0x81, }; 1546 static int jz4775_pwm_pwm2_pins[] = { 0x82, }; 1547 static int jz4775_pwm_pwm3_pins[] = { 0x83, }; 1548 static int jz4775_mac_rmii_pins[] = { 1549 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 1550 }; 1551 static int jz4775_mac_mii_pins[] = { 1552 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, 1553 }; 1554 static int jz4775_mac_rgmii_pins[] = { 1555 0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4, 1556 0xad, 0xae, 0xa7, 0xa6, 1557 }; 1558 static int jz4775_mac_gmii_pins[] = { 1559 0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 1560 0xa8, 0x28, 0x24, 0xaf, 1561 }; 1562 static int jz4775_otg_pins[] = { 0x8a, }; 1563 1564 static u8 jz4775_uart3_data_funcs[] = { 0, 1, }; 1565 static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, }; 1566 static u8 jz4775_mac_rgmii_funcs[] = { 1567 0, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1568 0, 0, 0, 0, 1569 }; 1570 static u8 jz4775_mac_gmii_funcs[] = { 1571 1, 1, 1, 1, 1, 1, 1, 1, 1572 0, 1, 1, 0, 1573 }; 1574 1575 static const struct group_desc jz4775_groups[] = { 1576 INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0), 1577 INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0), 1578 INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0), 1579 INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0), 1580 INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2), 1581 INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1), 1582 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data, 1583 jz4775_uart3_data_funcs), 1584 INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2), 1585 INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1), 1586 INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2), 1587 INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1), 1588 INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2), 1589 INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1), 1590 INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1), 1591 INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2), 1592 INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1), 1593 INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1), 1594 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1), 1595 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1), 1596 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1), 1597 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0), 1598 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0), 1599 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0), 1600 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0), 1601 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1), 1602 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1), 1603 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0), 1604 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0), 1605 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2), 1606 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2), 1607 INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0), 1608 INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1), 1609 INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0), 1610 INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0), 1611 INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0), 1612 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0), 1613 INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0), 1614 INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0), 1615 INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0), 1616 INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0), 1617 INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0), 1618 INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0), 1619 INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1), 1620 INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1), 1621 INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1), 1622 INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1), 1623 INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2), 1624 INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1), 1625 INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0), 1626 INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0), 1627 INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0), 1628 INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0), 1629 INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0), 1630 INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0), 1631 INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1), 1632 INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0), 1633 INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0), 1634 INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0), 1635 INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0), 1636 INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0), 1637 INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii, 1638 jz4775_mac_mii_funcs), 1639 INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii, 1640 jz4775_mac_rgmii_funcs), 1641 INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii, 1642 jz4775_mac_gmii_funcs), 1643 INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0), 1644 }; 1645 1646 static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1647 static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 1648 static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", }; 1649 static const char *jz4775_uart3_groups[] = { "uart3-data", }; 1650 static const char *jz4775_ssi_groups[] = { 1651 "ssi-dt-a", "ssi-dt-d", 1652 "ssi-dr-a", "ssi-dr-d", 1653 "ssi-clk-a", "ssi-clk-d", 1654 "ssi-gpc", 1655 "ssi-ce0-a", "ssi-ce0-d", 1656 "ssi-ce1", 1657 }; 1658 static const char *jz4775_mmc0_groups[] = { 1659 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1660 "mmc0-1bit-e", "mmc0-4bit-e", 1661 }; 1662 static const char *jz4775_mmc1_groups[] = { 1663 "mmc1-1bit-d", "mmc1-4bit-d", 1664 "mmc1-1bit-e", "mmc1-4bit-e", 1665 }; 1666 static const char *jz4775_mmc2_groups[] = { 1667 "mmc2-1bit-b", "mmc2-4bit-b", 1668 "mmc2-1bit-e", "mmc2-4bit-e", 1669 }; 1670 static const char *jz4775_nemc_groups[] = { 1671 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 1672 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1673 }; 1674 static const char *jz4775_cs1_groups[] = { "nemc-cs1", }; 1675 static const char *jz4775_cs2_groups[] = { "nemc-cs2", }; 1676 static const char *jz4775_cs3_groups[] = { "nemc-cs3", }; 1677 static const char *jz4775_i2c0_groups[] = { "i2c0-data", }; 1678 static const char *jz4775_i2c1_groups[] = { "i2c1-data", }; 1679 static const char *jz4775_i2c2_groups[] = { "i2c2-data", }; 1680 static const char *jz4775_i2s_groups[] = { 1681 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 1682 }; 1683 static const char *jz4775_dmic_groups[] = { "dmic", }; 1684 static const char *jz4775_cim_groups[] = { "cim-data", }; 1685 static const char *jz4775_lcd_groups[] = { 1686 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 1687 "lcd-special", "lcd-generic", 1688 }; 1689 static const char *jz4775_pwm0_groups[] = { "pwm0", }; 1690 static const char *jz4775_pwm1_groups[] = { "pwm1", }; 1691 static const char *jz4775_pwm2_groups[] = { "pwm2", }; 1692 static const char *jz4775_pwm3_groups[] = { "pwm3", }; 1693 static const char *jz4775_mac_groups[] = { 1694 "mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii", 1695 }; 1696 static const char *jz4775_otg_groups[] = { "otg-vbus", }; 1697 1698 static const struct function_desc jz4775_functions[] = { 1699 { "uart0", jz4775_uart0_groups, ARRAY_SIZE(jz4775_uart0_groups), }, 1700 { "uart1", jz4775_uart1_groups, ARRAY_SIZE(jz4775_uart1_groups), }, 1701 { "uart2", jz4775_uart2_groups, ARRAY_SIZE(jz4775_uart2_groups), }, 1702 { "uart3", jz4775_uart3_groups, ARRAY_SIZE(jz4775_uart3_groups), }, 1703 { "ssi", jz4775_ssi_groups, ARRAY_SIZE(jz4775_ssi_groups), }, 1704 { "mmc0", jz4775_mmc0_groups, ARRAY_SIZE(jz4775_mmc0_groups), }, 1705 { "mmc1", jz4775_mmc1_groups, ARRAY_SIZE(jz4775_mmc1_groups), }, 1706 { "mmc2", jz4775_mmc2_groups, ARRAY_SIZE(jz4775_mmc2_groups), }, 1707 { "nemc", jz4775_nemc_groups, ARRAY_SIZE(jz4775_nemc_groups), }, 1708 { "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), }, 1709 { "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), }, 1710 { "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), }, 1711 { "i2c0", jz4775_i2c0_groups, ARRAY_SIZE(jz4775_i2c0_groups), }, 1712 { "i2c1", jz4775_i2c1_groups, ARRAY_SIZE(jz4775_i2c1_groups), }, 1713 { "i2c2", jz4775_i2c2_groups, ARRAY_SIZE(jz4775_i2c2_groups), }, 1714 { "i2s", jz4775_i2s_groups, ARRAY_SIZE(jz4775_i2s_groups), }, 1715 { "dmic", jz4775_dmic_groups, ARRAY_SIZE(jz4775_dmic_groups), }, 1716 { "cim", jz4775_cim_groups, ARRAY_SIZE(jz4775_cim_groups), }, 1717 { "lcd", jz4775_lcd_groups, ARRAY_SIZE(jz4775_lcd_groups), }, 1718 { "pwm0", jz4775_pwm0_groups, ARRAY_SIZE(jz4775_pwm0_groups), }, 1719 { "pwm1", jz4775_pwm1_groups, ARRAY_SIZE(jz4775_pwm1_groups), }, 1720 { "pwm2", jz4775_pwm2_groups, ARRAY_SIZE(jz4775_pwm2_groups), }, 1721 { "pwm3", jz4775_pwm3_groups, ARRAY_SIZE(jz4775_pwm3_groups), }, 1722 { "mac", jz4775_mac_groups, ARRAY_SIZE(jz4775_mac_groups), }, 1723 { "otg", jz4775_otg_groups, ARRAY_SIZE(jz4775_otg_groups), }, 1724 }; 1725 1726 static const struct ingenic_chip_info jz4775_chip_info = { 1727 .num_chips = 7, 1728 .reg_offset = 0x100, 1729 .version = ID_JZ4775, 1730 .groups = jz4775_groups, 1731 .num_groups = ARRAY_SIZE(jz4775_groups), 1732 .functions = jz4775_functions, 1733 .num_functions = ARRAY_SIZE(jz4775_functions), 1734 .pull_ups = jz4775_pull_ups, 1735 .pull_downs = jz4775_pull_downs, 1736 }; 1737 1738 static const u32 jz4780_pull_ups[6] = { 1739 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f, 1740 }; 1741 1742 static const u32 jz4780_pull_downs[6] = { 1743 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 1744 }; 1745 1746 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; 1747 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; 1748 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; 1749 static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, }; 1750 static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, }; 1751 static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, }; 1752 static int jz4780_ssi0_dt_b_pins[] = { 0x3d, }; 1753 static int jz4780_ssi0_dt_d_pins[] = { 0x79, }; 1754 static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, }; 1755 static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, }; 1756 static int jz4780_ssi0_dr_b_pins[] = { 0x34, }; 1757 static int jz4780_ssi0_dr_d_pins[] = { 0x74, }; 1758 static int jz4780_ssi0_clk_a_pins[] = { 0x12, }; 1759 static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, }; 1760 static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, }; 1761 static int jz4780_ssi0_clk_d_pins[] = { 0x78, }; 1762 static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, }; 1763 static int jz4780_ssi0_gpc_d_pins[] = { 0x76, }; 1764 static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, }; 1765 static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, }; 1766 static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, }; 1767 static int jz4780_ssi0_ce0_d_pins[] = { 0x77, }; 1768 static int jz4780_ssi0_ce1_b_pins[] = { 0x35, }; 1769 static int jz4780_ssi0_ce1_d_pins[] = { 0x75, }; 1770 static int jz4780_ssi1_dt_b_pins[] = { 0x3d, }; 1771 static int jz4780_ssi1_dt_d_pins[] = { 0x79, }; 1772 static int jz4780_ssi1_dr_b_pins[] = { 0x34, }; 1773 static int jz4780_ssi1_dr_d_pins[] = { 0x74, }; 1774 static int jz4780_ssi1_clk_b_pins[] = { 0x3c, }; 1775 static int jz4780_ssi1_clk_d_pins[] = { 0x78, }; 1776 static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, }; 1777 static int jz4780_ssi1_gpc_d_pins[] = { 0x76, }; 1778 static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, }; 1779 static int jz4780_ssi1_ce0_d_pins[] = { 0x77, }; 1780 static int jz4780_ssi1_ce1_b_pins[] = { 0x35, }; 1781 static int jz4780_ssi1_ce1_d_pins[] = { 0x75, }; 1782 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; 1783 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; 1784 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; 1785 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; 1786 static int jz4780_i2s_data_tx_pins[] = { 0x87, }; 1787 static int jz4780_i2s_data_rx_pins[] = { 0x86, }; 1788 static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, }; 1789 static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, }; 1790 static int jz4780_i2s_sysclk_pins[] = { 0x85, }; 1791 static int jz4780_dmic_pins[] = { 0x32, 0x33, }; 1792 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; 1793 1794 static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, }; 1795 1796 static const struct group_desc jz4780_groups[] = { 1797 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), 1798 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), 1799 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0), 1800 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0), 1801 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1), 1802 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1), 1803 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data, 1804 jz4760_uart3_data_funcs), 1805 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0), 1806 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2), 1807 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2), 1808 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2), 1809 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2), 1810 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1), 1811 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1), 1812 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0), 1813 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2), 1814 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2), 1815 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1), 1816 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1), 1817 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0), 1818 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2), 1819 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1), 1820 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1), 1821 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1), 1822 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0), 1823 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1), 1824 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1), 1825 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0), 1826 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2), 1827 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2), 1828 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1), 1829 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1), 1830 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0), 1831 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1), 1832 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1), 1833 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0), 1834 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2), 1835 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2), 1836 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1), 1837 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2), 1838 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2), 1839 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1), 1840 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2), 1841 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2), 1842 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1), 1843 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2), 1844 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2), 1845 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1), 1846 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2), 1847 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2), 1848 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1), 1849 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2), 1850 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2), 1851 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1), 1852 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a, 1853 jz4760_mmc0_1bit_a_funcs), 1854 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1), 1855 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1), 1856 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0), 1857 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0), 1858 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0), 1859 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0), 1860 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1), 1861 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1), 1862 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0), 1863 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0), 1864 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2), 1865 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2), 1866 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0), 1867 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0), 1868 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0), 1869 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0), 1870 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0), 1871 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0), 1872 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0), 1873 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0), 1874 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0), 1875 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0), 1876 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0), 1877 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0), 1878 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0), 1879 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0), 1880 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2), 1881 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1), 1882 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1), 1883 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1), 1884 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0), 1885 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0), 1886 INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx, 1887 jz4780_i2s_clk_txrx_funcs), 1888 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1), 1889 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2), 1890 INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1), 1891 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0), 1892 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0), 1893 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), 1894 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), 1895 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), 1896 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), 1897 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), 1898 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), 1899 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), 1900 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), 1901 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), 1902 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), 1903 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0), 1904 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0), 1905 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0), 1906 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0), 1907 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0), 1908 }; 1909 1910 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 1911 static const char *jz4780_uart4_groups[] = { "uart4-data", }; 1912 static const char *jz4780_ssi0_groups[] = { 1913 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", 1914 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", 1915 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e", 1916 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", 1917 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", 1918 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", 1919 }; 1920 static const char *jz4780_ssi1_groups[] = { 1921 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", 1922 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", 1923 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", 1924 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", 1925 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", 1926 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", 1927 }; 1928 static const char *jz4780_mmc0_groups[] = { 1929 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 1930 "mmc0-1bit-e", "mmc0-4bit-e", 1931 }; 1932 static const char *jz4780_mmc1_groups[] = { 1933 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e", 1934 }; 1935 static const char *jz4780_mmc2_groups[] = { 1936 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e", 1937 }; 1938 static const char *jz4780_nemc_groups[] = { 1939 "nemc-data", "nemc-cle-ale", "nemc-addr", 1940 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 1941 }; 1942 static const char *jz4780_i2c3_groups[] = { "i2c3-data", }; 1943 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; 1944 static const char *jz4780_i2s_groups[] = { 1945 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 1946 }; 1947 static const char *jz4780_dmic_groups[] = { "dmic", }; 1948 static const char *jz4780_cim_groups[] = { "cim-data", }; 1949 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", }; 1950 1951 static const struct function_desc jz4780_functions[] = { 1952 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 1953 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 1954 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), }, 1955 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 1956 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), }, 1957 { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), }, 1958 { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), }, 1959 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), }, 1960 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), }, 1961 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), }, 1962 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), }, 1963 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1964 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1965 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1966 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1967 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1968 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1969 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1970 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1971 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1972 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), }, 1973 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), }, 1974 { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), }, 1975 { "dmic", jz4780_dmic_groups, ARRAY_SIZE(jz4780_dmic_groups), }, 1976 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), }, 1977 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1978 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1979 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1980 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1981 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1982 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1983 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1984 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1985 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1986 { "hdmi-ddc", jz4780_hdmi_ddc_groups, 1987 ARRAY_SIZE(jz4780_hdmi_ddc_groups), }, 1988 }; 1989 1990 static const struct ingenic_chip_info jz4780_chip_info = { 1991 .num_chips = 6, 1992 .reg_offset = 0x100, 1993 .version = ID_JZ4780, 1994 .groups = jz4780_groups, 1995 .num_groups = ARRAY_SIZE(jz4780_groups), 1996 .functions = jz4780_functions, 1997 .num_functions = ARRAY_SIZE(jz4780_functions), 1998 .pull_ups = jz4780_pull_ups, 1999 .pull_downs = jz4780_pull_downs, 2000 }; 2001 2002 static const u32 x1000_pull_ups[4] = { 2003 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, 2004 }; 2005 2006 static const u32 x1000_pull_downs[4] = { 2007 0x00000000, 0x02000000, 0x02000000, 0x00000000, 2008 }; 2009 2010 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; 2011 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 2012 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; 2013 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; 2014 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; 2015 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; 2016 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; 2017 static int x1000_sfc_data_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, }; 2018 static int x1000_sfc_clk_pins[] = { 0x1a, }; 2019 static int x1000_sfc_ce_pins[] = { 0x1b, }; 2020 static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; 2021 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; 2022 static int x1000_ssi_dt_d_pins[] = { 0x62, }; 2023 static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; 2024 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; 2025 static int x1000_ssi_dr_d_pins[] = { 0x63, }; 2026 static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; 2027 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; 2028 static int x1000_ssi_clk_d_pins[] = { 0x60, }; 2029 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; 2030 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; 2031 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; 2032 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; 2033 static int x1000_ssi_ce0_d_pins[] = { 0x61, }; 2034 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; 2035 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; 2036 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; 2037 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; 2038 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; 2039 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; 2040 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; 2041 static int x1000_emc_8bit_data_pins[] = { 2042 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2043 }; 2044 static int x1000_emc_16bit_data_pins[] = { 2045 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 2046 }; 2047 static int x1000_emc_addr_pins[] = { 2048 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2049 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 2050 }; 2051 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; 2052 static int x1000_emc_wait_pins[] = { 0x34, }; 2053 static int x1000_emc_cs1_pins[] = { 0x32, }; 2054 static int x1000_emc_cs2_pins[] = { 0x33, }; 2055 static int x1000_i2c0_pins[] = { 0x38, 0x37, }; 2056 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; 2057 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; 2058 static int x1000_i2c2_pins[] = { 0x61, 0x60, }; 2059 static int x1000_i2s_data_tx_pins[] = { 0x24, }; 2060 static int x1000_i2s_data_rx_pins[] = { 0x23, }; 2061 static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 2062 static int x1000_i2s_sysclk_pins[] = { 0x20, }; 2063 static int x1000_dmic_if0_pins[] = { 0x35, 0x36, }; 2064 static int x1000_dmic_if1_pins[] = { 0x25, }; 2065 static int x1000_cim_pins[] = { 2066 0x08, 0x09, 0x0a, 0x0b, 2067 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 2068 }; 2069 static int x1000_lcd_8bit_pins[] = { 2070 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2071 0x30, 0x31, 0x32, 0x33, 0x34, 2072 }; 2073 static int x1000_lcd_16bit_pins[] = { 2074 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 2075 }; 2076 static int x1000_pwm_pwm0_pins[] = { 0x59, }; 2077 static int x1000_pwm_pwm1_pins[] = { 0x5a, }; 2078 static int x1000_pwm_pwm2_pins[] = { 0x5b, }; 2079 static int x1000_pwm_pwm3_pins[] = { 0x26, }; 2080 static int x1000_pwm_pwm4_pins[] = { 0x58, }; 2081 static int x1000_mac_pins[] = { 2082 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, 2083 }; 2084 2085 static const struct group_desc x1000_groups[] = { 2086 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0), 2087 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0), 2088 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2), 2089 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1), 2090 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1), 2091 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2), 2092 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0), 2093 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1), 2094 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1), 2095 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1), 2096 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2), 2097 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2), 2098 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0), 2099 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2), 2100 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2), 2101 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0), 2102 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2), 2103 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2), 2104 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0), 2105 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2), 2106 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2), 2107 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2), 2108 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2), 2109 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0), 2110 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2), 2111 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2), 2112 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1), 2113 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1), 2114 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1), 2115 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0), 2116 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0), 2117 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0), 2118 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0), 2119 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0), 2120 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0), 2121 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0), 2122 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0), 2123 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0), 2124 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0), 2125 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2), 2126 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0), 2127 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1), 2128 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1), 2129 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1), 2130 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1), 2131 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1), 2132 INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0), 2133 INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1), 2134 INGENIC_PIN_GROUP("cim-data", x1000_cim, 2), 2135 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1), 2136 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1), 2137 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0), 2138 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1), 2139 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1), 2140 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2), 2141 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0), 2142 INGENIC_PIN_GROUP("mac", x1000_mac, 1), 2143 }; 2144 2145 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2146 static const char *x1000_uart1_groups[] = { 2147 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 2148 }; 2149 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 2150 static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", }; 2151 static const char *x1000_ssi_groups[] = { 2152 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", 2153 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", 2154 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d", 2155 "ssi-gpc-a-20", "ssi-gpc-a-31", 2156 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d", 2157 "ssi-ce1-a-21", "ssi-ce1-a-30", 2158 }; 2159 static const char *x1000_mmc0_groups[] = { 2160 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 2161 }; 2162 static const char *x1000_mmc1_groups[] = { 2163 "mmc1-1bit", "mmc1-4bit", 2164 }; 2165 static const char *x1000_emc_groups[] = { 2166 "emc-8bit-data", "emc-16bit-data", 2167 "emc-addr", "emc-rd-we", "emc-wait", 2168 }; 2169 static const char *x1000_cs1_groups[] = { "emc-cs1", }; 2170 static const char *x1000_cs2_groups[] = { "emc-cs2", }; 2171 static const char *x1000_i2c0_groups[] = { "i2c0-data", }; 2172 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 2173 static const char *x1000_i2c2_groups[] = { "i2c2-data", }; 2174 static const char *x1000_i2s_groups[] = { 2175 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 2176 }; 2177 static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", }; 2178 static const char *x1000_cim_groups[] = { "cim-data", }; 2179 static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", }; 2180 static const char *x1000_pwm0_groups[] = { "pwm0", }; 2181 static const char *x1000_pwm1_groups[] = { "pwm1", }; 2182 static const char *x1000_pwm2_groups[] = { "pwm2", }; 2183 static const char *x1000_pwm3_groups[] = { "pwm3", }; 2184 static const char *x1000_pwm4_groups[] = { "pwm4", }; 2185 static const char *x1000_mac_groups[] = { "mac", }; 2186 2187 static const struct function_desc x1000_functions[] = { 2188 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, 2189 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, 2190 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, 2191 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 2192 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), }, 2193 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, 2194 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, 2195 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, 2196 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, 2197 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, 2198 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, 2199 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, 2200 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, 2201 { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), }, 2202 { "dmic", x1000_dmic_groups, ARRAY_SIZE(x1000_dmic_groups), }, 2203 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, 2204 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, 2205 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, 2206 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), }, 2207 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), }, 2208 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), }, 2209 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), }, 2210 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, 2211 }; 2212 2213 static const struct regmap_range x1000_access_ranges[] = { 2214 regmap_reg_range(0x000, 0x400 - 4), 2215 regmap_reg_range(0x700, 0x800 - 4), 2216 }; 2217 2218 /* shared with X1500 */ 2219 static const struct regmap_access_table x1000_access_table = { 2220 .yes_ranges = x1000_access_ranges, 2221 .n_yes_ranges = ARRAY_SIZE(x1000_access_ranges), 2222 }; 2223 2224 static const struct ingenic_chip_info x1000_chip_info = { 2225 .num_chips = 4, 2226 .reg_offset = 0x100, 2227 .version = ID_X1000, 2228 .groups = x1000_groups, 2229 .num_groups = ARRAY_SIZE(x1000_groups), 2230 .functions = x1000_functions, 2231 .num_functions = ARRAY_SIZE(x1000_functions), 2232 .pull_ups = x1000_pull_ups, 2233 .pull_downs = x1000_pull_downs, 2234 .access_table = &x1000_access_table, 2235 }; 2236 2237 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; 2238 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 2239 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; 2240 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; 2241 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; 2242 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; 2243 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; 2244 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; 2245 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; 2246 static int x1500_i2c0_pins[] = { 0x38, 0x37, }; 2247 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; 2248 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; 2249 static int x1500_i2c2_pins[] = { 0x61, 0x60, }; 2250 static int x1500_i2s_data_tx_pins[] = { 0x24, }; 2251 static int x1500_i2s_data_rx_pins[] = { 0x23, }; 2252 static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; 2253 static int x1500_i2s_sysclk_pins[] = { 0x20, }; 2254 static int x1500_dmic_if0_pins[] = { 0x35, 0x36, }; 2255 static int x1500_dmic_if1_pins[] = { 0x25, }; 2256 static int x1500_cim_pins[] = { 2257 0x08, 0x09, 0x0a, 0x0b, 2258 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 2259 }; 2260 static int x1500_pwm_pwm0_pins[] = { 0x59, }; 2261 static int x1500_pwm_pwm1_pins[] = { 0x5a, }; 2262 static int x1500_pwm_pwm2_pins[] = { 0x5b, }; 2263 static int x1500_pwm_pwm3_pins[] = { 0x26, }; 2264 static int x1500_pwm_pwm4_pins[] = { 0x58, }; 2265 2266 static const struct group_desc x1500_groups[] = { 2267 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0), 2268 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0), 2269 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2), 2270 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1), 2271 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1), 2272 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2), 2273 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0), 2274 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1), 2275 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1), 2276 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1), 2277 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1), 2278 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1), 2279 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0), 2280 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2), 2281 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0), 2282 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1), 2283 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1), 2284 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1), 2285 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1), 2286 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1), 2287 INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0), 2288 INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1), 2289 INGENIC_PIN_GROUP("cim-data", x1500_cim, 2), 2290 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0), 2291 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1), 2292 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1), 2293 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2), 2294 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0), 2295 }; 2296 2297 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2298 static const char *x1500_uart1_groups[] = { 2299 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 2300 }; 2301 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 2302 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 2303 static const char *x1500_i2c0_groups[] = { "i2c0-data", }; 2304 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 2305 static const char *x1500_i2c2_groups[] = { "i2c2-data", }; 2306 static const char *x1500_i2s_groups[] = { 2307 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", 2308 }; 2309 static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", }; 2310 static const char *x1500_cim_groups[] = { "cim-data", }; 2311 static const char *x1500_pwm0_groups[] = { "pwm0", }; 2312 static const char *x1500_pwm1_groups[] = { "pwm1", }; 2313 static const char *x1500_pwm2_groups[] = { "pwm2", }; 2314 static const char *x1500_pwm3_groups[] = { "pwm3", }; 2315 static const char *x1500_pwm4_groups[] = { "pwm4", }; 2316 2317 static const struct function_desc x1500_functions[] = { 2318 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, 2319 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, 2320 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, 2321 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 2322 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, 2323 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, 2324 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, 2325 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, 2326 { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), }, 2327 { "dmic", x1500_dmic_groups, ARRAY_SIZE(x1500_dmic_groups), }, 2328 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, 2329 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, 2330 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, 2331 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, 2332 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), }, 2333 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), }, 2334 }; 2335 2336 static const struct ingenic_chip_info x1500_chip_info = { 2337 .num_chips = 4, 2338 .reg_offset = 0x100, 2339 .version = ID_X1500, 2340 .groups = x1500_groups, 2341 .num_groups = ARRAY_SIZE(x1500_groups), 2342 .functions = x1500_functions, 2343 .num_functions = ARRAY_SIZE(x1500_functions), 2344 .pull_ups = x1000_pull_ups, 2345 .pull_downs = x1000_pull_downs, 2346 .access_table = &x1000_access_table, 2347 }; 2348 2349 static const u32 x1830_pull_ups[4] = { 2350 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 2351 }; 2352 2353 static const u32 x1830_pull_downs[4] = { 2354 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 2355 }; 2356 2357 static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; 2358 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; 2359 static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; 2360 static int x1830_sfc_data_pins[] = { 0x17, 0x18, 0x1a, 0x19, }; 2361 static int x1830_sfc_clk_pins[] = { 0x1b, }; 2362 static int x1830_sfc_ce_pins[] = { 0x1c, }; 2363 static int x1830_ssi0_dt_pins[] = { 0x4c, }; 2364 static int x1830_ssi0_dr_pins[] = { 0x4b, }; 2365 static int x1830_ssi0_clk_pins[] = { 0x4f, }; 2366 static int x1830_ssi0_gpc_pins[] = { 0x4d, }; 2367 static int x1830_ssi0_ce0_pins[] = { 0x50, }; 2368 static int x1830_ssi0_ce1_pins[] = { 0x4e, }; 2369 static int x1830_ssi1_dt_c_pins[] = { 0x53, }; 2370 static int x1830_ssi1_dt_d_pins[] = { 0x62, }; 2371 static int x1830_ssi1_dr_c_pins[] = { 0x54, }; 2372 static int x1830_ssi1_dr_d_pins[] = { 0x63, }; 2373 static int x1830_ssi1_clk_c_pins[] = { 0x57, }; 2374 static int x1830_ssi1_clk_d_pins[] = { 0x66, }; 2375 static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; 2376 static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; 2377 static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; 2378 static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; 2379 static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; 2380 static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; 2381 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; 2382 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; 2383 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; 2384 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; 2385 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; 2386 static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; 2387 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; 2388 static int x1830_i2s_data_tx_pins[] = { 0x53, }; 2389 static int x1830_i2s_data_rx_pins[] = { 0x54, }; 2390 static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, }; 2391 static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, }; 2392 static int x1830_i2s_sysclk_pins[] = { 0x57, }; 2393 static int x1830_dmic_if0_pins[] = { 0x48, 0x59, }; 2394 static int x1830_dmic_if1_pins[] = { 0x5a, }; 2395 static int x1830_lcd_tft_8bit_pins[] = { 2396 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 2397 0x68, 0x73, 0x72, 0x69, 2398 }; 2399 static int x1830_lcd_tft_24bit_pins[] = { 2400 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 2401 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 2402 }; 2403 static int x1830_lcd_slcd_8bit_pins[] = { 2404 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d, 2405 0x69, 0x72, 0x73, 0x7b, 0x7a, 2406 }; 2407 static int x1830_lcd_slcd_16bit_pins[] = { 2408 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79, 2409 }; 2410 static int x1830_pwm_pwm0_b_pins[] = { 0x31, }; 2411 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, }; 2412 static int x1830_pwm_pwm1_b_pins[] = { 0x32, }; 2413 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, }; 2414 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, }; 2415 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, }; 2416 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, }; 2417 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, }; 2418 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, }; 2419 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, }; 2420 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, }; 2421 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, }; 2422 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, }; 2423 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, }; 2424 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, }; 2425 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, }; 2426 static int x1830_mac_pins[] = { 2427 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, 2428 }; 2429 2430 static const struct group_desc x1830_groups[] = { 2431 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0), 2432 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0), 2433 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0), 2434 INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1), 2435 INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1), 2436 INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1), 2437 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0), 2438 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0), 2439 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0), 2440 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0), 2441 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0), 2442 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0), 2443 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1), 2444 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1), 2445 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1), 2446 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1), 2447 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1), 2448 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1), 2449 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2), 2450 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2), 2451 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2), 2452 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2), 2453 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2), 2454 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2), 2455 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0), 2456 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0), 2457 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0), 2458 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0), 2459 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1), 2460 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0), 2461 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1), 2462 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0), 2463 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0), 2464 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0), 2465 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0), 2466 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0), 2467 INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2), 2468 INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2), 2469 INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0), 2470 INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0), 2471 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1), 2472 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1), 2473 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0), 2474 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1), 2475 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0), 2476 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1), 2477 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0), 2478 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1), 2479 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0), 2480 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1), 2481 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1), 2482 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0), 2483 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1), 2484 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0), 2485 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1), 2486 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0), 2487 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1), 2488 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0), 2489 INGENIC_PIN_GROUP("mac", x1830_mac, 0), 2490 }; 2491 2492 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2493 static const char *x1830_uart1_groups[] = { "uart1-data", }; 2494 static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", }; 2495 static const char *x1830_ssi0_groups[] = { 2496 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", 2497 }; 2498 static const char *x1830_ssi1_groups[] = { 2499 "ssi1-dt-c", "ssi1-dt-d", 2500 "ssi1-dr-c", "ssi1-dr-d", 2501 "ssi1-clk-c", "ssi1-clk-d", 2502 "ssi1-gpc-c", "ssi1-gpc-d", 2503 "ssi1-ce0-c", "ssi1-ce0-d", 2504 "ssi1-ce1-c", "ssi1-ce1-d", 2505 }; 2506 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 2507 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 2508 static const char *x1830_i2c0_groups[] = { "i2c0-data", }; 2509 static const char *x1830_i2c1_groups[] = { "i2c1-data", }; 2510 static const char *x1830_i2c2_groups[] = { "i2c2-data", }; 2511 static const char *x1830_i2s_groups[] = { 2512 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", 2513 }; 2514 static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", }; 2515 static const char *x1830_lcd_groups[] = { 2516 "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit", 2517 }; 2518 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; 2519 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; 2520 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", }; 2521 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", }; 2522 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", }; 2523 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", }; 2524 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", }; 2525 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", }; 2526 static const char *x1830_mac_groups[] = { "mac", }; 2527 2528 static const struct function_desc x1830_functions[] = { 2529 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), }, 2530 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), }, 2531 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), }, 2532 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), }, 2533 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), }, 2534 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), }, 2535 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), }, 2536 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, 2537 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, 2538 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, 2539 { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), }, 2540 { "dmic", x1830_dmic_groups, ARRAY_SIZE(x1830_dmic_groups), }, 2541 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), }, 2542 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, 2543 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, 2544 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), }, 2545 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), }, 2546 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2547 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2548 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2549 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 2550 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, 2551 }; 2552 2553 static const struct regmap_range x1830_access_ranges[] = { 2554 regmap_reg_range(0x0000, 0x4000 - 4), 2555 regmap_reg_range(0x7000, 0x8000 - 4), 2556 }; 2557 2558 static const struct regmap_access_table x1830_access_table = { 2559 .yes_ranges = x1830_access_ranges, 2560 .n_yes_ranges = ARRAY_SIZE(x1830_access_ranges), 2561 }; 2562 2563 static const struct ingenic_chip_info x1830_chip_info = { 2564 .num_chips = 4, 2565 .reg_offset = 0x1000, 2566 .version = ID_X1830, 2567 .groups = x1830_groups, 2568 .num_groups = ARRAY_SIZE(x1830_groups), 2569 .functions = x1830_functions, 2570 .num_functions = ARRAY_SIZE(x1830_functions), 2571 .pull_ups = x1830_pull_ups, 2572 .pull_downs = x1830_pull_downs, 2573 .access_table = &x1830_access_table, 2574 }; 2575 2576 static const u32 x2000_pull_ups[5] = { 2577 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f, 2578 }; 2579 2580 static const u32 x2000_pull_downs[5] = { 2581 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f, 2582 }; 2583 2584 static int x2000_uart0_data_pins[] = { 0x77, 0x78, }; 2585 static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, }; 2586 static int x2000_uart1_data_pins[] = { 0x57, 0x58, }; 2587 static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, }; 2588 static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, }; 2589 static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, }; 2590 static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, }; 2591 static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, }; 2592 static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, }; 2593 static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, }; 2594 static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, }; 2595 static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, }; 2596 static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, }; 2597 static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, }; 2598 static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, }; 2599 static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, }; 2600 static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, }; 2601 static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, }; 2602 static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, }; 2603 static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, }; 2604 static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, }; 2605 static int x2000_sfc_data_if0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, }; 2606 static int x2000_sfc_data_if0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, }; 2607 static int x2000_sfc_data_if1_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; 2608 static int x2000_sfc_clk_d_pins[] = { 0x71, }; 2609 static int x2000_sfc_clk_e_pins[] = { 0x90, }; 2610 static int x2000_sfc_ce_d_pins[] = { 0x72, }; 2611 static int x2000_sfc_ce_e_pins[] = { 0x91, }; 2612 static int x2000_ssi0_dt_b_pins[] = { 0x3e, }; 2613 static int x2000_ssi0_dt_d_pins[] = { 0x69, }; 2614 static int x2000_ssi0_dr_b_pins[] = { 0x3d, }; 2615 static int x2000_ssi0_dr_d_pins[] = { 0x6a, }; 2616 static int x2000_ssi0_clk_b_pins[] = { 0x3f, }; 2617 static int x2000_ssi0_clk_d_pins[] = { 0x68, }; 2618 static int x2000_ssi0_ce_b_pins[] = { 0x3c, }; 2619 static int x2000_ssi0_ce_d_pins[] = { 0x6d, }; 2620 static int x2000_ssi1_dt_c_pins[] = { 0x4b, }; 2621 static int x2000_ssi1_dt_d_pins[] = { 0x72, }; 2622 static int x2000_ssi1_dt_e_pins[] = { 0x91, }; 2623 static int x2000_ssi1_dr_c_pins[] = { 0x4a, }; 2624 static int x2000_ssi1_dr_d_pins[] = { 0x73, }; 2625 static int x2000_ssi1_dr_e_pins[] = { 0x92, }; 2626 static int x2000_ssi1_clk_c_pins[] = { 0x4c, }; 2627 static int x2000_ssi1_clk_d_pins[] = { 0x71, }; 2628 static int x2000_ssi1_clk_e_pins[] = { 0x90, }; 2629 static int x2000_ssi1_ce_c_pins[] = { 0x49, }; 2630 static int x2000_ssi1_ce_d_pins[] = { 0x76, }; 2631 static int x2000_ssi1_ce_e_pins[] = { 0x95, }; 2632 static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, }; 2633 static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, }; 2634 static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; 2635 static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, }; 2636 static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 2637 static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, }; 2638 static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, }; 2639 static int x2000_emc_8bit_data_pins[] = { 2640 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 2641 }; 2642 static int x2000_emc_16bit_data_pins[] = { 2643 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 2644 }; 2645 static int x2000_emc_addr_pins[] = { 2646 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2647 0x28, 0x29, 0x2a, 0x2b, 0x2c, 2648 }; 2649 static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, }; 2650 static int x2000_emc_wait_pins[] = { 0x2f, }; 2651 static int x2000_emc_cs1_pins[] = { 0x57, }; 2652 static int x2000_emc_cs2_pins[] = { 0x58, }; 2653 static int x2000_i2c0_pins[] = { 0x4e, 0x4d, }; 2654 static int x2000_i2c1_c_pins[] = { 0x58, 0x57, }; 2655 static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, }; 2656 static int x2000_i2c2_b_pins[] = { 0x37, 0x36, }; 2657 static int x2000_i2c2_d_pins[] = { 0x75, 0x74, }; 2658 static int x2000_i2c2_e_pins[] = { 0x94, 0x93, }; 2659 static int x2000_i2c3_a_pins[] = { 0x11, 0x10, }; 2660 static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, }; 2661 static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, }; 2662 static int x2000_i2c4_d_pins[] = { 0x61, 0x60, }; 2663 static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, }; 2664 static int x2000_i2c5_d_pins[] = { 0x65, 0x64, }; 2665 static int x2000_i2s1_data_tx_pins[] = { 0x47, }; 2666 static int x2000_i2s1_data_rx_pins[] = { 0x44, }; 2667 static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, }; 2668 static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, }; 2669 static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, }; 2670 static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, }; 2671 static int x2000_i2s2_data_rx0_pins[] = { 0x0a, }; 2672 static int x2000_i2s2_data_rx1_pins[] = { 0x0b, }; 2673 static int x2000_i2s2_data_rx2_pins[] = { 0x0c, }; 2674 static int x2000_i2s2_data_rx3_pins[] = { 0x0d, }; 2675 static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, }; 2676 static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, }; 2677 static int x2000_i2s3_data_tx0_pins[] = { 0x03, }; 2678 static int x2000_i2s3_data_tx1_pins[] = { 0x04, }; 2679 static int x2000_i2s3_data_tx2_pins[] = { 0x05, }; 2680 static int x2000_i2s3_data_tx3_pins[] = { 0x06, }; 2681 static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, }; 2682 static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, }; 2683 static int x2000_dmic_if0_pins[] = { 0x54, 0x55, }; 2684 static int x2000_dmic_if1_pins[] = { 0x56, }; 2685 static int x2000_dmic_if2_pins[] = { 0x57, }; 2686 static int x2000_dmic_if3_pins[] = { 0x58, }; 2687 static int x2000_cim_8bit_pins[] = { 2688 0x0e, 0x0c, 0x0d, 0x4f, 2689 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 2690 }; 2691 static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, }; 2692 static int x2000_lcd_tft_8bit_pins[] = { 2693 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2694 0x38, 0x3a, 0x39, 0x3b, 2695 }; 2696 static int x2000_lcd_tft_16bit_pins[] = { 2697 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 2698 }; 2699 static int x2000_lcd_tft_18bit_pins[] = { 2700 0x30, 0x31, 2701 }; 2702 static int x2000_lcd_tft_24bit_pins[] = { 2703 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 2704 }; 2705 static int x2000_lcd_slcd_8bit_pins[] = { 2706 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 2707 0x3a, 0x38, 0x3b, 0x30, 0x39, 2708 }; 2709 static int x2000_pwm_pwm0_c_pins[] = { 0x40, }; 2710 static int x2000_pwm_pwm0_d_pins[] = { 0x7e, }; 2711 static int x2000_pwm_pwm1_c_pins[] = { 0x41, }; 2712 static int x2000_pwm_pwm1_d_pins[] = { 0x7f, }; 2713 static int x2000_pwm_pwm2_c_pins[] = { 0x42, }; 2714 static int x2000_pwm_pwm2_e_pins[] = { 0x80, }; 2715 static int x2000_pwm_pwm3_c_pins[] = { 0x43, }; 2716 static int x2000_pwm_pwm3_e_pins[] = { 0x81, }; 2717 static int x2000_pwm_pwm4_c_pins[] = { 0x44, }; 2718 static int x2000_pwm_pwm4_e_pins[] = { 0x82, }; 2719 static int x2000_pwm_pwm5_c_pins[] = { 0x45, }; 2720 static int x2000_pwm_pwm5_e_pins[] = { 0x83, }; 2721 static int x2000_pwm_pwm6_c_pins[] = { 0x46, }; 2722 static int x2000_pwm_pwm6_e_pins[] = { 0x84, }; 2723 static int x2000_pwm_pwm7_c_pins[] = { 0x47, }; 2724 static int x2000_pwm_pwm7_e_pins[] = { 0x85, }; 2725 static int x2000_pwm_pwm8_pins[] = { 0x48, }; 2726 static int x2000_pwm_pwm9_pins[] = { 0x49, }; 2727 static int x2000_pwm_pwm10_pins[] = { 0x4a, }; 2728 static int x2000_pwm_pwm11_pins[] = { 0x4b, }; 2729 static int x2000_pwm_pwm12_pins[] = { 0x4c, }; 2730 static int x2000_pwm_pwm13_pins[] = { 0x4d, }; 2731 static int x2000_pwm_pwm14_pins[] = { 0x4e, }; 2732 static int x2000_pwm_pwm15_pins[] = { 0x4f, }; 2733 static int x2000_mac0_rmii_pins[] = { 2734 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41, 2735 }; 2736 static int x2000_mac0_rgmii_pins[] = { 2737 0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42, 2738 0x4c, 0x4d, 0x4f, 0x4e, 0x41, 2739 }; 2740 static int x2000_mac1_rmii_pins[] = { 2741 0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37, 2742 }; 2743 static int x2000_mac1_rgmii_pins[] = { 2744 0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28, 2745 0x33, 0x34, 0x36, 0x35, 0x37, 2746 }; 2747 static int x2000_otg_pins[] = { 0x96, }; 2748 2749 static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, }; 2750 2751 static const struct group_desc x2000_groups[] = { 2752 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2), 2753 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2), 2754 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1), 2755 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1), 2756 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0), 2757 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0), 2758 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1), 2759 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0), 2760 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1), 2761 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1), 2762 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3), 2763 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1), 2764 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3), 2765 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1), 2766 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3), 2767 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1), 2768 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3), 2769 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1), 2770 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3), 2771 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3), 2772 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3), 2773 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1), 2774 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0), 2775 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1), 2776 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1), 2777 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0), 2778 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1), 2779 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0), 2780 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1), 2781 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1), 2782 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1), 2783 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1), 2784 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1), 2785 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1), 2786 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1), 2787 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1), 2788 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2), 2789 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2), 2790 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1), 2791 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2), 2792 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2), 2793 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1), 2794 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2), 2795 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2), 2796 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1), 2797 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2), 2798 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2), 2799 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1), 2800 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0), 2801 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0), 2802 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0), 2803 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0), 2804 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0), 2805 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0), 2806 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0), 2807 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0), 2808 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0), 2809 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0), 2810 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0), 2811 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0), 2812 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3), 2813 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3), 2814 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3), 2815 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2), 2816 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1), 2817 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2), 2818 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2), 2819 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1), 2820 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0), 2821 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1), 2822 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1), 2823 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2), 2824 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1), 2825 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1), 2826 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2), 2827 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2), 2828 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2), 2829 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2), 2830 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2), 2831 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2), 2832 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2), 2833 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2), 2834 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2), 2835 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2), 2836 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2), 2837 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2), 2838 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2), 2839 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2), 2840 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2), 2841 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2), 2842 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2), 2843 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2), 2844 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0), 2845 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0), 2846 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0), 2847 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0), 2848 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit, 2849 x2000_cim_8bit_funcs), 2850 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0), 2851 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1), 2852 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1), 2853 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1), 2854 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1), 2855 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2), 2856 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2), 2857 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0), 2858 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2), 2859 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0), 2860 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2), 2861 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0), 2862 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1), 2863 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0), 2864 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1), 2865 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0), 2866 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1), 2867 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0), 2868 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1), 2869 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0), 2870 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1), 2871 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0), 2872 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1), 2873 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0), 2874 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0), 2875 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0), 2876 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0), 2877 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0), 2878 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0), 2879 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0), 2880 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0), 2881 INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1), 2882 INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1), 2883 INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3), 2884 INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3), 2885 INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0), 2886 }; 2887 2888 static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 2889 static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 2890 static const char *x2000_uart2_groups[] = { "uart2-data", }; 2891 static const char *x2000_uart3_groups[] = { 2892 "uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d", 2893 }; 2894 static const char *x2000_uart4_groups[] = { 2895 "uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c", 2896 }; 2897 static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", }; 2898 static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", }; 2899 static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", }; 2900 static const char *x2000_uart8_groups[] = { "uart8-data", }; 2901 static const char *x2000_uart9_groups[] = { "uart9-data", }; 2902 static const char *x2000_sfc_groups[] = { 2903 "sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1", 2904 "sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e", 2905 }; 2906 static const char *x2000_ssi0_groups[] = { 2907 "ssi0-dt-b", "ssi0-dt-d", 2908 "ssi0-dr-b", "ssi0-dr-d", 2909 "ssi0-clk-b", "ssi0-clk-d", 2910 "ssi0-ce-b", "ssi0-ce-d", 2911 }; 2912 static const char *x2000_ssi1_groups[] = { 2913 "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e", 2914 "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e", 2915 "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e", 2916 "ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e", 2917 }; 2918 static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", }; 2919 static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 2920 static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", }; 2921 static const char *x2000_emc_groups[] = { 2922 "emc-8bit-data", "emc-16bit-data", 2923 "emc-addr", "emc-rd-we", "emc-wait", 2924 }; 2925 static const char *x2000_cs1_groups[] = { "emc-cs1", }; 2926 static const char *x2000_cs2_groups[] = { "emc-cs2", }; 2927 static const char *x2000_i2c0_groups[] = { "i2c0-data", }; 2928 static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", }; 2929 static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", }; 2930 static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", }; 2931 static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", }; 2932 static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", }; 2933 static const char *x2000_i2s1_groups[] = { 2934 "i2s1-data-tx", "i2s1-data-rx", 2935 "i2s1-clk-tx", "i2s1-clk-rx", 2936 "i2s1-sysclk-tx", "i2s1-sysclk-rx", 2937 }; 2938 static const char *x2000_i2s2_groups[] = { 2939 "i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3", 2940 "i2s2-clk-rx", "i2s2-sysclk-rx", 2941 }; 2942 static const char *x2000_i2s3_groups[] = { 2943 "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3", 2944 "i2s3-clk-tx", "i2s3-sysclk-tx", 2945 }; 2946 static const char *x2000_dmic_groups[] = { 2947 "dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3", 2948 }; 2949 static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 2950 static const char *x2000_lcd_groups[] = { 2951 "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit", 2952 "lcd-slcd-8bit", "lcd-slcd-16bit", 2953 }; 2954 static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", }; 2955 static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", }; 2956 static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", }; 2957 static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", }; 2958 static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", }; 2959 static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", }; 2960 static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", }; 2961 static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", }; 2962 static const char *x2000_pwm8_groups[] = { "pwm8", }; 2963 static const char *x2000_pwm9_groups[] = { "pwm9", }; 2964 static const char *x2000_pwm10_groups[] = { "pwm10", }; 2965 static const char *x2000_pwm11_groups[] = { "pwm11", }; 2966 static const char *x2000_pwm12_groups[] = { "pwm12", }; 2967 static const char *x2000_pwm13_groups[] = { "pwm13", }; 2968 static const char *x2000_pwm14_groups[] = { "pwm14", }; 2969 static const char *x2000_pwm15_groups[] = { "pwm15", }; 2970 static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", }; 2971 static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", }; 2972 static const char *x2000_otg_groups[] = { "otg-vbus", }; 2973 2974 static const struct function_desc x2000_functions[] = { 2975 { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), }, 2976 { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), }, 2977 { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), }, 2978 { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), }, 2979 { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), }, 2980 { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), }, 2981 { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), }, 2982 { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), }, 2983 { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), }, 2984 { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), }, 2985 { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), }, 2986 { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), }, 2987 { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), }, 2988 { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), }, 2989 { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), }, 2990 { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), }, 2991 { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), }, 2992 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), }, 2993 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), }, 2994 { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), }, 2995 { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), }, 2996 { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), }, 2997 { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), }, 2998 { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), }, 2999 { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), }, 3000 { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), }, 3001 { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), }, 3002 { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), }, 3003 { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), }, 3004 { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), }, 3005 { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), }, 3006 { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), }, 3007 { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), }, 3008 { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), }, 3009 { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), }, 3010 { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), }, 3011 { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), }, 3012 { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), }, 3013 { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), }, 3014 { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), }, 3015 { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), }, 3016 { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), }, 3017 { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), }, 3018 { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), }, 3019 { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), }, 3020 { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), }, 3021 { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), }, 3022 { "mac0", x2000_mac0_groups, ARRAY_SIZE(x2000_mac0_groups), }, 3023 { "mac1", x2000_mac1_groups, ARRAY_SIZE(x2000_mac1_groups), }, 3024 { "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), }, 3025 }; 3026 3027 static const struct regmap_range x2000_access_ranges[] = { 3028 regmap_reg_range(0x000, 0x500 - 4), 3029 regmap_reg_range(0x700, 0x800 - 4), 3030 }; 3031 3032 /* shared with X2100 */ 3033 static const struct regmap_access_table x2000_access_table = { 3034 .yes_ranges = x2000_access_ranges, 3035 .n_yes_ranges = ARRAY_SIZE(x2000_access_ranges), 3036 }; 3037 3038 static const struct ingenic_chip_info x2000_chip_info = { 3039 .num_chips = 5, 3040 .reg_offset = 0x100, 3041 .version = ID_X2000, 3042 .groups = x2000_groups, 3043 .num_groups = ARRAY_SIZE(x2000_groups), 3044 .functions = x2000_functions, 3045 .num_functions = ARRAY_SIZE(x2000_functions), 3046 .pull_ups = x2000_pull_ups, 3047 .pull_downs = x2000_pull_downs, 3048 .access_table = &x2000_access_table, 3049 }; 3050 3051 static const u32 x2100_pull_ups[5] = { 3052 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x0fbf003f, 3053 }; 3054 3055 static const u32 x2100_pull_downs[5] = { 3056 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x0fbf003f, 3057 }; 3058 3059 static int x2100_mac_pins[] = { 3060 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4f, 0x41, 3061 }; 3062 3063 static const struct group_desc x2100_groups[] = { 3064 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2), 3065 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2), 3066 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1), 3067 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1), 3068 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0), 3069 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0), 3070 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1), 3071 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0), 3072 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1), 3073 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1), 3074 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3), 3075 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1), 3076 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3), 3077 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1), 3078 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3), 3079 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1), 3080 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3), 3081 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1), 3082 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3), 3083 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3), 3084 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3), 3085 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1), 3086 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0), 3087 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1), 3088 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1), 3089 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0), 3090 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1), 3091 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0), 3092 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1), 3093 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1), 3094 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1), 3095 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1), 3096 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1), 3097 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1), 3098 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1), 3099 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1), 3100 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2), 3101 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2), 3102 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1), 3103 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2), 3104 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2), 3105 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1), 3106 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2), 3107 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2), 3108 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1), 3109 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2), 3110 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2), 3111 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1), 3112 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0), 3113 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0), 3114 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0), 3115 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0), 3116 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0), 3117 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0), 3118 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0), 3119 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0), 3120 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0), 3121 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0), 3122 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0), 3123 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0), 3124 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3), 3125 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3), 3126 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3), 3127 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2), 3128 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1), 3129 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2), 3130 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2), 3131 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1), 3132 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0), 3133 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1), 3134 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1), 3135 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2), 3136 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1), 3137 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1), 3138 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2), 3139 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2), 3140 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2), 3141 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2), 3142 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2), 3143 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2), 3144 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2), 3145 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2), 3146 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2), 3147 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2), 3148 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2), 3149 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2), 3150 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2), 3151 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2), 3152 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2), 3153 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2), 3154 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2), 3155 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2), 3156 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0), 3157 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0), 3158 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0), 3159 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0), 3160 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit, 3161 x2000_cim_8bit_funcs), 3162 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0), 3163 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1), 3164 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1), 3165 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1), 3166 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1), 3167 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2), 3168 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2), 3169 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0), 3170 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2), 3171 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0), 3172 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2), 3173 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0), 3174 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1), 3175 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0), 3176 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1), 3177 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0), 3178 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1), 3179 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0), 3180 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1), 3181 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0), 3182 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1), 3183 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0), 3184 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1), 3185 INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0), 3186 INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0), 3187 INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0), 3188 INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0), 3189 INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0), 3190 INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0), 3191 INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0), 3192 INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0), 3193 INGENIC_PIN_GROUP("mac", x2100_mac, 1), 3194 }; 3195 3196 static const char *x2100_mac_groups[] = { "mac", }; 3197 3198 static const struct function_desc x2100_functions[] = { 3199 { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), }, 3200 { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), }, 3201 { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), }, 3202 { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), }, 3203 { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), }, 3204 { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), }, 3205 { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), }, 3206 { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), }, 3207 { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), }, 3208 { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), }, 3209 { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), }, 3210 { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), }, 3211 { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), }, 3212 { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), }, 3213 { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), }, 3214 { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), }, 3215 { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), }, 3216 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), }, 3217 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), }, 3218 { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), }, 3219 { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), }, 3220 { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), }, 3221 { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), }, 3222 { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), }, 3223 { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), }, 3224 { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), }, 3225 { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), }, 3226 { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), }, 3227 { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), }, 3228 { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), }, 3229 { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), }, 3230 { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), }, 3231 { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), }, 3232 { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), }, 3233 { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), }, 3234 { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), }, 3235 { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), }, 3236 { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), }, 3237 { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), }, 3238 { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), }, 3239 { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), }, 3240 { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), }, 3241 { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), }, 3242 { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), }, 3243 { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), }, 3244 { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), }, 3245 { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), }, 3246 { "mac", x2100_mac_groups, ARRAY_SIZE(x2100_mac_groups), }, 3247 }; 3248 3249 static const struct ingenic_chip_info x2100_chip_info = { 3250 .num_chips = 5, 3251 .reg_offset = 0x100, 3252 .version = ID_X2100, 3253 .groups = x2100_groups, 3254 .num_groups = ARRAY_SIZE(x2100_groups), 3255 .functions = x2100_functions, 3256 .num_functions = ARRAY_SIZE(x2100_functions), 3257 .pull_ups = x2100_pull_ups, 3258 .pull_downs = x2100_pull_downs, 3259 .access_table = &x2000_access_table, 3260 }; 3261 3262 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) 3263 { 3264 unsigned int val; 3265 3266 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); 3267 3268 return (u32) val; 3269 } 3270 3271 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, 3272 u8 reg, u8 offset, bool set) 3273 { 3274 if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) { 3275 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, 3276 BIT(offset), set ? BIT(offset) : 0); 3277 return; 3278 } 3279 3280 if (set) 3281 reg = REG_SET(reg); 3282 else 3283 reg = REG_CLEAR(reg); 3284 3285 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); 3286 } 3287 3288 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, 3289 u8 reg, u8 offset, bool set) 3290 { 3291 if (set) 3292 reg = REG_SET(reg); 3293 else 3294 reg = REG_CLEAR(reg); 3295 3296 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( 3297 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); 3298 } 3299 3300 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) 3301 { 3302 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( 3303 jzgc->jzpc->info->reg_offset), 3304 jzgc->gc.base / PINS_PER_GPIO_CHIP); 3305 } 3306 3307 static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc, 3308 u8 reg_upper, u8 reg_lower, u8 offset, u8 value) 3309 { 3310 /* 3311 * JZ4730 function and IRQ registers support two-bits-per-pin 3312 * definitions, split into two groups of 16. 3313 */ 3314 u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; 3315 unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG; 3316 unsigned int mask = GENMASK(1, 0) << idx * 2; 3317 3318 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2)); 3319 } 3320 3321 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, 3322 u8 offset) 3323 { 3324 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); 3325 3326 return !!(val & BIT(offset)); 3327 } 3328 3329 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, 3330 u8 offset, int value) 3331 { 3332 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3333 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value); 3334 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3335 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); 3336 else 3337 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value); 3338 } 3339 3340 static void irq_set_type(struct ingenic_gpio_chip *jzgc, 3341 u8 offset, unsigned int type) 3342 { 3343 u8 reg1, reg2; 3344 bool val1, val2, val3; 3345 3346 switch (type) { 3347 case IRQ_TYPE_EDGE_BOTH: 3348 val1 = val2 = false; 3349 val3 = true; 3350 break; 3351 case IRQ_TYPE_EDGE_RISING: 3352 val1 = val2 = true; 3353 val3 = false; 3354 break; 3355 case IRQ_TYPE_EDGE_FALLING: 3356 val1 = val3 = false; 3357 val2 = true; 3358 break; 3359 case IRQ_TYPE_LEVEL_HIGH: 3360 val1 = true; 3361 val2 = val3 = false; 3362 break; 3363 case IRQ_TYPE_LEVEL_LOW: 3364 default: 3365 val1 = val2 = val3 = false; 3366 break; 3367 } 3368 3369 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) { 3370 reg1 = JZ4770_GPIO_PAT1; 3371 reg2 = JZ4770_GPIO_PAT0; 3372 } else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) { 3373 reg1 = JZ4740_GPIO_TRIG; 3374 reg2 = JZ4740_GPIO_DIR; 3375 } else { 3376 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false); 3377 jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR, 3378 JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1); 3379 return; 3380 } 3381 3382 if (is_soc_or_above(jzgc->jzpc, ID_X2000)) { 3383 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 3384 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 3385 ingenic_gpio_shadow_set_bit_load(jzgc); 3386 ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3); 3387 } else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) { 3388 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 3389 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 3390 ingenic_gpio_shadow_set_bit_load(jzgc); 3391 } else { 3392 ingenic_gpio_set_bit(jzgc, reg2, offset, val1); 3393 ingenic_gpio_set_bit(jzgc, reg1, offset, val2); 3394 } 3395 } 3396 3397 static void ingenic_gpio_irq_mask(struct irq_data *irqd) 3398 { 3399 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3400 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3401 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3402 3403 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3404 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true); 3405 else 3406 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true); 3407 } 3408 3409 static void ingenic_gpio_irq_unmask(struct irq_data *irqd) 3410 { 3411 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3412 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3413 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3414 3415 if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3416 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false); 3417 else 3418 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false); 3419 } 3420 3421 static void ingenic_gpio_irq_enable(struct irq_data *irqd) 3422 { 3423 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3424 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3425 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3426 3427 gpiochip_enable_irq(gc, irq); 3428 3429 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3430 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); 3431 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3432 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); 3433 else 3434 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true); 3435 3436 ingenic_gpio_irq_unmask(irqd); 3437 } 3438 3439 static void ingenic_gpio_irq_disable(struct irq_data *irqd) 3440 { 3441 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3442 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3443 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3444 3445 ingenic_gpio_irq_mask(irqd); 3446 3447 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3448 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false); 3449 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3450 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); 3451 else 3452 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false); 3453 3454 gpiochip_disable_irq(gc, irq); 3455 } 3456 3457 static void ingenic_gpio_irq_ack(struct irq_data *irqd) 3458 { 3459 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3460 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3461 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3462 bool high; 3463 3464 if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) && 3465 !is_soc_or_above(jzgc->jzpc, ID_X2000)) { 3466 /* 3467 * Switch to an interrupt for the opposite edge to the one that 3468 * triggered the interrupt being ACKed. 3469 */ 3470 high = ingenic_gpio_get_value(jzgc, irq); 3471 if (high) 3472 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW); 3473 else 3474 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH); 3475 } 3476 3477 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3478 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false); 3479 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3480 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); 3481 else 3482 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false); 3483 } 3484 3485 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 3486 { 3487 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3488 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3489 irq_hw_number_t irq = irqd_to_hwirq(irqd); 3490 3491 switch (type) { 3492 case IRQ_TYPE_EDGE_BOTH: 3493 case IRQ_TYPE_EDGE_RISING: 3494 case IRQ_TYPE_EDGE_FALLING: 3495 irq_set_handler_locked(irqd, handle_edge_irq); 3496 break; 3497 case IRQ_TYPE_LEVEL_HIGH: 3498 case IRQ_TYPE_LEVEL_LOW: 3499 irq_set_handler_locked(irqd, handle_level_irq); 3500 break; 3501 default: 3502 irq_set_handler_locked(irqd, handle_bad_irq); 3503 } 3504 3505 if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) { 3506 /* 3507 * The hardware does not support interrupts on both edges. The 3508 * best we can do is to set up a single-edge interrupt and then 3509 * switch to the opposing edge when ACKing the interrupt. 3510 */ 3511 bool high = ingenic_gpio_get_value(jzgc, irq); 3512 3513 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH; 3514 } 3515 3516 irq_set_type(jzgc, irq, type); 3517 return 0; 3518 } 3519 3520 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on) 3521 { 3522 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 3523 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3524 3525 return irq_set_irq_wake(jzgc->irq, on); 3526 } 3527 3528 static void ingenic_gpio_irq_handler(struct irq_desc *desc) 3529 { 3530 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 3531 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3532 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); 3533 unsigned long flag, i; 3534 3535 chained_irq_enter(irq_chip, desc); 3536 3537 if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) 3538 flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG); 3539 else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) 3540 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); 3541 else 3542 flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR); 3543 3544 for_each_set_bit(i, &flag, 32) 3545 generic_handle_domain_irq(gc->irq.domain, i); 3546 chained_irq_exit(irq_chip, desc); 3547 } 3548 3549 static void ingenic_gpio_set(struct gpio_chip *gc, 3550 unsigned int offset, int value) 3551 { 3552 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3553 3554 ingenic_gpio_set_value(jzgc, offset, value); 3555 } 3556 3557 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) 3558 { 3559 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3560 3561 return (int) ingenic_gpio_get_value(jzgc, offset); 3562 } 3563 3564 static int ingenic_gpio_direction_output(struct gpio_chip *gc, 3565 unsigned int offset, int value) 3566 { 3567 ingenic_gpio_set(gc, offset, value); 3568 return pinctrl_gpio_direction_output(gc, offset); 3569 } 3570 3571 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, 3572 unsigned int pin, unsigned int reg, bool set) 3573 { 3574 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3575 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3576 3577 if (set) { 3578 if (is_soc_or_above(jzpc, ID_JZ4740)) 3579 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3580 REG_SET(reg), BIT(idx)); 3581 else 3582 regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset + 3583 reg, BIT(idx)); 3584 } else { 3585 if (is_soc_or_above(jzpc, ID_JZ4740)) 3586 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3587 REG_CLEAR(reg), BIT(idx)); 3588 else 3589 regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset + 3590 reg, BIT(idx)); 3591 } 3592 } 3593 3594 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, 3595 unsigned int pin, u8 reg, bool set) 3596 { 3597 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3598 3599 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + 3600 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 3601 } 3602 3603 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, 3604 unsigned int pin) 3605 { 3606 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), 3607 pin / PINS_PER_GPIO_CHIP); 3608 } 3609 3610 static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc, 3611 unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value) 3612 { 3613 /* 3614 * JZ4730 function and IRQ registers support two-bits-per-pin 3615 * definitions, split into two groups of 16. 3616 */ 3617 unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG; 3618 unsigned int mask = GENMASK(1, 0) << idx * 2; 3619 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3620 u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; 3621 3622 regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg, 3623 mask, value << (idx * 2)); 3624 } 3625 3626 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, 3627 unsigned int pin, unsigned int reg) 3628 { 3629 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3630 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3631 unsigned int val; 3632 3633 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); 3634 3635 return val & BIT(idx); 3636 } 3637 3638 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 3639 { 3640 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 3641 struct ingenic_pinctrl *jzpc = jzgc->jzpc; 3642 unsigned int pin = gc->base + offset; 3643 3644 if (is_soc_or_above(jzpc, ID_JZ4770)) { 3645 if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) || 3646 ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1)) 3647 return GPIO_LINE_DIRECTION_IN; 3648 return GPIO_LINE_DIRECTION_OUT; 3649 } else if (!is_soc_or_above(jzpc, ID_JZ4740)) { 3650 if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR)) 3651 return GPIO_LINE_DIRECTION_IN; 3652 return GPIO_LINE_DIRECTION_OUT; 3653 } 3654 3655 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) 3656 return GPIO_LINE_DIRECTION_IN; 3657 3658 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR)) 3659 return GPIO_LINE_DIRECTION_OUT; 3660 3661 return GPIO_LINE_DIRECTION_IN; 3662 } 3663 3664 static const struct pinctrl_ops ingenic_pctlops = { 3665 .get_groups_count = pinctrl_generic_get_group_count, 3666 .get_group_name = pinctrl_generic_get_group_name, 3667 .get_group_pins = pinctrl_generic_get_group_pins, 3668 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 3669 .dt_free_map = pinconf_generic_dt_free_map, 3670 }; 3671 3672 static int ingenic_gpio_irq_request(struct irq_data *data) 3673 { 3674 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3675 irq_hw_number_t irq = irqd_to_hwirq(data); 3676 int ret; 3677 3678 ret = pinctrl_gpio_direction_input(gpio_chip, irq); 3679 if (ret) 3680 return ret; 3681 3682 return gpiochip_reqres_irq(gpio_chip, irq); 3683 } 3684 3685 static void ingenic_gpio_irq_release(struct irq_data *data) 3686 { 3687 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3688 irq_hw_number_t irq = irqd_to_hwirq(data); 3689 3690 return gpiochip_relres_irq(gpio_chip, irq); 3691 } 3692 3693 static void ingenic_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 3694 { 3695 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 3696 3697 seq_printf(p, "%s", gpio_chip->label); 3698 } 3699 3700 static const struct irq_chip ingenic_gpio_irqchip = { 3701 .irq_enable = ingenic_gpio_irq_enable, 3702 .irq_disable = ingenic_gpio_irq_disable, 3703 .irq_unmask = ingenic_gpio_irq_unmask, 3704 .irq_mask = ingenic_gpio_irq_mask, 3705 .irq_ack = ingenic_gpio_irq_ack, 3706 .irq_set_type = ingenic_gpio_irq_set_type, 3707 .irq_set_wake = ingenic_gpio_irq_set_wake, 3708 .irq_request_resources = ingenic_gpio_irq_request, 3709 .irq_release_resources = ingenic_gpio_irq_release, 3710 .irq_print_chip = ingenic_gpio_irq_print_chip, 3711 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 3712 }; 3713 3714 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, 3715 int pin, int func) 3716 { 3717 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3718 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3719 3720 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 3721 'A' + offt, idx, func); 3722 3723 if (is_soc_or_above(jzpc, ID_X1000)) { 3724 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3725 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); 3726 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); 3727 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); 3728 ingenic_shadow_config_pin_load(jzpc, pin); 3729 } else if (is_soc_or_above(jzpc, ID_JZ4770)) { 3730 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3731 ingenic_config_pin(jzpc, pin, GPIO_MSK, false); 3732 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); 3733 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); 3734 } else if (is_soc_or_above(jzpc, ID_JZ4740)) { 3735 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); 3736 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); 3737 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1); 3738 } else { 3739 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); 3740 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func); 3741 } 3742 3743 return 0; 3744 } 3745 3746 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, 3747 unsigned int selector, unsigned int group) 3748 { 3749 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3750 struct function_desc *func; 3751 struct group_desc *grp; 3752 unsigned int i; 3753 uintptr_t mode; 3754 u8 *pin_modes; 3755 3756 func = pinmux_generic_get_function(pctldev, selector); 3757 if (!func) 3758 return -EINVAL; 3759 3760 grp = pinctrl_generic_get_group(pctldev, group); 3761 if (!grp) 3762 return -EINVAL; 3763 3764 dev_dbg(pctldev->dev, "enable function %s group %s\n", 3765 func->name, grp->grp.name); 3766 3767 mode = (uintptr_t)grp->data; 3768 if (mode <= 3) { 3769 for (i = 0; i < grp->grp.npins; i++) 3770 ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], mode); 3771 } else { 3772 pin_modes = grp->data; 3773 3774 for (i = 0; i < grp->grp.npins; i++) 3775 ingenic_pinmux_set_pin_fn(jzpc, grp->grp.pins[i], pin_modes[i]); 3776 } 3777 3778 return 0; 3779 } 3780 3781 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 3782 struct pinctrl_gpio_range *range, 3783 unsigned int pin, bool input) 3784 { 3785 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3786 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3787 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3788 3789 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 3790 'A' + offt, idx, input ? "in" : "out"); 3791 3792 if (is_soc_or_above(jzpc, ID_X1000)) { 3793 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3794 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); 3795 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); 3796 ingenic_shadow_config_pin_load(jzpc, pin); 3797 } else if (is_soc_or_above(jzpc, ID_JZ4770)) { 3798 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); 3799 ingenic_config_pin(jzpc, pin, GPIO_MSK, true); 3800 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); 3801 } else if (is_soc_or_above(jzpc, ID_JZ4740)) { 3802 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); 3803 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); 3804 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); 3805 } else { 3806 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); 3807 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input); 3808 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0); 3809 } 3810 3811 return 0; 3812 } 3813 3814 static const struct pinmux_ops ingenic_pmxops = { 3815 .get_functions_count = pinmux_generic_get_function_count, 3816 .get_function_name = pinmux_generic_get_function_name, 3817 .get_function_groups = pinmux_generic_get_function_groups, 3818 .set_mux = ingenic_pinmux_set_mux, 3819 .gpio_set_direction = ingenic_pinmux_gpio_set_direction, 3820 }; 3821 3822 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, 3823 unsigned int pin, unsigned long *config) 3824 { 3825 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3826 enum pin_config_param param = pinconf_to_config_param(*config); 3827 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3828 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3829 unsigned int arg = 1; 3830 unsigned int bias, reg; 3831 bool pull, pullup, pulldown; 3832 3833 if (is_soc_or_above(jzpc, ID_X2000)) { 3834 pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && 3835 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && 3836 (jzpc->info->pull_ups[offt] & BIT(idx)); 3837 pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && 3838 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && 3839 (jzpc->info->pull_downs[offt] & BIT(idx)); 3840 3841 } else if (is_soc_or_above(jzpc, ID_X1830)) { 3842 unsigned int half = PINS_PER_GPIO_CHIP / 2; 3843 unsigned int idxh = (pin % half) * 2; 3844 3845 if (idx < half) 3846 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + 3847 X1830_GPIO_PEL, &bias); 3848 else 3849 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + 3850 X1830_GPIO_PEH, &bias); 3851 3852 bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN); 3853 3854 pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx)); 3855 pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx)); 3856 3857 } else { 3858 if (is_soc_or_above(jzpc, ID_JZ4770)) 3859 pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); 3860 else if (is_soc_or_above(jzpc, ID_JZ4740)) 3861 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); 3862 else 3863 pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR); 3864 3865 pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx)); 3866 pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx)); 3867 } 3868 3869 switch (param) { 3870 case PIN_CONFIG_BIAS_DISABLE: 3871 if (pullup || pulldown) 3872 return -EINVAL; 3873 3874 break; 3875 3876 case PIN_CONFIG_BIAS_PULL_UP: 3877 if (!pullup) 3878 return -EINVAL; 3879 3880 break; 3881 3882 case PIN_CONFIG_BIAS_PULL_DOWN: 3883 if (!pulldown) 3884 return -EINVAL; 3885 3886 break; 3887 3888 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3889 if (is_soc_or_above(jzpc, ID_X2000)) 3890 reg = X2000_GPIO_SMT; 3891 else if (is_soc_or_above(jzpc, ID_X1830)) 3892 reg = X1830_GPIO_SMT; 3893 else 3894 return -EINVAL; 3895 3896 arg = !!ingenic_get_pin_config(jzpc, pin, reg); 3897 break; 3898 3899 case PIN_CONFIG_SLEW_RATE: 3900 if (is_soc_or_above(jzpc, ID_X2000)) 3901 reg = X2000_GPIO_SR; 3902 else if (is_soc_or_above(jzpc, ID_X1830)) 3903 reg = X1830_GPIO_SR; 3904 else 3905 return -EINVAL; 3906 3907 arg = !!ingenic_get_pin_config(jzpc, pin, reg); 3908 break; 3909 3910 default: 3911 return -ENOTSUPP; 3912 } 3913 3914 *config = pinconf_to_config_packed(param, arg); 3915 return 0; 3916 } 3917 3918 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, 3919 unsigned int pin, unsigned int bias) 3920 { 3921 if (is_soc_or_above(jzpc, ID_X2000)) { 3922 switch (bias) { 3923 case GPIO_PULL_UP: 3924 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); 3925 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true); 3926 break; 3927 3928 case GPIO_PULL_DOWN: 3929 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); 3930 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true); 3931 break; 3932 3933 case GPIO_PULL_DIS: 3934 default: 3935 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); 3936 ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); 3937 } 3938 3939 } else if (is_soc_or_above(jzpc, ID_X1830)) { 3940 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 3941 unsigned int half = PINS_PER_GPIO_CHIP / 2; 3942 unsigned int idxh = (pin % half) * 2; 3943 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 3944 3945 if (idx < half) { 3946 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3947 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); 3948 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3949 REG_SET(X1830_GPIO_PEL), bias << idxh); 3950 } else { 3951 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3952 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); 3953 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 3954 REG_SET(X1830_GPIO_PEH), bias << idxh); 3955 } 3956 3957 } else if (is_soc_or_above(jzpc, ID_JZ4770)) { 3958 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias); 3959 } else if (is_soc_or_above(jzpc, ID_JZ4740)) { 3960 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); 3961 } else { 3962 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias); 3963 } 3964 } 3965 3966 static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc, 3967 unsigned int pin, bool enable) 3968 { 3969 if (is_soc_or_above(jzpc, ID_X2000)) 3970 ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable); 3971 else 3972 ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable); 3973 } 3974 3975 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, 3976 unsigned int pin, bool high) 3977 { 3978 if (is_soc_or_above(jzpc, ID_JZ4770)) 3979 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high); 3980 else if (is_soc_or_above(jzpc, ID_JZ4740)) 3981 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); 3982 else 3983 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high); 3984 } 3985 3986 static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc, 3987 unsigned int pin, unsigned int slew) 3988 { 3989 if (is_soc_or_above(jzpc, ID_X2000)) 3990 ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew); 3991 else 3992 ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew); 3993 } 3994 3995 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 3996 unsigned long *configs, unsigned int num_configs) 3997 { 3998 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 3999 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 4000 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 4001 unsigned int cfg, arg; 4002 int ret; 4003 4004 for (cfg = 0; cfg < num_configs; cfg++) { 4005 switch (pinconf_to_config_param(configs[cfg])) { 4006 case PIN_CONFIG_BIAS_DISABLE: 4007 case PIN_CONFIG_BIAS_PULL_UP: 4008 case PIN_CONFIG_BIAS_PULL_DOWN: 4009 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 4010 case PIN_CONFIG_OUTPUT: 4011 case PIN_CONFIG_SLEW_RATE: 4012 continue; 4013 default: 4014 return -ENOTSUPP; 4015 } 4016 } 4017 4018 for (cfg = 0; cfg < num_configs; cfg++) { 4019 arg = pinconf_to_config_argument(configs[cfg]); 4020 4021 switch (pinconf_to_config_param(configs[cfg])) { 4022 case PIN_CONFIG_BIAS_DISABLE: 4023 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 4024 'A' + offt, idx); 4025 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS); 4026 break; 4027 4028 case PIN_CONFIG_BIAS_PULL_UP: 4029 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) 4030 return -EINVAL; 4031 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 4032 'A' + offt, idx); 4033 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP); 4034 break; 4035 4036 case PIN_CONFIG_BIAS_PULL_DOWN: 4037 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) 4038 return -EINVAL; 4039 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 4040 'A' + offt, idx); 4041 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); 4042 break; 4043 4044 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 4045 if (!is_soc_or_above(jzpc, ID_X1830)) 4046 return -EINVAL; 4047 4048 ingenic_set_schmitt_trigger(jzpc, pin, arg); 4049 break; 4050 4051 case PIN_CONFIG_OUTPUT: 4052 ret = pinctrl_gpio_direction_output(jzpc->gc, 4053 pin - jzpc->gc->base); 4054 if (ret) 4055 return ret; 4056 4057 ingenic_set_output_level(jzpc, pin, arg); 4058 break; 4059 4060 case PIN_CONFIG_SLEW_RATE: 4061 if (!is_soc_or_above(jzpc, ID_X1830)) 4062 return -EINVAL; 4063 4064 ingenic_set_slew_rate(jzpc, pin, arg); 4065 break; 4066 4067 default: 4068 /* unreachable */ 4069 break; 4070 } 4071 } 4072 4073 return 0; 4074 } 4075 4076 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, 4077 unsigned int group, unsigned long *config) 4078 { 4079 const unsigned int *pins; 4080 unsigned int i, npins, old = 0; 4081 int ret; 4082 4083 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 4084 if (ret) 4085 return ret; 4086 4087 for (i = 0; i < npins; i++) { 4088 if (ingenic_pinconf_get(pctldev, pins[i], config)) 4089 return -ENOTSUPP; 4090 4091 /* configs do not match between two pins */ 4092 if (i && (old != *config)) 4093 return -ENOTSUPP; 4094 4095 old = *config; 4096 } 4097 4098 return 0; 4099 } 4100 4101 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, 4102 unsigned int group, unsigned long *configs, 4103 unsigned int num_configs) 4104 { 4105 const unsigned int *pins; 4106 unsigned int i, npins; 4107 int ret; 4108 4109 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 4110 if (ret) 4111 return ret; 4112 4113 for (i = 0; i < npins; i++) { 4114 ret = ingenic_pinconf_set(pctldev, 4115 pins[i], configs, num_configs); 4116 if (ret) 4117 return ret; 4118 } 4119 4120 return 0; 4121 } 4122 4123 static const struct pinconf_ops ingenic_confops = { 4124 .is_generic = true, 4125 .pin_config_get = ingenic_pinconf_get, 4126 .pin_config_set = ingenic_pinconf_set, 4127 .pin_config_group_get = ingenic_pinconf_group_get, 4128 .pin_config_group_set = ingenic_pinconf_group_set, 4129 }; 4130 4131 static const struct regmap_config ingenic_pinctrl_regmap_config = { 4132 .reg_bits = 32, 4133 .val_bits = 32, 4134 .reg_stride = 4, 4135 }; 4136 4137 static const struct of_device_id ingenic_gpio_of_matches[] __initconst = { 4138 { .compatible = "ingenic,jz4730-gpio" }, 4139 { .compatible = "ingenic,jz4740-gpio" }, 4140 { .compatible = "ingenic,jz4725b-gpio" }, 4141 { .compatible = "ingenic,jz4750-gpio" }, 4142 { .compatible = "ingenic,jz4755-gpio" }, 4143 { .compatible = "ingenic,jz4760-gpio" }, 4144 { .compatible = "ingenic,jz4770-gpio" }, 4145 { .compatible = "ingenic,jz4775-gpio" }, 4146 { .compatible = "ingenic,jz4780-gpio" }, 4147 { .compatible = "ingenic,x1000-gpio" }, 4148 { .compatible = "ingenic,x1830-gpio" }, 4149 { .compatible = "ingenic,x2000-gpio" }, 4150 { .compatible = "ingenic,x2100-gpio" }, 4151 {}, 4152 }; 4153 4154 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, 4155 struct fwnode_handle *fwnode) 4156 { 4157 struct ingenic_gpio_chip *jzgc; 4158 struct device *dev = jzpc->dev; 4159 struct gpio_irq_chip *girq; 4160 unsigned int bank; 4161 int err; 4162 4163 err = fwnode_property_read_u32(fwnode, "reg", &bank); 4164 if (err) { 4165 dev_err(dev, "Cannot read \"reg\" property: %i\n", err); 4166 return err; 4167 } 4168 4169 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL); 4170 if (!jzgc) 4171 return -ENOMEM; 4172 4173 jzpc->gc = &jzgc->gc; 4174 4175 jzgc->jzpc = jzpc; 4176 jzgc->reg_base = bank * jzpc->info->reg_offset; 4177 4178 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); 4179 if (!jzgc->gc.label) 4180 return -ENOMEM; 4181 4182 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY 4183 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN 4184 * <linux/gpio/consumer.h> INSTEAD. 4185 */ 4186 jzgc->gc.base = bank * 32; 4187 4188 jzgc->gc.ngpio = 32; 4189 jzgc->gc.parent = dev; 4190 jzgc->gc.fwnode = fwnode; 4191 jzgc->gc.owner = THIS_MODULE; 4192 4193 jzgc->gc.set = ingenic_gpio_set; 4194 jzgc->gc.get = ingenic_gpio_get; 4195 jzgc->gc.direction_input = pinctrl_gpio_direction_input; 4196 jzgc->gc.direction_output = ingenic_gpio_direction_output; 4197 jzgc->gc.get_direction = ingenic_gpio_get_direction; 4198 jzgc->gc.request = gpiochip_generic_request; 4199 jzgc->gc.free = gpiochip_generic_free; 4200 4201 err = fwnode_irq_get(fwnode, 0); 4202 if (err < 0) 4203 return err; 4204 if (!err) 4205 return -EINVAL; 4206 jzgc->irq = err; 4207 4208 girq = &jzgc->gc.irq; 4209 gpio_irq_chip_set_chip(girq, &ingenic_gpio_irqchip); 4210 girq->parent_handler = ingenic_gpio_irq_handler; 4211 girq->num_parents = 1; 4212 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 4213 GFP_KERNEL); 4214 if (!girq->parents) 4215 return -ENOMEM; 4216 4217 girq->parents[0] = jzgc->irq; 4218 girq->default_type = IRQ_TYPE_NONE; 4219 girq->handler = handle_level_irq; 4220 4221 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); 4222 if (err) 4223 return err; 4224 4225 return 0; 4226 } 4227 4228 static int __init ingenic_pinctrl_probe(struct platform_device *pdev) 4229 { 4230 struct device *dev = &pdev->dev; 4231 struct ingenic_pinctrl *jzpc; 4232 struct pinctrl_desc *pctl_desc; 4233 void __iomem *base; 4234 const struct ingenic_chip_info *chip_info; 4235 struct regmap_config regmap_config; 4236 struct fwnode_handle *fwnode; 4237 unsigned int i; 4238 int err; 4239 4240 chip_info = device_get_match_data(dev); 4241 if (!chip_info) { 4242 dev_err(dev, "Unsupported SoC\n"); 4243 return -EINVAL; 4244 } 4245 4246 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL); 4247 if (!jzpc) 4248 return -ENOMEM; 4249 4250 base = devm_platform_ioremap_resource(pdev, 0); 4251 if (IS_ERR(base)) 4252 return PTR_ERR(base); 4253 4254 regmap_config = ingenic_pinctrl_regmap_config; 4255 if (chip_info->access_table) { 4256 regmap_config.rd_table = chip_info->access_table; 4257 regmap_config.wr_table = chip_info->access_table; 4258 } else { 4259 regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4; 4260 } 4261 4262 jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config); 4263 if (IS_ERR(jzpc->map)) { 4264 dev_err(dev, "Failed to create regmap\n"); 4265 return PTR_ERR(jzpc->map); 4266 } 4267 4268 jzpc->dev = dev; 4269 jzpc->info = chip_info; 4270 4271 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 4272 if (!pctl_desc) 4273 return -ENOMEM; 4274 4275 /* fill in pinctrl_desc structure */ 4276 pctl_desc->name = dev_name(dev); 4277 pctl_desc->owner = THIS_MODULE; 4278 pctl_desc->pctlops = &ingenic_pctlops; 4279 pctl_desc->pmxops = &ingenic_pmxops; 4280 pctl_desc->confops = &ingenic_confops; 4281 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; 4282 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, 4283 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); 4284 if (!jzpc->pdesc) 4285 return -ENOMEM; 4286 4287 for (i = 0; i < pctl_desc->npins; i++) { 4288 jzpc->pdesc[i].number = i; 4289 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 4290 'A' + (i / PINS_PER_GPIO_CHIP), 4291 i % PINS_PER_GPIO_CHIP); 4292 } 4293 4294 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); 4295 if (IS_ERR(jzpc->pctl)) { 4296 dev_err(dev, "Failed to register pinctrl\n"); 4297 return PTR_ERR(jzpc->pctl); 4298 } 4299 4300 for (i = 0; i < chip_info->num_groups; i++) { 4301 const struct group_desc *group = &chip_info->groups[i]; 4302 const struct pingroup *grp = &group->grp; 4303 4304 err = pinctrl_generic_add_group(jzpc->pctl, grp->name, grp->pins, grp->npins, 4305 group->data); 4306 if (err < 0) { 4307 dev_err(dev, "Failed to register group %s\n", grp->name); 4308 return err; 4309 } 4310 } 4311 4312 for (i = 0; i < chip_info->num_functions; i++) { 4313 const struct function_desc *func = &chip_info->functions[i]; 4314 4315 err = pinmux_generic_add_function(jzpc->pctl, func->name, 4316 func->group_names, func->num_group_names, 4317 func->data); 4318 if (err < 0) { 4319 dev_err(dev, "Failed to register function %s\n", 4320 func->name); 4321 return err; 4322 } 4323 } 4324 4325 dev_set_drvdata(dev, jzpc->map); 4326 4327 device_for_each_child_node(dev, fwnode) { 4328 if (of_match_node(ingenic_gpio_of_matches, to_of_node(fwnode))) { 4329 err = ingenic_gpio_probe(jzpc, fwnode); 4330 if (err) { 4331 fwnode_handle_put(fwnode); 4332 return err; 4333 } 4334 } 4335 } 4336 4337 return 0; 4338 } 4339 4340 #define IF_ENABLED(cfg, ptr) PTR_IF(IS_ENABLED(cfg), (ptr)) 4341 4342 static const struct of_device_id ingenic_pinctrl_of_matches[] = { 4343 { 4344 .compatible = "ingenic,jz4730-pinctrl", 4345 .data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info) 4346 }, 4347 { 4348 .compatible = "ingenic,jz4740-pinctrl", 4349 .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info) 4350 }, 4351 { 4352 .compatible = "ingenic,jz4725b-pinctrl", 4353 .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info) 4354 }, 4355 { 4356 .compatible = "ingenic,jz4750-pinctrl", 4357 .data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info) 4358 }, 4359 { 4360 .compatible = "ingenic,jz4755-pinctrl", 4361 .data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info) 4362 }, 4363 { 4364 .compatible = "ingenic,jz4760-pinctrl", 4365 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info) 4366 }, 4367 { 4368 .compatible = "ingenic,jz4760b-pinctrl", 4369 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info) 4370 }, 4371 { 4372 .compatible = "ingenic,jz4770-pinctrl", 4373 .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info) 4374 }, 4375 { 4376 .compatible = "ingenic,jz4775-pinctrl", 4377 .data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info) 4378 }, 4379 { 4380 .compatible = "ingenic,jz4780-pinctrl", 4381 .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info) 4382 }, 4383 { 4384 .compatible = "ingenic,x1000-pinctrl", 4385 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info) 4386 }, 4387 { 4388 .compatible = "ingenic,x1000e-pinctrl", 4389 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info) 4390 }, 4391 { 4392 .compatible = "ingenic,x1500-pinctrl", 4393 .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info) 4394 }, 4395 { 4396 .compatible = "ingenic,x1830-pinctrl", 4397 .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info) 4398 }, 4399 { 4400 .compatible = "ingenic,x2000-pinctrl", 4401 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) 4402 }, 4403 { 4404 .compatible = "ingenic,x2000e-pinctrl", 4405 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) 4406 }, 4407 { 4408 .compatible = "ingenic,x2100-pinctrl", 4409 .data = IF_ENABLED(CONFIG_MACH_X2100, &x2100_chip_info) 4410 }, 4411 { /* sentinel */ }, 4412 }; 4413 4414 static struct platform_driver ingenic_pinctrl_driver = { 4415 .driver = { 4416 .name = "pinctrl-ingenic", 4417 .of_match_table = ingenic_pinctrl_of_matches, 4418 }, 4419 }; 4420 4421 static int __init ingenic_pinctrl_drv_register(void) 4422 { 4423 return platform_driver_probe(&ingenic_pinctrl_driver, 4424 ingenic_pinctrl_probe); 4425 } 4426 subsys_initcall(ingenic_pinctrl_drv_register); 4427