1 /* 2 * Driver for the Gemini pin controller 3 * 4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 5 * 6 * This is a group-only pin controller. 7 */ 8 #include <linux/err.h> 9 #include <linux/init.h> 10 #include <linux/io.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/of.h> 13 #include <linux/pinctrl/machine.h> 14 #include <linux/pinctrl/pinctrl.h> 15 #include <linux/pinctrl/pinmux.h> 16 #include <linux/pinctrl/pinconf.h> 17 #include <linux/pinctrl/pinconf-generic.h> 18 #include <linux/platform_device.h> 19 #include <linux/slab.h> 20 #include <linux/regmap.h> 21 22 #include "pinctrl-utils.h" 23 24 #define DRIVER_NAME "pinctrl-gemini" 25 26 /** 27 * struct gemini_pin_conf - information about configuring a pin 28 * @pin: the pin number 29 * @reg: config register 30 * @mask: the bits affecting the configuration of the pin 31 */ 32 struct gemini_pin_conf { 33 unsigned int pin; 34 u32 reg; 35 u32 mask; 36 }; 37 38 /** 39 * struct gemini_pmx - state holder for the gemini pin controller 40 * @dev: a pointer back to containing device 41 * @virtbase: the offset to the controller in virtual memory 42 * @map: regmap to access registers 43 * @is_3512: whether the SoC/package is the 3512 variant 44 * @is_3516: whether the SoC/package is the 3516 variant 45 * @flash_pin: whether the flash pin (extended pins for parallel 46 * flash) is set 47 * @confs: pin config information 48 * @nconfs: number of pin config information items 49 */ 50 struct gemini_pmx { 51 struct device *dev; 52 struct pinctrl_dev *pctl; 53 struct regmap *map; 54 bool is_3512; 55 bool is_3516; 56 bool flash_pin; 57 const struct gemini_pin_conf *confs; 58 unsigned int nconfs; 59 }; 60 61 /** 62 * struct gemini_pin_group - describes a Gemini pin group 63 * @name: the name of this specific pin group 64 * @pins: an array of discrete physical pins used in this group, taken 65 * from the driver-local pin enumeration space 66 * @num_pins: the number of pins in this group array, i.e. the number of 67 * elements in .pins so we can iterate over that array 68 * @mask: bits to clear to enable this when doing pin muxing 69 * @value: bits to set to enable this when doing pin muxing 70 * @driving_mask: bitmask for the IO Pad driving register for this 71 * group, if it supports altering the driving strength of 72 * its lines. 73 */ 74 struct gemini_pin_group { 75 const char *name; 76 const unsigned int *pins; 77 const unsigned int num_pins; 78 u32 mask; 79 u32 value; 80 u32 driving_mask; 81 }; 82 83 /* Some straight-forward control registers */ 84 #define GLOBAL_WORD_ID 0x00 85 #define GLOBAL_STATUS 0x04 86 #define GLOBAL_STATUS_FLPIN BIT(20) 87 #define GLOBAL_IODRIVE 0x10 88 #define GLOBAL_GMAC_CTRL_SKEW 0x1c 89 #define GLOBAL_GMAC0_DATA_SKEW 0x20 90 #define GLOBAL_GMAC1_DATA_SKEW 0x24 91 /* 92 * Global Miscellaneous Control Register 93 * This register controls all Gemini pad/pin multiplexing 94 * 95 * It is a tricky register though: 96 * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot 97 * be brought back online, so it means permanent disablement of the 98 * corresponding pads. 99 * - For the bits named *_DISABLE, once you enable something, it cannot be 100 * DISABLED again. So you select a flash configuration once, and then 101 * you are stuck with it. 102 */ 103 #define GLOBAL_MISC_CTRL 0x30 104 #define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27) 105 /* Not really used */ 106 #define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28) 107 /* Activated with GMAC1 */ 108 #define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27) 109 /* This will be the default */ 110 #define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0 111 #define TVC_CLK_PAD_ENABLE BIT(20) 112 #define PCI_CLK_PAD_ENABLE BIT(17) 113 #define LPC_CLK_PAD_ENABLE BIT(16) 114 #define TVC_PADS_ENABLE BIT(9) 115 #define SSP_PADS_ENABLE BIT(8) 116 #define LCD_PADS_ENABLE BIT(7) 117 #define LPC_PADS_ENABLE BIT(6) 118 #define PCI_PADS_ENABLE BIT(5) 119 #define IDE_PADS_ENABLE BIT(4) 120 #define DRAM_PADS_POWERDOWN BIT(3) 121 #define NAND_PADS_DISABLE BIT(2) 122 #define PFLASH_PADS_DISABLE BIT(1) 123 #define SFLASH_PADS_DISABLE BIT(0) 124 #define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27)) 125 #define PADS_MAXBIT 27 126 127 /* Ordered by bit index */ 128 static const char * const gemini_padgroups[] = { 129 "serial flash", 130 "parallel flash", 131 "NAND flash", 132 "DRAM", 133 "IDE", 134 "PCI", 135 "LPC", 136 "LCD", 137 "SSP", 138 "TVC", 139 NULL, NULL, NULL, NULL, NULL, NULL, 140 "LPC CLK", 141 "PCI CLK", 142 NULL, NULL, 143 "TVC CLK", 144 NULL, NULL, NULL, NULL, NULL, 145 "GMAC1", 146 }; 147 148 static const struct pinctrl_pin_desc gemini_3512_pins[] = { 149 /* Row A */ 150 PINCTRL_PIN(0, "A1 VREF CTRL"), 151 PINCTRL_PIN(1, "A2 VCC2IO CTRL"), 152 PINCTRL_PIN(2, "A3 DRAM CK"), 153 PINCTRL_PIN(3, "A4 DRAM CK N"), 154 PINCTRL_PIN(4, "A5 DRAM A5"), 155 PINCTRL_PIN(5, "A6 DRAM CKE"), 156 PINCTRL_PIN(6, "A7 DRAM DQ11"), 157 PINCTRL_PIN(7, "A8 DRAM DQ0"), 158 PINCTRL_PIN(8, "A9 DRAM DQ5"), 159 PINCTRL_PIN(9, "A10 DRAM DQ6"), 160 PINCTRL_PIN(10, "A11 DRAM DRAM VREF"), 161 PINCTRL_PIN(11, "A12 DRAM BA1"), 162 PINCTRL_PIN(12, "A13 DRAM A2"), 163 PINCTRL_PIN(13, "A14 PCI GNT1 N"), 164 PINCTRL_PIN(14, "A15 PCI REQ9 N"), 165 PINCTRL_PIN(15, "A16 PCI REQ2 N"), 166 PINCTRL_PIN(16, "A17 PCI REQ3 N"), 167 PINCTRL_PIN(17, "A18 PCI AD31"), 168 /* Row B */ 169 PINCTRL_PIN(18, "B1 VCCK CTRL"), 170 PINCTRL_PIN(19, "B2 PWR EN"), 171 PINCTRL_PIN(20, "B3 RTC CLKI"), 172 PINCTRL_PIN(21, "B4 DRAM A4"), 173 PINCTRL_PIN(22, "B5 DRAM A6"), 174 PINCTRL_PIN(23, "B6 DRAM A12"), 175 PINCTRL_PIN(24, "B7 DRAM DQS1"), 176 PINCTRL_PIN(25, "B8 DRAM DQ15"), 177 PINCTRL_PIN(26, "B9 DRAM DQ4"), 178 PINCTRL_PIN(27, "B10 DRAM DQS0"), 179 PINCTRL_PIN(28, "B11 DRAM WE N"), 180 PINCTRL_PIN(29, "B12 DRAM A10"), 181 PINCTRL_PIN(30, "B13 DRAM A3"), 182 PINCTRL_PIN(31, "B14 PCI GNT0 N"), 183 PINCTRL_PIN(32, "B15 PCI GNT3 N"), 184 PINCTRL_PIN(33, "B16 PCI REQ1 N"), 185 PINCTRL_PIN(34, "B17 PCI AD30"), 186 PINCTRL_PIN(35, "B18 PCI AD29"), 187 /* Row C */ 188 PINCTRL_PIN(36, "C1 CIR RST N"), /* REALLY? CIR is not in 3512... */ 189 PINCTRL_PIN(37, "C2 XTALI"), 190 PINCTRL_PIN(38, "C3 PWR BTN"), 191 PINCTRL_PIN(39, "C4 RTC CLKO"), 192 PINCTRL_PIN(40, "C5 DRAM A7"), 193 PINCTRL_PIN(41, "C6 DRAM A11"), 194 PINCTRL_PIN(42, "C7 DRAM DQ10"), 195 PINCTRL_PIN(43, "C8 DRAM DQ14"), 196 PINCTRL_PIN(44, "C9 DRAM DQ3"), 197 PINCTRL_PIN(45, "C10 DRAM DQ7"), 198 PINCTRL_PIN(46, "C11 DRAM CAS N"), 199 PINCTRL_PIN(47, "C12 DRAM A0"), 200 PINCTRL_PIN(48, "C13 PCI INT0 N"), 201 PINCTRL_PIN(49, "C14 EXT RESET N"), 202 PINCTRL_PIN(50, "C15 PCI GNT2 N"), 203 PINCTRL_PIN(51, "C16 PCI AD28"), 204 PINCTRL_PIN(52, "C17 PCI AD27"), 205 PINCTRL_PIN(53, "C18 PCI AD26"), 206 /* Row D */ 207 PINCTRL_PIN(54, "D1 AVCCKHA"), 208 PINCTRL_PIN(55, "D2 AGNDIOHA"), 209 PINCTRL_PIN(56, "D3 XTALO"), 210 PINCTRL_PIN(57, "D4 AVCC3IOHA"), 211 PINCTRL_PIN(58, "D5 DRAM A8"), 212 PINCTRL_PIN(59, "D6 DRAM A9"), 213 PINCTRL_PIN(60, "D7 DRAM DQ9"), 214 PINCTRL_PIN(61, "D8 DRAM DQ13"), 215 PINCTRL_PIN(62, "D9 DRAM DQ2"), 216 PINCTRL_PIN(63, "D10 DRAM A13"), 217 PINCTRL_PIN(64, "D11 DRAM RAS N"), 218 PINCTRL_PIN(65, "D12 DRAM A1"), 219 PINCTRL_PIN(66, "D13 PCI INTC N"), 220 PINCTRL_PIN(67, "D14 PCI CLK"), 221 PINCTRL_PIN(68, "D15 PCI AD25"), 222 PINCTRL_PIN(69, "D16 PCI AD24"), 223 PINCTRL_PIN(70, "D17 PCI CBE3 N"), 224 PINCTRL_PIN(71, "D18 PCI AD23"), 225 /* Row E */ 226 PINCTRL_PIN(72, "E1 AVCC3IOHA"), 227 PINCTRL_PIN(73, "E2 EBG"), 228 PINCTRL_PIN(74, "E3 AVCC3IOHB"), 229 PINCTRL_PIN(75, "E4 REXT"), 230 PINCTRL_PIN(76, "E5 GND"), 231 PINCTRL_PIN(77, "E6 DRAM DQM1"), 232 PINCTRL_PIN(78, "E7 DRAM DQ8"), 233 PINCTRL_PIN(79, "E8 DRAM DQ12"), 234 PINCTRL_PIN(80, "E9 DRAM DQ1"), 235 PINCTRL_PIN(81, "E10 DRAM DQM0"), 236 PINCTRL_PIN(82, "E11 DRAM BA0"), 237 PINCTRL_PIN(83, "E12 PCI INTA N"), 238 PINCTRL_PIN(84, "E13 PCI INTB N"), 239 PINCTRL_PIN(85, "E14 GND"), 240 PINCTRL_PIN(86, "E15 PCI AD22"), 241 PINCTRL_PIN(87, "E16 PCI AD21"), 242 PINCTRL_PIN(88, "E17 PCI AD20"), 243 PINCTRL_PIN(89, "E18 PCI AD19"), 244 /* Row F */ 245 PINCTRL_PIN(90, "F1 SATA0 RXDP"), 246 PINCTRL_PIN(91, "F2 SATA0 RXDN"), 247 PINCTRL_PIN(92, "F3 AGNDK 0"), 248 PINCTRL_PIN(93, "F4 AVCC3 S"), 249 PINCTRL_PIN(94, "F5 AVCCK P"), 250 PINCTRL_PIN(95, "F6 GND"), 251 PINCTRL_PIN(96, "F7 VCC2IOHA 2"), 252 PINCTRL_PIN(97, "F8 VCC2IOHA 2"), 253 PINCTRL_PIN(98, "F9 V1"), 254 PINCTRL_PIN(99, "F10 V1"), 255 PINCTRL_PIN(100, "F11 VCC2IOHA 2"), 256 PINCTRL_PIN(101, "F12 VCC2IOHA 2"), 257 PINCTRL_PIN(102, "F13 GND"), 258 PINCTRL_PIN(103, "F14 PCI AD18"), 259 PINCTRL_PIN(104, "F15 PCI AD17"), 260 PINCTRL_PIN(105, "F16 PCI AD16"), 261 PINCTRL_PIN(106, "F17 PCI CBE2 N"), 262 PINCTRL_PIN(107, "F18 PCI FRAME N"), 263 /* Row G */ 264 PINCTRL_PIN(108, "G1 SATA0 TXDP"), 265 PINCTRL_PIN(109, "G2 SATA0 TXDN"), 266 PINCTRL_PIN(110, "G3 AGNDK 1"), 267 PINCTRL_PIN(111, "G4 AVCCK 0"), 268 PINCTRL_PIN(112, "G5 TEST CLKOUT"), 269 PINCTRL_PIN(113, "G6 AGND"), 270 PINCTRL_PIN(114, "G7 GND"), 271 PINCTRL_PIN(115, "G8 VCC2IOHA 2"), 272 PINCTRL_PIN(116, "G9 V1"), 273 PINCTRL_PIN(117, "G10 V1"), 274 PINCTRL_PIN(118, "G11 VCC2IOHA 2"), 275 PINCTRL_PIN(119, "G12 GND"), 276 PINCTRL_PIN(120, "G13 VCC3IOHA"), 277 PINCTRL_PIN(121, "G14 PCI IRDY N"), 278 PINCTRL_PIN(122, "G15 PCI TRDY N"), 279 PINCTRL_PIN(123, "G16 PCI DEVSEL N"), 280 PINCTRL_PIN(124, "G17 PCI STOP N"), 281 PINCTRL_PIN(125, "G18 PCI PAR"), 282 /* Row H */ 283 PINCTRL_PIN(126, "H1 SATA1 TXDP"), 284 PINCTRL_PIN(127, "H2 SATA1 TXDN"), 285 PINCTRL_PIN(128, "H3 AGNDK 2"), 286 PINCTRL_PIN(129, "H4 AVCCK 1"), 287 PINCTRL_PIN(130, "H5 AVCCK S"), 288 PINCTRL_PIN(131, "H6 AVCCKHB"), 289 PINCTRL_PIN(132, "H7 AGND"), 290 PINCTRL_PIN(133, "H8 GND"), 291 PINCTRL_PIN(134, "H9 GND"), 292 PINCTRL_PIN(135, "H10 GND"), 293 PINCTRL_PIN(136, "H11 GND"), 294 PINCTRL_PIN(137, "H12 VCC3IOHA"), 295 PINCTRL_PIN(138, "H13 VCC3IOHA"), 296 PINCTRL_PIN(139, "H14 PCI CBE1 N"), 297 PINCTRL_PIN(140, "H15 PCI AD15"), 298 PINCTRL_PIN(141, "H16 PCI AD14"), 299 PINCTRL_PIN(142, "H17 PCI AD13"), 300 PINCTRL_PIN(143, "H18 PCI AD12"), 301 /* Row J (for some reason I is skipped) */ 302 PINCTRL_PIN(144, "J1 SATA1 RXDP"), 303 PINCTRL_PIN(145, "J2 SATA1 RXDN"), 304 PINCTRL_PIN(146, "J3 AGNDK 3"), 305 PINCTRL_PIN(147, "J4 AVCCK 2"), 306 PINCTRL_PIN(148, "J5 IDE DA1"), 307 PINCTRL_PIN(149, "J6 V1"), 308 PINCTRL_PIN(150, "J7 V1"), 309 PINCTRL_PIN(151, "J8 GND"), 310 PINCTRL_PIN(152, "J9 GND"), 311 PINCTRL_PIN(153, "J10 GND"), 312 PINCTRL_PIN(154, "J11 GND"), 313 PINCTRL_PIN(155, "J12 V1"), 314 PINCTRL_PIN(156, "J13 V1"), 315 PINCTRL_PIN(157, "J14 PCI AD11"), 316 PINCTRL_PIN(158, "J15 PCI AD10"), 317 PINCTRL_PIN(159, "J16 PCI AD9"), 318 PINCTRL_PIN(160, "J17 PCI AD8"), 319 PINCTRL_PIN(161, "J18 PCI CBE0 N"), 320 /* Row K */ 321 PINCTRL_PIN(162, "K1 IDE CS1 N"), 322 PINCTRL_PIN(163, "K2 IDE CS0 N"), 323 PINCTRL_PIN(164, "K3 AVCCK 3"), 324 PINCTRL_PIN(165, "K4 IDE DA2"), 325 PINCTRL_PIN(166, "K5 IDE DA0"), 326 PINCTRL_PIN(167, "K6 V1"), 327 PINCTRL_PIN(168, "K7 V1"), 328 PINCTRL_PIN(169, "K8 GND"), 329 PINCTRL_PIN(170, "K9 GND"), 330 PINCTRL_PIN(171, "K10 GND"), 331 PINCTRL_PIN(172, "K11 GND"), 332 PINCTRL_PIN(173, "K12 V1"), 333 PINCTRL_PIN(174, "K13 V1"), 334 PINCTRL_PIN(175, "K14 PCI AD3"), 335 PINCTRL_PIN(176, "K15 PCI AD4"), 336 PINCTRL_PIN(177, "K16 PCI AD5"), 337 PINCTRL_PIN(178, "K17 PCI AD6"), 338 PINCTRL_PIN(179, "K18 PCI AD7"), 339 /* Row L */ 340 PINCTRL_PIN(180, "L1 IDE INTRQ"), 341 PINCTRL_PIN(181, "L2 IDE DMACK N"), 342 PINCTRL_PIN(182, "L3 IDE IORDY"), 343 PINCTRL_PIN(183, "L4 IDE DIOR N"), 344 PINCTRL_PIN(184, "L5 IDE DIOW N"), 345 PINCTRL_PIN(185, "L6 VCC3IOHA"), 346 PINCTRL_PIN(186, "L7 VCC3IOHA"), 347 PINCTRL_PIN(187, "L8 GND"), 348 PINCTRL_PIN(188, "L9 GND"), 349 PINCTRL_PIN(189, "L10 GND"), 350 PINCTRL_PIN(190, "L11 GND"), 351 PINCTRL_PIN(191, "L12 VCC3IOHA"), 352 PINCTRL_PIN(192, "L13 VCC3IOHA"), 353 PINCTRL_PIN(193, "L14 GPIO0 30"), 354 PINCTRL_PIN(194, "L15 GPIO0 31"), 355 PINCTRL_PIN(195, "L16 PCI AD0"), 356 PINCTRL_PIN(196, "L17 PCI AD1"), 357 PINCTRL_PIN(197, "L18 PCI AD2"), 358 /* Row M */ 359 PINCTRL_PIN(198, "M1 IDE DMARQ"), 360 PINCTRL_PIN(199, "M2 IDE DD15"), 361 PINCTRL_PIN(200, "M3 IDE DD0"), 362 PINCTRL_PIN(201, "M4 IDE DD14"), 363 PINCTRL_PIN(202, "M5 IDE DD1"), 364 PINCTRL_PIN(203, "M6 VCC3IOHA"), 365 PINCTRL_PIN(204, "M7 GND"), 366 PINCTRL_PIN(205, "M8 VCC2IOHA 1"), 367 PINCTRL_PIN(206, "M9 V1"), 368 PINCTRL_PIN(207, "M10 V1"), 369 PINCTRL_PIN(208, "M11 VCC3IOHA"), 370 PINCTRL_PIN(209, "M12 GND"), 371 PINCTRL_PIN(210, "M13 VCC3IOHA"), 372 PINCTRL_PIN(211, "M14 GPIO0 25"), 373 PINCTRL_PIN(212, "M15 GPIO0 26"), 374 PINCTRL_PIN(213, "M16 GPIO0 27"), 375 PINCTRL_PIN(214, "M17 GPIO0 28"), 376 PINCTRL_PIN(215, "M18 GPIO0 29"), 377 /* Row N */ 378 PINCTRL_PIN(216, "N1 IDE DD13"), 379 PINCTRL_PIN(217, "N2 IDE DD2"), 380 PINCTRL_PIN(218, "N3 IDE DD12"), 381 PINCTRL_PIN(219, "N4 IDE DD3"), 382 PINCTRL_PIN(220, "N5 IDE DD11"), 383 PINCTRL_PIN(221, "N6 GND"), 384 PINCTRL_PIN(222, "N7 VCC2IOHA 1"), 385 PINCTRL_PIN(223, "N8 VCC2IOHA 1"), 386 PINCTRL_PIN(224, "N9 V1"), 387 PINCTRL_PIN(225, "N10 V1"), 388 PINCTRL_PIN(226, "N11 VCC3IOHA"), 389 PINCTRL_PIN(227, "N12 VCC3IOHA"), 390 PINCTRL_PIN(228, "N13 GND"), 391 PINCTRL_PIN(229, "N14 GPIO0 20"), 392 PINCTRL_PIN(230, "N15 GPIO0 21"), 393 PINCTRL_PIN(231, "N16 GPIO0 22"), 394 PINCTRL_PIN(232, "N17 GPIO0 23"), 395 PINCTRL_PIN(233, "N18 GPIO0 24"), 396 /* Row P (for some reason O is skipped) */ 397 PINCTRL_PIN(234, "P1 IDE DD4"), 398 PINCTRL_PIN(235, "P2 IDE DD10"), 399 PINCTRL_PIN(236, "P3 IDE DD5"), 400 PINCTRL_PIN(237, "P4 IDE DD9"), 401 PINCTRL_PIN(238, "P5 GND"), 402 PINCTRL_PIN(239, "P6 USB XSCO"), 403 PINCTRL_PIN(240, "P7 GMAC0 TXD3"), 404 PINCTRL_PIN(241, "P8 GMAC0 TXEN"), 405 PINCTRL_PIN(242, "P9 GMAC0 RXD2"), 406 PINCTRL_PIN(243, "P10 GMAC1 TXC"), 407 PINCTRL_PIN(244, "P11 GMAC1 RXD1"), 408 PINCTRL_PIN(245, "P12 MODE SEL 1"), 409 PINCTRL_PIN(246, "P13 GPIO1 28"), 410 PINCTRL_PIN(247, "P14 GND"), 411 PINCTRL_PIN(248, "P15 GPIO0 5"), 412 PINCTRL_PIN(249, "P16 GPIO0 17"), 413 PINCTRL_PIN(250, "P17 GPIO0 18"), 414 PINCTRL_PIN(251, "P18 GPIO0 19"), 415 /* Row R (for some reason Q is skipped) */ 416 PINCTRL_PIN(252, "R1 IDE DD6"), 417 PINCTRL_PIN(253, "R2 IDE DD8"), 418 PINCTRL_PIN(254, "R3 IDE DD7"), 419 PINCTRL_PIN(255, "R4 IDE RESET N"), 420 PINCTRL_PIN(256, "R5 ICE0 DBGACK"), 421 PINCTRL_PIN(257, "R6 USB XSCI"), 422 PINCTRL_PIN(258, "R7 GMAC0 TXD2"), 423 PINCTRL_PIN(259, "R8 GMAC0 RXDV"), 424 PINCTRL_PIN(260, "R9 GMAC0 RXD3"), 425 PINCTRL_PIN(261, "R10 GMAC1 TXD0"), 426 PINCTRL_PIN(262, "R11 GMAC1 RXD0"), 427 PINCTRL_PIN(263, "R12 MODE SEL 0"), 428 PINCTRL_PIN(264, "R13 MODE SEL 3"), 429 PINCTRL_PIN(265, "R14 GPIO0 0"), 430 PINCTRL_PIN(266, "R15 GPIO0 4"), 431 PINCTRL_PIN(267, "R16 GPIO0 9"), 432 PINCTRL_PIN(268, "R17 GPIO0 15"), 433 PINCTRL_PIN(269, "R18 GPIO0 16"), 434 /* Row T (for some reason S is skipped) */ 435 PINCTRL_PIN(270, "T1 ICE0 DBGRQ"), 436 PINCTRL_PIN(271, "T2 ICE0 IDO"), 437 PINCTRL_PIN(272, "T3 ICE0 ICK"), 438 PINCTRL_PIN(273, "T4 ICE0 IMS"), 439 PINCTRL_PIN(274, "T5 ICE0 IDI"), 440 PINCTRL_PIN(275, "T6 USB RREF"), 441 PINCTRL_PIN(276, "T7 GMAC0 TXD1"), 442 PINCTRL_PIN(277, "T8 GMAC0 RXC"), 443 PINCTRL_PIN(278, "T9 GMAC0 CRS"), 444 PINCTRL_PIN(279, "T10 GMAC1 TXD1"), 445 PINCTRL_PIN(280, "T11 GMAC1 RXC"), 446 PINCTRL_PIN(281, "T12 GMAC1 CRS"), 447 PINCTRL_PIN(282, "T13 EXT CLK"), 448 PINCTRL_PIN(283, "T14 GPIO1 31"), 449 PINCTRL_PIN(284, "T15 GPIO0 3"), 450 PINCTRL_PIN(285, "T16 GPIO0 8"), 451 PINCTRL_PIN(286, "T17 GPIO0 12"), 452 PINCTRL_PIN(287, "T18 GPIO0 14"), 453 /* Row U */ 454 PINCTRL_PIN(288, "U1 ICE0 IRST N"), 455 PINCTRL_PIN(289, "U2 USB0 VCCHSRT"), 456 PINCTRL_PIN(290, "U3 USB0 DP"), 457 PINCTRL_PIN(291, "U4 USB VCCA U20"), 458 PINCTRL_PIN(292, "U5 USB1 DP"), 459 PINCTRL_PIN(293, "U6 USB1 GNDHSRT 1"), 460 PINCTRL_PIN(294, "U7 GMAC0 TXD0"), 461 PINCTRL_PIN(295, "U8 GMAC0 RXD0"), 462 PINCTRL_PIN(296, "U9 GMAC1 COL"), 463 PINCTRL_PIN(297, "U10 GMAC1 TXD2"), 464 PINCTRL_PIN(298, "U11 GMAC1 RXDV"), 465 PINCTRL_PIN(299, "U12 GMAC1 RXD3"), 466 PINCTRL_PIN(300, "U13 MODE SEL 2"), 467 PINCTRL_PIN(301, "U14 GPIO1 30"), 468 PINCTRL_PIN(302, "U15 GPIO0 2"), 469 PINCTRL_PIN(303, "U16 GPIO0 7"), 470 PINCTRL_PIN(304, "U17 GPIO0 11"), 471 PINCTRL_PIN(305, "U18 GPIO0 13"), 472 /* Row V */ 473 PINCTRL_PIN(306, "V1 USB0 GNDHSRT"), 474 PINCTRL_PIN(307, "V2 USB0 DM"), 475 PINCTRL_PIN(308, "V3 USB GNDA U20"), 476 PINCTRL_PIN(309, "V4 USB1 DM"), 477 PINCTRL_PIN(310, "V5 USB1 VCCHSRT1"), 478 PINCTRL_PIN(311, "V6 GMAC0 COL"), 479 PINCTRL_PIN(312, "V7 GMAC0 TXC"), 480 PINCTRL_PIN(313, "V8 GMAC0 RXD1"), 481 PINCTRL_PIN(314, "V9 REF CLK"), 482 PINCTRL_PIN(315, "V10 GMAC1 TXD3"), 483 PINCTRL_PIN(316, "V11 GMAC1 TXEN"), 484 PINCTRL_PIN(317, "V12 GMAC1 RXD2"), 485 PINCTRL_PIN(318, "V13 M30 CLK"), 486 PINCTRL_PIN(319, "V14 GPIO1 29"), 487 PINCTRL_PIN(320, "V15 GPIO0 1"), 488 PINCTRL_PIN(321, "V16 GPIO0 6"), 489 PINCTRL_PIN(322, "V17 GPIO0 10"), 490 PINCTRL_PIN(323, "V18 SYS RESET N"), 491 }; 492 493 494 /* Digital ground */ 495 static const unsigned int gnd_3512_pins[] = { 496 76, 85, 95, 102, 114, 119, 133, 134, 135, 136, 151, 152, 153, 154, 169, 497 170, 171, 172, 187, 188, 189, 190, 204, 209, 221, 228, 238, 247 498 }; 499 500 static const unsigned int dram_3512_pins[] = { 501 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 22, 23, 24, 25, 26, 27, 28, 29, 502 30, 40, 41, 42, 43, 44, 45, 46, 47, 58, 59, 60, 61, 62, 63, 64, 65, 77, 503 78, 79, 80, 81, 82 504 }; 505 506 static const unsigned int rtc_3512_pins[] = { 57, 20, 39 }; 507 508 static const unsigned int power_3512_pins[] = { 19, 38, 36, 55, 37, 56, 54, 72 }; 509 510 static const unsigned int system_3512_pins[] = { 511 318, 264, 300, 245, 263, 282, 314, 323, 49, 512 }; 513 514 static const unsigned int vcontrol_3512_pins[] = { 18, 0, 1 }; 515 516 static const unsigned int ice_3512_pins[] = { 256, 270, 271, 272, 273, 274, 288 }; 517 518 static const unsigned int ide_3512_pins[] = { 519 162, 163, 165, 166, 148, 180, 181, 182, 183, 184, 198, 199, 200, 201, 202, 520 216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 253, 254, 255 521 }; 522 523 static const unsigned int sata_3512_pins[] = { 524 75, 74, 73, 93, 94, 131, 112, 130, 92, 91, 90, 111, 110, 109, 108, 129, 525 128, 127, 126, 147, 146, 145, 144, 164 526 }; 527 528 static const unsigned int usb_3512_pins[] = { 529 306, 289, 307, 290, 239, 257, 275, 308, 291, 309, 292, 310, 293 530 }; 531 532 /* GMII, ethernet pins */ 533 static const unsigned int gmii_gmac0_3512_pins[] = { 534 240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313 535 }; 536 537 static const unsigned int gmii_gmac1_3512_pins[] = { 538 243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317 539 }; 540 541 static const unsigned int pci_3512_pins[] = { 542 13, 14, 15, 16, 17, 31, 32, 33, 34, 35, 48, 50, 51, 52, 53, 66, 67, 68, 69, 543 70, 71, 83, 84, 86, 87, 88, 89, 103, 104, 105, 106, 107, 121, 122, 123, 544 124, 125, 139, 140, 141, 142, 143, 157, 158, 159, 160, 161, 175, 176, 177, 545 178, 179, 195, 196, 197 546 }; 547 548 /* 549 * Apparently the LPC interface is using the PCICLK for the clocking so 550 * PCI needs to be active at the same time. 551 */ 552 static const unsigned int lpc_3512_pins[] = { 553 285, /* LPC_LAD[0] */ 554 304, /* LPC_SERIRQ */ 555 286, /* LPC_LAD[2] */ 556 305, /* LPC_LFRAME# */ 557 287, /* LPC_LAD[3] */ 558 268, /* LPC_LAD[1] */ 559 }; 560 561 /* Character LCD */ 562 static const unsigned int lcd_3512_pins[] = { 563 262, 244, 317, 299, 246, 319, 301, 283, 269, 233, 211 564 }; 565 566 static const unsigned int ssp_3512_pins[] = { 567 285, /* SSP_97RST# SSP AC97 Reset, active low */ 568 304, /* SSP_FSC */ 569 286, /* SSP_ECLK */ 570 305, /* SSP_TXD */ 571 287, /* SSP_RXD */ 572 268, /* SSP_SCLK */ 573 }; 574 575 static const unsigned int uart_rxtx_3512_pins[] = { 576 267, /* UART_SIN serial input, RX */ 577 322, /* UART_SOUT serial output, TX */ 578 }; 579 580 static const unsigned int uart_modem_3512_pins[] = { 581 285, /* UART_NDCD DCD carrier detect */ 582 304, /* UART_NDTR DTR data terminal ready */ 583 286, /* UART_NDSR DSR data set ready */ 584 305, /* UART_NRTS RTS request to send */ 585 287, /* UART_NCTS CTS clear to send */ 586 268, /* UART_NRI RI ring indicator */ 587 }; 588 589 static const unsigned int tvc_3512_pins[] = { 590 246, /* TVC_DATA[0] */ 591 319, /* TVC_DATA[1] */ 592 301, /* TVC_DATA[2] */ 593 283, /* TVC_DATA[3] */ 594 320, /* TVC_DATA[4] */ 595 302, /* TVC_DATA[5] */ 596 284, /* TVC_DATA[6] */ 597 266, /* TVC_DATA[7] */ 598 }; 599 600 static const unsigned int tvc_clk_3512_pins[] = { 601 265, /* TVC_CLK */ 602 }; 603 604 /* NAND flash pins */ 605 static const unsigned int nflash_3512_pins[] = { 606 199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 607 253, 254, 249, 250, 232, 233, 211, 193, 194 608 }; 609 610 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */ 611 static const unsigned int pflash_3512_pins[] = { 612 162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220, 613 234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213, 614 214, 215, 193, 194 615 }; 616 617 /* 618 * The parallel flash can be set up in a 26-bit address bus mode exposing 619 * A[0-15] (A[15] takes the place of ALE), but it has the 620 * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be 621 * used at the same time. 622 */ 623 static const unsigned int pflash_3512_pins_extended[] = { 624 162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220, 625 234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213, 626 214, 215, 193, 194, 627 /* The extra pins */ 628 296, 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281, 629 265, 630 }; 631 632 /* Serial flash pins CE0, CE1, DI, DO, CK */ 633 static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 }; 634 635 /* The GPIO0A (0) pin overlap with TVC CLK and extended parallel flash */ 636 static const unsigned int gpio0a_3512_pins[] = { 265 }; 637 638 /* The GPIO0B (1-4) pins overlap with TVC and ICE */ 639 static const unsigned int gpio0b_3512_pins[] = { 320, 302, 284, 266 }; 640 641 /* The GPIO0C (5-7) pins overlap with ICE */ 642 static const unsigned int gpio0c_3512_pins[] = { 248, 321, 303 }; 643 644 /* The GPIO0D (9,10) pins overlap with UART RX/TX */ 645 static const unsigned int gpio0d_3512_pins[] = { 267, 322 }; 646 647 /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */ 648 static const unsigned int gpio0e_3512_pins[] = { 285, 304, 286, 305, 287, 268 }; 649 650 /* The GPIO0F (16) pins overlap with LCD */ 651 static const unsigned int gpio0f_3512_pins[] = { 269 }; 652 653 /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */ 654 static const unsigned int gpio0g_3512_pins[] = { 249, 250 }; 655 656 /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */ 657 static const unsigned int gpio0h_3512_pins[] = { 251, 229 }; 658 659 /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */ 660 static const unsigned int gpio0i_3512_pins[] = { 230, 231 }; 661 662 /* The GPIO0J (23) pins overlap with all flash */ 663 static const unsigned int gpio0j_3512_pins[] = { 232 }; 664 665 /* The GPIO0K (24,25) pins overlap with all flash and LCD */ 666 static const unsigned int gpio0k_3512_pins[] = { 233, 211 }; 667 668 /* The GPIO0L (26-29) pins overlap with parallel flash */ 669 static const unsigned int gpio0l_3512_pins[] = { 212, 213, 214, 215 }; 670 671 /* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */ 672 static const unsigned int gpio0m_3512_pins[] = { 193, 194 }; 673 674 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */ 675 static const unsigned int gpio1a_3512_pins[] = { 162, 163, 165, 166, 148 }; 676 677 /* The GPIO1B (5-10, 27) pins overlap with just IDE */ 678 static const unsigned int gpio1b_3512_pins[] = { 679 180, 181, 182, 183, 184, 198, 255 680 }; 681 682 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */ 683 static const unsigned int gpio1c_3512_pins[] = { 684 199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 685 252, 253, 254 686 }; 687 688 /* The GPIO1D (28-31) pins overlap with LCD and TVC */ 689 static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 }; 690 691 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ 692 static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 }; 693 694 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ 695 static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 }; 696 697 /* The GPIO2C (8-31) pins overlap with PCI */ 698 static const unsigned int gpio2c_3512_pins[] = { 699 17, 34, 35, 51, 52, 53, 68, 69, 71, 86, 87, 88, 89, 103, 104, 105, 700 140, 141, 142, 143, 157, 158, 159, 160 701 }; 702 703 /* Groups for the 3512 SoC/package */ 704 static const struct gemini_pin_group gemini_3512_pin_groups[] = { 705 { 706 .name = "gndgrp", 707 .pins = gnd_3512_pins, 708 .num_pins = ARRAY_SIZE(gnd_3512_pins), 709 }, 710 { 711 .name = "dramgrp", 712 .pins = dram_3512_pins, 713 .num_pins = ARRAY_SIZE(dram_3512_pins), 714 .mask = DRAM_PADS_POWERDOWN, 715 }, 716 { 717 .name = "rtcgrp", 718 .pins = rtc_3512_pins, 719 .num_pins = ARRAY_SIZE(rtc_3512_pins), 720 }, 721 { 722 .name = "powergrp", 723 .pins = power_3512_pins, 724 .num_pins = ARRAY_SIZE(power_3512_pins), 725 }, 726 { 727 .name = "systemgrp", 728 .pins = system_3512_pins, 729 .num_pins = ARRAY_SIZE(system_3512_pins), 730 }, 731 { 732 .name = "vcontrolgrp", 733 .pins = vcontrol_3512_pins, 734 .num_pins = ARRAY_SIZE(vcontrol_3512_pins), 735 }, 736 { 737 .name = "icegrp", 738 .pins = ice_3512_pins, 739 .num_pins = ARRAY_SIZE(ice_3512_pins), 740 /* Conflict with some GPIO groups */ 741 }, 742 { 743 .name = "idegrp", 744 .pins = ide_3512_pins, 745 .num_pins = ARRAY_SIZE(ide_3512_pins), 746 /* Conflict with all flash usage */ 747 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | 748 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 749 .driving_mask = GENMASK(21, 20), 750 }, 751 { 752 .name = "satagrp", 753 .pins = sata_3512_pins, 754 .num_pins = ARRAY_SIZE(sata_3512_pins), 755 }, 756 { 757 .name = "usbgrp", 758 .pins = usb_3512_pins, 759 .num_pins = ARRAY_SIZE(usb_3512_pins), 760 }, 761 { 762 .name = "gmii_gmac0_grp", 763 .pins = gmii_gmac0_3512_pins, 764 .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins), 765 .driving_mask = GENMASK(17, 16), 766 }, 767 { 768 .name = "gmii_gmac1_grp", 769 .pins = gmii_gmac1_3512_pins, 770 .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins), 771 /* Bring out RGMII on the GMAC1 pins */ 772 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 773 .driving_mask = GENMASK(19, 18), 774 }, 775 { 776 .name = "pcigrp", 777 .pins = pci_3512_pins, 778 .num_pins = ARRAY_SIZE(pci_3512_pins), 779 /* Conflict only with GPIO2 */ 780 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, 781 .driving_mask = GENMASK(23, 22), 782 }, 783 { 784 .name = "lpcgrp", 785 .pins = lpc_3512_pins, 786 .num_pins = ARRAY_SIZE(lpc_3512_pins), 787 /* Conflict with SSP and UART modem pins */ 788 .mask = SSP_PADS_ENABLE, 789 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE, 790 }, 791 { 792 .name = "lcdgrp", 793 .pins = lcd_3512_pins, 794 .num_pins = ARRAY_SIZE(lcd_3512_pins), 795 /* Conflict with TVC and ICE */ 796 .mask = TVC_PADS_ENABLE, 797 .value = LCD_PADS_ENABLE, 798 }, 799 { 800 .name = "sspgrp", 801 .pins = ssp_3512_pins, 802 .num_pins = ARRAY_SIZE(ssp_3512_pins), 803 /* Conflict with LPC and UART modem pins */ 804 .mask = LPC_PADS_ENABLE, 805 .value = SSP_PADS_ENABLE, 806 }, 807 { 808 .name = "uartrxtxgrp", 809 .pins = uart_rxtx_3512_pins, 810 .num_pins = ARRAY_SIZE(uart_rxtx_3512_pins), 811 /* No conflicts except GPIO */ 812 }, 813 { 814 .name = "uartmodemgrp", 815 .pins = uart_modem_3512_pins, 816 .num_pins = ARRAY_SIZE(uart_modem_3512_pins), 817 /* 818 * Conflict with LPC and SSP, 819 * so when those are both disabled, modem UART can thrive. 820 */ 821 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, 822 }, 823 { 824 .name = "tvcgrp", 825 .pins = tvc_3512_pins, 826 .num_pins = ARRAY_SIZE(tvc_3512_pins), 827 /* Conflict with character LCD and ICE */ 828 .mask = LCD_PADS_ENABLE, 829 .value = TVC_PADS_ENABLE, 830 }, 831 { 832 .name = "tvcclkgrp", 833 .pins = tvc_clk_3512_pins, 834 .num_pins = ARRAY_SIZE(tvc_clk_3512_pins), 835 .value = TVC_CLK_PAD_ENABLE, 836 }, 837 /* 838 * The construction is done such that it is possible to use a serial 839 * flash together with a NAND or parallel (NOR) flash, but it is not 840 * possible to use NAND and parallel flash together. To use serial 841 * flash with one of the two others, the muxbits need to be flipped 842 * around before any access. 843 */ 844 { 845 .name = "nflashgrp", 846 .pins = nflash_3512_pins, 847 .num_pins = ARRAY_SIZE(nflash_3512_pins), 848 /* Conflict with IDE, parallel and serial flash */ 849 .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE, 850 .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 851 }, 852 { 853 .name = "pflashgrp", 854 .pins = pflash_3512_pins, 855 .num_pins = ARRAY_SIZE(pflash_3512_pins), 856 /* Conflict with IDE, NAND and serial flash */ 857 .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE, 858 .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE, 859 }, 860 { 861 .name = "sflashgrp", 862 .pins = sflash_3512_pins, 863 .num_pins = ARRAY_SIZE(sflash_3512_pins), 864 /* Conflict with IDE, NAND and parallel flash */ 865 .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE, 866 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, 867 }, 868 { 869 .name = "gpio0agrp", 870 .pins = gpio0a_3512_pins, 871 .num_pins = ARRAY_SIZE(gpio0a_3512_pins), 872 /* Conflict with TVC CLK */ 873 .mask = TVC_CLK_PAD_ENABLE, 874 }, 875 { 876 .name = "gpio0bgrp", 877 .pins = gpio0b_3512_pins, 878 .num_pins = ARRAY_SIZE(gpio0b_3512_pins), 879 /* Conflict with TVC and ICE */ 880 .mask = TVC_PADS_ENABLE, 881 }, 882 { 883 .name = "gpio0cgrp", 884 .pins = gpio0c_3512_pins, 885 .num_pins = ARRAY_SIZE(gpio0c_3512_pins), 886 /* Conflict with ICE */ 887 }, 888 { 889 .name = "gpio0dgrp", 890 .pins = gpio0d_3512_pins, 891 .num_pins = ARRAY_SIZE(gpio0d_3512_pins), 892 /* Conflict with UART RX/TX */ 893 }, 894 { 895 .name = "gpio0egrp", 896 .pins = gpio0e_3512_pins, 897 .num_pins = ARRAY_SIZE(gpio0e_3512_pins), 898 /* Conflict with LPC, UART modem pins, SSP */ 899 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, 900 }, 901 { 902 .name = "gpio0fgrp", 903 .pins = gpio0f_3512_pins, 904 .num_pins = ARRAY_SIZE(gpio0f_3512_pins), 905 /* Conflict with LCD */ 906 .mask = LCD_PADS_ENABLE, 907 }, 908 { 909 .name = "gpio0ggrp", 910 .pins = gpio0g_3512_pins, 911 .num_pins = ARRAY_SIZE(gpio0g_3512_pins), 912 /* Conflict with NAND flash */ 913 .value = NAND_PADS_DISABLE, 914 }, 915 { 916 .name = "gpio0hgrp", 917 .pins = gpio0h_3512_pins, 918 .num_pins = ARRAY_SIZE(gpio0h_3512_pins), 919 /* Conflict with parallel flash */ 920 .value = PFLASH_PADS_DISABLE, 921 }, 922 { 923 .name = "gpio0igrp", 924 .pins = gpio0i_3512_pins, 925 .num_pins = ARRAY_SIZE(gpio0i_3512_pins), 926 /* Conflict with serial flash */ 927 .value = SFLASH_PADS_DISABLE, 928 }, 929 { 930 .name = "gpio0jgrp", 931 .pins = gpio0j_3512_pins, 932 .num_pins = ARRAY_SIZE(gpio0j_3512_pins), 933 /* Conflict with all flash */ 934 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | 935 SFLASH_PADS_DISABLE, 936 }, 937 { 938 .name = "gpio0kgrp", 939 .pins = gpio0k_3512_pins, 940 .num_pins = ARRAY_SIZE(gpio0k_3512_pins), 941 /* Conflict with all flash and LCD */ 942 .mask = LCD_PADS_ENABLE, 943 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | 944 SFLASH_PADS_DISABLE, 945 }, 946 { 947 .name = "gpio0lgrp", 948 .pins = gpio0l_3512_pins, 949 .num_pins = ARRAY_SIZE(gpio0l_3512_pins), 950 /* Conflict with parallel flash */ 951 .value = PFLASH_PADS_DISABLE, 952 }, 953 { 954 .name = "gpio0mgrp", 955 .pins = gpio0m_3512_pins, 956 .num_pins = ARRAY_SIZE(gpio0m_3512_pins), 957 /* Conflict with parallel and NAND flash */ 958 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE, 959 }, 960 { 961 .name = "gpio1agrp", 962 .pins = gpio1a_3512_pins, 963 .num_pins = ARRAY_SIZE(gpio1a_3512_pins), 964 /* Conflict with IDE and parallel flash */ 965 .mask = IDE_PADS_ENABLE, 966 .value = PFLASH_PADS_DISABLE, 967 }, 968 { 969 .name = "gpio1bgrp", 970 .pins = gpio1b_3512_pins, 971 .num_pins = ARRAY_SIZE(gpio1b_3512_pins), 972 /* Conflict with IDE only */ 973 .mask = IDE_PADS_ENABLE, 974 }, 975 { 976 .name = "gpio1cgrp", 977 .pins = gpio1c_3512_pins, 978 .num_pins = ARRAY_SIZE(gpio1c_3512_pins), 979 /* Conflict with IDE, parallel and NAND flash */ 980 .mask = IDE_PADS_ENABLE, 981 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, 982 }, 983 { 984 .name = "gpio1dgrp", 985 .pins = gpio1d_3512_pins, 986 .num_pins = ARRAY_SIZE(gpio1d_3512_pins), 987 /* Conflict with LCD and TVC */ 988 .mask = LCD_PADS_ENABLE | TVC_PADS_ENABLE, 989 }, 990 { 991 .name = "gpio2agrp", 992 .pins = gpio2a_3512_pins, 993 .num_pins = ARRAY_SIZE(gpio2a_3512_pins), 994 .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 995 /* Conflict with GMII GMAC1 and extended parallel flash */ 996 }, 997 { 998 .name = "gpio2bgrp", 999 .pins = gpio2b_3512_pins, 1000 .num_pins = ARRAY_SIZE(gpio2b_3512_pins), 1001 /* Conflict with GMII GMAC1, extended parallel flash and LCD */ 1002 .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 1003 }, 1004 { 1005 .name = "gpio2cgrp", 1006 .pins = gpio2c_3512_pins, 1007 .num_pins = ARRAY_SIZE(gpio2c_3512_pins), 1008 /* Conflict with PCI */ 1009 .mask = PCI_PADS_ENABLE, 1010 }, 1011 }; 1012 1013 /* Pin names for the pinmux subsystem, 3516 variant */ 1014 static const struct pinctrl_pin_desc gemini_3516_pins[] = { 1015 /* Row A */ 1016 PINCTRL_PIN(0, "A1 AVCC3IOHA"), 1017 PINCTRL_PIN(1, "A2 DRAM CK N"), 1018 PINCTRL_PIN(2, "A3 DRAM CK"), 1019 PINCTRL_PIN(3, "A4 DRAM DQM1"), 1020 PINCTRL_PIN(4, "A5 DRAM DQ9"), 1021 PINCTRL_PIN(5, "A6 DRAM DQ13"), 1022 PINCTRL_PIN(6, "A7 DRAM DQ1"), 1023 PINCTRL_PIN(7, "A8 DRAM DQ2"), 1024 PINCTRL_PIN(8, "A9 DRAM DQ4"), 1025 PINCTRL_PIN(9, "A10 DRAM VREF"), 1026 PINCTRL_PIN(10, "A11 DRAM DQ24"), 1027 PINCTRL_PIN(11, "A12 DRAM DQ28"), 1028 PINCTRL_PIN(12, "A13 DRAM DQ30"), 1029 PINCTRL_PIN(13, "A14 DRAM DQ18"), 1030 PINCTRL_PIN(14, "A15 DRAM DQ21"), 1031 PINCTRL_PIN(15, "A16 DRAM CAS_N"), 1032 PINCTRL_PIN(16, "A17 DRAM BA1"), 1033 PINCTRL_PIN(17, "A18 PCI INTA N"), 1034 PINCTRL_PIN(18, "A19 PCI INTB N"), 1035 PINCTRL_PIN(19, "A20 PCI INTC N"), 1036 /* Row B */ 1037 PINCTRL_PIN(20, "B1 PWR EN"), 1038 PINCTRL_PIN(21, "B2 GND"), 1039 PINCTRL_PIN(22, "B3 RTC CLKO"), 1040 PINCTRL_PIN(23, "B4 DRAM A5"), 1041 PINCTRL_PIN(24, "B5 DRAM A6"), 1042 PINCTRL_PIN(25, "B6 DRAM DQS1"), 1043 PINCTRL_PIN(26, "B7 DRAM DQ11"), 1044 PINCTRL_PIN(27, "B8 DRAM DQ0"), 1045 PINCTRL_PIN(28, "B9 DRAM DQS0"), 1046 PINCTRL_PIN(29, "B10 DRAM DQ7"), 1047 PINCTRL_PIN(30, "B11 DRAM DQS3"), 1048 PINCTRL_PIN(31, "B12 DRAM DQ27"), 1049 PINCTRL_PIN(32, "B13 DRAM DQ31"), 1050 PINCTRL_PIN(33, "B14 DRAM DQ20"), 1051 PINCTRL_PIN(34, "B15 DRAM DQS2"), 1052 PINCTRL_PIN(35, "B16 DRAM WE N"), 1053 PINCTRL_PIN(36, "B17 DRAM A10"), 1054 PINCTRL_PIN(37, "B18 DRAM A2"), 1055 PINCTRL_PIN(38, "B19 GND"), 1056 PINCTRL_PIN(39, "B20 PCI GNT0 N"), 1057 /* Row C */ 1058 PINCTRL_PIN(40, "C1 AGNDIOHA"), 1059 PINCTRL_PIN(41, "C2 XTALI"), 1060 PINCTRL_PIN(42, "C3 GND"), 1061 PINCTRL_PIN(43, "C4 RTC CLKI"), 1062 PINCTRL_PIN(44, "C5 DRAM A12"), 1063 PINCTRL_PIN(45, "C6 DRAM A11"), 1064 PINCTRL_PIN(46, "C7 DRAM DQ8"), 1065 PINCTRL_PIN(47, "C8 DRAM DQ10"), 1066 PINCTRL_PIN(48, "C9 DRAM DQ3"), 1067 PINCTRL_PIN(49, "C10 DRAM DQ6"), 1068 PINCTRL_PIN(50, "C11 DRAM DQM0"), 1069 PINCTRL_PIN(51, "C12 DRAM DQ26"), 1070 PINCTRL_PIN(52, "C13 DRAM DQ16"), 1071 PINCTRL_PIN(53, "C14 DRAM DQ22"), 1072 PINCTRL_PIN(54, "C15 DRAM DQM2"), 1073 PINCTRL_PIN(55, "C16 DRAM BA0"), 1074 PINCTRL_PIN(56, "C17 DRAM A3"), 1075 PINCTRL_PIN(57, "C18 GND"), 1076 PINCTRL_PIN(58, "C19 PCI GNT1 N"), 1077 PINCTRL_PIN(59, "C20 PCI REQ2 N"), 1078 /* Row D */ 1079 PINCTRL_PIN(60, "D1 AVCC3IOAHA"), 1080 PINCTRL_PIN(61, "D2 AVCCKHA"), 1081 PINCTRL_PIN(62, "D3 XTALO"), 1082 PINCTRL_PIN(63, "D4 GND"), 1083 PINCTRL_PIN(64, "D5 CIR RXD"), 1084 PINCTRL_PIN(65, "D6 DRAM A7"), 1085 PINCTRL_PIN(66, "D7 DRAM A4"), 1086 PINCTRL_PIN(67, "D8 DRAM A8"), 1087 PINCTRL_PIN(68, "D9 DRAM CKE"), 1088 PINCTRL_PIN(69, "D10 DRAM DQ14"), 1089 PINCTRL_PIN(70, "D11 DRAM DQ5"), 1090 PINCTRL_PIN(71, "D12 DRAM DQ25"), 1091 PINCTRL_PIN(72, "D13 DRAM DQ17"), 1092 PINCTRL_PIN(73, "D14 DRAM DQ23"), 1093 PINCTRL_PIN(74, "D15 DRAM RAS N"), 1094 PINCTRL_PIN(75, "D16 DRAM A1"), 1095 PINCTRL_PIN(76, "D17 GND"), 1096 PINCTRL_PIN(77, "D18 EXT RESET N"), 1097 PINCTRL_PIN(78, "D19 PCI REQ1 N"), 1098 PINCTRL_PIN(79, "D20 PCI REQ3 N"), 1099 /* Row E */ 1100 PINCTRL_PIN(80, "E1 VCC2IO CTRL"), 1101 PINCTRL_PIN(81, "E2 VREF CTRL"), 1102 PINCTRL_PIN(82, "E3 CIR RST N"), 1103 PINCTRL_PIN(83, "E4 PWR BTN"), 1104 PINCTRL_PIN(84, "E5 GND"), 1105 PINCTRL_PIN(85, "E6 CIR TXD"), 1106 PINCTRL_PIN(86, "E7 VCCK CTRL"), 1107 PINCTRL_PIN(87, "E8 DRAM A9"), 1108 PINCTRL_PIN(88, "E9 DRAM DQ12"), 1109 PINCTRL_PIN(89, "E10 DRAM DQ15"), 1110 PINCTRL_PIN(90, "E11 DRAM DQM3"), 1111 PINCTRL_PIN(91, "E12 DRAM DQ29"), 1112 PINCTRL_PIN(92, "E13 DRAM DQ19"), 1113 PINCTRL_PIN(93, "E14 DRAM A13"), 1114 PINCTRL_PIN(94, "E15 DRAM A0"), 1115 PINCTRL_PIN(95, "E16 GND"), 1116 PINCTRL_PIN(96, "E17 PCI INTD N"), 1117 PINCTRL_PIN(97, "E18 PCI GNT3 N"), 1118 PINCTRL_PIN(98, "E19 PCI AD29"), 1119 PINCTRL_PIN(99, "E20 PCI AD28"), 1120 /* Row F */ 1121 PINCTRL_PIN(100, "F1 AVCCKHB"), 1122 PINCTRL_PIN(101, "F2 AVCCK P"), 1123 PINCTRL_PIN(102, "F3 EBG"), 1124 PINCTRL_PIN(103, "F4 REXT"), 1125 PINCTRL_PIN(104, "F5 AVCC3IOHB"), 1126 PINCTRL_PIN(105, "F6 GND"), 1127 PINCTRL_PIN(106, "F7 VCC2IOHA 2"), 1128 PINCTRL_PIN(107, "F8 VCC2IOHA 2"), 1129 PINCTRL_PIN(108, "F9 VCC2IOHA 2"), 1130 PINCTRL_PIN(109, "F10 V1"), 1131 PINCTRL_PIN(110, "F11 V1"), 1132 PINCTRL_PIN(111, "F12 VCC2IOHA 2"), 1133 PINCTRL_PIN(112, "F13 VCC2IOHA 2"), 1134 PINCTRL_PIN(113, "F14 VCC2IOHA 2"), 1135 PINCTRL_PIN(114, "F15 GND"), 1136 PINCTRL_PIN(115, "F16 PCI CLK"), 1137 PINCTRL_PIN(116, "F17 PCI GNT2 N"), 1138 PINCTRL_PIN(117, "F18 PCI AD31"), 1139 PINCTRL_PIN(118, "F19 PCI AD26"), 1140 PINCTRL_PIN(119, "F20 PCI CBE3 N"), 1141 /* Row G */ 1142 PINCTRL_PIN(120, "G1 SATA0 RXDP"), 1143 PINCTRL_PIN(121, "G2 SATA0 RXDN"), 1144 PINCTRL_PIN(122, "G3 AGNDK 0"), 1145 PINCTRL_PIN(123, "G4 AVCCK S"), 1146 PINCTRL_PIN(124, "G5 AVCC3 S"), 1147 PINCTRL_PIN(125, "G6 VCC2IOHA 2"), 1148 PINCTRL_PIN(126, "G7 GND"), 1149 PINCTRL_PIN(127, "G8 VCC2IOHA 2"), 1150 PINCTRL_PIN(128, "G9 V1"), 1151 PINCTRL_PIN(129, "G10 V1"), 1152 PINCTRL_PIN(130, "G11 V1"), 1153 PINCTRL_PIN(131, "G12 V1"), 1154 PINCTRL_PIN(132, "G13 VCC2IOHA 2"), 1155 PINCTRL_PIN(133, "G14 GND"), 1156 PINCTRL_PIN(134, "G15 VCC3IOHA"), 1157 PINCTRL_PIN(135, "G16 PCI REQ0 N"), 1158 PINCTRL_PIN(136, "G17 PCI AD30"), 1159 PINCTRL_PIN(137, "G18 PCI AD24"), 1160 PINCTRL_PIN(138, "G19 PCI AD23"), 1161 PINCTRL_PIN(139, "G20 PCI AD21"), 1162 /* Row H */ 1163 PINCTRL_PIN(140, "H1 SATA0 TXDP"), 1164 PINCTRL_PIN(141, "H2 SATA0 TXDN"), 1165 PINCTRL_PIN(142, "H3 AGNDK 1"), 1166 PINCTRL_PIN(143, "H4 AVCCK 0"), 1167 PINCTRL_PIN(144, "H5 TEST CLKOUT"), 1168 PINCTRL_PIN(145, "H6 AGND"), 1169 PINCTRL_PIN(146, "H7 VCC2IOHA 2"), 1170 PINCTRL_PIN(147, "H8 GND"), 1171 PINCTRL_PIN(148, "H9 GND"), 1172 PINCTRL_PIN(149, "H10 GDN"), 1173 PINCTRL_PIN(150, "H11 GND"), 1174 PINCTRL_PIN(151, "H12 GND"), 1175 PINCTRL_PIN(152, "H13 GND"), 1176 PINCTRL_PIN(153, "H14 VCC3IOHA"), 1177 PINCTRL_PIN(154, "H15 VCC3IOHA"), 1178 PINCTRL_PIN(155, "H16 PCI AD27"), 1179 PINCTRL_PIN(156, "H17 PCI AD25"), 1180 PINCTRL_PIN(157, "H18 PCI AD22"), 1181 PINCTRL_PIN(158, "H19 PCI AD18"), 1182 PINCTRL_PIN(159, "H20 PCI AD17"), 1183 /* Row J (for some reason I is skipped) */ 1184 PINCTRL_PIN(160, "J1 SATA1 TXDP"), 1185 PINCTRL_PIN(161, "J2 SATA1 TXDN"), 1186 PINCTRL_PIN(162, "J3 AGNDK 2"), 1187 PINCTRL_PIN(163, "J4 AVCCK 1"), 1188 PINCTRL_PIN(164, "J5 AGND"), 1189 PINCTRL_PIN(165, "J6 AGND"), 1190 PINCTRL_PIN(166, "J7 V1"), 1191 PINCTRL_PIN(167, "J8 GND"), 1192 PINCTRL_PIN(168, "J9 GND"), 1193 PINCTRL_PIN(169, "J10 GND"), 1194 PINCTRL_PIN(170, "J11 GND"), 1195 PINCTRL_PIN(171, "J12 GND"), 1196 PINCTRL_PIN(172, "J13 GND"), 1197 PINCTRL_PIN(173, "J14 V1"), 1198 PINCTRL_PIN(174, "J15 VCC3IOHA"), 1199 PINCTRL_PIN(175, "J16 PCI AD19"), 1200 PINCTRL_PIN(176, "J17 PCI AD20"), 1201 PINCTRL_PIN(177, "J18 PCI AD16"), 1202 PINCTRL_PIN(178, "J19 PCI CBE2 N"), 1203 PINCTRL_PIN(179, "J20 PCI FRAME N"), 1204 /* Row K */ 1205 PINCTRL_PIN(180, "K1 SATA1 RXDP"), 1206 PINCTRL_PIN(181, "K2 SATA1 RXDN"), 1207 PINCTRL_PIN(182, "K3 AGNDK 3"), 1208 PINCTRL_PIN(183, "K4 AVCCK 2"), 1209 PINCTRL_PIN(184, "K5 AGND"), 1210 PINCTRL_PIN(185, "K6 V1"), 1211 PINCTRL_PIN(186, "K7 V1"), 1212 PINCTRL_PIN(187, "K8 GND"), 1213 PINCTRL_PIN(188, "K9 GND"), 1214 PINCTRL_PIN(189, "K10 GND"), 1215 PINCTRL_PIN(190, "K11 GND"), 1216 PINCTRL_PIN(191, "K12 GND"), 1217 PINCTRL_PIN(192, "K13 GND"), 1218 PINCTRL_PIN(193, "K14 V1"), 1219 PINCTRL_PIN(194, "K15 V1"), 1220 PINCTRL_PIN(195, "K16 PCI TRDY N"), 1221 PINCTRL_PIN(196, "K17 PCI IRDY N"), 1222 PINCTRL_PIN(197, "K18 PCI DEVSEL N"), 1223 PINCTRL_PIN(198, "K19 PCI STOP N"), 1224 PINCTRL_PIN(199, "K20 PCI PAR"), 1225 /* Row L */ 1226 PINCTRL_PIN(200, "L1 IDE CS0 N"), 1227 PINCTRL_PIN(201, "L2 IDE DA0"), 1228 PINCTRL_PIN(202, "L3 AVCCK 3"), 1229 PINCTRL_PIN(203, "L4 AGND"), 1230 PINCTRL_PIN(204, "L5 IDE DIOR N"), 1231 PINCTRL_PIN(205, "L6 V1"), 1232 PINCTRL_PIN(206, "L7 V1"), 1233 PINCTRL_PIN(207, "L8 GND"), 1234 PINCTRL_PIN(208, "L9 GND"), 1235 PINCTRL_PIN(209, "L10 GND"), 1236 PINCTRL_PIN(210, "L11 GND"), 1237 PINCTRL_PIN(211, "L12 GND"), 1238 PINCTRL_PIN(212, "L13 GND"), 1239 PINCTRL_PIN(213, "L14 V1"), 1240 PINCTRL_PIN(214, "L15 V1"), 1241 PINCTRL_PIN(215, "L16 PCI AD12"), 1242 PINCTRL_PIN(216, "L17 PCI AD13"), 1243 PINCTRL_PIN(217, "L18 PCI AD14"), 1244 PINCTRL_PIN(218, "L19 PCI AD15"), 1245 PINCTRL_PIN(219, "L20 PCI CBE1 N"), 1246 /* Row M */ 1247 PINCTRL_PIN(220, "M1 IDE DA1"), 1248 PINCTRL_PIN(221, "M2 IDE CS1 N"), 1249 PINCTRL_PIN(222, "M3 IDE DA2"), 1250 PINCTRL_PIN(223, "M4 IDE DMACK N"), 1251 PINCTRL_PIN(224, "M5 IDE DD1"), 1252 PINCTRL_PIN(225, "M6 VCC3IOHA"), 1253 PINCTRL_PIN(226, "M7 V1"), 1254 PINCTRL_PIN(227, "M8 GND"), 1255 PINCTRL_PIN(228, "M9 GND"), 1256 PINCTRL_PIN(229, "M10 GND"), 1257 PINCTRL_PIN(230, "M11 GND"), 1258 PINCTRL_PIN(231, "M12 GND"), 1259 PINCTRL_PIN(232, "M13 GND"), 1260 PINCTRL_PIN(233, "M14 V1"), 1261 PINCTRL_PIN(234, "M15 VCC3IOHA"), 1262 PINCTRL_PIN(235, "M16 PCI AD7"), 1263 PINCTRL_PIN(236, "M17 PCI AD6"), 1264 PINCTRL_PIN(237, "M18 PCI AD9"), 1265 PINCTRL_PIN(238, "M19 PCI AD10"), 1266 PINCTRL_PIN(239, "M20 PCI AD11"), 1267 /* Row N */ 1268 PINCTRL_PIN(240, "N1 IDE IORDY"), 1269 PINCTRL_PIN(241, "N2 IDE INTRQ"), 1270 PINCTRL_PIN(242, "N3 IDE DIOW N"), 1271 PINCTRL_PIN(243, "N4 IDE DD15"), 1272 PINCTRL_PIN(244, "N5 IDE DMARQ"), 1273 PINCTRL_PIN(245, "N6 VCC3IOHA"), 1274 PINCTRL_PIN(246, "N7 VCC3IOHA"), 1275 PINCTRL_PIN(247, "N8 GND"), 1276 PINCTRL_PIN(248, "N9 GND"), 1277 PINCTRL_PIN(249, "N10 GND"), 1278 PINCTRL_PIN(250, "N11 GND"), 1279 PINCTRL_PIN(251, "N12 GND"), 1280 PINCTRL_PIN(252, "N13 GND"), 1281 PINCTRL_PIN(253, "N14 VCC3IOHA"), 1282 PINCTRL_PIN(254, "N15 VCC3IOHA"), 1283 PINCTRL_PIN(255, "N16 PCI CLKRUN N"), 1284 PINCTRL_PIN(256, "N17 PCI AD0"), 1285 PINCTRL_PIN(257, "N18 PCI AD4"), 1286 PINCTRL_PIN(258, "N19 PCI CBE0 N"), 1287 PINCTRL_PIN(259, "N20 PCI AD8"), 1288 /* Row P (for some reason O is skipped) */ 1289 PINCTRL_PIN(260, "P1 IDE DD0"), 1290 PINCTRL_PIN(261, "P2 IDE DD14"), 1291 PINCTRL_PIN(262, "P3 IDE DD2"), 1292 PINCTRL_PIN(263, "P4 IDE DD4"), 1293 PINCTRL_PIN(264, "P5 IDE DD3"), 1294 PINCTRL_PIN(265, "P6 VCC3IOHA"), 1295 PINCTRL_PIN(266, "P7 GND"), 1296 PINCTRL_PIN(267, "P8 VCC2IOHA 1"), 1297 PINCTRL_PIN(268, "P9 V1"), 1298 PINCTRL_PIN(269, "P10 V1"), 1299 PINCTRL_PIN(270, "P11 V1"), 1300 PINCTRL_PIN(271, "P12 V1"), 1301 PINCTRL_PIN(272, "P13 VCC3IOHA"), 1302 PINCTRL_PIN(273, "P14 GND"), 1303 PINCTRL_PIN(274, "P15 VCC3IOHA"), 1304 PINCTRL_PIN(275, "P16 GPIO0 30"), 1305 PINCTRL_PIN(276, "P17 GPIO0 28"), 1306 PINCTRL_PIN(277, "P18 PCI AD1"), 1307 PINCTRL_PIN(278, "P19 PCI AD3"), 1308 PINCTRL_PIN(279, "P20 PCI AD5"), 1309 /* Row R (for some reason Q is skipped) */ 1310 PINCTRL_PIN(280, "R1 IDE DD13"), 1311 PINCTRL_PIN(281, "R2 IDE DD12"), 1312 PINCTRL_PIN(282, "R3 IDE DD10"), 1313 PINCTRL_PIN(283, "R4 IDE DD6"), 1314 PINCTRL_PIN(284, "R5 ICE0 IDI"), 1315 PINCTRL_PIN(285, "R6 GND"), 1316 PINCTRL_PIN(286, "R7 VCC2IOHA 1"), 1317 PINCTRL_PIN(287, "R8 VCC2IOHA 1"), 1318 PINCTRL_PIN(288, "R9 VCC2IOHA 1"), 1319 PINCTRL_PIN(289, "R10 V1"), 1320 PINCTRL_PIN(290, "R11 V1"), 1321 PINCTRL_PIN(291, "R12 VCC3IOHA"), 1322 PINCTRL_PIN(292, "R13 VCC3IOHA"), 1323 PINCTRL_PIN(293, "R14 VCC3IOHA"), 1324 PINCTRL_PIN(294, "R15 GND"), 1325 PINCTRL_PIN(295, "R16 GPIO0 23"), 1326 PINCTRL_PIN(296, "R17 GPIO0 21"), 1327 PINCTRL_PIN(297, "R18 GPIO0 26"), 1328 PINCTRL_PIN(298, "R19 GPIO0 31"), 1329 PINCTRL_PIN(299, "R20 PCI AD2"), 1330 /* Row T (for some reason S is skipped) */ 1331 PINCTRL_PIN(300, "T1 IDE DD11"), 1332 PINCTRL_PIN(301, "T2 IDE DD5"), 1333 PINCTRL_PIN(302, "T3 IDE DD8"), 1334 PINCTRL_PIN(303, "T4 ICE0 IDO"), 1335 PINCTRL_PIN(304, "T5 GND"), 1336 PINCTRL_PIN(305, "T6 USB GNDA U20"), 1337 PINCTRL_PIN(306, "T7 GMAC0 TXD0"), 1338 PINCTRL_PIN(307, "T8 GMAC0 TXEN"), 1339 PINCTRL_PIN(308, "T9 GMAC1 TXD3"), 1340 PINCTRL_PIN(309, "T10 GMAC1 RXDV"), 1341 PINCTRL_PIN(310, "T11 GMAC1 RXD2"), 1342 PINCTRL_PIN(311, "T12 GPIO1 29"), 1343 PINCTRL_PIN(312, "T13 GPIO0 3"), 1344 PINCTRL_PIN(313, "T14 GPIO0 9"), 1345 PINCTRL_PIN(314, "T15 GPIO0 16"), 1346 PINCTRL_PIN(315, "T16 GND"), 1347 PINCTRL_PIN(316, "T17 GPIO0 14"), 1348 PINCTRL_PIN(317, "T18 GPIO0 19"), 1349 PINCTRL_PIN(318, "T19 GPIO0 27"), 1350 PINCTRL_PIN(319, "T20 GPIO0 29"), 1351 /* Row U */ 1352 PINCTRL_PIN(320, "U1 IDE DD9"), 1353 PINCTRL_PIN(321, "U2 IDE DD7"), 1354 PINCTRL_PIN(322, "U3 ICE0 ICK"), 1355 PINCTRL_PIN(323, "U4 GND"), 1356 PINCTRL_PIN(324, "U5 USB XSCO"), 1357 PINCTRL_PIN(325, "U6 GMAC0 TXD1"), 1358 PINCTRL_PIN(326, "U7 GMAC0 TXD3"), 1359 PINCTRL_PIN(327, "U8 GMAC0 TXC"), 1360 PINCTRL_PIN(328, "U9 GMAC0 RXD3"), 1361 PINCTRL_PIN(329, "U10 GMAC1 TXD0"), 1362 PINCTRL_PIN(330, "U11 GMAC1 CRS"), 1363 PINCTRL_PIN(331, "U12 EXT CLK"), 1364 PINCTRL_PIN(332, "U13 DEV DEF"), 1365 PINCTRL_PIN(333, "U14 GPIO0 0"), 1366 PINCTRL_PIN(334, "U15 GPIO0 4"), 1367 PINCTRL_PIN(335, "U16 GPIO0 10"), 1368 PINCTRL_PIN(336, "U17 GND"), 1369 PINCTRL_PIN(337, "U18 GPIO0 17"), 1370 PINCTRL_PIN(338, "U19 GPIO0 22"), 1371 PINCTRL_PIN(339, "U20 GPIO0 25"), 1372 /* Row V */ 1373 PINCTRL_PIN(340, "V1 ICE0 DBGACK"), 1374 PINCTRL_PIN(341, "V2 ICE0 DBGRQ"), 1375 PINCTRL_PIN(342, "V3 GND"), 1376 PINCTRL_PIN(343, "V4 ICE0 IRST N"), 1377 PINCTRL_PIN(344, "V5 USB XSCI"), 1378 PINCTRL_PIN(345, "V6 GMAC0 COL"), 1379 PINCTRL_PIN(346, "V7 GMAC0 TXD2"), 1380 PINCTRL_PIN(347, "V8 GMAC0 RXDV"), 1381 PINCTRL_PIN(348, "V9 GMAC0 RXD1"), 1382 PINCTRL_PIN(349, "V10 GMAC1 COL"), 1383 PINCTRL_PIN(350, "V11 GMAC1 TXC"), 1384 PINCTRL_PIN(351, "V12 GMAC1 RXD1"), 1385 PINCTRL_PIN(352, "V13 MODE SEL1"), 1386 PINCTRL_PIN(353, "V14 GPIO1 28"), 1387 PINCTRL_PIN(354, "V15 GPIO0 1"), 1388 PINCTRL_PIN(355, "V16 GPIO0 8"), 1389 PINCTRL_PIN(356, "V17 GPIO0 11"), 1390 PINCTRL_PIN(357, "V18 GND"), 1391 PINCTRL_PIN(358, "V19 GPIO0 18"), 1392 PINCTRL_PIN(359, "V20 GPIO0 24"), 1393 /* Row W */ 1394 PINCTRL_PIN(360, "W1 IDE RESET N"), 1395 PINCTRL_PIN(361, "W2 GND"), 1396 PINCTRL_PIN(362, "W3 USB0 VCCHSRT"), 1397 PINCTRL_PIN(363, "W4 USB0 DP"), 1398 PINCTRL_PIN(364, "W5 USB VCCA U20"), 1399 PINCTRL_PIN(365, "W6 USB1 DP"), 1400 PINCTRL_PIN(366, "W7 USB1 GNDHSRT"), 1401 PINCTRL_PIN(367, "W8 GMAC0 RXD0"), 1402 PINCTRL_PIN(368, "W9 GMAC0 CRS"), 1403 PINCTRL_PIN(369, "W10 GMAC1 TXD2"), 1404 PINCTRL_PIN(370, "W11 GMAC1 TXEN"), 1405 PINCTRL_PIN(371, "W12 GMAC1 RXD3"), 1406 PINCTRL_PIN(372, "W13 MODE SEL0"), 1407 PINCTRL_PIN(373, "W14 MODE SEL3"), 1408 PINCTRL_PIN(374, "W15 GPIO1 31"), 1409 PINCTRL_PIN(375, "W16 GPIO0 5"), 1410 PINCTRL_PIN(376, "W17 GPIO0 7"), 1411 PINCTRL_PIN(377, "W18 GPIO0 12"), 1412 PINCTRL_PIN(378, "W19 GND"), 1413 PINCTRL_PIN(379, "W20 GPIO0 20"), 1414 /* Row Y */ 1415 PINCTRL_PIN(380, "Y1 ICE0 IMS"), 1416 PINCTRL_PIN(381, "Y2 USB0 GNDHSRT"), 1417 PINCTRL_PIN(382, "Y3 USB0 DM"), 1418 PINCTRL_PIN(383, "Y4 USB RREF"), 1419 PINCTRL_PIN(384, "Y5 USB1 DM"), 1420 PINCTRL_PIN(385, "Y6 USB1 VCCHSRT"), 1421 PINCTRL_PIN(386, "Y7 GMAC0 RXC"), 1422 PINCTRL_PIN(387, "Y8 GMAC0 RXD2"), 1423 PINCTRL_PIN(388, "Y9 REF CLK"), 1424 PINCTRL_PIN(389, "Y10 GMAC1 TXD1"), 1425 PINCTRL_PIN(390, "Y11 GMAC1 RXC"), 1426 PINCTRL_PIN(391, "Y12 GMAC1 RXD0"), 1427 PINCTRL_PIN(392, "Y13 M30 CLK"), 1428 PINCTRL_PIN(393, "Y14 MODE SEL2"), 1429 PINCTRL_PIN(394, "Y15 GPIO1 30"), 1430 PINCTRL_PIN(395, "Y16 GPIO0 2"), 1431 PINCTRL_PIN(396, "Y17 GPIO0 6"), 1432 PINCTRL_PIN(397, "Y18 SYS RESET N"), 1433 PINCTRL_PIN(398, "Y19 GPIO0 13"), 1434 PINCTRL_PIN(399, "Y20 GPIO0 15"), 1435 }; 1436 1437 /* Digital ground */ 1438 static const unsigned int gnd_3516_pins[] = { 1439 21, 38, 42, 57, 63, 76, 84, 95, 105, 114, 126, 133, 147, 148, 149, 150, 1440 151, 152, 167, 168, 169, 170, 171, 172, 187, 188, 189, 190, 191, 192, 1441 207, 208, 209, 210, 211, 212, 227, 228, 229, 230, 231, 232, 247, 248, 1442 249, 250, 251, 252, 266, 273, 285, 294, 304, 315, 323, 336, 342, 357, 1443 361, 378 1444 }; 1445 1446 static const unsigned int dram_3516_pins[] = { 1447 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 23, 24, 25, 26, 1448 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 44, 45, 46, 47, 48, 49, 50, 1449 51, 52, 53, 54, 55, 56, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 1450 87, 88, 89, 90, 91, 92, 93, 94 1451 }; 1452 1453 static const unsigned int rtc_3516_pins[] = { 0, 43, 22 }; 1454 1455 static const unsigned int power_3516_pins[] = { 20, 83, 40, 41, 60, 61, 62 }; 1456 1457 static const unsigned int cir_3516_pins[] = { 85, 64, 82 }; 1458 1459 static const unsigned int system_3516_pins[] = { 1460 332, 392, 372, 373, 393, 352, 331, 388, 397, 77 1461 }; 1462 1463 static const unsigned int vcontrol_3516_pins[] = { 86, 81, 80 }; 1464 1465 static const unsigned int ice_3516_pins[] = { 340, 341, 303, 322, 380, 284, 343 }; 1466 1467 static const unsigned int ide_3516_pins[] = { 1468 200, 201, 204, 220, 221, 222, 223, 224, 240, 241, 242, 243, 244, 260, 1469 261, 262, 263, 264, 280, 281, 282, 283, 300, 301, 302, 320, 321, 360 1470 }; 1471 1472 static const unsigned int sata_3516_pins[] = { 1473 100, 101, 102, 103, 104, 120, 121, 122, 123, 124, 140, 141, 142, 143, 1474 144, 160, 161, 162, 163, 180, 181, 182, 183, 202 1475 }; 1476 1477 static const unsigned int usb_3516_pins[] = { 1478 305, 324, 344, 362, 363, 364, 365, 366, 381, 382, 383, 384, 385 1479 }; 1480 1481 /* GMII, ethernet pins */ 1482 static const unsigned int gmii_gmac0_3516_pins[] = { 1483 306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387 1484 }; 1485 1486 static const unsigned int gmii_gmac1_3516_pins[] = { 1487 308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391 1488 }; 1489 1490 static const unsigned int pci_3516_pins[] = { 1491 17, 18, 19, 39, 58, 59, 78, 79, 96, 97, 98, 99, 115, 116, 117, 118, 1492 119, 135, 136, 137, 138, 139, 155, 156, 157, 158, 159, 175, 176, 177, 1493 178, 179, 195, 196, 197, 198, 199, 215, 216, 217, 218, 219, 235, 236, 1494 237, 238, 239, 255, 256, 257, 258, 259, 277, 278, 279, 299 1495 }; 1496 1497 /* 1498 * Apparently the LPC interface is using the PCICLK for the clocking so 1499 * PCI needs to be active at the same time. 1500 */ 1501 static const unsigned int lpc_3516_pins[] = { 1502 355, /* LPC_LAD[0] */ 1503 356, /* LPC_SERIRQ */ 1504 377, /* LPC_LAD[2] */ 1505 398, /* LPC_LFRAME# */ 1506 316, /* LPC_LAD[3] */ 1507 399, /* LPC_LAD[1] */ 1508 }; 1509 1510 /* Character LCD */ 1511 static const unsigned int lcd_3516_pins[] = { 1512 391, 351, 310, 371, 353, 311, 394, 374, 314, 359, 339 1513 }; 1514 1515 static const unsigned int ssp_3516_pins[] = { 1516 355, /* SSP_97RST# SSP AC97 Reset, active low */ 1517 356, /* SSP_FSC */ 1518 377, /* SSP_ECLK */ 1519 398, /* SSP_TXD */ 1520 316, /* SSP_RXD */ 1521 399, /* SSP_SCLK */ 1522 }; 1523 1524 static const unsigned int uart_rxtx_3516_pins[] = { 1525 313, /* UART_SIN serial input, RX */ 1526 335, /* UART_SOUT serial output, TX */ 1527 }; 1528 1529 static const unsigned int uart_modem_3516_pins[] = { 1530 355, /* UART_NDCD DCD carrier detect */ 1531 356, /* UART_NDTR DTR data terminal ready */ 1532 377, /* UART_NDSR DSR data set ready */ 1533 398, /* UART_NRTS RTS request to send */ 1534 316, /* UART_NCTS CTS clear to send */ 1535 399, /* UART_NRI RI ring indicator */ 1536 }; 1537 1538 static const unsigned int tvc_3516_pins[] = { 1539 353, /* TVC_DATA[0] */ 1540 311, /* TVC_DATA[1] */ 1541 394, /* TVC_DATA[2] */ 1542 374, /* TVC_DATA[3] */ 1543 354, /* TVC_DATA[4] */ 1544 395, /* TVC_DATA[5] */ 1545 312, /* TVC_DATA[6] */ 1546 334, /* TVC_DATA[7] */ 1547 }; 1548 1549 static const unsigned int tvc_clk_3516_pins[] = { 1550 333, /* TVC_CLK */ 1551 }; 1552 1553 /* NAND flash pins */ 1554 static const unsigned int nflash_3516_pins[] = { 1555 243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283, 1556 302, 321, 337, 358, 295, 359, 339, 275, 298 1557 }; 1558 1559 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */ 1560 static const unsigned int pflash_3516_pins[] = { 1561 221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300, 1562 263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318, 1563 276, 319, 275, 298 1564 }; 1565 1566 /* 1567 * The parallel flash can be set up in a 26-bit address bus mode exposing 1568 * A[0-15] (A[15] takes the place of ALE), but it has the 1569 * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be 1570 * used at the same time. 1571 */ 1572 static const unsigned int pflash_3516_pins_extended[] = { 1573 221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300, 1574 263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318, 1575 276, 319, 275, 298, 1576 /* The extra pins */ 1577 349, 308, 369, 389, 329, 350, 370, 309, 390, 391, 351, 310, 371, 330, 1578 333 1579 }; 1580 1581 /* Serial flash pins CE0, CE1, DI, DO, CK */ 1582 static const unsigned int sflash_3516_pins[] = { 296, 338, 295, 359, 339 }; 1583 1584 /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */ 1585 static const unsigned int gpio0a_3516_pins[] = { 354, 395, 312, 334 }; 1586 1587 /* The GPIO0B (5-7) pins overlap with ICE */ 1588 static const unsigned int gpio0b_3516_pins[] = { 375, 396, 376 }; 1589 1590 /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */ 1591 static const unsigned int gpio0c_3516_pins[] = { 355, 356, 377, 398, 316, 399 }; 1592 1593 /* The GPIO0D (9,10) pins overlap with UART RX/TX */ 1594 static const unsigned int gpio0d_3516_pins[] = { 313, 335 }; 1595 1596 /* The GPIO0E (16) pins overlap with LCD */ 1597 static const unsigned int gpio0e_3516_pins[] = { 314 }; 1598 1599 /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */ 1600 static const unsigned int gpio0f_3516_pins[] = { 337, 358 }; 1601 1602 /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */ 1603 static const unsigned int gpio0g_3516_pins[] = { 317, 379, 297, 318, 276, 319 }; 1604 1605 /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */ 1606 static const unsigned int gpio0h_3516_pins[] = { 296, 338 }; 1607 1608 /* The GPIO0I (23) pins overlap with all flash */ 1609 static const unsigned int gpio0i_3516_pins[] = { 295 }; 1610 1611 /* The GPIO0J (24,25) pins overlap with all flash and LCD */ 1612 static const unsigned int gpio0j_3516_pins[] = { 359, 339 }; 1613 1614 /* The GPIO0K (30,31) pins overlap with NAND flash */ 1615 static const unsigned int gpio0k_3516_pins[] = { 275, 298 }; 1616 1617 /* The GPIO0L (0) pins overlap with TVC_CLK */ 1618 static const unsigned int gpio0l_3516_pins[] = { 333 }; 1619 1620 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */ 1621 static const unsigned int gpio1a_3516_pins[] = { 221, 200, 222, 201, 220 }; 1622 1623 /* The GPIO1B (5-10,27) pins overlap with just IDE */ 1624 static const unsigned int gpio1b_3516_pins[] = { 241, 223, 240, 204, 242, 244, 360 }; 1625 1626 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */ 1627 static const unsigned int gpio1c_3516_pins[] = { 1628 243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283, 1629 302, 321 1630 }; 1631 1632 /* The GPIO1D (28-31) pins overlap with TVC */ 1633 static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 }; 1634 1635 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ 1636 static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 }; 1637 1638 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ 1639 static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 }; 1640 1641 /* The GPIO2C (8-31) pins overlap with PCI */ 1642 static const unsigned int gpio2c_3516_pins[] = { 1643 259, 237, 238, 239, 215, 216, 217, 218, 177, 159, 158, 175, 176, 139, 1644 157, 138, 137, 156, 118, 155, 99, 98, 136, 117 1645 }; 1646 1647 /* Groups for the 3516 SoC/package */ 1648 static const struct gemini_pin_group gemini_3516_pin_groups[] = { 1649 { 1650 .name = "gndgrp", 1651 .pins = gnd_3516_pins, 1652 .num_pins = ARRAY_SIZE(gnd_3516_pins), 1653 }, 1654 { 1655 .name = "dramgrp", 1656 .pins = dram_3516_pins, 1657 .num_pins = ARRAY_SIZE(dram_3516_pins), 1658 .mask = DRAM_PADS_POWERDOWN, 1659 }, 1660 { 1661 .name = "rtcgrp", 1662 .pins = rtc_3516_pins, 1663 .num_pins = ARRAY_SIZE(rtc_3516_pins), 1664 }, 1665 { 1666 .name = "powergrp", 1667 .pins = power_3516_pins, 1668 .num_pins = ARRAY_SIZE(power_3516_pins), 1669 }, 1670 { 1671 .name = "cirgrp", 1672 .pins = cir_3516_pins, 1673 .num_pins = ARRAY_SIZE(cir_3516_pins), 1674 }, 1675 { 1676 .name = "systemgrp", 1677 .pins = system_3516_pins, 1678 .num_pins = ARRAY_SIZE(system_3516_pins), 1679 }, 1680 { 1681 .name = "vcontrolgrp", 1682 .pins = vcontrol_3516_pins, 1683 .num_pins = ARRAY_SIZE(vcontrol_3516_pins), 1684 }, 1685 { 1686 .name = "icegrp", 1687 .pins = ice_3516_pins, 1688 .num_pins = ARRAY_SIZE(ice_3516_pins), 1689 /* Conflict with some GPIO groups */ 1690 }, 1691 { 1692 .name = "idegrp", 1693 .pins = ide_3516_pins, 1694 .num_pins = ARRAY_SIZE(ide_3516_pins), 1695 /* Conflict with all flash usage */ 1696 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | 1697 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 1698 .driving_mask = GENMASK(21, 20), 1699 }, 1700 { 1701 .name = "satagrp", 1702 .pins = sata_3516_pins, 1703 .num_pins = ARRAY_SIZE(sata_3516_pins), 1704 }, 1705 { 1706 .name = "usbgrp", 1707 .pins = usb_3516_pins, 1708 .num_pins = ARRAY_SIZE(usb_3516_pins), 1709 }, 1710 { 1711 .name = "gmii_gmac0_grp", 1712 .pins = gmii_gmac0_3516_pins, 1713 .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins), 1714 .mask = GEMINI_GMAC_IOSEL_MASK, 1715 .driving_mask = GENMASK(17, 16), 1716 }, 1717 { 1718 .name = "gmii_gmac1_grp", 1719 .pins = gmii_gmac1_3516_pins, 1720 .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins), 1721 /* Bring out RGMII on the GMAC1 pins */ 1722 .mask = GEMINI_GMAC_IOSEL_MASK, 1723 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 1724 .driving_mask = GENMASK(19, 18), 1725 }, 1726 { 1727 .name = "pcigrp", 1728 .pins = pci_3516_pins, 1729 .num_pins = ARRAY_SIZE(pci_3516_pins), 1730 /* Conflict only with GPIO2 */ 1731 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, 1732 .driving_mask = GENMASK(23, 22), 1733 }, 1734 { 1735 .name = "lpcgrp", 1736 .pins = lpc_3516_pins, 1737 .num_pins = ARRAY_SIZE(lpc_3516_pins), 1738 /* Conflict with SSP */ 1739 .mask = SSP_PADS_ENABLE, 1740 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE, 1741 }, 1742 { 1743 .name = "lcdgrp", 1744 .pins = lcd_3516_pins, 1745 .num_pins = ARRAY_SIZE(lcd_3516_pins), 1746 .mask = TVC_PADS_ENABLE, 1747 .value = LCD_PADS_ENABLE, 1748 }, 1749 { 1750 .name = "sspgrp", 1751 .pins = ssp_3516_pins, 1752 .num_pins = ARRAY_SIZE(ssp_3516_pins), 1753 /* Conflict with LPC */ 1754 .mask = LPC_PADS_ENABLE, 1755 .value = SSP_PADS_ENABLE, 1756 }, 1757 { 1758 .name = "uartrxtxgrp", 1759 .pins = uart_rxtx_3516_pins, 1760 .num_pins = ARRAY_SIZE(uart_rxtx_3516_pins), 1761 /* No conflicts except GPIO */ 1762 }, 1763 { 1764 .name = "uartmodemgrp", 1765 .pins = uart_modem_3516_pins, 1766 .num_pins = ARRAY_SIZE(uart_modem_3516_pins), 1767 /* 1768 * Conflict with LPC and SSP, 1769 * so when those are both disabled, modem UART can thrive. 1770 */ 1771 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, 1772 }, 1773 { 1774 .name = "tvcgrp", 1775 .pins = tvc_3516_pins, 1776 .num_pins = ARRAY_SIZE(tvc_3516_pins), 1777 /* Conflict with character LCD */ 1778 .mask = LCD_PADS_ENABLE, 1779 .value = TVC_PADS_ENABLE, 1780 }, 1781 { 1782 .name = "tvcclkgrp", 1783 .pins = tvc_clk_3516_pins, 1784 .num_pins = ARRAY_SIZE(tvc_clk_3516_pins), 1785 .value = TVC_CLK_PAD_ENABLE, 1786 }, 1787 /* 1788 * The construction is done such that it is possible to use a serial 1789 * flash together with a NAND or parallel (NOR) flash, but it is not 1790 * possible to use NAND and parallel flash together. To use serial 1791 * flash with one of the two others, the muxbits need to be flipped 1792 * around before any access. 1793 */ 1794 { 1795 .name = "nflashgrp", 1796 .pins = nflash_3516_pins, 1797 .num_pins = ARRAY_SIZE(nflash_3516_pins), 1798 /* Conflict with IDE, parallel and serial flash */ 1799 .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE, 1800 .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 1801 }, 1802 { 1803 .name = "pflashgrp", 1804 .pins = pflash_3516_pins, 1805 .num_pins = ARRAY_SIZE(pflash_3516_pins), 1806 /* Conflict with IDE, NAND and serial flash */ 1807 .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE, 1808 .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE, 1809 }, 1810 { 1811 .name = "sflashgrp", 1812 .pins = sflash_3516_pins, 1813 .num_pins = ARRAY_SIZE(sflash_3516_pins), 1814 /* Conflict with IDE, NAND and parallel flash */ 1815 .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE, 1816 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, 1817 }, 1818 { 1819 .name = "gpio0agrp", 1820 .pins = gpio0a_3516_pins, 1821 .num_pins = ARRAY_SIZE(gpio0a_3516_pins), 1822 /* Conflict with TVC and ICE */ 1823 .mask = TVC_PADS_ENABLE, 1824 }, 1825 { 1826 .name = "gpio0bgrp", 1827 .pins = gpio0b_3516_pins, 1828 .num_pins = ARRAY_SIZE(gpio0b_3516_pins), 1829 /* Conflict with ICE */ 1830 }, 1831 { 1832 .name = "gpio0cgrp", 1833 .pins = gpio0c_3516_pins, 1834 .num_pins = ARRAY_SIZE(gpio0c_3516_pins), 1835 /* Conflict with LPC, UART and SSP */ 1836 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, 1837 }, 1838 { 1839 .name = "gpio0dgrp", 1840 .pins = gpio0d_3516_pins, 1841 .num_pins = ARRAY_SIZE(gpio0d_3516_pins), 1842 /* Conflict with UART */ 1843 }, 1844 { 1845 .name = "gpio0egrp", 1846 .pins = gpio0e_3516_pins, 1847 .num_pins = ARRAY_SIZE(gpio0e_3516_pins), 1848 /* Conflict with LCD */ 1849 .mask = LCD_PADS_ENABLE, 1850 }, 1851 { 1852 .name = "gpio0fgrp", 1853 .pins = gpio0f_3516_pins, 1854 .num_pins = ARRAY_SIZE(gpio0f_3516_pins), 1855 /* Conflict with NAND flash */ 1856 .value = NAND_PADS_DISABLE, 1857 }, 1858 { 1859 .name = "gpio0ggrp", 1860 .pins = gpio0g_3516_pins, 1861 .num_pins = ARRAY_SIZE(gpio0g_3516_pins), 1862 /* Conflict with parallel flash */ 1863 .value = PFLASH_PADS_DISABLE, 1864 }, 1865 { 1866 .name = "gpio0hgrp", 1867 .pins = gpio0h_3516_pins, 1868 .num_pins = ARRAY_SIZE(gpio0h_3516_pins), 1869 /* Conflict with serial flash */ 1870 .value = SFLASH_PADS_DISABLE, 1871 }, 1872 { 1873 .name = "gpio0igrp", 1874 .pins = gpio0i_3516_pins, 1875 .num_pins = ARRAY_SIZE(gpio0i_3516_pins), 1876 /* Conflict with all flash */ 1877 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | 1878 SFLASH_PADS_DISABLE, 1879 }, 1880 { 1881 .name = "gpio0jgrp", 1882 .pins = gpio0j_3516_pins, 1883 .num_pins = ARRAY_SIZE(gpio0j_3516_pins), 1884 /* Conflict with all flash and LCD */ 1885 .mask = LCD_PADS_ENABLE, 1886 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | 1887 SFLASH_PADS_DISABLE, 1888 }, 1889 { 1890 .name = "gpio0kgrp", 1891 .pins = gpio0k_3516_pins, 1892 .num_pins = ARRAY_SIZE(gpio0k_3516_pins), 1893 /* Conflict with parallel and NAND flash */ 1894 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE, 1895 }, 1896 { 1897 .name = "gpio0lgrp", 1898 .pins = gpio0l_3516_pins, 1899 .num_pins = ARRAY_SIZE(gpio0l_3516_pins), 1900 /* Conflict with TVE CLK */ 1901 .mask = TVC_CLK_PAD_ENABLE, 1902 }, 1903 { 1904 .name = "gpio1agrp", 1905 .pins = gpio1a_3516_pins, 1906 .num_pins = ARRAY_SIZE(gpio1a_3516_pins), 1907 /* Conflict with IDE and parallel flash */ 1908 .mask = IDE_PADS_ENABLE, 1909 .value = PFLASH_PADS_DISABLE, 1910 }, 1911 { 1912 .name = "gpio1bgrp", 1913 .pins = gpio1b_3516_pins, 1914 .num_pins = ARRAY_SIZE(gpio1b_3516_pins), 1915 /* Conflict with IDE only */ 1916 .mask = IDE_PADS_ENABLE, 1917 }, 1918 { 1919 .name = "gpio1cgrp", 1920 .pins = gpio1c_3516_pins, 1921 .num_pins = ARRAY_SIZE(gpio1c_3516_pins), 1922 /* Conflict with IDE, parallel and NAND flash */ 1923 .mask = IDE_PADS_ENABLE, 1924 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, 1925 }, 1926 { 1927 .name = "gpio1dgrp", 1928 .pins = gpio1d_3516_pins, 1929 .num_pins = ARRAY_SIZE(gpio1d_3516_pins), 1930 /* Conflict with TVC */ 1931 .mask = TVC_PADS_ENABLE, 1932 }, 1933 { 1934 .name = "gpio2agrp", 1935 .pins = gpio2a_3516_pins, 1936 .num_pins = ARRAY_SIZE(gpio2a_3516_pins), 1937 .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 1938 /* Conflict with GMII GMAC1 and extended parallel flash */ 1939 }, 1940 { 1941 .name = "gpio2bgrp", 1942 .pins = gpio2b_3516_pins, 1943 .num_pins = ARRAY_SIZE(gpio2b_3516_pins), 1944 /* Conflict with GMII GMAC1, extended parallel flash and LCD */ 1945 .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 1946 }, 1947 { 1948 .name = "gpio2cgrp", 1949 .pins = gpio2c_3516_pins, 1950 .num_pins = ARRAY_SIZE(gpio2c_3516_pins), 1951 /* Conflict with PCI */ 1952 .mask = PCI_PADS_ENABLE, 1953 }, 1954 }; 1955 1956 static int gemini_get_groups_count(struct pinctrl_dev *pctldev) 1957 { 1958 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 1959 1960 if (pmx->is_3512) 1961 return ARRAY_SIZE(gemini_3512_pin_groups); 1962 if (pmx->is_3516) 1963 return ARRAY_SIZE(gemini_3516_pin_groups); 1964 return 0; 1965 } 1966 1967 static const char *gemini_get_group_name(struct pinctrl_dev *pctldev, 1968 unsigned int selector) 1969 { 1970 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 1971 1972 if (pmx->is_3512) 1973 return gemini_3512_pin_groups[selector].name; 1974 if (pmx->is_3516) 1975 return gemini_3516_pin_groups[selector].name; 1976 return NULL; 1977 } 1978 1979 static int gemini_get_group_pins(struct pinctrl_dev *pctldev, 1980 unsigned int selector, 1981 const unsigned int **pins, 1982 unsigned int *num_pins) 1983 { 1984 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 1985 1986 /* The special case with the 3516 flash pin */ 1987 if (pmx->flash_pin && 1988 pmx->is_3512 && 1989 !strcmp(gemini_3512_pin_groups[selector].name, "pflashgrp")) { 1990 *pins = pflash_3512_pins_extended; 1991 *num_pins = ARRAY_SIZE(pflash_3512_pins_extended); 1992 return 0; 1993 } 1994 if (pmx->flash_pin && 1995 pmx->is_3516 && 1996 !strcmp(gemini_3516_pin_groups[selector].name, "pflashgrp")) { 1997 *pins = pflash_3516_pins_extended; 1998 *num_pins = ARRAY_SIZE(pflash_3516_pins_extended); 1999 return 0; 2000 } 2001 if (pmx->is_3512) { 2002 *pins = gemini_3512_pin_groups[selector].pins; 2003 *num_pins = gemini_3512_pin_groups[selector].num_pins; 2004 } 2005 if (pmx->is_3516) { 2006 *pins = gemini_3516_pin_groups[selector].pins; 2007 *num_pins = gemini_3516_pin_groups[selector].num_pins; 2008 } 2009 return 0; 2010 } 2011 2012 static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 2013 unsigned int offset) 2014 { 2015 seq_printf(s, " " DRIVER_NAME); 2016 } 2017 2018 static const struct pinctrl_ops gemini_pctrl_ops = { 2019 .get_groups_count = gemini_get_groups_count, 2020 .get_group_name = gemini_get_group_name, 2021 .get_group_pins = gemini_get_group_pins, 2022 .pin_dbg_show = gemini_pin_dbg_show, 2023 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 2024 .dt_free_map = pinconf_generic_dt_free_map, 2025 }; 2026 2027 /** 2028 * struct gemini_pmx_func - describes Gemini pinmux functions 2029 * @name: the name of this specific function 2030 * @groups: corresponding pin groups 2031 */ 2032 struct gemini_pmx_func { 2033 const char *name; 2034 const char * const *groups; 2035 const unsigned int num_groups; 2036 }; 2037 2038 static const char * const dramgrps[] = { "dramgrp" }; 2039 static const char * const rtcgrps[] = { "rtcgrp" }; 2040 static const char * const powergrps[] = { "powergrp" }; 2041 static const char * const cirgrps[] = { "cirgrp" }; 2042 static const char * const systemgrps[] = { "systemgrp" }; 2043 static const char * const vcontrolgrps[] = { "vcontrolgrp" }; 2044 static const char * const icegrps[] = { "icegrp" }; 2045 static const char * const idegrps[] = { "idegrp" }; 2046 static const char * const satagrps[] = { "satagrp" }; 2047 static const char * const usbgrps[] = { "usbgrp" }; 2048 static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" }; 2049 static const char * const pcigrps[] = { "pcigrp" }; 2050 static const char * const lpcgrps[] = { "lpcgrp" }; 2051 static const char * const lcdgrps[] = { "lcdgrp" }; 2052 static const char * const sspgrps[] = { "sspgrp" }; 2053 static const char * const uartgrps[] = { "uartrxtxgrp", "uartmodemgrp" }; 2054 static const char * const tvcgrps[] = { "tvcgrp" }; 2055 static const char * const nflashgrps[] = { "nflashgrp" }; 2056 static const char * const pflashgrps[] = { "pflashgrp", "pflashextgrp" }; 2057 static const char * const sflashgrps[] = { "sflashgrp" }; 2058 static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp", 2059 "gpio0dgrp", "gpio0egrp", "gpio0fgrp", 2060 "gpio0ggrp", "gpio0hgrp", "gpio0igrp", 2061 "gpio0jgrp", "gpio0kgrp", "gpio0lgrp", 2062 "gpio0mgrp" }; 2063 static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp", 2064 "gpio1dgrp" }; 2065 static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" }; 2066 2067 static const struct gemini_pmx_func gemini_pmx_functions[] = { 2068 { 2069 .name = "dram", 2070 .groups = dramgrps, 2071 .num_groups = ARRAY_SIZE(idegrps), 2072 }, 2073 { 2074 .name = "rtc", 2075 .groups = rtcgrps, 2076 .num_groups = ARRAY_SIZE(rtcgrps), 2077 }, 2078 { 2079 .name = "power", 2080 .groups = powergrps, 2081 .num_groups = ARRAY_SIZE(powergrps), 2082 }, 2083 { 2084 /* This function is strictly unavailable on 3512 */ 2085 .name = "cir", 2086 .groups = cirgrps, 2087 .num_groups = ARRAY_SIZE(cirgrps), 2088 }, 2089 { 2090 .name = "system", 2091 .groups = systemgrps, 2092 .num_groups = ARRAY_SIZE(systemgrps), 2093 }, 2094 { 2095 .name = "vcontrol", 2096 .groups = vcontrolgrps, 2097 .num_groups = ARRAY_SIZE(vcontrolgrps), 2098 }, 2099 { 2100 .name = "ice", 2101 .groups = icegrps, 2102 .num_groups = ARRAY_SIZE(icegrps), 2103 }, 2104 { 2105 .name = "ide", 2106 .groups = idegrps, 2107 .num_groups = ARRAY_SIZE(idegrps), 2108 }, 2109 { 2110 .name = "sata", 2111 .groups = satagrps, 2112 .num_groups = ARRAY_SIZE(satagrps), 2113 }, 2114 { 2115 .name = "usb", 2116 .groups = usbgrps, 2117 .num_groups = ARRAY_SIZE(usbgrps), 2118 }, 2119 { 2120 .name = "gmii", 2121 .groups = gmiigrps, 2122 .num_groups = ARRAY_SIZE(gmiigrps), 2123 }, 2124 { 2125 .name = "pci", 2126 .groups = pcigrps, 2127 .num_groups = ARRAY_SIZE(pcigrps), 2128 }, 2129 { 2130 .name = "lpc", 2131 .groups = lpcgrps, 2132 .num_groups = ARRAY_SIZE(lpcgrps), 2133 }, 2134 { 2135 .name = "lcd", 2136 .groups = lcdgrps, 2137 .num_groups = ARRAY_SIZE(lcdgrps), 2138 }, 2139 { 2140 .name = "ssp", 2141 .groups = sspgrps, 2142 .num_groups = ARRAY_SIZE(sspgrps), 2143 }, 2144 { 2145 .name = "uart", 2146 .groups = uartgrps, 2147 .num_groups = ARRAY_SIZE(uartgrps), 2148 }, 2149 { 2150 .name = "tvc", 2151 .groups = tvcgrps, 2152 .num_groups = ARRAY_SIZE(tvcgrps), 2153 }, 2154 { 2155 .name = "nflash", 2156 .groups = nflashgrps, 2157 .num_groups = ARRAY_SIZE(nflashgrps), 2158 }, 2159 { 2160 .name = "pflash", 2161 .groups = pflashgrps, 2162 .num_groups = ARRAY_SIZE(pflashgrps), 2163 }, 2164 { 2165 .name = "sflash", 2166 .groups = sflashgrps, 2167 .num_groups = ARRAY_SIZE(sflashgrps), 2168 }, 2169 { 2170 .name = "gpio0", 2171 .groups = gpio0grps, 2172 .num_groups = ARRAY_SIZE(gpio0grps), 2173 }, 2174 { 2175 .name = "gpio1", 2176 .groups = gpio1grps, 2177 .num_groups = ARRAY_SIZE(gpio1grps), 2178 }, 2179 { 2180 .name = "gpio2", 2181 .groups = gpio2grps, 2182 .num_groups = ARRAY_SIZE(gpio2grps), 2183 }, 2184 }; 2185 2186 2187 static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev, 2188 unsigned int selector, 2189 unsigned int group) 2190 { 2191 struct gemini_pmx *pmx; 2192 const struct gemini_pmx_func *func; 2193 const struct gemini_pin_group *grp; 2194 u32 before, after, expected; 2195 unsigned long tmp; 2196 int i; 2197 2198 pmx = pinctrl_dev_get_drvdata(pctldev); 2199 2200 func = &gemini_pmx_functions[selector]; 2201 if (pmx->is_3512) 2202 grp = &gemini_3512_pin_groups[group]; 2203 else if (pmx->is_3516) 2204 grp = &gemini_3516_pin_groups[group]; 2205 else { 2206 dev_err(pmx->dev, "invalid SoC type\n"); 2207 return -ENODEV; 2208 } 2209 2210 dev_dbg(pmx->dev, 2211 "ACTIVATE function \"%s\" with group \"%s\"\n", 2212 func->name, grp->name); 2213 2214 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before); 2215 regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL, 2216 grp->mask | grp->value, 2217 grp->value); 2218 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after); 2219 2220 /* Which bits changed */ 2221 before &= PADS_MASK; 2222 after &= PADS_MASK; 2223 expected = before &= ~grp->mask; 2224 expected |= grp->value; 2225 expected &= PADS_MASK; 2226 2227 /* Print changed states */ 2228 tmp = grp->mask; 2229 for_each_set_bit(i, &tmp, PADS_MAXBIT) { 2230 bool enabled = !(i > 3); 2231 2232 /* Did not go low though it should */ 2233 if (after & BIT(i)) { 2234 dev_err(pmx->dev, 2235 "pin group %s could not be %s: " 2236 "probably a hardware limitation\n", 2237 gemini_padgroups[i], 2238 enabled ? "enabled" : "disabled"); 2239 dev_err(pmx->dev, 2240 "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n", 2241 before, after, expected); 2242 } else { 2243 dev_dbg(pmx->dev, 2244 "padgroup %s %s\n", 2245 gemini_padgroups[i], 2246 enabled ? "enabled" : "disabled"); 2247 } 2248 } 2249 2250 tmp = grp->value; 2251 for_each_set_bit(i, &tmp, PADS_MAXBIT) { 2252 bool enabled = (i > 3); 2253 2254 /* Did not go high though it should */ 2255 if (!(after & BIT(i))) { 2256 dev_err(pmx->dev, 2257 "pin group %s could not be %s: " 2258 "probably a hardware limitation\n", 2259 gemini_padgroups[i], 2260 enabled ? "enabled" : "disabled"); 2261 dev_err(pmx->dev, 2262 "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n", 2263 before, after, expected); 2264 } else { 2265 dev_dbg(pmx->dev, 2266 "padgroup %s %s\n", 2267 gemini_padgroups[i], 2268 enabled ? "enabled" : "disabled"); 2269 } 2270 } 2271 2272 return 0; 2273 } 2274 2275 static int gemini_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2276 { 2277 return ARRAY_SIZE(gemini_pmx_functions); 2278 } 2279 2280 static const char *gemini_pmx_get_func_name(struct pinctrl_dev *pctldev, 2281 unsigned int selector) 2282 { 2283 return gemini_pmx_functions[selector].name; 2284 } 2285 2286 static int gemini_pmx_get_groups(struct pinctrl_dev *pctldev, 2287 unsigned int selector, 2288 const char * const **groups, 2289 unsigned int * const num_groups) 2290 { 2291 *groups = gemini_pmx_functions[selector].groups; 2292 *num_groups = gemini_pmx_functions[selector].num_groups; 2293 return 0; 2294 } 2295 2296 static const struct pinmux_ops gemini_pmx_ops = { 2297 .get_functions_count = gemini_pmx_get_funcs_count, 2298 .get_function_name = gemini_pmx_get_func_name, 2299 .get_function_groups = gemini_pmx_get_groups, 2300 .set_mux = gemini_pmx_set_mux, 2301 }; 2302 2303 #define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \ 2304 .pin = _n, \ 2305 .reg = _r, \ 2306 .mask = GENMASK(_hb, _lb) \ 2307 } 2308 2309 static const struct gemini_pin_conf gemini_confs_3512[] = { 2310 GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ 2311 GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ 2312 GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ 2313 GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ 2314 GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ 2315 GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ 2316 GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ 2317 GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ 2318 GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ 2319 GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ 2320 GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ 2321 GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ 2322 GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ 2323 GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ 2324 GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ 2325 GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ 2326 GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ 2327 GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ 2328 GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ 2329 GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ 2330 GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ 2331 GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ 2332 GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ 2333 GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ 2334 }; 2335 2336 static const struct gemini_pin_conf gemini_confs_3516[] = { 2337 GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ 2338 GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ 2339 GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ 2340 GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ 2341 GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ 2342 GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ 2343 GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ 2344 GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ 2345 GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ 2346 GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ 2347 GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ 2348 GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ 2349 GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ 2350 GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ 2351 GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ 2352 GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ 2353 GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ 2354 GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ 2355 GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ 2356 GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ 2357 GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ 2358 GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ 2359 GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ 2360 GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ 2361 }; 2362 2363 static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx, 2364 unsigned int pin) 2365 { 2366 const struct gemini_pin_conf *retconf; 2367 int i; 2368 2369 for (i = 0; i < pmx->nconfs; i++) { 2370 retconf = &pmx->confs[i]; 2371 if (retconf->pin == pin) 2372 return retconf; 2373 } 2374 return NULL; 2375 } 2376 2377 static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2378 unsigned long *config) 2379 { 2380 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 2381 enum pin_config_param param = pinconf_to_config_param(*config); 2382 const struct gemini_pin_conf *conf; 2383 u32 val; 2384 2385 switch (param) { 2386 case PIN_CONFIG_SKEW_DELAY: 2387 conf = gemini_get_pin_conf(pmx, pin); 2388 if (!conf) 2389 return -ENOTSUPP; 2390 regmap_read(pmx->map, conf->reg, &val); 2391 val &= conf->mask; 2392 val >>= (ffs(conf->mask) - 1); 2393 *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val); 2394 break; 2395 default: 2396 return -ENOTSUPP; 2397 } 2398 2399 return 0; 2400 } 2401 2402 static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2403 unsigned long *configs, unsigned int num_configs) 2404 { 2405 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 2406 const struct gemini_pin_conf *conf; 2407 enum pin_config_param param; 2408 u32 arg; 2409 int ret = 0; 2410 int i; 2411 2412 for (i = 0; i < num_configs; i++) { 2413 param = pinconf_to_config_param(configs[i]); 2414 arg = pinconf_to_config_argument(configs[i]); 2415 2416 switch (param) { 2417 case PIN_CONFIG_SKEW_DELAY: 2418 if (arg > 0xf) 2419 return -EINVAL; 2420 conf = gemini_get_pin_conf(pmx, pin); 2421 if (!conf) { 2422 dev_err(pmx->dev, 2423 "invalid pin for skew delay %d\n", pin); 2424 return -ENOTSUPP; 2425 } 2426 arg <<= (ffs(conf->mask) - 1); 2427 dev_dbg(pmx->dev, 2428 "set pin %d to skew delay mask %08x, val %08x\n", 2429 pin, conf->mask, arg); 2430 regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); 2431 break; 2432 default: 2433 dev_err(pmx->dev, "Invalid config param %04x\n", param); 2434 return -ENOTSUPP; 2435 } 2436 } 2437 2438 return ret; 2439 } 2440 2441 static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev, 2442 unsigned selector, 2443 unsigned long *configs, 2444 unsigned num_configs) 2445 { 2446 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 2447 const struct gemini_pin_group *grp = NULL; 2448 enum pin_config_param param; 2449 u32 arg; 2450 u32 val; 2451 int i; 2452 2453 if (pmx->is_3512) 2454 grp = &gemini_3512_pin_groups[selector]; 2455 if (pmx->is_3516) 2456 grp = &gemini_3516_pin_groups[selector]; 2457 2458 /* First figure out if this group supports configs */ 2459 if (!grp->driving_mask) { 2460 dev_err(pmx->dev, "pin config group \"%s\" does " 2461 "not support drive strength setting\n", 2462 grp->name); 2463 return -EINVAL; 2464 } 2465 2466 for (i = 0; i < num_configs; i++) { 2467 param = pinconf_to_config_param(configs[i]); 2468 arg = pinconf_to_config_argument(configs[i]); 2469 2470 switch (param) { 2471 case PIN_CONFIG_DRIVE_STRENGTH: 2472 switch (arg) { 2473 case 4: 2474 val = 0; 2475 break; 2476 case 8: 2477 val = 1; 2478 break; 2479 case 12: 2480 val = 2; 2481 break; 2482 case 16: 2483 val = 3; 2484 break; 2485 default: 2486 dev_err(pmx->dev, 2487 "invalid drive strength %d mA\n", 2488 arg); 2489 return -ENOTSUPP; 2490 } 2491 val <<= (ffs(grp->driving_mask) - 1); 2492 regmap_update_bits(pmx->map, GLOBAL_IODRIVE, 2493 grp->driving_mask, 2494 val); 2495 dev_dbg(pmx->dev, 2496 "set group %s to %d mA drive strength mask %08x val %08x\n", 2497 grp->name, arg, grp->driving_mask, val); 2498 break; 2499 default: 2500 dev_err(pmx->dev, "invalid config param %04x\n", param); 2501 return -ENOTSUPP; 2502 } 2503 } 2504 2505 return 0; 2506 } 2507 2508 static const struct pinconf_ops gemini_pinconf_ops = { 2509 .pin_config_get = gemini_pinconf_get, 2510 .pin_config_set = gemini_pinconf_set, 2511 .pin_config_group_set = gemini_pinconf_group_set, 2512 .is_generic = true, 2513 }; 2514 2515 static struct pinctrl_desc gemini_pmx_desc = { 2516 .name = DRIVER_NAME, 2517 .pctlops = &gemini_pctrl_ops, 2518 .pmxops = &gemini_pmx_ops, 2519 .confops = &gemini_pinconf_ops, 2520 .owner = THIS_MODULE, 2521 }; 2522 2523 static int gemini_pmx_probe(struct platform_device *pdev) 2524 { 2525 struct gemini_pmx *pmx; 2526 struct regmap *map; 2527 struct device *dev = &pdev->dev; 2528 struct device *parent; 2529 unsigned long tmp; 2530 u32 val; 2531 int ret; 2532 int i; 2533 2534 /* Create state holders etc for this driver */ 2535 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 2536 if (!pmx) 2537 return -ENOMEM; 2538 2539 pmx->dev = &pdev->dev; 2540 parent = dev->parent; 2541 if (!parent) { 2542 dev_err(dev, "no parent to pin controller\n"); 2543 return -ENODEV; 2544 } 2545 map = syscon_node_to_regmap(parent->of_node); 2546 if (IS_ERR(map)) { 2547 dev_err(dev, "no syscon regmap\n"); 2548 return PTR_ERR(map); 2549 } 2550 pmx->map = map; 2551 2552 /* Check that regmap works at first call, then no more */ 2553 ret = regmap_read(map, GLOBAL_WORD_ID, &val); 2554 if (ret) { 2555 dev_err(dev, "cannot access regmap\n"); 2556 return ret; 2557 } 2558 val >>= 8; 2559 val &= 0xffff; 2560 if (val == 0x3512) { 2561 pmx->is_3512 = true; 2562 pmx->confs = gemini_confs_3512; 2563 pmx->nconfs = ARRAY_SIZE(gemini_confs_3512); 2564 gemini_pmx_desc.pins = gemini_3512_pins; 2565 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins); 2566 dev_info(dev, "detected 3512 chip variant\n"); 2567 } else if (val == 0x3516) { 2568 pmx->is_3516 = true; 2569 pmx->confs = gemini_confs_3516; 2570 pmx->nconfs = ARRAY_SIZE(gemini_confs_3516); 2571 gemini_pmx_desc.pins = gemini_3516_pins; 2572 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins); 2573 dev_info(dev, "detected 3516 chip variant\n"); 2574 } else { 2575 dev_err(dev, "unknown chip ID: %04x\n", val); 2576 return -ENODEV; 2577 } 2578 2579 ret = regmap_read(map, GLOBAL_MISC_CTRL, &val); 2580 dev_info(dev, "GLOBAL MISC CTRL at boot: 0x%08x\n", val); 2581 /* Mask off relevant pads */ 2582 val &= PADS_MASK; 2583 /* Invert the meaning of the DRAM+flash pads */ 2584 val ^= 0x0f; 2585 /* Print initial state */ 2586 tmp = val; 2587 for_each_set_bit(i, &tmp, PADS_MAXBIT) { 2588 dev_dbg(dev, "pad group %s %s\n", gemini_padgroups[i], 2589 (val & BIT(i)) ? "enabled" : "disabled"); 2590 } 2591 2592 /* Check if flash pin is set */ 2593 regmap_read(map, GLOBAL_STATUS, &val); 2594 pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN); 2595 dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set"); 2596 2597 pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx); 2598 if (IS_ERR(pmx->pctl)) { 2599 dev_err(dev, "could not register pinmux driver\n"); 2600 return PTR_ERR(pmx->pctl); 2601 } 2602 2603 dev_info(dev, "initialized Gemini pin control driver\n"); 2604 2605 return 0; 2606 } 2607 2608 static const struct of_device_id gemini_pinctrl_match[] = { 2609 { .compatible = "cortina,gemini-pinctrl" }, 2610 {}, 2611 }; 2612 2613 static struct platform_driver gemini_pmx_driver = { 2614 .driver = { 2615 .name = DRIVER_NAME, 2616 .of_match_table = gemini_pinctrl_match, 2617 }, 2618 .probe = gemini_pmx_probe, 2619 }; 2620 2621 static int __init gemini_pmx_init(void) 2622 { 2623 return platform_driver_register(&gemini_pmx_driver); 2624 } 2625 arch_initcall(gemini_pmx_init); 2626