1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2019 Intel Corporation */ 3 4 #include <linux/gpio/driver.h> 5 #include <linux/gpio/generic.h> 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/of_address.h> 9 #include <linux/of_irq.h> 10 #include <linux/pinctrl/pinctrl.h> 11 #include <linux/pinctrl/pinconf.h> 12 #include <linux/pinctrl/pinconf-generic.h> 13 #include <linux/pinctrl/pinmux.h> 14 #include <linux/platform_device.h> 15 #include <linux/property.h> 16 17 #include "core.h" 18 #include "pinconf.h" 19 #include "pinmux.h" 20 #include "pinctrl-equilibrium.h" 21 22 #define PIN_NAME_FMT "io-%d" 23 #define PIN_NAME_LEN 10 24 #define PAD_REG_OFF 0x100 25 26 static void eqbr_gpio_disable_irq(struct irq_data *d) 27 { 28 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 29 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); 30 unsigned int offset = irqd_to_hwirq(d); 31 unsigned long flags; 32 33 raw_spin_lock_irqsave(&gctrl->lock, flags); 34 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); 35 raw_spin_unlock_irqrestore(&gctrl->lock, flags); 36 gpiochip_disable_irq(gc, offset); 37 } 38 39 static void eqbr_gpio_enable_irq(struct irq_data *d) 40 { 41 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 42 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); 43 unsigned int offset = irqd_to_hwirq(d); 44 unsigned long flags; 45 46 gc->direction_input(gc, offset); 47 gpiochip_enable_irq(gc, offset); 48 raw_spin_lock_irqsave(&gctrl->lock, flags); 49 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); 50 raw_spin_unlock_irqrestore(&gctrl->lock, flags); 51 } 52 53 static void eqbr_gpio_ack_irq(struct irq_data *d) 54 { 55 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 56 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); 57 unsigned int offset = irqd_to_hwirq(d); 58 unsigned long flags; 59 60 raw_spin_lock_irqsave(&gctrl->lock, flags); 61 writel(BIT(offset), gctrl->membase + GPIO_IRNCR); 62 raw_spin_unlock_irqrestore(&gctrl->lock, flags); 63 } 64 65 static void eqbr_gpio_mask_ack_irq(struct irq_data *d) 66 { 67 eqbr_gpio_disable_irq(d); 68 eqbr_gpio_ack_irq(d); 69 } 70 71 static inline void eqbr_cfg_bit(void __iomem *addr, 72 unsigned int offset, unsigned int set) 73 { 74 if (set) 75 writel(readl(addr) | BIT(offset), addr); 76 else 77 writel(readl(addr) & ~BIT(offset), addr); 78 } 79 80 static int eqbr_irq_type_cfg(struct gpio_irq_type *type, 81 struct eqbr_gpio_ctrl *gctrl, 82 unsigned int offset) 83 { 84 unsigned long flags; 85 86 raw_spin_lock_irqsave(&gctrl->lock, flags); 87 eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type); 88 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type); 89 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type); 90 raw_spin_unlock_irqrestore(&gctrl->lock, flags); 91 92 return 0; 93 } 94 95 static int eqbr_gpio_set_irq_type(struct irq_data *d, unsigned int type) 96 { 97 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 98 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); 99 unsigned int offset = irqd_to_hwirq(d); 100 struct gpio_irq_type it; 101 102 memset(&it, 0, sizeof(it)); 103 104 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE) 105 return 0; 106 107 switch (type) { 108 case IRQ_TYPE_EDGE_RISING: 109 it.trig_type = GPIO_EDGE_TRIG; 110 it.edge_type = GPIO_SINGLE_EDGE; 111 it.logic_type = GPIO_POSITIVE_TRIG; 112 break; 113 114 case IRQ_TYPE_EDGE_FALLING: 115 it.trig_type = GPIO_EDGE_TRIG; 116 it.edge_type = GPIO_SINGLE_EDGE; 117 it.logic_type = GPIO_NEGATIVE_TRIG; 118 break; 119 120 case IRQ_TYPE_EDGE_BOTH: 121 it.trig_type = GPIO_EDGE_TRIG; 122 it.edge_type = GPIO_BOTH_EDGE; 123 it.logic_type = GPIO_POSITIVE_TRIG; 124 break; 125 126 case IRQ_TYPE_LEVEL_HIGH: 127 it.trig_type = GPIO_LEVEL_TRIG; 128 it.edge_type = GPIO_SINGLE_EDGE; 129 it.logic_type = GPIO_POSITIVE_TRIG; 130 break; 131 132 case IRQ_TYPE_LEVEL_LOW: 133 it.trig_type = GPIO_LEVEL_TRIG; 134 it.edge_type = GPIO_SINGLE_EDGE; 135 it.logic_type = GPIO_NEGATIVE_TRIG; 136 break; 137 138 default: 139 return -EINVAL; 140 } 141 142 eqbr_irq_type_cfg(&it, gctrl, offset); 143 if (it.trig_type == GPIO_EDGE_TRIG) 144 irq_set_handler_locked(d, handle_edge_irq); 145 else 146 irq_set_handler_locked(d, handle_level_irq); 147 148 return 0; 149 } 150 151 static void eqbr_irq_handler(struct irq_desc *desc) 152 { 153 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 154 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); 155 struct irq_chip *ic = irq_desc_get_chip(desc); 156 unsigned long pins, offset; 157 158 chained_irq_enter(ic, desc); 159 pins = readl(gctrl->membase + GPIO_IRNCR); 160 161 for_each_set_bit(offset, &pins, gc->ngpio) 162 generic_handle_domain_irq(gc->irq.domain, offset); 163 164 chained_irq_exit(ic, desc); 165 } 166 167 static const struct irq_chip eqbr_irq_chip = { 168 .name = "gpio_irq", 169 .irq_mask = eqbr_gpio_disable_irq, 170 .irq_unmask = eqbr_gpio_enable_irq, 171 .irq_ack = eqbr_gpio_ack_irq, 172 .irq_mask_ack = eqbr_gpio_mask_ack_irq, 173 .irq_set_type = eqbr_gpio_set_irq_type, 174 .flags = IRQCHIP_IMMUTABLE, 175 GPIOCHIP_IRQ_RESOURCE_HELPERS, 176 }; 177 178 static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl) 179 { 180 struct gpio_irq_chip *girq; 181 struct gpio_chip *gc; 182 183 gc = &gctrl->chip.gc; 184 gc->label = gctrl->name; 185 gc->fwnode = gctrl->fwnode; 186 gc->request = gpiochip_generic_request; 187 gc->free = gpiochip_generic_free; 188 189 if (!fwnode_property_read_bool(gctrl->fwnode, "interrupt-controller")) { 190 dev_dbg(dev, "gc %s: doesn't act as interrupt controller!\n", 191 gctrl->name); 192 return 0; 193 } 194 195 girq = &gctrl->chip.gc.irq; 196 gpio_irq_chip_set_chip(girq, &eqbr_irq_chip); 197 girq->parent_handler = eqbr_irq_handler; 198 girq->num_parents = 1; 199 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL); 200 if (!girq->parents) 201 return -ENOMEM; 202 203 girq->default_type = IRQ_TYPE_NONE; 204 girq->handler = handle_bad_irq; 205 girq->parents[0] = gctrl->virq; 206 207 return 0; 208 } 209 210 static int gpiolib_reg(struct eqbr_pinctrl_drv_data *drvdata) 211 { 212 struct gpio_generic_chip_config config; 213 struct device *dev = drvdata->dev; 214 struct eqbr_gpio_ctrl *gctrl; 215 struct device_node *np; 216 struct resource res; 217 int i, ret; 218 219 for (i = 0; i < drvdata->nr_gpio_ctrls; i++) { 220 gctrl = drvdata->gpio_ctrls + i; 221 np = to_of_node(gctrl->fwnode); 222 223 gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i); 224 if (!gctrl->name) 225 return -ENOMEM; 226 227 if (of_address_to_resource(np, 0, &res)) { 228 dev_err(dev, "Failed to get GPIO register address\n"); 229 return -ENXIO; 230 } 231 232 gctrl->membase = devm_ioremap_resource(dev, &res); 233 if (IS_ERR(gctrl->membase)) 234 return PTR_ERR(gctrl->membase); 235 236 gctrl->virq = irq_of_parse_and_map(np, 0); 237 if (!gctrl->virq) { 238 dev_err(dev, "%s: failed to parse and map irq\n", 239 gctrl->name); 240 return -ENXIO; 241 } 242 raw_spin_lock_init(&gctrl->lock); 243 244 config = (struct gpio_generic_chip_config) { 245 .dev = dev, 246 .sz = gctrl->bank->nr_pins / 8, 247 .dat = gctrl->membase + GPIO_IN, 248 .set = gctrl->membase + GPIO_OUTSET, 249 .clr = gctrl->membase + GPIO_OUTCLR, 250 .dirout = gctrl->membase + GPIO_DIR, 251 }; 252 253 ret = gpio_generic_chip_init(&gctrl->chip, &config); 254 if (ret) { 255 dev_err(dev, "unable to init generic GPIO\n"); 256 return ret; 257 } 258 259 ret = gpiochip_setup(dev, gctrl); 260 if (ret) 261 return ret; 262 263 ret = devm_gpiochip_add_data(dev, &gctrl->chip.gc, gctrl); 264 if (ret) 265 return ret; 266 } 267 268 return 0; 269 } 270 271 static inline struct eqbr_pin_bank 272 *find_pinbank_via_pin(struct eqbr_pinctrl_drv_data *pctl, unsigned int pin) 273 { 274 struct eqbr_pin_bank *bank; 275 int i; 276 277 for (i = 0; i < pctl->nr_banks; i++) { 278 bank = &pctl->pin_banks[i]; 279 if (pin >= bank->pin_base && 280 (pin - bank->pin_base) < bank->nr_pins) 281 return bank; 282 } 283 284 return NULL; 285 } 286 287 static const struct pinctrl_ops eqbr_pctl_ops = { 288 .get_groups_count = pinctrl_generic_get_group_count, 289 .get_group_name = pinctrl_generic_get_group_name, 290 .get_group_pins = pinctrl_generic_get_group_pins, 291 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 292 .dt_free_map = pinconf_generic_dt_free_map, 293 }; 294 295 static int eqbr_set_pin_mux(struct eqbr_pinctrl_drv_data *pctl, 296 unsigned int pmx, unsigned int pin) 297 { 298 struct eqbr_pin_bank *bank; 299 unsigned long flags; 300 unsigned int offset; 301 void __iomem *mem; 302 303 bank = find_pinbank_via_pin(pctl, pin); 304 if (!bank) { 305 dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin); 306 return -ENODEV; 307 } 308 mem = bank->membase; 309 offset = pin - bank->pin_base; 310 311 if (!(bank->aval_pinmap & BIT(offset))) { 312 dev_err(pctl->dev, 313 "PIN: %u is not valid, pinbase: %u, bitmap: %u\n", 314 pin, bank->pin_base, bank->aval_pinmap); 315 return -ENODEV; 316 } 317 318 raw_spin_lock_irqsave(&pctl->lock, flags); 319 writel(pmx, mem + (offset * 4)); 320 raw_spin_unlock_irqrestore(&pctl->lock, flags); 321 return 0; 322 } 323 324 static int eqbr_pinmux_set_mux(struct pinctrl_dev *pctldev, 325 unsigned int selector, unsigned int group) 326 { 327 struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev); 328 const struct function_desc *func; 329 struct group_desc *grp; 330 unsigned int *pinmux; 331 int i; 332 333 func = pinmux_generic_get_function(pctldev, selector); 334 if (!func) 335 return -EINVAL; 336 337 grp = pinctrl_generic_get_group(pctldev, group); 338 if (!grp) 339 return -EINVAL; 340 341 pinmux = grp->data; 342 for (i = 0; i < grp->grp.npins; i++) 343 eqbr_set_pin_mux(pctl, pinmux[i], grp->grp.pins[i]); 344 345 return 0; 346 } 347 348 static int eqbr_pinmux_gpio_request(struct pinctrl_dev *pctldev, 349 struct pinctrl_gpio_range *range, 350 unsigned int pin) 351 { 352 struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev); 353 354 return eqbr_set_pin_mux(pctl, EQBR_GPIO_MODE, pin); 355 } 356 357 static const struct pinmux_ops eqbr_pinmux_ops = { 358 .get_functions_count = pinmux_generic_get_function_count, 359 .get_function_name = pinmux_generic_get_function_name, 360 .get_function_groups = pinmux_generic_get_function_groups, 361 .set_mux = eqbr_pinmux_set_mux, 362 .gpio_request_enable = eqbr_pinmux_gpio_request, 363 .strict = true, 364 }; 365 366 static int get_drv_cur(void __iomem *mem, unsigned int offset) 367 { 368 unsigned int idx = offset / DRV_CUR_PINS; /* 0-15, 16-31 per register*/ 369 unsigned int pin_offset = offset % DRV_CUR_PINS; 370 371 return PARSE_DRV_CURRENT(readl(mem + REG_DRCC(idx)), pin_offset); 372 } 373 374 static struct eqbr_gpio_ctrl 375 *get_gpio_ctrls_via_bank(struct eqbr_pinctrl_drv_data *pctl, 376 struct eqbr_pin_bank *bank) 377 { 378 int i; 379 380 for (i = 0; i < pctl->nr_gpio_ctrls; i++) { 381 if (pctl->gpio_ctrls[i].bank == bank) 382 return &pctl->gpio_ctrls[i]; 383 } 384 385 return NULL; 386 } 387 388 static int eqbr_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 389 unsigned long *config) 390 { 391 struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev); 392 enum pin_config_param param = pinconf_to_config_param(*config); 393 struct eqbr_gpio_ctrl *gctrl; 394 struct eqbr_pin_bank *bank; 395 unsigned long flags; 396 unsigned int offset; 397 void __iomem *mem; 398 u32 val; 399 400 bank = find_pinbank_via_pin(pctl, pin); 401 if (!bank) { 402 dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin); 403 return -ENODEV; 404 } 405 mem = bank->membase; 406 offset = pin - bank->pin_base; 407 408 if (!(bank->aval_pinmap & BIT(offset))) { 409 dev_err(pctl->dev, 410 "PIN: %u is not valid, pinbase: %u, bitmap: %u\n", 411 pin, bank->pin_base, bank->aval_pinmap); 412 return -ENODEV; 413 } 414 415 raw_spin_lock_irqsave(&pctl->lock, flags); 416 switch (param) { 417 case PIN_CONFIG_BIAS_PULL_UP: 418 val = !!(readl(mem + REG_PUEN) & BIT(offset)); 419 break; 420 case PIN_CONFIG_BIAS_PULL_DOWN: 421 val = !!(readl(mem + REG_PDEN) & BIT(offset)); 422 break; 423 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 424 val = !!(readl(mem + REG_OD) & BIT(offset)); 425 break; 426 case PIN_CONFIG_DRIVE_STRENGTH: 427 val = get_drv_cur(mem, offset); 428 break; 429 case PIN_CONFIG_SLEW_RATE: 430 val = !!(readl(mem + REG_SRC) & BIT(offset)); 431 break; 432 case PIN_CONFIG_OUTPUT_ENABLE: 433 gctrl = get_gpio_ctrls_via_bank(pctl, bank); 434 if (!gctrl) { 435 dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n", 436 bank->pin_base, pin); 437 raw_spin_unlock_irqrestore(&pctl->lock, flags); 438 return -ENODEV; 439 } 440 val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset)); 441 break; 442 default: 443 raw_spin_unlock_irqrestore(&pctl->lock, flags); 444 return -ENOTSUPP; 445 } 446 raw_spin_unlock_irqrestore(&pctl->lock, flags); 447 *config = pinconf_to_config_packed(param, val); 448 449 return 0; 450 } 451 452 static int eqbr_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 453 unsigned long *configs, unsigned int num_configs) 454 { 455 struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev); 456 struct eqbr_gpio_ctrl *gctrl; 457 enum pin_config_param param; 458 struct eqbr_pin_bank *bank; 459 unsigned int val, offset; 460 struct gpio_chip *gc; 461 unsigned long flags; 462 void __iomem *mem; 463 u32 regval, mask; 464 int i; 465 466 for (i = 0; i < num_configs; i++) { 467 param = pinconf_to_config_param(configs[i]); 468 val = pinconf_to_config_argument(configs[i]); 469 470 bank = find_pinbank_via_pin(pctl, pin); 471 if (!bank) { 472 dev_err(pctl->dev, 473 "Couldn't find pin bank for pin %u\n", pin); 474 return -ENODEV; 475 } 476 mem = bank->membase; 477 offset = pin - bank->pin_base; 478 479 switch (param) { 480 case PIN_CONFIG_BIAS_PULL_UP: 481 mem += REG_PUEN; 482 mask = BIT(offset); 483 break; 484 case PIN_CONFIG_BIAS_PULL_DOWN: 485 mem += REG_PDEN; 486 mask = BIT(offset); 487 break; 488 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 489 mem += REG_OD; 490 mask = BIT(offset); 491 break; 492 case PIN_CONFIG_DRIVE_STRENGTH: 493 mem += REG_DRCC(offset / DRV_CUR_PINS); 494 offset = (offset % DRV_CUR_PINS) * 2; 495 mask = GENMASK(1, 0) << offset; 496 break; 497 case PIN_CONFIG_SLEW_RATE: 498 mem += REG_SRC; 499 mask = BIT(offset); 500 break; 501 case PIN_CONFIG_OUTPUT_ENABLE: 502 gctrl = get_gpio_ctrls_via_bank(pctl, bank); 503 if (!gctrl) { 504 dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n", 505 bank->pin_base, pin); 506 return -ENODEV; 507 } 508 gc = &gctrl->chip.gc; 509 gc->direction_output(gc, offset, 0); 510 continue; 511 default: 512 return -ENOTSUPP; 513 } 514 515 raw_spin_lock_irqsave(&pctl->lock, flags); 516 regval = readl(mem); 517 regval = (regval & ~mask) | ((val << offset) & mask); 518 writel(regval, mem); 519 raw_spin_unlock_irqrestore(&pctl->lock, flags); 520 } 521 522 return 0; 523 } 524 525 static int eqbr_pinconf_group_get(struct pinctrl_dev *pctldev, 526 unsigned int group, unsigned long *config) 527 { 528 unsigned int i, npins, old = 0; 529 const unsigned int *pins; 530 int ret; 531 532 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 533 if (ret) 534 return ret; 535 536 for (i = 0; i < npins; i++) { 537 if (eqbr_pinconf_get(pctldev, pins[i], config)) 538 return -ENOTSUPP; 539 540 if (i && old != *config) 541 return -ENOTSUPP; 542 543 old = *config; 544 } 545 return 0; 546 } 547 548 static int eqbr_pinconf_group_set(struct pinctrl_dev *pctldev, 549 unsigned int group, unsigned long *configs, 550 unsigned int num_configs) 551 { 552 const unsigned int *pins; 553 unsigned int i, npins; 554 int ret; 555 556 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 557 if (ret) 558 return ret; 559 560 for (i = 0; i < npins; i++) { 561 ret = eqbr_pinconf_set(pctldev, pins[i], configs, num_configs); 562 if (ret) 563 return ret; 564 } 565 return 0; 566 } 567 568 static const struct pinconf_ops eqbr_pinconf_ops = { 569 .is_generic = true, 570 .pin_config_get = eqbr_pinconf_get, 571 .pin_config_set = eqbr_pinconf_set, 572 .pin_config_group_get = eqbr_pinconf_group_get, 573 .pin_config_group_set = eqbr_pinconf_group_set, 574 .pin_config_config_dbg_show = pinconf_generic_dump_config, 575 }; 576 577 static bool is_func_exist(struct pinfunction *funcs, const char *name, 578 unsigned int nr_funcs, unsigned int *idx) 579 { 580 int i; 581 582 if (!funcs) 583 return false; 584 585 for (i = 0; i < nr_funcs; i++) { 586 if (funcs[i].name && !strcmp(funcs[i].name, name)) { 587 *idx = i; 588 return true; 589 } 590 } 591 592 return false; 593 } 594 595 static int funcs_utils(struct device *dev, struct pinfunction *funcs, 596 unsigned int *nr_funcs, funcs_util_ops op) 597 { 598 struct device_node *node = dev->of_node; 599 struct property *prop; 600 const char *fn_name; 601 const char **groups; 602 unsigned int fid; 603 int i, j; 604 605 i = 0; 606 for_each_child_of_node_scoped(node, np) { 607 prop = of_find_property(np, "groups", NULL); 608 if (!prop) 609 continue; 610 611 if (of_property_read_string(np, "function", &fn_name)) { 612 /* some groups may not have function, it's OK */ 613 dev_dbg(dev, "Group %s: not function binded!\n", 614 (char *)prop->value); 615 continue; 616 } 617 618 switch (op) { 619 case OP_COUNT_NR_FUNCS: 620 if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid)) 621 *nr_funcs = *nr_funcs + 1; 622 break; 623 624 case OP_ADD_FUNCS: 625 if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid)) 626 funcs[i].name = fn_name; 627 break; 628 629 case OP_COUNT_NR_FUNC_GRPS: 630 if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) 631 funcs[fid].ngroups++; 632 break; 633 634 case OP_ADD_FUNC_GRPS: 635 if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) { 636 groups = (const char **)funcs[fid].groups; 637 for (j = 0; j < funcs[fid].ngroups; j++) 638 if (!groups[j]) 639 break; 640 groups[j] = prop->value; 641 } 642 break; 643 644 default: 645 return -EINVAL; 646 } 647 i++; 648 } 649 650 return 0; 651 } 652 653 static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata) 654 { 655 struct device *dev = drvdata->dev; 656 struct pinfunction *funcs = NULL; 657 unsigned int nr_funcs = 0; 658 int i, ret; 659 660 ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNCS); 661 if (ret) 662 return ret; 663 664 funcs = devm_kcalloc(dev, nr_funcs, sizeof(*funcs), GFP_KERNEL); 665 if (!funcs) 666 return -ENOMEM; 667 668 ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNCS); 669 if (ret) 670 return ret; 671 672 ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNC_GRPS); 673 if (ret) 674 return ret; 675 676 for (i = 0; i < nr_funcs; i++) { 677 if (!funcs[i].ngroups) 678 continue; 679 funcs[i].groups = devm_kcalloc(dev, funcs[i].ngroups, 680 sizeof(*(funcs[i].groups)), 681 GFP_KERNEL); 682 if (!funcs[i].groups) 683 return -ENOMEM; 684 } 685 686 ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNC_GRPS); 687 if (ret) 688 return ret; 689 690 for (i = 0; i < nr_funcs; i++) { 691 692 /* Ignore the same function with multiple groups */ 693 if (funcs[i].name == NULL) 694 continue; 695 696 ret = pinmux_generic_add_pinfunction(drvdata->pctl_dev, 697 &funcs[i], drvdata); 698 if (ret < 0) { 699 dev_err(dev, "Failed to register function %s\n", 700 funcs[i].name); 701 return ret; 702 } 703 } 704 705 return 0; 706 } 707 708 static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata) 709 { 710 struct device *dev = drvdata->dev; 711 struct device_node *node = dev->of_node; 712 unsigned int *pins, *pinmux, pin_id, pinmux_id; 713 struct pingroup group, *grp = &group; 714 struct property *prop; 715 int j, err; 716 717 for_each_child_of_node_scoped(node, np) { 718 prop = of_find_property(np, "groups", NULL); 719 if (!prop) 720 continue; 721 722 err = of_property_count_u32_elems(np, "pins"); 723 if (err < 0) { 724 dev_err(dev, "No pins in the group: %s\n", prop->name); 725 return err; 726 } 727 grp->npins = err; 728 grp->name = prop->value; 729 pins = devm_kcalloc(dev, grp->npins, sizeof(*pins), GFP_KERNEL); 730 if (!pins) 731 return -ENOMEM; 732 733 grp->pins = pins; 734 735 pinmux = devm_kcalloc(dev, grp->npins, sizeof(*pinmux), GFP_KERNEL); 736 if (!pinmux) 737 return -ENOMEM; 738 739 for (j = 0; j < grp->npins; j++) { 740 if (of_property_read_u32_index(np, "pins", j, &pin_id)) { 741 dev_err(dev, "Group %s: Read intel pins id failed\n", 742 grp->name); 743 return -EINVAL; 744 } 745 if (pin_id >= drvdata->pctl_desc.npins) { 746 dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n", 747 grp->name, j, pin_id); 748 return -EINVAL; 749 } 750 pins[j] = pin_id; 751 if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) { 752 dev_err(dev, "Group %s: Read intel pinmux id failed\n", 753 grp->name); 754 return -EINVAL; 755 } 756 pinmux[j] = pinmux_id; 757 } 758 759 err = pinctrl_generic_add_group(drvdata->pctl_dev, 760 grp->name, grp->pins, grp->npins, 761 pinmux); 762 if (err < 0) { 763 dev_err(dev, "Failed to register group %s\n", grp->name); 764 return err; 765 } 766 memset(&group, 0, sizeof(group)); 767 pinmux = NULL; 768 } 769 770 return 0; 771 } 772 773 static int pinctrl_reg(struct eqbr_pinctrl_drv_data *drvdata) 774 { 775 struct pinctrl_desc *pctl_desc; 776 struct pinctrl_pin_desc *pdesc; 777 struct device *dev; 778 unsigned int nr_pins; 779 char *pin_names; 780 int i, ret; 781 782 dev = drvdata->dev; 783 pctl_desc = &drvdata->pctl_desc; 784 pctl_desc->name = "eqbr-pinctrl"; 785 pctl_desc->owner = THIS_MODULE; 786 pctl_desc->pctlops = &eqbr_pctl_ops; 787 pctl_desc->pmxops = &eqbr_pinmux_ops; 788 pctl_desc->confops = &eqbr_pinconf_ops; 789 raw_spin_lock_init(&drvdata->lock); 790 791 for (i = 0, nr_pins = 0; i < drvdata->nr_banks; i++) 792 nr_pins += drvdata->pin_banks[i].nr_pins; 793 794 pdesc = devm_kcalloc(dev, nr_pins, sizeof(*pdesc), GFP_KERNEL); 795 if (!pdesc) 796 return -ENOMEM; 797 pin_names = devm_kcalloc(dev, nr_pins, PIN_NAME_LEN, GFP_KERNEL); 798 if (!pin_names) 799 return -ENOMEM; 800 801 for (i = 0; i < nr_pins; i++) { 802 sprintf(pin_names, PIN_NAME_FMT, i); 803 pdesc[i].number = i; 804 pdesc[i].name = pin_names; 805 pin_names += PIN_NAME_LEN; 806 } 807 pctl_desc->pins = pdesc; 808 pctl_desc->npins = nr_pins; 809 dev_dbg(dev, "pinctrl total pin number: %u\n", nr_pins); 810 811 ret = devm_pinctrl_register_and_init(dev, pctl_desc, drvdata, 812 &drvdata->pctl_dev); 813 if (ret) 814 return ret; 815 816 ret = eqbr_build_groups(drvdata); 817 if (ret) { 818 dev_err(dev, "Failed to build groups\n"); 819 return ret; 820 } 821 822 ret = eqbr_build_functions(drvdata); 823 if (ret) { 824 dev_err(dev, "Failed to build functions\n"); 825 return ret; 826 } 827 828 return pinctrl_enable(drvdata->pctl_dev); 829 } 830 831 static int pinbank_init(struct device_node *np, 832 struct eqbr_pinctrl_drv_data *drvdata, 833 struct eqbr_pin_bank *bank, unsigned int id) 834 { 835 struct device *dev = drvdata->dev; 836 struct of_phandle_args spec; 837 int ret; 838 839 bank->membase = drvdata->membase + id * PAD_REG_OFF; 840 841 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &spec); 842 if (ret) { 843 dev_err(dev, "gpio-range not available!\n"); 844 return ret; 845 } 846 847 bank->pin_base = spec.args[1]; 848 bank->nr_pins = spec.args[2]; 849 850 bank->aval_pinmap = readl(bank->membase + REG_AVAIL); 851 bank->id = id; 852 853 dev_dbg(dev, "pinbank id: %d, reg: %px, pinbase: %u, pin number: %u, pinmap: 0x%x\n", 854 id, bank->membase, bank->pin_base, 855 bank->nr_pins, bank->aval_pinmap); 856 857 return ret; 858 } 859 860 static int pinbank_probe(struct eqbr_pinctrl_drv_data *drvdata) 861 { 862 struct device *dev = drvdata->dev; 863 struct device_node *np_gpio; 864 struct eqbr_gpio_ctrl *gctrls; 865 struct eqbr_pin_bank *banks; 866 int i, nr_gpio; 867 868 /* Count gpio bank number */ 869 nr_gpio = 0; 870 for_each_node_by_name(np_gpio, "gpio") { 871 if (of_device_is_available(np_gpio)) 872 nr_gpio++; 873 } 874 875 if (!nr_gpio) { 876 dev_err(dev, "NO pin bank available!\n"); 877 return -ENODEV; 878 } 879 880 /* Count pin bank number and gpio controller number */ 881 banks = devm_kcalloc(dev, nr_gpio, sizeof(*banks), GFP_KERNEL); 882 if (!banks) 883 return -ENOMEM; 884 885 gctrls = devm_kcalloc(dev, nr_gpio, sizeof(*gctrls), GFP_KERNEL); 886 if (!gctrls) 887 return -ENOMEM; 888 889 dev_dbg(dev, "found %d gpio controller!\n", nr_gpio); 890 891 /* Initialize Pin bank */ 892 i = 0; 893 for_each_node_by_name(np_gpio, "gpio") { 894 if (!of_device_is_available(np_gpio)) 895 continue; 896 897 pinbank_init(np_gpio, drvdata, banks + i, i); 898 899 gctrls[i].fwnode = of_fwnode_handle(np_gpio); 900 gctrls[i].bank = banks + i; 901 i++; 902 } 903 904 drvdata->pin_banks = banks; 905 drvdata->nr_banks = nr_gpio; 906 drvdata->gpio_ctrls = gctrls; 907 drvdata->nr_gpio_ctrls = nr_gpio; 908 909 return 0; 910 } 911 912 static int eqbr_pinctrl_probe(struct platform_device *pdev) 913 { 914 struct eqbr_pinctrl_drv_data *drvdata; 915 struct device *dev = &pdev->dev; 916 int ret; 917 918 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 919 if (!drvdata) 920 return -ENOMEM; 921 922 drvdata->dev = dev; 923 924 drvdata->membase = devm_platform_ioremap_resource(pdev, 0); 925 if (IS_ERR(drvdata->membase)) 926 return PTR_ERR(drvdata->membase); 927 928 ret = pinbank_probe(drvdata); 929 if (ret) 930 return ret; 931 932 ret = pinctrl_reg(drvdata); 933 if (ret) 934 return ret; 935 936 ret = gpiolib_reg(drvdata); 937 if (ret) 938 return ret; 939 940 platform_set_drvdata(pdev, drvdata); 941 return 0; 942 } 943 944 static const struct of_device_id eqbr_pinctrl_dt_match[] = { 945 { .compatible = "intel,lgm-io" }, 946 {} 947 }; 948 MODULE_DEVICE_TABLE(of, eqbr_pinctrl_dt_match); 949 950 static struct platform_driver eqbr_pinctrl_driver = { 951 .probe = eqbr_pinctrl_probe, 952 .driver = { 953 .name = "eqbr-pinctrl", 954 .of_match_table = eqbr_pinctrl_dt_match, 955 }, 956 }; 957 958 module_platform_driver(eqbr_pinctrl_driver); 959 960 MODULE_AUTHOR("Zhu Yixin <yixin.zhu@intel.com>, Rahul Tanwar <rahul.tanwar@intel.com>"); 961 MODULE_DESCRIPTION("Pinctrl Driver for LGM SoC (Equilibrium)"); 962 MODULE_LICENSE("GPL v2"); 963