1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ESWIN Pinctrl Controller Platform Device Driver
4 *
5 * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
6 *
7 * Authors: Samuel Holland <samuel.holland@sifive.com>
8 * Yulin Lu <luyulin@eswincomputing.com>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/seq_file.h>
18 #include <linux/regulator/consumer.h>
19
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24
25 #include "core.h"
26 #include "pinmux.h"
27 #include "pinconf.h"
28
29 #define EIC7700_PIN_REG(i) (4 * (i))
30 #define EIC7700_IE BIT(0)
31 #define EIC7700_PU BIT(1)
32 #define EIC7700_PD BIT(2)
33 #define EIC7700_DS GENMASK(6, 3)
34 #define EIC7700_ST BIT(7)
35 #define EIC7700_FUNC_SEL GENMASK(18, 16)
36
37 #define EIC7700_BIAS (EIC7700_PD | EIC7700_PU)
38 #define EIC7700_PINCONF GENMASK(7, 0)
39
40 #define EIC7700_RGMII0_SEL_MODE (0x310 - 0x80)
41 #define EIC7700_RGMII1_SEL_MODE (0x314 - 0x80)
42 #define EIC7700_MS GENMASK(1, 0)
43 #define EIC7700_MS_3V3 0x0
44 #define EIC7700_MS_1V8 0x3
45
46 #define EIC7700_FUNCTIONS_PER_PIN 8
47
48 struct eic7700_pin {
49 u8 functions[EIC7700_FUNCTIONS_PER_PIN];
50 };
51
52 struct eic7700_pinctrl {
53 void __iomem *base;
54 struct pinctrl_desc desc;
55 unsigned int functions_count;
56 struct pinfunction functions[] __counted_by(functions_count);
57 };
58
59 enum {
60 F_DISABLED,
61 F_BOOT_SEL,
62 F_CHIP_MODE,
63 F_EMMC,
64 F_FAN_TACH,
65 F_GPIO,
66 F_HDMI,
67 F_I2C,
68 F_I2S,
69 F_JTAG,
70 F_DDR_REF_CLK_SEL,
71 F_LPDDR_REF_CLK,
72 F_MIPI_CSI,
73 F_OSC,
74 F_PCIE,
75 F_PWM,
76 F_RGMII,
77 F_RESET,
78 F_SATA,
79 F_SDIO,
80 F_SPI,
81 F_S_MODE,
82 F_UART,
83 F_USB,
84 EIC7700_FUNCTIONS_COUNT
85 };
86
87 static const char *const eic7700_functions[EIC7700_FUNCTIONS_COUNT] = {
88 [F_DISABLED] = "disabled",
89 [F_BOOT_SEL] = "boot_sel",
90 [F_CHIP_MODE] = "chip_mode",
91 [F_EMMC] = "emmc",
92 [F_FAN_TACH] = "fan_tach",
93 [F_GPIO] = "gpio",
94 [F_HDMI] = "hdmi",
95 [F_I2C] = "i2c",
96 [F_I2S] = "i2s",
97 [F_JTAG] = "jtag",
98 [F_DDR_REF_CLK_SEL] = "ddr_ref_clk_sel",
99 [F_LPDDR_REF_CLK] = "lpddr_ref_clk",
100 [F_MIPI_CSI] = "mipi_csi",
101 [F_OSC] = "osc",
102 [F_PCIE] = "pcie",
103 [F_PWM] = "pwm",
104 [F_RGMII] = "rgmii",
105 [F_RESET] = "reset",
106 [F_SATA] = "sata",
107 [F_SDIO] = "sdio",
108 [F_SPI] = "spi",
109 [F_S_MODE] = "s_mode",
110 [F_UART] = "uart",
111 [F_USB] = "usb",
112 };
113
114 #define EIC7700_PIN(_number, _name, ...) \
115 { \
116 .number = _number, \
117 .name = _name, \
118 .drv_data = (void *)&(struct eic7700_pin) { { __VA_ARGS__ } } \
119 }
120
121 static const struct pinctrl_pin_desc eic7700_pins[] = {
122 EIC7700_PIN(0, "chip_mode", [0] = F_CHIP_MODE),
123 EIC7700_PIN(1, "mode_set0", [0] = F_SDIO, [2] = F_GPIO),
124 EIC7700_PIN(2, "mode_set1", [0] = F_SDIO, [2] = F_GPIO),
125 EIC7700_PIN(3, "mode_set2", [0] = F_SDIO, [2] = F_GPIO),
126 EIC7700_PIN(4, "mode_set3", [0] = F_SDIO, [2] = F_GPIO),
127 EIC7700_PIN(5, "xin", [0] = F_OSC),
128 EIC7700_PIN(6, "rtc_xin", [0] = F_DISABLED),
129 EIC7700_PIN(7, "rst_out_n", [0] = F_RESET),
130 EIC7700_PIN(8, "key_reset_n", [0] = F_RESET),
131 EIC7700_PIN(9, "rst_in_n", [0] = F_DISABLED),
132 EIC7700_PIN(10, "por_in_n", [0] = F_DISABLED),
133 EIC7700_PIN(11, "por_out_n", [0] = F_DISABLED),
134 EIC7700_PIN(12, "gpio0", [0] = F_GPIO),
135 EIC7700_PIN(13, "por_sel", [0] = F_RESET),
136 EIC7700_PIN(14, "jtag0_tck", [0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
137 EIC7700_PIN(15, "jtag0_tms", [0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
138 EIC7700_PIN(16, "jtag0_tdi", [0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
139 EIC7700_PIN(17, "jtag0_tdo", [0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
140 EIC7700_PIN(18, "gpio5", [0] = F_GPIO, [1] = F_SPI),
141 EIC7700_PIN(19, "spi2_cs0_n", [0] = F_SPI, [2] = F_GPIO),
142 EIC7700_PIN(20, "jtag1_tck", [0] = F_JTAG, [2] = F_GPIO),
143 EIC7700_PIN(21, "jtag1_tms", [0] = F_JTAG, [2] = F_GPIO),
144 EIC7700_PIN(22, "jtag1_tdi", [0] = F_JTAG, [2] = F_GPIO),
145 EIC7700_PIN(23, "jtag1_tdo", [0] = F_JTAG, [2] = F_GPIO),
146 EIC7700_PIN(24, "gpio11", [0] = F_GPIO),
147 EIC7700_PIN(25, "spi2_cs1_n", [0] = F_SPI, [2] = F_GPIO),
148 EIC7700_PIN(26, "pcie_clkreq_n", [0] = F_PCIE),
149 EIC7700_PIN(27, "pcie_wake_n", [0] = F_PCIE),
150 EIC7700_PIN(28, "pcie_perst_n", [0] = F_PCIE),
151 EIC7700_PIN(29, "hdmi_scl", [0] = F_HDMI),
152 EIC7700_PIN(30, "hdmi_sda", [0] = F_HDMI),
153 EIC7700_PIN(31, "hdmi_cec", [0] = F_HDMI),
154 EIC7700_PIN(32, "jtag2_trst", [0] = F_JTAG, [2] = F_GPIO),
155 EIC7700_PIN(33, "rgmii0_clk_125", [0] = F_RGMII),
156 EIC7700_PIN(34, "rgmii0_txen", [0] = F_RGMII),
157 EIC7700_PIN(35, "rgmii0_txclk", [0] = F_RGMII),
158 EIC7700_PIN(36, "rgmii0_txd0", [0] = F_RGMII),
159 EIC7700_PIN(37, "rgmii0_txd1", [0] = F_RGMII),
160 EIC7700_PIN(38, "rgmii0_txd2", [0] = F_RGMII),
161 EIC7700_PIN(39, "rgmii0_txd3", [0] = F_RGMII),
162 EIC7700_PIN(40, "i2s0_bclk", [0] = F_I2S, [2] = F_GPIO),
163 EIC7700_PIN(41, "i2s0_wclk", [0] = F_I2S, [2] = F_GPIO),
164 EIC7700_PIN(42, "i2s0_sdi", [0] = F_I2S, [2] = F_GPIO),
165 EIC7700_PIN(43, "i2s0_sdo", [0] = F_I2S, [2] = F_GPIO),
166 EIC7700_PIN(44, "i2s_mclk", [0] = F_I2S, [2] = F_GPIO),
167 EIC7700_PIN(45, "rgmii0_rxclk", [0] = F_RGMII),
168 EIC7700_PIN(46, "rgmii0_rxdv", [0] = F_RGMII),
169 EIC7700_PIN(47, "rgmii0_rxd0", [0] = F_RGMII),
170 EIC7700_PIN(48, "rgmii0_rxd1", [0] = F_RGMII),
171 EIC7700_PIN(49, "rgmii0_rxd2", [0] = F_RGMII),
172 EIC7700_PIN(50, "rgmii0_rxd3", [0] = F_RGMII),
173 EIC7700_PIN(51, "i2s2_bclk", [0] = F_I2S, [2] = F_GPIO),
174 EIC7700_PIN(52, "i2s2_wclk", [0] = F_I2S, [2] = F_GPIO),
175 EIC7700_PIN(53, "i2s2_sdi", [0] = F_I2S, [2] = F_GPIO),
176 EIC7700_PIN(54, "i2s2_sdo", [0] = F_I2S, [2] = F_GPIO),
177 EIC7700_PIN(55, "gpio27", [0] = F_GPIO, [1] = F_SATA),
178 EIC7700_PIN(56, "gpio28", [0] = F_GPIO),
179 EIC7700_PIN(57, "gpio29", [0] = F_RESET, [1] = F_EMMC, [2] = F_GPIO),
180 EIC7700_PIN(58, "rgmii0_mdc", [0] = F_RGMII),
181 EIC7700_PIN(59, "rgmii0_mdio", [0] = F_RGMII),
182 EIC7700_PIN(60, "rgmii0_intb", [0] = F_RGMII),
183 EIC7700_PIN(61, "rgmii1_clk_125", [0] = F_RGMII),
184 EIC7700_PIN(62, "rgmii1_txen", [0] = F_RGMII),
185 EIC7700_PIN(63, "rgmii1_txclk", [0] = F_RGMII),
186 EIC7700_PIN(64, "rgmii1_txd0", [0] = F_RGMII),
187 EIC7700_PIN(65, "rgmii1_txd1", [0] = F_RGMII),
188 EIC7700_PIN(66, "rgmii1_txd2", [0] = F_RGMII),
189 EIC7700_PIN(67, "rgmii1_txd3", [0] = F_RGMII),
190 EIC7700_PIN(68, "i2s1_bclk", [0] = F_I2S, [2] = F_GPIO),
191 EIC7700_PIN(69, "i2s1_wclk", [0] = F_I2S, [2] = F_GPIO),
192 EIC7700_PIN(70, "i2s1_sdi", [0] = F_I2S, [2] = F_GPIO),
193 EIC7700_PIN(71, "i2s1_sdo", [0] = F_I2S, [2] = F_GPIO),
194 EIC7700_PIN(72, "gpio34", [0] = F_RESET, [1] = F_SDIO, [2] = F_GPIO),
195 EIC7700_PIN(73, "rgmii1_rxclk", [0] = F_RGMII),
196 EIC7700_PIN(74, "rgmii1_rxdv", [0] = F_RGMII),
197 EIC7700_PIN(75, "rgmii1_rxd0", [0] = F_RGMII),
198 EIC7700_PIN(76, "rgmii1_rxd1", [0] = F_RGMII),
199 EIC7700_PIN(77, "rgmii1_rxd2", [0] = F_RGMII),
200 EIC7700_PIN(78, "rgmii1_rxd3", [0] = F_RGMII),
201 EIC7700_PIN(79, "spi1_cs0_n", [0] = F_SPI, [2] = F_GPIO),
202 EIC7700_PIN(80, "spi1_clk", [0] = F_SPI, [2] = F_GPIO),
203 EIC7700_PIN(81, "spi1_d0", [0] = F_SPI, [1] = F_I2C, [2] = F_GPIO, [3] = F_UART),
204 EIC7700_PIN(82, "spi1_d1", [0] = F_SPI, [1] = F_I2C, [2] = F_GPIO, [3] = F_UART),
205 EIC7700_PIN(83, "spi1_d2", [0] = F_SPI, [1] = F_SDIO, [2] = F_GPIO),
206 EIC7700_PIN(84, "spi1_d3", [0] = F_SPI, [1] = F_PWM, [2] = F_GPIO),
207 EIC7700_PIN(85, "spi1_cs1_n", [0] = F_SPI, [1] = F_PWM, [2] = F_GPIO),
208 EIC7700_PIN(86, "rgmii1_mdc", [0] = F_RGMII),
209 EIC7700_PIN(87, "rgmii1_mdio", [0] = F_RGMII),
210 EIC7700_PIN(88, "rgmii1_intb", [0] = F_RGMII),
211 EIC7700_PIN(89, "usb0_pwren", [0] = F_USB, [2] = F_GPIO),
212 EIC7700_PIN(90, "usb1_pwren", [0] = F_USB, [2] = F_GPIO),
213 EIC7700_PIN(91, "i2c0_scl", [0] = F_I2C, [2] = F_GPIO),
214 EIC7700_PIN(92, "i2c0_sda", [0] = F_I2C, [2] = F_GPIO),
215 EIC7700_PIN(93, "i2c1_scl", [0] = F_I2C, [2] = F_GPIO),
216 EIC7700_PIN(94, "i2c1_sda", [0] = F_I2C, [2] = F_GPIO),
217 EIC7700_PIN(95, "i2c2_scl", [0] = F_I2C, [2] = F_GPIO),
218 EIC7700_PIN(96, "i2c2_sda", [0] = F_I2C, [2] = F_GPIO),
219 EIC7700_PIN(97, "i2c3_scl", [0] = F_I2C, [2] = F_GPIO),
220 EIC7700_PIN(98, "i2c3_sda", [0] = F_I2C, [2] = F_GPIO),
221 EIC7700_PIN(99, "i2c4_scl", [0] = F_I2C, [2] = F_GPIO),
222 EIC7700_PIN(100, "i2c4_sda", [0] = F_I2C, [2] = F_GPIO),
223 EIC7700_PIN(101, "i2c5_scl", [0] = F_I2C, [2] = F_GPIO),
224 EIC7700_PIN(102, "i2c5_sda", [0] = F_I2C, [2] = F_GPIO),
225 EIC7700_PIN(103, "uart0_tx", [0] = F_UART, [2] = F_GPIO),
226 EIC7700_PIN(104, "uart0_rx", [0] = F_UART, [2] = F_GPIO),
227 EIC7700_PIN(105, "uart1_tx", [0] = F_UART, [2] = F_GPIO),
228 EIC7700_PIN(106, "uart1_rx", [0] = F_UART, [2] = F_GPIO),
229 EIC7700_PIN(107, "uart1_cts", [0] = F_UART, [1] = F_I2C, [2] = F_GPIO),
230 EIC7700_PIN(108, "uart1_rts", [0] = F_UART, [1] = F_I2C, [2] = F_GPIO),
231 EIC7700_PIN(109, "uart2_tx", [0] = F_UART, [1] = F_I2C, [2] = F_GPIO),
232 EIC7700_PIN(110, "uart2_rx", [0] = F_UART, [1] = F_I2C, [2] = F_GPIO),
233 EIC7700_PIN(111, "jtag2_tck", [0] = F_JTAG, [2] = F_GPIO),
234 EIC7700_PIN(112, "jtag2_tms", [0] = F_JTAG, [2] = F_GPIO),
235 EIC7700_PIN(113, "jtag2_tdi", [0] = F_JTAG, [2] = F_GPIO),
236 EIC7700_PIN(114, "jtag2_tdo", [0] = F_JTAG, [2] = F_GPIO),
237 EIC7700_PIN(115, "fan_pwm", [0] = F_PWM, [2] = F_GPIO),
238 EIC7700_PIN(116, "fan_tach", [0] = F_FAN_TACH, [2] = F_GPIO),
239 EIC7700_PIN(117, "mipi_csi0_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO),
240 EIC7700_PIN(118, "mipi_csi0_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO),
241 EIC7700_PIN(119, "mipi_csi0_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO),
242 EIC7700_PIN(120, "mipi_csi1_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO),
243 EIC7700_PIN(121, "mipi_csi1_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO),
244 EIC7700_PIN(122, "mipi_csi1_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO),
245 EIC7700_PIN(123, "mipi_csi2_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO),
246 EIC7700_PIN(124, "mipi_csi2_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO),
247 EIC7700_PIN(125, "mipi_csi2_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO),
248 EIC7700_PIN(126, "mipi_csi3_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO),
249 EIC7700_PIN(127, "mipi_csi3_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO),
250 EIC7700_PIN(128, "mipi_csi3_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO),
251 EIC7700_PIN(129, "mipi_csi4_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO),
252 EIC7700_PIN(130, "mipi_csi4_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO),
253 EIC7700_PIN(131, "mipi_csi4_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO),
254 EIC7700_PIN(132, "mipi_csi5_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO),
255 EIC7700_PIN(133, "mipi_csi5_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO),
256 EIC7700_PIN(134, "mipi_csi5_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO),
257 EIC7700_PIN(135, "spi3_cs_n", [0] = F_SPI, [2] = F_GPIO),
258 EIC7700_PIN(136, "spi3_clk", [0] = F_SPI, [2] = F_GPIO),
259 EIC7700_PIN(137, "spi3_di", [0] = F_SPI, [2] = F_GPIO),
260 EIC7700_PIN(138, "spi3_do", [0] = F_SPI, [2] = F_GPIO),
261 EIC7700_PIN(139, "gpio92", [0] = F_I2C, [1] = F_MIPI_CSI, [2] = F_GPIO, [3] = F_UART),
262 EIC7700_PIN(140, "gpio93", [0] = F_I2C, [1] = F_MIPI_CSI, [2] = F_GPIO, [3] = F_UART),
263 EIC7700_PIN(141, "s_mode", [0] = F_S_MODE, [2] = F_GPIO),
264 EIC7700_PIN(142, "gpio95", [0] = F_DDR_REF_CLK_SEL, [2] = F_GPIO),
265 EIC7700_PIN(143, "spi0_cs_n", [0] = F_SPI, [2] = F_GPIO),
266 EIC7700_PIN(144, "spi0_clk", [0] = F_SPI, [2] = F_GPIO),
267 EIC7700_PIN(145, "spi0_d0", [0] = F_SPI, [2] = F_GPIO),
268 EIC7700_PIN(146, "spi0_d1", [0] = F_SPI, [2] = F_GPIO),
269 EIC7700_PIN(147, "spi0_d2", [0] = F_SPI, [2] = F_GPIO),
270 EIC7700_PIN(148, "spi0_d3", [0] = F_SPI, [2] = F_GPIO),
271 EIC7700_PIN(149, "i2c10_scl", [0] = F_I2C, [2] = F_GPIO),
272 EIC7700_PIN(150, "i2c10_sda", [0] = F_I2C, [2] = F_GPIO),
273 EIC7700_PIN(151, "i2c11_scl", [0] = F_I2C, [2] = F_GPIO),
274 EIC7700_PIN(152, "i2c11_sda", [0] = F_I2C, [2] = F_GPIO),
275 EIC7700_PIN(153, "gpio106", [0] = F_GPIO),
276 EIC7700_PIN(154, "boot_sel0", [0] = F_BOOT_SEL, [2] = F_GPIO),
277 EIC7700_PIN(155, "boot_sel1", [0] = F_BOOT_SEL, [2] = F_GPIO),
278 EIC7700_PIN(156, "boot_sel2", [0] = F_BOOT_SEL, [2] = F_GPIO),
279 EIC7700_PIN(157, "boot_sel3", [0] = F_BOOT_SEL, [2] = F_GPIO),
280 EIC7700_PIN(158, "gpio111", [0] = F_GPIO),
281 EIC7700_PIN(159, "reserved0", [0] = F_DISABLED),
282 EIC7700_PIN(160, "reserved1", [0] = F_DISABLED),
283 EIC7700_PIN(161, "reserved2", [0] = F_DISABLED),
284 EIC7700_PIN(162, "reserved3", [0] = F_DISABLED),
285 EIC7700_PIN(163, "lpddr_ref_clk", [0] = F_LPDDR_REF_CLK),
286 };
287
eic7700_get_groups_count(struct pinctrl_dev * pctldev)288 static int eic7700_get_groups_count(struct pinctrl_dev *pctldev)
289 {
290 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
291
292 return pc->desc.npins;
293 }
294
eic7700_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)295 static const char *eic7700_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
296 {
297 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
298
299 return pc->desc.pins[selector].name;
300 }
301
eic7700_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * npins)302 static int eic7700_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
303 const unsigned int **pins, unsigned int *npins)
304 {
305 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
306
307 *pins = &pc->desc.pins[selector].number;
308 *npins = 1;
309
310 return 0;
311 }
312
313 static const struct pinctrl_ops eic7700_pinctrl_ops = {
314 .get_groups_count = eic7700_get_groups_count,
315 .get_group_name = eic7700_get_group_name,
316 .get_group_pins = eic7700_get_group_pins,
317 #ifdef CONFIG_OF
318 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
319 .dt_free_map = pinconf_generic_dt_free_map,
320 #endif
321 };
322
eic7700_pin_config_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)323 static int eic7700_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
324 unsigned long *config)
325 {
326 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
327 const struct eic7700_pin *pin_data = pc->desc.pins[pin].drv_data;
328 u32 arg, value;
329 int param;
330
331 if (pin_data->functions[0] == F_OSC || pin_data->functions[0] == F_DISABLED)
332 return -EOPNOTSUPP;
333
334 value = readl_relaxed(pc->base + EIC7700_PIN_REG(pin));
335
336 param = pinconf_to_config_param(*config);
337 switch (param) {
338 case PIN_CONFIG_BIAS_DISABLE:
339 arg = (value & EIC7700_BIAS) == 0;
340 break;
341 case PIN_CONFIG_BIAS_PULL_DOWN:
342 arg = (value & EIC7700_BIAS) == EIC7700_PD;
343 break;
344 case PIN_CONFIG_BIAS_PULL_UP:
345 arg = (value & EIC7700_BIAS) == EIC7700_PU;
346 break;
347 case PIN_CONFIG_DRIVE_STRENGTH_UA:
348 if (pin_data->functions[0] == F_RGMII ||
349 pin_data->functions[0] == F_LPDDR_REF_CLK)
350 arg = FIELD_GET(EIC7700_DS, value) * 3000 + 3000;
351 else
352 arg = FIELD_GET(EIC7700_DS, value) * 3000 + 6000;
353 break;
354 case PIN_CONFIG_INPUT_ENABLE:
355 arg = value & EIC7700_IE;
356 break;
357 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
358 arg = value & EIC7700_ST;
359 break;
360 default:
361 return -EOPNOTSUPP;
362 }
363
364 *config = pinconf_to_config_packed(param, arg);
365 return arg ? 0 : -EINVAL;
366 }
367
eic7700_pin_config_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)368 static int eic7700_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
369 unsigned long *configs, unsigned int num_configs)
370 {
371 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
372 const struct eic7700_pin *pin_data = pc->desc.pins[pin].drv_data;
373 u32 value;
374
375 if (pin_data->functions[0] == F_OSC || pin_data->functions[0] == F_DISABLED)
376 return -EOPNOTSUPP;
377
378 value = readl_relaxed(pc->base + EIC7700_PIN_REG(pin));
379
380 for (unsigned int i = 0; i < num_configs; i++) {
381 int param = pinconf_to_config_param(configs[i]);
382 u32 arg = pinconf_to_config_argument(configs[i]);
383
384 switch (param) {
385 case PIN_CONFIG_BIAS_DISABLE:
386 value &= ~EIC7700_BIAS;
387 break;
388 case PIN_CONFIG_BIAS_PULL_DOWN:
389 if (arg == 0)
390 return -EOPNOTSUPP;
391 value &= ~EIC7700_BIAS;
392 value |= EIC7700_PD;
393 break;
394 case PIN_CONFIG_BIAS_PULL_UP:
395 if (arg == 0)
396 return -EOPNOTSUPP;
397 value &= ~EIC7700_BIAS;
398 value |= EIC7700_PU;
399 break;
400 case PIN_CONFIG_DRIVE_STRENGTH_UA:
401 value &= ~EIC7700_DS;
402 if (pin_data->functions[0] == F_RGMII ||
403 pin_data->functions[0] == F_LPDDR_REF_CLK) {
404 if (arg < 3000 || arg > 24000)
405 return -EOPNOTSUPP;
406 value |= FIELD_PREP(EIC7700_DS, (arg - 3000) / 3000);
407 } else {
408 if (arg < 6000 || arg > 27000)
409 return -EOPNOTSUPP;
410 value |= FIELD_PREP(EIC7700_DS, (arg - 6000) / 3000);
411 }
412 break;
413 case PIN_CONFIG_INPUT_ENABLE:
414 if (arg)
415 value |= EIC7700_IE;
416 else
417 value &= ~EIC7700_IE;
418 break;
419 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
420 if (arg)
421 value |= EIC7700_ST;
422 else
423 value &= ~EIC7700_ST;
424 break;
425 default:
426 return -EOPNOTSUPP;
427 }
428 }
429
430 writel_relaxed(value, pc->base + EIC7700_PIN_REG(pin));
431
432 return 0;
433 }
434
435 #ifdef CONFIG_DEBUG_FS
eic7700_pin_config_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int pin)436 static void eic7700_pin_config_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
437 unsigned int pin)
438 {
439 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
440 u32 value = readl_relaxed(pc->base + EIC7700_PIN_REG(pin)) & EIC7700_PINCONF;
441
442 seq_printf(s, " [0x%02x]", value);
443 }
444 #else
445 #define eic7700_pin_config_dbg_show NULL
446 #endif
447
448 static const struct pinconf_ops eic7700_pinconf_ops = {
449 .is_generic = true,
450 .pin_config_get = eic7700_pin_config_get,
451 .pin_config_set = eic7700_pin_config_set,
452 .pin_config_group_get = eic7700_pin_config_get,
453 .pin_config_group_set = eic7700_pin_config_set,
454 .pin_config_dbg_show = eic7700_pin_config_dbg_show,
455 .pin_config_group_dbg_show = eic7700_pin_config_dbg_show,
456 };
457
eic7700_get_functions_count(struct pinctrl_dev * pctldev)458 static int eic7700_get_functions_count(struct pinctrl_dev *pctldev)
459 {
460 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
461
462 return pc->functions_count;
463 }
464
eic7700_get_function_name(struct pinctrl_dev * pctldev,unsigned int selector)465 static const char *eic7700_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector)
466 {
467 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
468
469 return pc->functions[selector].name;
470 }
471
eic7700_get_function_groups(struct pinctrl_dev * pctldev,unsigned int selector,const char * const ** groups,unsigned int * num_groups)472 static int eic7700_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
473 const char *const **groups, unsigned int *num_groups)
474 {
475 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
476
477 *groups = pc->functions[selector].groups;
478 *num_groups = pc->functions[selector].ngroups;
479
480 return 0;
481 }
482
eic7700_set_mux(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)483 static int eic7700_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
484 unsigned int group_selector)
485 {
486 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
487 const struct eic7700_pin *pin_data = pc->desc.pins[group_selector].drv_data;
488 u32 fs, value;
489
490 if (pin_data->functions[0] == F_OSC || pin_data->functions[0] == F_DISABLED)
491 return -EOPNOTSUPP;
492
493 for (fs = 0; fs < EIC7700_FUNCTIONS_PER_PIN; fs++)
494 if (pin_data->functions[fs] == func_selector)
495 break;
496
497 if (fs == EIC7700_FUNCTIONS_PER_PIN) {
498 dev_err(pctldev->dev, "invalid mux %s for pin %s\n",
499 pc->functions[func_selector].name,
500 pc->desc.pins[group_selector].name);
501 return -EINVAL;
502 }
503
504 value = readl_relaxed(pc->base + EIC7700_PIN_REG(group_selector));
505 value &= ~EIC7700_FUNC_SEL;
506 value |= FIELD_PREP(EIC7700_FUNC_SEL, fs);
507 writel_relaxed(value, pc->base + EIC7700_PIN_REG(group_selector));
508
509 return 0;
510 }
511
eic7700_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)512 static int eic7700_gpio_request_enable(struct pinctrl_dev *pctldev,
513 struct pinctrl_gpio_range *range, unsigned int offset)
514 {
515 return eic7700_set_mux(pctldev, F_GPIO, offset);
516 }
517
eic7700_gpio_disable_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)518 static void eic7700_gpio_disable_free(struct pinctrl_dev *pctldev,
519 struct pinctrl_gpio_range *range, unsigned int offset)
520 {
521 eic7700_set_mux(pctldev, F_DISABLED, offset);
522 }
523
eic7700_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset,bool input)524 static int eic7700_gpio_set_direction(struct pinctrl_dev *pctldev,
525 struct pinctrl_gpio_range *range, unsigned int offset,
526 bool input)
527 {
528 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
529 u32 value;
530
531 value = readl_relaxed(pc->base + EIC7700_PIN_REG(offset));
532 if (input)
533 value |= EIC7700_IE;
534 else
535 value &= ~EIC7700_IE;
536 writel_relaxed(value, pc->base + EIC7700_PIN_REG(offset));
537
538 return 0;
539 }
540
541 static const struct pinmux_ops eic7700_pinmux_ops = {
542 .get_functions_count = eic7700_get_functions_count,
543 .get_function_name = eic7700_get_function_name,
544 .get_function_groups = eic7700_get_function_groups,
545 .set_mux = eic7700_set_mux,
546 .gpio_request_enable = eic7700_gpio_request_enable,
547 .gpio_disable_free = eic7700_gpio_disable_free,
548 .gpio_set_direction = eic7700_gpio_set_direction,
549 .strict = true,
550 };
551
eic7700_pinctrl_init_function_groups(struct device * dev,struct eic7700_pinctrl * pc,const char * const * function_names)552 static int eic7700_pinctrl_init_function_groups(struct device *dev, struct eic7700_pinctrl *pc,
553 const char *const *function_names)
554 {
555 unsigned int ngroups = 0;
556 const char **groups;
557
558 /* Count the number of groups for each function */
559 for (unsigned int pin = 0; pin < pc->desc.npins; pin++) {
560 const struct eic7700_pin *pin_data = pc->desc.pins[pin].drv_data;
561 bool found_disabled = false;
562
563 for (unsigned int fs = 0; fs < EIC7700_FUNCTIONS_PER_PIN; fs++) {
564 unsigned int selector = pin_data->functions[fs];
565 struct pinfunction *function = &pc->functions[selector];
566
567 /* Only count F_DISABLED once per pin */
568 if (selector == F_DISABLED) {
569 if (found_disabled)
570 continue;
571 found_disabled = true;
572 }
573
574 function->ngroups++;
575 ngroups++;
576 }
577 }
578
579 groups = devm_kcalloc(dev, ngroups, sizeof(*groups), GFP_KERNEL);
580 if (!groups)
581 return -ENOMEM;
582
583 for (unsigned int selector = 0; selector < pc->functions_count; selector++) {
584 struct pinfunction *function = &pc->functions[selector];
585
586 function->name = function_names[selector];
587 function->groups = groups;
588 groups += function->ngroups;
589
590 /* Reset per-function ngroups for use as iterator below */
591 function->ngroups = 0;
592 }
593
594 /* Fill in the group pointers for each function */
595 for (unsigned int pin = 0; pin < pc->desc.npins; pin++) {
596 const struct pinctrl_pin_desc *desc = &pc->desc.pins[pin];
597 const struct eic7700_pin *pin_data = desc->drv_data;
598 bool found_disabled = false;
599
600 for (unsigned int fs = 0; fs < EIC7700_FUNCTIONS_PER_PIN; fs++) {
601 unsigned int selector = pin_data->functions[fs];
602 struct pinfunction *function = &pc->functions[selector];
603
604 /* Only count F_DISABLED once per pin */
605 if (selector == F_DISABLED) {
606 if (found_disabled)
607 continue;
608 found_disabled = true;
609 }
610
611 ((const char **)function->groups)[function->ngroups++] = desc->name;
612 }
613 }
614
615 return 0;
616 }
617
eic7700_pinctrl_probe(struct platform_device * pdev)618 static int eic7700_pinctrl_probe(struct platform_device *pdev)
619 {
620 struct device *dev = &pdev->dev;
621 struct pinctrl_dev *pctldev;
622 struct eic7700_pinctrl *pc;
623 struct regulator *regulator;
624 u32 rgmii0_mode, rgmii1_mode;
625 int ret, voltage;
626
627 pc = devm_kzalloc(dev, struct_size(pc, functions, EIC7700_FUNCTIONS_COUNT), GFP_KERNEL);
628 if (!pc)
629 return -ENOMEM;
630
631 pc->base = devm_platform_ioremap_resource(pdev, 0);
632 if (IS_ERR(pc->base))
633 return PTR_ERR(pc->base);
634
635 regulator = devm_regulator_get(dev, "vrgmii");
636 if (IS_ERR(regulator)) {
637 return dev_err_probe(dev, PTR_ERR(regulator),
638 "failed to get vrgmii regulator\n");
639 }
640
641 voltage = regulator_get_voltage(regulator);
642 if (voltage < 0) {
643 return dev_err_probe(&pdev->dev, voltage,
644 "Failed to get voltage from regulator\n");
645 }
646
647 rgmii0_mode = readl_relaxed(pc->base + EIC7700_RGMII0_SEL_MODE);
648 rgmii1_mode = readl_relaxed(pc->base + EIC7700_RGMII1_SEL_MODE);
649 rgmii0_mode &= ~EIC7700_MS;
650 rgmii1_mode &= ~EIC7700_MS;
651 if (voltage == 1800000) {
652 rgmii0_mode |= FIELD_PREP(EIC7700_MS, EIC7700_MS_1V8);
653 rgmii1_mode |= FIELD_PREP(EIC7700_MS, EIC7700_MS_1V8);
654 } else if (voltage == 3300000) {
655 rgmii0_mode |= FIELD_PREP(EIC7700_MS, EIC7700_MS_3V3);
656 rgmii1_mode |= FIELD_PREP(EIC7700_MS, EIC7700_MS_3V3);
657 } else {
658 return dev_err_probe(&pdev->dev, -EINVAL,
659 "Invalid voltage configuration, should be either 1.8V or 3.3V\n");
660 }
661
662 writel_relaxed(rgmii0_mode, pc->base + EIC7700_RGMII0_SEL_MODE);
663 writel_relaxed(rgmii1_mode, pc->base + EIC7700_RGMII1_SEL_MODE);
664
665 pc->desc.name = dev_name(dev);
666 pc->desc.pins = eic7700_pins;
667 pc->desc.npins = ARRAY_SIZE(eic7700_pins);
668 pc->desc.pctlops = &eic7700_pinctrl_ops;
669 pc->desc.pmxops = &eic7700_pinmux_ops;
670 pc->desc.confops = &eic7700_pinconf_ops;
671 pc->desc.owner = THIS_MODULE;
672
673 pc->functions_count = EIC7700_FUNCTIONS_COUNT;
674 ret = eic7700_pinctrl_init_function_groups(dev, pc, eic7700_functions);
675 if (ret)
676 return ret;
677
678 ret = devm_pinctrl_register_and_init(dev, &pc->desc, pc, &pctldev);
679 if (ret)
680 return dev_err_probe(dev, ret, "could not register pinctrl driver\n");
681
682 return pinctrl_enable(pctldev);
683 }
684
685 static const struct of_device_id eic7700_pinctrl_of_match[] = {
686 { .compatible = "eswin,eic7700-pinctrl" },
687 { /* sentinel */ }
688 };
689 MODULE_DEVICE_TABLE(of, eic7700_pinctrl_of_match);
690
691 static struct platform_driver eic7700_pinctrl_driver = {
692 .probe = eic7700_pinctrl_probe,
693 .driver = {
694 .name = "pinctrl-eic7700",
695 .of_match_table = eic7700_pinctrl_of_match,
696 },
697 };
698 module_platform_driver(eic7700_pinctrl_driver);
699
700 MODULE_DESCRIPTION("Pinctrl driver for the ESWIN EIC7700 SoC");
701 MODULE_AUTHOR("Samuel Holland <samuel.holland@sifive.com>");
702 MODULE_AUTHOR("Yulin Lu <luyulin@eswincomputing.com>");
703 MODULE_LICENSE("GPL");
704