xref: /linux/drivers/pinctrl/pinctrl-cy8c95x0.c (revision 9208c05f9fdfd927ea160b97dfef3c379049fff2)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support
4  *
5  * Copyright (C) 2022 9elements GmbH
6  * Authors: Patrick Rudolph <patrick.rudolph@9elements.com>
7  *	    Naresh Solanki <Naresh.Solanki@9elements.com>
8  */
9 
10 #include <linux/acpi.h>
11 #include <linux/bitmap.h>
12 #include <linux/cleanup.h>
13 #include <linux/dmi.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/i2c.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/property.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/seq_file.h>
25 
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pinctrl/pinconf.h>
28 #include <linux/pinctrl/pinconf-generic.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 
32 /* Fast access registers */
33 #define CY8C95X0_INPUT		0x00
34 #define CY8C95X0_OUTPUT		0x08
35 #define CY8C95X0_INTSTATUS	0x10
36 
37 #define CY8C95X0_INPUT_(x)	(CY8C95X0_INPUT + (x))
38 #define CY8C95X0_OUTPUT_(x)	(CY8C95X0_OUTPUT + (x))
39 #define CY8C95X0_INTSTATUS_(x)	(CY8C95X0_INTSTATUS + (x))
40 
41 /* Port Select configures the port */
42 #define CY8C95X0_PORTSEL	0x18
43 /* Port settings, write PORTSEL first */
44 #define CY8C95X0_INTMASK	0x19
45 #define CY8C95X0_PWMSEL		0x1A
46 #define CY8C95X0_INVERT		0x1B
47 #define CY8C95X0_DIRECTION	0x1C
48 /* Drive mode register change state on writing '1' */
49 #define CY8C95X0_DRV_PU		0x1D
50 #define CY8C95X0_DRV_PD		0x1E
51 #define CY8C95X0_DRV_ODH	0x1F
52 #define CY8C95X0_DRV_ODL	0x20
53 #define CY8C95X0_DRV_PP_FAST	0x21
54 #define CY8C95X0_DRV_PP_SLOW	0x22
55 #define CY8C95X0_DRV_HIZ	0x23
56 #define CY8C95X0_DEVID		0x2E
57 #define CY8C95X0_WATCHDOG	0x2F
58 #define CY8C95X0_COMMAND	0x30
59 
60 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
61 
62 #define MAX_BANK		8
63 #define BANK_SZ			8
64 #define MAX_LINE		(MAX_BANK * BANK_SZ)
65 #define MUXED_STRIDE		16
66 #define CY8C95X0_GPIO_MASK	GENMASK(7, 0)
67 #define CY8C95X0_VIRTUAL	0x40
68 #define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \
69 	(CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE)
70 
71 static const struct i2c_device_id cy8c95x0_id[] = {
72 	{ "cy8c9520", 20, },
73 	{ "cy8c9540", 40, },
74 	{ "cy8c9560", 60, },
75 	{ }
76 };
77 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
78 
79 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
80 
81 static const struct of_device_id cy8c95x0_dt_ids[] = {
82 	{ .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), },
83 	{ .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), },
84 	{ .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), },
85 	{ }
86 };
87 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
88 
89 static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true };
90 
91 static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = {
92 	{ "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
93 	{ }
94 };
95 
96 static int cy8c95x0_acpi_get_irq(struct device *dev)
97 {
98 	int ret;
99 
100 	ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios);
101 	if (ret)
102 		dev_warn(dev, "can't add GPIO ACPI mapping\n");
103 
104 	ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0);
105 	if (ret < 0)
106 		return ret;
107 
108 	dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
109 	return ret;
110 }
111 
112 static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
113 	{
114 		/*
115 		 * On Intel Galileo Gen 1 board the IRQ pin is provided
116 		 * as an absolute number instead of being relative.
117 		 * Since first controller (gpio-sch.c) and second
118 		 * (gpio-dwapb.c) are at the fixed bases, we may safely
119 		 * refer to the number in the global space to get an IRQ
120 		 * out of it.
121 		 */
122 		.matches = {
123 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
124 		},
125 	},
126 	{}
127 };
128 
129 /**
130  * struct cy8c95x0_pinctrl - driver data
131  * @regmap:         Device's regmap. Only direct access registers.
132  * @irq_lock:       IRQ bus lock
133  * @i2c_lock:       Mutex to hold while using the regmap
134  * @irq_mask:       I/O bits affected by interrupts
135  * @irq_trig_raise: I/O bits affected by raising voltage level
136  * @irq_trig_fall:  I/O bits affected by falling voltage level
137  * @irq_trig_low:   I/O bits affected by a low voltage level
138  * @irq_trig_high:  I/O bits affected by a high voltage level
139  * @push_pull:      I/O bits configured as push pull driver
140  * @shiftmask:      Mask used to compensate for Gport2 width
141  * @nport:          Number of Gports in this chip
142  * @gpio_chip:      gpiolib chip
143  * @driver_data:    private driver data
144  * @dev:            struct device
145  * @pctldev:        pin controller device
146  * @pinctrl_desc:   pin controller description
147  * @name:           Chip controller name
148  * @tpin:           Total number of pins
149  * @gpio_reset:     GPIO line handler that can reset the IC
150  */
151 struct cy8c95x0_pinctrl {
152 	struct regmap *regmap;
153 	struct mutex irq_lock;
154 	struct mutex i2c_lock;
155 	DECLARE_BITMAP(irq_mask, MAX_LINE);
156 	DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
157 	DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
158 	DECLARE_BITMAP(irq_trig_low, MAX_LINE);
159 	DECLARE_BITMAP(irq_trig_high, MAX_LINE);
160 	DECLARE_BITMAP(push_pull, MAX_LINE);
161 	DECLARE_BITMAP(shiftmask, MAX_LINE);
162 	unsigned int nport;
163 	struct gpio_chip gpio_chip;
164 	unsigned long driver_data;
165 	struct device *dev;
166 	struct pinctrl_dev *pctldev;
167 	struct pinctrl_desc pinctrl_desc;
168 	char name[32];
169 	unsigned int tpin;
170 	struct gpio_desc *gpio_reset;
171 };
172 
173 static const struct pinctrl_pin_desc cy8c9560_pins[] = {
174 	PINCTRL_PIN(0, "gp00"),
175 	PINCTRL_PIN(1, "gp01"),
176 	PINCTRL_PIN(2, "gp02"),
177 	PINCTRL_PIN(3, "gp03"),
178 	PINCTRL_PIN(4, "gp04"),
179 	PINCTRL_PIN(5, "gp05"),
180 	PINCTRL_PIN(6, "gp06"),
181 	PINCTRL_PIN(7, "gp07"),
182 
183 	PINCTRL_PIN(8, "gp10"),
184 	PINCTRL_PIN(9, "gp11"),
185 	PINCTRL_PIN(10, "gp12"),
186 	PINCTRL_PIN(11, "gp13"),
187 	PINCTRL_PIN(12, "gp14"),
188 	PINCTRL_PIN(13, "gp15"),
189 	PINCTRL_PIN(14, "gp16"),
190 	PINCTRL_PIN(15, "gp17"),
191 
192 	PINCTRL_PIN(16, "gp20"),
193 	PINCTRL_PIN(17, "gp21"),
194 	PINCTRL_PIN(18, "gp22"),
195 	PINCTRL_PIN(19, "gp23"),
196 
197 	PINCTRL_PIN(20, "gp30"),
198 	PINCTRL_PIN(21, "gp31"),
199 	PINCTRL_PIN(22, "gp32"),
200 	PINCTRL_PIN(23, "gp33"),
201 	PINCTRL_PIN(24, "gp34"),
202 	PINCTRL_PIN(25, "gp35"),
203 	PINCTRL_PIN(26, "gp36"),
204 	PINCTRL_PIN(27, "gp37"),
205 
206 	PINCTRL_PIN(28, "gp40"),
207 	PINCTRL_PIN(29, "gp41"),
208 	PINCTRL_PIN(30, "gp42"),
209 	PINCTRL_PIN(31, "gp43"),
210 	PINCTRL_PIN(32, "gp44"),
211 	PINCTRL_PIN(33, "gp45"),
212 	PINCTRL_PIN(34, "gp46"),
213 	PINCTRL_PIN(35, "gp47"),
214 
215 	PINCTRL_PIN(36, "gp50"),
216 	PINCTRL_PIN(37, "gp51"),
217 	PINCTRL_PIN(38, "gp52"),
218 	PINCTRL_PIN(39, "gp53"),
219 	PINCTRL_PIN(40, "gp54"),
220 	PINCTRL_PIN(41, "gp55"),
221 	PINCTRL_PIN(42, "gp56"),
222 	PINCTRL_PIN(43, "gp57"),
223 
224 	PINCTRL_PIN(44, "gp60"),
225 	PINCTRL_PIN(45, "gp61"),
226 	PINCTRL_PIN(46, "gp62"),
227 	PINCTRL_PIN(47, "gp63"),
228 	PINCTRL_PIN(48, "gp64"),
229 	PINCTRL_PIN(49, "gp65"),
230 	PINCTRL_PIN(50, "gp66"),
231 	PINCTRL_PIN(51, "gp67"),
232 
233 	PINCTRL_PIN(52, "gp70"),
234 	PINCTRL_PIN(53, "gp71"),
235 	PINCTRL_PIN(54, "gp72"),
236 	PINCTRL_PIN(55, "gp73"),
237 	PINCTRL_PIN(56, "gp74"),
238 	PINCTRL_PIN(57, "gp75"),
239 	PINCTRL_PIN(58, "gp76"),
240 	PINCTRL_PIN(59, "gp77"),
241 };
242 
243 static const char * const cy8c95x0_groups[] = {
244 	"gp00",
245 	"gp01",
246 	"gp02",
247 	"gp03",
248 	"gp04",
249 	"gp05",
250 	"gp06",
251 	"gp07",
252 
253 	"gp10",
254 	"gp11",
255 	"gp12",
256 	"gp13",
257 	"gp14",
258 	"gp15",
259 	"gp16",
260 	"gp17",
261 
262 	"gp20",
263 	"gp21",
264 	"gp22",
265 	"gp23",
266 
267 	"gp30",
268 	"gp31",
269 	"gp32",
270 	"gp33",
271 	"gp34",
272 	"gp35",
273 	"gp36",
274 	"gp37",
275 
276 	"gp40",
277 	"gp41",
278 	"gp42",
279 	"gp43",
280 	"gp44",
281 	"gp45",
282 	"gp46",
283 	"gp47",
284 
285 	"gp50",
286 	"gp51",
287 	"gp52",
288 	"gp53",
289 	"gp54",
290 	"gp55",
291 	"gp56",
292 	"gp57",
293 
294 	"gp60",
295 	"gp61",
296 	"gp62",
297 	"gp63",
298 	"gp64",
299 	"gp65",
300 	"gp66",
301 	"gp67",
302 
303 	"gp70",
304 	"gp71",
305 	"gp72",
306 	"gp73",
307 	"gp74",
308 	"gp75",
309 	"gp76",
310 	"gp77",
311 };
312 
313 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
314 				     unsigned int pin, bool input);
315 
316 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin)
317 {
318 	/* Account for GPORT2 which only has 4 bits */
319 	return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ;
320 }
321 
322 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
323 {
324 	/* Account for GPORT2 which only has 4 bits */
325 	return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ);
326 }
327 
328 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
329 {
330 	/*
331 	 * Only 12 registers are present per port (see Table 6 in the
332 	 * datasheet).
333 	 */
334 	if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) < 12)
335 		return true;
336 
337 	switch (reg) {
338 	case 0x24 ... 0x27:
339 		return false;
340 	default:
341 		return true;
342 	}
343 }
344 
345 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)
346 {
347 	if (reg >= CY8C95X0_VIRTUAL)
348 		return true;
349 
350 	switch (reg) {
351 	case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
352 		return false;
353 	case CY8C95X0_DEVID:
354 		return false;
355 	case 0x24 ... 0x27:
356 		return false;
357 	default:
358 		return true;
359 	}
360 }
361 
362 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)
363 {
364 	switch (reg) {
365 	case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
366 	case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
367 	case CY8C95X0_INTMASK:
368 	case CY8C95X0_INVERT:
369 	case CY8C95X0_PWMSEL:
370 	case CY8C95X0_DIRECTION:
371 	case CY8C95X0_DRV_PU:
372 	case CY8C95X0_DRV_PD:
373 	case CY8C95X0_DRV_ODH:
374 	case CY8C95X0_DRV_ODL:
375 	case CY8C95X0_DRV_PP_FAST:
376 	case CY8C95X0_DRV_PP_SLOW:
377 	case CY8C95X0_DRV_HIZ:
378 		return true;
379 	default:
380 		return false;
381 	}
382 }
383 
384 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg)
385 {
386 	switch (reg) {
387 	case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
388 		return true;
389 	default:
390 		return false;
391 	}
392 }
393 
394 static bool cy8c95x0_muxed_register(unsigned int reg)
395 {
396 	switch (reg) {
397 	case CY8C95X0_INTMASK:
398 	case CY8C95X0_PWMSEL:
399 	case CY8C95X0_INVERT:
400 	case CY8C95X0_DIRECTION:
401 	case CY8C95X0_DRV_PU:
402 	case CY8C95X0_DRV_PD:
403 	case CY8C95X0_DRV_ODH:
404 	case CY8C95X0_DRV_ODL:
405 	case CY8C95X0_DRV_PP_FAST:
406 	case CY8C95X0_DRV_PP_SLOW:
407 	case CY8C95X0_DRV_HIZ:
408 		return true;
409 	default:
410 		return false;
411 	}
412 }
413 
414 static bool cy8c95x0_wc_register(unsigned int reg)
415 {
416 	switch (reg) {
417 	case CY8C95X0_DRV_PU:
418 	case CY8C95X0_DRV_PD:
419 	case CY8C95X0_DRV_ODH:
420 	case CY8C95X0_DRV_ODL:
421 	case CY8C95X0_DRV_PP_FAST:
422 	case CY8C95X0_DRV_PP_SLOW:
423 	case CY8C95X0_DRV_HIZ:
424 		return true;
425 	default:
426 		return false;
427 	}
428 }
429 
430 static bool cy8c95x0_quick_path_register(unsigned int reg)
431 {
432 	switch (reg) {
433 	case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
434 	case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
435 	case CY8C95X0_OUTPUT_(0) ... CY8C95X0_OUTPUT_(7):
436 		return true;
437 	default:
438 		return false;
439 	}
440 }
441 
442 static const struct regmap_range_cfg cy8c95x0_ranges[] = {
443 	{
444 		.range_min = CY8C95X0_VIRTUAL,
445 		.range_max = 0,		/* Updated at runtime */
446 		.selector_reg = CY8C95X0_PORTSEL,
447 		.selector_mask = 0x07,
448 		.selector_shift = 0x0,
449 		.window_start = CY8C95X0_PORTSEL,
450 		.window_len = MUXED_STRIDE,
451 	}
452 };
453 
454 static const struct regmap_config cy8c9520_i2c_regmap = {
455 	.reg_bits = 8,
456 	.val_bits = 8,
457 
458 	.readable_reg = cy8c95x0_readable_register,
459 	.writeable_reg = cy8c95x0_writeable_register,
460 	.volatile_reg = cy8c95x0_volatile_register,
461 	.precious_reg = cy8c95x0_precious_register,
462 
463 	.cache_type = REGCACHE_MAPLE,
464 	.ranges	= NULL,			/* Updated at runtime */
465 	.num_ranges = 1,
466 	.max_register = 0,		/* Updated at runtime */
467 	.num_reg_defaults_raw = 0,	/* Updated at runtime */
468 	.use_single_read = true,	/* Workaround for regcache bug */
469 	.disable_locking = true,
470 };
471 
472 static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip,
473 						   unsigned int reg,
474 						   unsigned int port,
475 						   unsigned int mask,
476 						   unsigned int val,
477 						   bool *change, bool async,
478 						   bool force)
479 {
480 	int ret, off, i;
481 
482 	/* Caller should never modify PORTSEL directly */
483 	if (reg == CY8C95X0_PORTSEL)
484 		return -EINVAL;
485 
486 	/* Registers behind the PORTSEL mux have their own range in regmap */
487 	if (cy8c95x0_muxed_register(reg)) {
488 		off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
489 	} else {
490 		/* Quick path direct access registers honor the port argument */
491 		if (cy8c95x0_quick_path_register(reg))
492 			off = reg + port;
493 		else
494 			off = reg;
495 	}
496 	guard(mutex)(&chip->i2c_lock);
497 
498 	ret = regmap_update_bits_base(chip->regmap, off, mask, val, change, async, force);
499 	if (ret < 0)
500 		return ret;
501 
502 	/* Mimic what hardware does and update the cache when a WC bit is written.
503 	 * Allows to mark the registers as non-volatile and reduces I/O cycles.
504 	 */
505 	if (cy8c95x0_wc_register(reg) && (mask & val)) {
506 		/* Writing a 1 clears set bits in the other drive mode registers */
507 		regcache_cache_only(chip->regmap, true);
508 		for (i = CY8C95X0_DRV_PU; i <= CY8C95X0_DRV_HIZ; i++) {
509 			if (i == reg)
510 				continue;
511 
512 			off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port);
513 			regmap_clear_bits(chip->regmap, off, mask & val);
514 		}
515 		regcache_cache_only(chip->regmap, false);
516 	}
517 
518 	return ret;
519 }
520 
521 /**
522  * cy8c95x0_regmap_write_bits() - writes a register using the regmap cache
523  * @chip: The pinctrl to work on
524  * @reg: The register to write to. Can be direct access or muxed register.
525  *       MUST NOT be the PORTSEL register.
526  * @port: The port to be used for muxed registers or quick path direct access
527  *        registers. Otherwise unused.
528  * @mask: Bitmask to change
529  * @val: New value for bitmask
530  *
531  * This function handles the register writes to the direct access registers and
532  * the muxed registers while caching all register accesses, internally handling
533  * the correct state of the PORTSEL register and protecting the access to muxed
534  * registers.
535  * The caller must only use this function to change registers behind the PORTSEL mux.
536  *
537  * Return: 0 for successful request, else a corresponding error value
538  */
539 static int cy8c95x0_regmap_write_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg,
540 				      unsigned int port, unsigned int mask, unsigned int val)
541 {
542 	return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, true);
543 }
544 
545 /**
546  * cy8c95x0_regmap_update_bits() - updates a register using the regmap cache
547  * @chip: The pinctrl to work on
548  * @reg: The register to write to. Can be direct access or muxed register.
549  *       MUST NOT be the PORTSEL register.
550  * @port: The port to be used for muxed registers or quick path direct access
551  *        registers. Otherwise unused.
552  * @mask: Bitmask to change
553  * @val: New value for bitmask
554  *
555  * This function handles the register updates to the direct access registers and
556  * the muxed registers while caching all register accesses, internally handling
557  * the correct state of the PORTSEL register and protecting the access to muxed
558  * registers.
559  * The caller must only use this function to change registers behind the PORTSEL mux.
560  *
561  * Return: 0 for successful request, else a corresponding error value
562  */
563 static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg,
564 				       unsigned int port, unsigned int mask, unsigned int val)
565 {
566 	return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, false);
567 }
568 
569 /**
570  * cy8c95x0_regmap_read() - reads a register using the regmap cache
571  * @chip: The pinctrl to work on
572  * @reg: The register to read from. Can be direct access or muxed register.
573  * @port: The port to be used for muxed registers or quick path direct access
574  *        registers. Otherwise unused.
575  * @read_val: Value read from hardware or cache
576  *
577  * This function handles the register reads from the direct access registers and
578  * the muxed registers while caching all register accesses, internally handling
579  * the correct state of the PORTSEL register and protecting the access to muxed
580  * registers.
581  * The caller must only use this function to read registers behind the PORTSEL mux.
582  *
583  * Return: 0 for successful request, else a corresponding error value
584  */
585 static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg,
586 				unsigned int port, unsigned int *read_val)
587 {
588 	int off, ret;
589 
590 	/* Registers behind the PORTSEL mux have their own range in regmap */
591 	if (cy8c95x0_muxed_register(reg)) {
592 		off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
593 	} else {
594 		/* Quick path direct access registers honor the port argument */
595 		if (cy8c95x0_quick_path_register(reg))
596 			off = reg + port;
597 		else
598 			off = reg;
599 	}
600 	guard(mutex)(&chip->i2c_lock);
601 
602 	ret = regmap_read(chip->regmap, off, read_val);
603 
604 	return ret;
605 }
606 
607 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
608 				    unsigned long *val, unsigned long *mask)
609 {
610 	DECLARE_BITMAP(tmask, MAX_LINE);
611 	DECLARE_BITMAP(tval, MAX_LINE);
612 	int write_val;
613 	u8 bits;
614 	int ret;
615 
616 	/* Add the 4 bit gap of Gport2 */
617 	bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
618 	bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
619 	bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
620 
621 	bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
622 	bitmap_shift_left(tval, tval, 4, MAX_LINE);
623 	bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
624 
625 	for (unsigned int i = 0; i < chip->nport; i++) {
626 		/* Skip over unused banks */
627 		bits = bitmap_get_value8(tmask, i * BANK_SZ);
628 		if (!bits)
629 			continue;
630 
631 		write_val = bitmap_get_value8(tval, i * BANK_SZ);
632 
633 		ret = cy8c95x0_regmap_update_bits(chip, reg, i, bits, write_val);
634 		if (ret < 0) {
635 			dev_err(chip->dev, "failed writing register %d, port %u: err %d\n", reg, i, ret);
636 			return ret;
637 		}
638 	}
639 
640 	return 0;
641 }
642 
643 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
644 				   unsigned long *val, unsigned long *mask)
645 {
646 	DECLARE_BITMAP(tmask, MAX_LINE);
647 	DECLARE_BITMAP(tval, MAX_LINE);
648 	DECLARE_BITMAP(tmp, MAX_LINE);
649 	int read_val;
650 	u8 bits;
651 	int ret;
652 
653 	/* Add the 4 bit gap of Gport2 */
654 	bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
655 	bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
656 	bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
657 
658 	bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
659 	bitmap_shift_left(tval, tval, 4, MAX_LINE);
660 	bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
661 
662 	for (unsigned int i = 0; i < chip->nport; i++) {
663 		/* Skip over unused banks */
664 		bits = bitmap_get_value8(tmask, i * BANK_SZ);
665 		if (!bits)
666 			continue;
667 
668 		ret = cy8c95x0_regmap_read(chip, reg, i, &read_val);
669 		if (ret < 0) {
670 			dev_err(chip->dev, "failed reading register %d, port %u: err %d\n", reg, i, ret);
671 			return ret;
672 		}
673 
674 		read_val &= bits;
675 		read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits;
676 		bitmap_set_value8(tval, read_val, i * BANK_SZ);
677 	}
678 
679 	/* Fill the 4 bit gap of Gport2 */
680 	bitmap_shift_right(tmp, tval, 4, MAX_LINE);
681 	bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE);
682 
683 	return 0;
684 }
685 
686 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off)
687 {
688 	return pinctrl_gpio_direction_input(gc, off);
689 }
690 
691 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,
692 					  unsigned int off, int val)
693 {
694 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
695 	u8 port = cypress_get_port(chip, off);
696 	u8 bit = cypress_get_pin_mask(chip, off);
697 	int ret;
698 
699 	/* Set output level */
700 	ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0);
701 	if (ret)
702 		return ret;
703 
704 	return pinctrl_gpio_direction_output(gc, off);
705 }
706 
707 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
708 {
709 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
710 	u8 port = cypress_get_port(chip, off);
711 	u8 bit = cypress_get_pin_mask(chip, off);
712 	u32 reg_val;
713 	int ret;
714 
715 	ret = cy8c95x0_regmap_read(chip, CY8C95X0_INPUT, port, &reg_val);
716 	if (ret < 0) {
717 		/*
718 		 * NOTE:
719 		 * Diagnostic already emitted; that's all we should
720 		 * do unless gpio_*_value_cansleep() calls become different
721 		 * from their nonsleeping siblings (and report faults).
722 		 */
723 		return 0;
724 	}
725 
726 	return !!(reg_val & bit);
727 }
728 
729 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off,
730 				    int val)
731 {
732 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
733 	u8 port = cypress_get_port(chip, off);
734 	u8 bit = cypress_get_pin_mask(chip, off);
735 
736 	cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0);
737 }
738 
739 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
740 {
741 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
742 	u8 port = cypress_get_port(chip, off);
743 	u8 bit = cypress_get_pin_mask(chip, off);
744 	u32 reg_val;
745 	int ret;
746 
747 	ret = cy8c95x0_regmap_read(chip, CY8C95X0_DIRECTION, port, &reg_val);
748 	if (ret < 0)
749 		return ret;
750 
751 	if (reg_val & bit)
752 		return GPIO_LINE_DIRECTION_IN;
753 
754 	return GPIO_LINE_DIRECTION_OUT;
755 }
756 
757 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
758 				    unsigned int off,
759 				    unsigned long *config)
760 {
761 	enum pin_config_param param = pinconf_to_config_param(*config);
762 	u8 port = cypress_get_port(chip, off);
763 	u8 bit = cypress_get_pin_mask(chip, off);
764 	unsigned int reg;
765 	u32 reg_val;
766 	u16 arg = 0;
767 	int ret;
768 
769 	switch (param) {
770 	case PIN_CONFIG_BIAS_PULL_UP:
771 		reg = CY8C95X0_DRV_PU;
772 		break;
773 	case PIN_CONFIG_BIAS_PULL_DOWN:
774 		reg = CY8C95X0_DRV_PD;
775 		break;
776 	case PIN_CONFIG_BIAS_DISABLE:
777 		reg = CY8C95X0_DRV_HIZ;
778 		break;
779 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
780 		reg = CY8C95X0_DRV_ODL;
781 		break;
782 	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
783 		reg = CY8C95X0_DRV_ODH;
784 		break;
785 	case PIN_CONFIG_DRIVE_PUSH_PULL:
786 		reg = CY8C95X0_DRV_PP_FAST;
787 		break;
788 	case PIN_CONFIG_INPUT_ENABLE:
789 		reg = CY8C95X0_DIRECTION;
790 		break;
791 	case PIN_CONFIG_MODE_PWM:
792 		reg = CY8C95X0_PWMSEL;
793 		break;
794 	case PIN_CONFIG_OUTPUT:
795 		reg = CY8C95X0_OUTPUT;
796 		break;
797 	case PIN_CONFIG_OUTPUT_ENABLE:
798 		reg = CY8C95X0_DIRECTION;
799 		break;
800 
801 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
802 	case PIN_CONFIG_BIAS_BUS_HOLD:
803 	case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
804 	case PIN_CONFIG_DRIVE_STRENGTH:
805 	case PIN_CONFIG_DRIVE_STRENGTH_UA:
806 	case PIN_CONFIG_INPUT_DEBOUNCE:
807 	case PIN_CONFIG_INPUT_SCHMITT:
808 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
809 	case PIN_CONFIG_MODE_LOW_POWER:
810 	case PIN_CONFIG_PERSIST_STATE:
811 	case PIN_CONFIG_POWER_SOURCE:
812 	case PIN_CONFIG_SKEW_DELAY:
813 	case PIN_CONFIG_SLEEP_HARDWARE_STATE:
814 	case PIN_CONFIG_SLEW_RATE:
815 	default:
816 		return -ENOTSUPP;
817 	}
818 	/*
819 	 * Writing 1 to one of the drive mode registers will automatically
820 	 * clear conflicting set bits in the other drive mode registers.
821 	 */
822 	ret = cy8c95x0_regmap_read(chip, reg, port, &reg_val);
823 	if (ret < 0)
824 		return ret;
825 
826 	if (reg_val & bit)
827 		arg = 1;
828 	if (param == PIN_CONFIG_OUTPUT_ENABLE)
829 		arg = !arg;
830 
831 	*config = pinconf_to_config_packed(param, (u16)arg);
832 	return 0;
833 }
834 
835 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
836 				    unsigned int off,
837 				    unsigned long config)
838 {
839 	u8 port = cypress_get_port(chip, off);
840 	u8 bit = cypress_get_pin_mask(chip, off);
841 	unsigned long param = pinconf_to_config_param(config);
842 	unsigned long arg = pinconf_to_config_argument(config);
843 	unsigned int reg;
844 
845 	switch (param) {
846 	case PIN_CONFIG_BIAS_PULL_UP:
847 		__clear_bit(off, chip->push_pull);
848 		reg = CY8C95X0_DRV_PU;
849 		break;
850 	case PIN_CONFIG_BIAS_PULL_DOWN:
851 		__clear_bit(off, chip->push_pull);
852 		reg = CY8C95X0_DRV_PD;
853 		break;
854 	case PIN_CONFIG_BIAS_DISABLE:
855 		__clear_bit(off, chip->push_pull);
856 		reg = CY8C95X0_DRV_HIZ;
857 		break;
858 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
859 		__clear_bit(off, chip->push_pull);
860 		reg = CY8C95X0_DRV_ODL;
861 		break;
862 	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
863 		__clear_bit(off, chip->push_pull);
864 		reg = CY8C95X0_DRV_ODH;
865 		break;
866 	case PIN_CONFIG_DRIVE_PUSH_PULL:
867 		__set_bit(off, chip->push_pull);
868 		reg = CY8C95X0_DRV_PP_FAST;
869 		break;
870 	case PIN_CONFIG_MODE_PWM:
871 		reg = CY8C95X0_PWMSEL;
872 		break;
873 	case PIN_CONFIG_OUTPUT_ENABLE:
874 		return cy8c95x0_pinmux_direction(chip, off, !arg);
875 	case PIN_CONFIG_INPUT_ENABLE:
876 		return cy8c95x0_pinmux_direction(chip, off, arg);
877 	default:
878 		return -ENOTSUPP;
879 	}
880 	/*
881 	 * Writing 1 to one of the drive mode registers will automatically
882 	 * clear conflicting set bits in the other drive mode registers.
883 	 */
884 	return cy8c95x0_regmap_write_bits(chip, reg, port, bit, bit);
885 }
886 
887 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc,
888 				      unsigned long *mask, unsigned long *bits)
889 {
890 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
891 
892 	return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask);
893 }
894 
895 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc,
896 				       unsigned long *mask, unsigned long *bits)
897 {
898 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
899 
900 	cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask);
901 }
902 
903 static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc)
904 {
905 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
906 	struct device *dev = chip->dev;
907 	int ret;
908 
909 	ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin);
910 	if (ret)
911 		dev_err(dev, "failed to add GPIO pin range\n");
912 
913 	return ret;
914 }
915 
916 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip)
917 {
918 	struct gpio_chip *gc = &chip->gpio_chip;
919 
920 	gc->request = gpiochip_generic_request;
921 	gc->free = gpiochip_generic_free;
922 	gc->direction_input  = cy8c95x0_gpio_direction_input;
923 	gc->direction_output = cy8c95x0_gpio_direction_output;
924 	gc->get = cy8c95x0_gpio_get_value;
925 	gc->set = cy8c95x0_gpio_set_value;
926 	gc->get_direction = cy8c95x0_gpio_get_direction;
927 	gc->get_multiple = cy8c95x0_gpio_get_multiple;
928 	gc->set_multiple = cy8c95x0_gpio_set_multiple;
929 	gc->set_config = gpiochip_generic_config;
930 	gc->can_sleep = true;
931 	gc->add_pin_ranges = cy8c95x0_add_pin_ranges;
932 
933 	gc->base = -1;
934 	gc->ngpio = chip->tpin;
935 
936 	gc->parent = chip->dev;
937 	gc->owner = THIS_MODULE;
938 	gc->names = NULL;
939 
940 	gc->label = dev_name(chip->dev);
941 
942 	return devm_gpiochip_add_data(chip->dev, gc, chip);
943 }
944 
945 static void cy8c95x0_irq_mask(struct irq_data *d)
946 {
947 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
948 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
949 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
950 
951 	set_bit(hwirq, chip->irq_mask);
952 	gpiochip_disable_irq(gc, hwirq);
953 }
954 
955 static void cy8c95x0_irq_unmask(struct irq_data *d)
956 {
957 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
958 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
959 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
960 
961 	gpiochip_enable_irq(gc, hwirq);
962 	clear_bit(hwirq, chip->irq_mask);
963 }
964 
965 static void cy8c95x0_irq_bus_lock(struct irq_data *d)
966 {
967 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
968 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
969 
970 	mutex_lock(&chip->irq_lock);
971 }
972 
973 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d)
974 {
975 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
976 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
977 	DECLARE_BITMAP(ones, MAX_LINE);
978 	DECLARE_BITMAP(irq_mask, MAX_LINE);
979 	DECLARE_BITMAP(reg_direction, MAX_LINE);
980 
981 	bitmap_fill(ones, MAX_LINE);
982 
983 	cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones);
984 
985 	/* Switch direction to input if needed */
986 	cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask);
987 	bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE);
988 	bitmap_complement(irq_mask, irq_mask, MAX_LINE);
989 
990 	/* Look for any newly setup interrupt */
991 	cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask);
992 
993 	mutex_unlock(&chip->irq_lock);
994 }
995 
996 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type)
997 {
998 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
999 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1000 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1001 	unsigned int trig_type;
1002 
1003 	switch (type) {
1004 	case IRQ_TYPE_EDGE_RISING:
1005 	case IRQ_TYPE_EDGE_FALLING:
1006 	case IRQ_TYPE_EDGE_BOTH:
1007 		trig_type = type;
1008 		break;
1009 	case IRQ_TYPE_LEVEL_HIGH:
1010 		trig_type = IRQ_TYPE_EDGE_RISING;
1011 		break;
1012 	case IRQ_TYPE_LEVEL_LOW:
1013 		trig_type = IRQ_TYPE_EDGE_FALLING;
1014 		break;
1015 	default:
1016 		dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type);
1017 		return -EINVAL;
1018 	}
1019 
1020 	assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING);
1021 	assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING);
1022 	assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW);
1023 	assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH);
1024 
1025 	return 0;
1026 }
1027 
1028 static void cy8c95x0_irq_shutdown(struct irq_data *d)
1029 {
1030 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1031 	struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
1032 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1033 
1034 	clear_bit(hwirq, chip->irq_trig_raise);
1035 	clear_bit(hwirq, chip->irq_trig_fall);
1036 	clear_bit(hwirq, chip->irq_trig_low);
1037 	clear_bit(hwirq, chip->irq_trig_high);
1038 }
1039 
1040 static const struct irq_chip cy8c95x0_irqchip = {
1041 	.name = "cy8c95x0-irq",
1042 	.irq_mask = cy8c95x0_irq_mask,
1043 	.irq_unmask = cy8c95x0_irq_unmask,
1044 	.irq_bus_lock = cy8c95x0_irq_bus_lock,
1045 	.irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock,
1046 	.irq_set_type = cy8c95x0_irq_set_type,
1047 	.irq_shutdown = cy8c95x0_irq_shutdown,
1048 	.flags = IRQCHIP_IMMUTABLE,
1049 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
1050 };
1051 
1052 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending)
1053 {
1054 	DECLARE_BITMAP(ones, MAX_LINE);
1055 	DECLARE_BITMAP(cur_stat, MAX_LINE);
1056 	DECLARE_BITMAP(new_stat, MAX_LINE);
1057 	DECLARE_BITMAP(trigger, MAX_LINE);
1058 
1059 	bitmap_fill(ones, MAX_LINE);
1060 
1061 	/* Read the current interrupt status from the device */
1062 	if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones))
1063 		return false;
1064 
1065 	/* Check latched inputs */
1066 	if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger))
1067 		return false;
1068 
1069 	/* Apply filter for rising/falling edge selection */
1070 	bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise,
1071 		       cur_stat, MAX_LINE);
1072 
1073 	bitmap_and(pending, new_stat, trigger, MAX_LINE);
1074 
1075 	return !bitmap_empty(pending, MAX_LINE);
1076 }
1077 
1078 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid)
1079 {
1080 	struct cy8c95x0_pinctrl *chip = devid;
1081 	struct gpio_chip *gc = &chip->gpio_chip;
1082 	DECLARE_BITMAP(pending, MAX_LINE);
1083 	int nested_irq, level;
1084 	bool ret;
1085 
1086 	ret = cy8c95x0_irq_pending(chip, pending);
1087 	if (!ret)
1088 		return IRQ_RETVAL(0);
1089 
1090 	ret = 0;
1091 	for_each_set_bit(level, pending, MAX_LINE) {
1092 		/* Already accounted for 4bit gap in GPort2 */
1093 		nested_irq = irq_find_mapping(gc->irq.domain, level);
1094 
1095 		if (unlikely(nested_irq <= 0)) {
1096 			dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
1097 			continue;
1098 		}
1099 
1100 		if (test_bit(level, chip->irq_trig_low))
1101 			while (!cy8c95x0_gpio_get_value(gc, level))
1102 				handle_nested_irq(nested_irq);
1103 		else if (test_bit(level, chip->irq_trig_high))
1104 			while (cy8c95x0_gpio_get_value(gc, level))
1105 				handle_nested_irq(nested_irq);
1106 		else
1107 			handle_nested_irq(nested_irq);
1108 
1109 		ret = 1;
1110 	}
1111 
1112 	return IRQ_RETVAL(ret);
1113 }
1114 
1115 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
1116 {
1117 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1118 
1119 	return chip->tpin;
1120 }
1121 
1122 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
1123 						   unsigned int group)
1124 {
1125 	return cy8c95x0_groups[group];
1126 }
1127 
1128 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1129 					   unsigned int group,
1130 					   const unsigned int **pins,
1131 					   unsigned int *num_pins)
1132 {
1133 	*pins = &cy8c9560_pins[group].number;
1134 	*num_pins = 1;
1135 	return 0;
1136 }
1137 
1138 static const char *cy8c95x0_get_fname(unsigned int selector)
1139 {
1140 	if (selector == 0)
1141 		return "gpio";
1142 	else
1143 		return "pwm";
1144 }
1145 
1146 static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1147 				  unsigned int pin)
1148 {
1149 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1150 	DECLARE_BITMAP(mask, MAX_LINE);
1151 	DECLARE_BITMAP(pwm, MAX_LINE);
1152 
1153 	bitmap_zero(mask, MAX_LINE);
1154 	__set_bit(pin, mask);
1155 
1156 	if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) {
1157 		seq_puts(s, "not available");
1158 		return;
1159 	}
1160 
1161 	seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm)));
1162 }
1163 
1164 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = {
1165 	.get_groups_count = cy8c95x0_pinctrl_get_groups_count,
1166 	.get_group_name = cy8c95x0_pinctrl_get_group_name,
1167 	.get_group_pins = cy8c95x0_pinctrl_get_group_pins,
1168 #ifdef CONFIG_OF
1169 	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1170 	.dt_free_map = pinconf_generic_dt_free_map,
1171 #endif
1172 	.pin_dbg_show = cy8c95x0_pin_dbg_show,
1173 };
1174 
1175 static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector)
1176 {
1177 	return cy8c95x0_get_fname(selector);
1178 }
1179 
1180 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev)
1181 {
1182 	return 2;
1183 }
1184 
1185 static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
1186 					const char * const **groups,
1187 					unsigned int * const num_groups)
1188 {
1189 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1190 
1191 	*groups = cy8c95x0_groups;
1192 	*num_groups = chip->tpin;
1193 	return 0;
1194 }
1195 
1196 static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode)
1197 {
1198 	u8 port = cypress_get_port(chip, off);
1199 	u8 bit = cypress_get_pin_mask(chip, off);
1200 
1201 	return cy8c95x0_regmap_write_bits(chip, CY8C95X0_PWMSEL, port, bit, mode ? bit : 0);
1202 }
1203 
1204 static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,
1205 				unsigned int selector, unsigned int group)
1206 {
1207 	u8 port = cypress_get_port(chip, group);
1208 	u8 bit = cypress_get_pin_mask(chip, group);
1209 	int ret;
1210 
1211 	ret = cy8c95x0_set_mode(chip, group, selector);
1212 	if (ret < 0)
1213 		return ret;
1214 
1215 	if (selector == 0)
1216 		return 0;
1217 
1218 	/* Set direction to output & set output to 1 so that PWM can work */
1219 	ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, bit);
1220 	if (ret < 0)
1221 		return ret;
1222 
1223 	return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, bit);
1224 }
1225 
1226 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1227 			    unsigned int group)
1228 {
1229 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1230 
1231 	return cy8c95x0_pinmux_mode(chip, selector, group);
1232 }
1233 
1234 static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev,
1235 					struct pinctrl_gpio_range *range,
1236 					unsigned int pin)
1237 {
1238 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1239 
1240 	return cy8c95x0_set_mode(chip, pin, false);
1241 }
1242 
1243 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
1244 				     unsigned int pin, bool input)
1245 {
1246 	u8 port = cypress_get_port(chip, pin);
1247 	u8 bit = cypress_get_pin_mask(chip, pin);
1248 	int ret;
1249 
1250 	ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0);
1251 	if (ret)
1252 		return ret;
1253 
1254 	/*
1255 	 * Disable driving the pin by forcing it to HighZ. Only setting
1256 	 * the direction register isn't sufficient in Push-Pull mode.
1257 	 */
1258 	if (input && test_bit(pin, chip->push_pull)) {
1259 		ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit);
1260 		if (ret)
1261 			return ret;
1262 
1263 		__clear_bit(pin, chip->push_pull);
1264 	}
1265 
1266 	return 0;
1267 }
1268 
1269 static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev,
1270 				       struct pinctrl_gpio_range *range,
1271 				       unsigned int pin, bool input)
1272 {
1273 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1274 
1275 	return cy8c95x0_pinmux_direction(chip, pin, input);
1276 }
1277 
1278 static const struct pinmux_ops cy8c95x0_pmxops = {
1279 	.get_functions_count = cy8c95x0_get_functions_count,
1280 	.get_function_name = cy8c95x0_get_function_name,
1281 	.get_function_groups = cy8c95x0_get_function_groups,
1282 	.set_mux = cy8c95x0_set_mux,
1283 	.gpio_request_enable = cy8c95x0_gpio_request_enable,
1284 	.gpio_set_direction = cy8c95x0_gpio_set_direction,
1285 	.strict = true,
1286 };
1287 
1288 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1289 				unsigned long *config)
1290 {
1291 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1292 
1293 	return cy8c95x0_gpio_get_pincfg(chip, pin, config);
1294 }
1295 
1296 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1297 				unsigned long *configs, unsigned int num_configs)
1298 {
1299 	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1300 	int ret = 0;
1301 	int i;
1302 
1303 	for (i = 0; i < num_configs; i++) {
1304 		ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]);
1305 		if (ret)
1306 			return ret;
1307 	}
1308 
1309 	return ret;
1310 }
1311 
1312 static const struct pinconf_ops cy8c95x0_pinconf_ops = {
1313 	.pin_config_get = cy8c95x0_pinconf_get,
1314 	.pin_config_set = cy8c95x0_pinconf_set,
1315 	.is_generic = true,
1316 };
1317 
1318 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq)
1319 {
1320 	struct gpio_irq_chip *girq = &chip->gpio_chip.irq;
1321 	DECLARE_BITMAP(pending_irqs, MAX_LINE);
1322 	int ret;
1323 
1324 	mutex_init(&chip->irq_lock);
1325 
1326 	bitmap_zero(pending_irqs, MAX_LINE);
1327 
1328 	/* Read IRQ status register to clear all pending interrupts */
1329 	ret = cy8c95x0_irq_pending(chip, pending_irqs);
1330 	if (ret) {
1331 		dev_err(chip->dev, "failed to clear irq status register\n");
1332 		return ret;
1333 	}
1334 
1335 	/* Mask all interrupts */
1336 	bitmap_fill(chip->irq_mask, MAX_LINE);
1337 
1338 	gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip);
1339 
1340 	/* This will let us handle the parent IRQ in the driver */
1341 	girq->parent_handler = NULL;
1342 	girq->num_parents = 0;
1343 	girq->parents = NULL;
1344 	girq->default_type = IRQ_TYPE_NONE;
1345 	girq->handler = handle_simple_irq;
1346 	girq->threaded = true;
1347 
1348 	ret = devm_request_threaded_irq(chip->dev, irq,
1349 					NULL, cy8c95x0_irq_handler,
1350 					IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH,
1351 					dev_name(chip->dev), chip);
1352 	if (ret) {
1353 		dev_err(chip->dev, "failed to request irq %d\n", irq);
1354 		return ret;
1355 	}
1356 	dev_info(chip->dev, "Registered threaded IRQ\n");
1357 
1358 	return 0;
1359 }
1360 
1361 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)
1362 {
1363 	struct pinctrl_desc *pd = &chip->pinctrl_desc;
1364 
1365 	pd->pctlops = &cy8c95x0_pinctrl_ops;
1366 	pd->confops = &cy8c95x0_pinconf_ops;
1367 	pd->pmxops = &cy8c95x0_pmxops;
1368 	pd->name = dev_name(chip->dev);
1369 	pd->pins = cy8c9560_pins;
1370 	pd->npins = chip->tpin;
1371 	pd->owner = THIS_MODULE;
1372 
1373 	chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip);
1374 	if (IS_ERR(chip->pctldev))
1375 		return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev),
1376 			"can't register controller\n");
1377 
1378 	return 0;
1379 }
1380 
1381 static int cy8c95x0_detect(struct i2c_client *client,
1382 			   struct i2c_board_info *info)
1383 {
1384 	struct i2c_adapter *adapter = client->adapter;
1385 	int ret;
1386 	const char *name;
1387 
1388 	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1389 		return -ENODEV;
1390 
1391 	ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID);
1392 	if (ret < 0)
1393 		return ret;
1394 	switch (ret & GENMASK(7, 4)) {
1395 	case 0x20:
1396 		name = cy8c95x0_id[0].name;
1397 		break;
1398 	case 0x40:
1399 		name = cy8c95x0_id[1].name;
1400 		break;
1401 	case 0x60:
1402 		name = cy8c95x0_id[2].name;
1403 		break;
1404 	default:
1405 		return -ENODEV;
1406 	}
1407 
1408 	dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr);
1409 	strscpy(info->type, name);
1410 
1411 	return 0;
1412 }
1413 
1414 static int cy8c95x0_probe(struct i2c_client *client)
1415 {
1416 	struct device *dev = &client->dev;
1417 	struct cy8c95x0_pinctrl *chip;
1418 	struct regmap_config regmap_conf;
1419 	struct regmap_range_cfg regmap_range_conf;
1420 	int ret;
1421 
1422 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
1423 	if (!chip)
1424 		return -ENOMEM;
1425 
1426 	chip->dev = dev;
1427 
1428 	/* Set the device type */
1429 	chip->driver_data = (uintptr_t)i2c_get_match_data(client);
1430 	if (!chip->driver_data)
1431 		return -ENODEV;
1432 
1433 	chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
1434 	chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
1435 
1436 	memcpy(&regmap_range_conf, &cy8c95x0_ranges[0], sizeof(regmap_range_conf));
1437 
1438 	switch (chip->tpin) {
1439 	case 20:
1440 		strscpy(chip->name, cy8c95x0_id[0].name);
1441 		regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE;
1442 		break;
1443 	case 40:
1444 		strscpy(chip->name, cy8c95x0_id[1].name);
1445 		regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE;
1446 		break;
1447 	case 60:
1448 		strscpy(chip->name, cy8c95x0_id[2].name);
1449 		regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE;
1450 		break;
1451 	default:
1452 		return -ENODEV;
1453 	}
1454 
1455 	ret = devm_regulator_get_enable(dev, "vdd");
1456 	if (ret)
1457 		return dev_err_probe(dev, ret, "failed to enable regulator vdd\n");
1458 
1459 	/* bring the chip out of reset if reset pin is provided */
1460 	chip->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1461 	if (IS_ERR(chip->gpio_reset))
1462 		return dev_err_probe(dev, PTR_ERR(chip->gpio_reset), "Failed to get GPIO 'reset'\n");
1463 	gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET");
1464 	if (chip->gpio_reset) {
1465 		fsleep(1000);
1466 		gpiod_set_value_cansleep(chip->gpio_reset, 0);
1467 		fsleep(250000);
1468 	}
1469 
1470 	/* Regmap for direct and paged registers */
1471 	memcpy(&regmap_conf, &cy8c9520_i2c_regmap, sizeof(regmap_conf));
1472 	regmap_conf.ranges = &regmap_range_conf;
1473 	regmap_conf.max_register = regmap_range_conf.range_max;
1474 	regmap_conf.num_reg_defaults_raw = regmap_range_conf.range_max;
1475 
1476 	chip->regmap = devm_regmap_init_i2c(client, &regmap_conf);
1477 	if (IS_ERR(chip->regmap))
1478 		return PTR_ERR(chip->regmap);
1479 
1480 	bitmap_zero(chip->push_pull, MAX_LINE);
1481 	bitmap_zero(chip->shiftmask, MAX_LINE);
1482 	bitmap_set(chip->shiftmask, 0, 20);
1483 	mutex_init(&chip->i2c_lock);
1484 
1485 	if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) {
1486 		ret = cy8c95x0_acpi_get_irq(&client->dev);
1487 		if (ret > 0)
1488 			client->irq = ret;
1489 	}
1490 
1491 	if (client->irq) {
1492 		ret = cy8c95x0_irq_setup(chip, client->irq);
1493 		if (ret)
1494 			return ret;
1495 	}
1496 
1497 	ret = cy8c95x0_setup_pinctrl(chip);
1498 	if (ret)
1499 		return ret;
1500 
1501 	return cy8c95x0_setup_gpiochip(chip);
1502 }
1503 
1504 static const struct acpi_device_id cy8c95x0_acpi_ids[] = {
1505 	{ "INT3490", 40, },
1506 	{ }
1507 };
1508 MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids);
1509 
1510 static struct i2c_driver cy8c95x0_driver = {
1511 	.driver = {
1512 		.name	= "cy8c95x0-pinctrl",
1513 		.of_match_table = cy8c95x0_dt_ids,
1514 		.acpi_match_table = cy8c95x0_acpi_ids,
1515 	},
1516 	.probe		= cy8c95x0_probe,
1517 	.id_table	= cy8c95x0_id,
1518 	.detect		= cy8c95x0_detect,
1519 };
1520 module_i2c_driver(cy8c95x0_driver);
1521 
1522 MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>");
1523 MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>");
1524 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0");
1525 MODULE_LICENSE("GPL");
1526