1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support 4 * 5 * Copyright (C) 2022 9elements GmbH 6 * Authors: Patrick Rudolph <patrick.rudolph@9elements.com> 7 * Naresh Solanki <Naresh.Solanki@9elements.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitmap.h> 12 #include <linux/dmi.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/i2c.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/module.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/seq_file.h> 24 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/pinctrl/pinconf.h> 27 #include <linux/pinctrl/pinconf-generic.h> 28 #include <linux/pinctrl/pinctrl.h> 29 #include <linux/pinctrl/pinmux.h> 30 31 /* Fast access registers */ 32 #define CY8C95X0_INPUT 0x00 33 #define CY8C95X0_OUTPUT 0x08 34 #define CY8C95X0_INTSTATUS 0x10 35 36 #define CY8C95X0_INPUT_(x) (CY8C95X0_INPUT + (x)) 37 #define CY8C95X0_OUTPUT_(x) (CY8C95X0_OUTPUT + (x)) 38 #define CY8C95X0_INTSTATUS_(x) (CY8C95X0_INTSTATUS + (x)) 39 40 /* Port Select configures the port */ 41 #define CY8C95X0_PORTSEL 0x18 42 /* Port settings, write PORTSEL first */ 43 #define CY8C95X0_INTMASK 0x19 44 #define CY8C95X0_PWMSEL 0x1A 45 #define CY8C95X0_INVERT 0x1B 46 #define CY8C95X0_DIRECTION 0x1C 47 /* Drive mode register change state on writing '1' */ 48 #define CY8C95X0_DRV_PU 0x1D 49 #define CY8C95X0_DRV_PD 0x1E 50 #define CY8C95X0_DRV_ODH 0x1F 51 #define CY8C95X0_DRV_ODL 0x20 52 #define CY8C95X0_DRV_PP_FAST 0x21 53 #define CY8C95X0_DRV_PP_SLOW 0x22 54 #define CY8C95X0_DRV_HIZ 0x23 55 #define CY8C95X0_DEVID 0x2E 56 #define CY8C95X0_WATCHDOG 0x2F 57 #define CY8C95X0_COMMAND 0x30 58 59 #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x)) 60 61 static const struct i2c_device_id cy8c95x0_id[] = { 62 { "cy8c9520", 20, }, 63 { "cy8c9540", 40, }, 64 { "cy8c9560", 60, }, 65 { } 66 }; 67 MODULE_DEVICE_TABLE(i2c, cy8c95x0_id); 68 69 #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio)) 70 71 static const struct of_device_id cy8c95x0_dt_ids[] = { 72 { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), }, 73 { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), }, 74 { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), }, 75 { } 76 }; 77 MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids); 78 79 static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true }; 80 81 static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = { 82 { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 83 { } 84 }; 85 86 static int cy8c95x0_acpi_get_irq(struct device *dev) 87 { 88 int ret; 89 90 ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios); 91 if (ret) 92 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 93 94 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0); 95 if (ret < 0) 96 return ret; 97 98 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 99 return ret; 100 } 101 102 static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = { 103 { 104 /* 105 * On Intel Galileo Gen 1 board the IRQ pin is provided 106 * as an absolute number instead of being relative. 107 * Since first controller (gpio-sch.c) and second 108 * (gpio-dwapb.c) are at the fixed bases, we may safely 109 * refer to the number in the global space to get an IRQ 110 * out of it. 111 */ 112 .matches = { 113 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 114 }, 115 }, 116 {} 117 }; 118 119 #define MAX_BANK 8 120 #define BANK_SZ 8 121 #define MAX_LINE (MAX_BANK * BANK_SZ) 122 123 #define CY8C95X0_GPIO_MASK GENMASK(7, 0) 124 125 /** 126 * struct cy8c95x0_pinctrl - driver data 127 * @regmap: Device's regmap 128 * @irq_lock: IRQ bus lock 129 * @i2c_lock: Mutex for the device internal mux register 130 * @irq_mask: I/O bits affected by interrupts 131 * @irq_trig_raise: I/O bits affected by raising voltage level 132 * @irq_trig_fall: I/O bits affected by falling voltage level 133 * @irq_trig_low: I/O bits affected by a low voltage level 134 * @irq_trig_high: I/O bits affected by a high voltage level 135 * @push_pull: I/O bits configured as push pull driver 136 * @shiftmask: Mask used to compensate for Gport2 width 137 * @nport: Number of Gports in this chip 138 * @gpio_chip: gpiolib chip 139 * @driver_data: private driver data 140 * @regulator: Pointer to the regulator for the IC 141 * @dev: struct device 142 * @pctldev: pin controller device 143 * @pinctrl_desc: pin controller description 144 * @name: Chip controller name 145 * @tpin: Total number of pins 146 * @gpio_reset: GPIO line handler that can reset the IC 147 */ 148 struct cy8c95x0_pinctrl { 149 struct regmap *regmap; 150 struct mutex irq_lock; 151 struct mutex i2c_lock; 152 DECLARE_BITMAP(irq_mask, MAX_LINE); 153 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 154 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 155 DECLARE_BITMAP(irq_trig_low, MAX_LINE); 156 DECLARE_BITMAP(irq_trig_high, MAX_LINE); 157 DECLARE_BITMAP(push_pull, MAX_LINE); 158 DECLARE_BITMAP(shiftmask, MAX_LINE); 159 int nport; 160 struct gpio_chip gpio_chip; 161 unsigned long driver_data; 162 struct regulator *regulator; 163 struct device *dev; 164 struct pinctrl_dev *pctldev; 165 struct pinctrl_desc pinctrl_desc; 166 char name[32]; 167 unsigned int tpin; 168 struct gpio_desc *gpio_reset; 169 }; 170 171 static const struct pinctrl_pin_desc cy8c9560_pins[] = { 172 PINCTRL_PIN(0, "gp00"), 173 PINCTRL_PIN(1, "gp01"), 174 PINCTRL_PIN(2, "gp02"), 175 PINCTRL_PIN(3, "gp03"), 176 PINCTRL_PIN(4, "gp04"), 177 PINCTRL_PIN(5, "gp05"), 178 PINCTRL_PIN(6, "gp06"), 179 PINCTRL_PIN(7, "gp07"), 180 181 PINCTRL_PIN(8, "gp10"), 182 PINCTRL_PIN(9, "gp11"), 183 PINCTRL_PIN(10, "gp12"), 184 PINCTRL_PIN(11, "gp13"), 185 PINCTRL_PIN(12, "gp14"), 186 PINCTRL_PIN(13, "gp15"), 187 PINCTRL_PIN(14, "gp16"), 188 PINCTRL_PIN(15, "gp17"), 189 190 PINCTRL_PIN(16, "gp20"), 191 PINCTRL_PIN(17, "gp21"), 192 PINCTRL_PIN(18, "gp22"), 193 PINCTRL_PIN(19, "gp23"), 194 195 PINCTRL_PIN(20, "gp30"), 196 PINCTRL_PIN(21, "gp31"), 197 PINCTRL_PIN(22, "gp32"), 198 PINCTRL_PIN(23, "gp33"), 199 PINCTRL_PIN(24, "gp34"), 200 PINCTRL_PIN(25, "gp35"), 201 PINCTRL_PIN(26, "gp36"), 202 PINCTRL_PIN(27, "gp37"), 203 204 PINCTRL_PIN(28, "gp40"), 205 PINCTRL_PIN(29, "gp41"), 206 PINCTRL_PIN(30, "gp42"), 207 PINCTRL_PIN(31, "gp43"), 208 PINCTRL_PIN(32, "gp44"), 209 PINCTRL_PIN(33, "gp45"), 210 PINCTRL_PIN(34, "gp46"), 211 PINCTRL_PIN(35, "gp47"), 212 213 PINCTRL_PIN(36, "gp50"), 214 PINCTRL_PIN(37, "gp51"), 215 PINCTRL_PIN(38, "gp52"), 216 PINCTRL_PIN(39, "gp53"), 217 PINCTRL_PIN(40, "gp54"), 218 PINCTRL_PIN(41, "gp55"), 219 PINCTRL_PIN(42, "gp56"), 220 PINCTRL_PIN(43, "gp57"), 221 222 PINCTRL_PIN(44, "gp60"), 223 PINCTRL_PIN(45, "gp61"), 224 PINCTRL_PIN(46, "gp62"), 225 PINCTRL_PIN(47, "gp63"), 226 PINCTRL_PIN(48, "gp64"), 227 PINCTRL_PIN(49, "gp65"), 228 PINCTRL_PIN(50, "gp66"), 229 PINCTRL_PIN(51, "gp67"), 230 231 PINCTRL_PIN(52, "gp70"), 232 PINCTRL_PIN(53, "gp71"), 233 PINCTRL_PIN(54, "gp72"), 234 PINCTRL_PIN(55, "gp73"), 235 PINCTRL_PIN(56, "gp74"), 236 PINCTRL_PIN(57, "gp75"), 237 PINCTRL_PIN(58, "gp76"), 238 PINCTRL_PIN(59, "gp77"), 239 }; 240 241 static const char * const cy8c95x0_groups[] = { 242 "gp00", 243 "gp01", 244 "gp02", 245 "gp03", 246 "gp04", 247 "gp05", 248 "gp06", 249 "gp07", 250 251 "gp10", 252 "gp11", 253 "gp12", 254 "gp13", 255 "gp14", 256 "gp15", 257 "gp16", 258 "gp17", 259 260 "gp20", 261 "gp21", 262 "gp22", 263 "gp23", 264 265 "gp30", 266 "gp31", 267 "gp32", 268 "gp33", 269 "gp34", 270 "gp35", 271 "gp36", 272 "gp37", 273 274 "gp40", 275 "gp41", 276 "gp42", 277 "gp43", 278 "gp44", 279 "gp45", 280 "gp46", 281 "gp47", 282 283 "gp50", 284 "gp51", 285 "gp52", 286 "gp53", 287 "gp54", 288 "gp55", 289 "gp56", 290 "gp57", 291 292 "gp60", 293 "gp61", 294 "gp62", 295 "gp63", 296 "gp64", 297 "gp65", 298 "gp66", 299 "gp67", 300 301 "gp70", 302 "gp71", 303 "gp72", 304 "gp73", 305 "gp74", 306 "gp75", 307 "gp76", 308 "gp77", 309 }; 310 311 static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin) 312 { 313 /* Account for GPORT2 which only has 4 bits */ 314 return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ; 315 } 316 317 static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin) 318 { 319 /* Account for GPORT2 which only has 4 bits */ 320 return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ); 321 } 322 323 static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg) 324 { 325 switch (reg) { 326 case 0x24 ... 0x27: 327 return false; 328 default: 329 return true; 330 } 331 } 332 333 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg) 334 { 335 switch (reg) { 336 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 337 return false; 338 case CY8C95X0_DEVID: 339 return false; 340 case 0x24 ... 0x27: 341 return false; 342 default: 343 return true; 344 } 345 } 346 347 static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg) 348 { 349 switch (reg) { 350 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 351 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 352 case CY8C95X0_INTMASK: 353 case CY8C95X0_INVERT: 354 case CY8C95X0_PWMSEL: 355 case CY8C95X0_DIRECTION: 356 case CY8C95X0_DRV_PU: 357 case CY8C95X0_DRV_PD: 358 case CY8C95X0_DRV_ODH: 359 case CY8C95X0_DRV_ODL: 360 case CY8C95X0_DRV_PP_FAST: 361 case CY8C95X0_DRV_PP_SLOW: 362 case CY8C95X0_DRV_HIZ: 363 return true; 364 default: 365 return false; 366 } 367 } 368 369 static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg) 370 { 371 switch (reg) { 372 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 373 return true; 374 default: 375 return false; 376 } 377 } 378 379 static const struct reg_default cy8c95x0_reg_defaults[] = { 380 { CY8C95X0_OUTPUT_(0), GENMASK(7, 0) }, 381 { CY8C95X0_OUTPUT_(1), GENMASK(7, 0) }, 382 { CY8C95X0_OUTPUT_(2), GENMASK(7, 0) }, 383 { CY8C95X0_OUTPUT_(3), GENMASK(7, 0) }, 384 { CY8C95X0_OUTPUT_(4), GENMASK(7, 0) }, 385 { CY8C95X0_OUTPUT_(5), GENMASK(7, 0) }, 386 { CY8C95X0_OUTPUT_(6), GENMASK(7, 0) }, 387 { CY8C95X0_OUTPUT_(7), GENMASK(7, 0) }, 388 { CY8C95X0_PORTSEL, 0 }, 389 { CY8C95X0_PWMSEL, 0 }, 390 }; 391 392 static const struct regmap_config cy8c95x0_i2c_regmap = { 393 .reg_bits = 8, 394 .val_bits = 8, 395 396 .reg_defaults = cy8c95x0_reg_defaults, 397 .num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults), 398 399 .readable_reg = cy8c95x0_readable_register, 400 .writeable_reg = cy8c95x0_writeable_register, 401 .volatile_reg = cy8c95x0_volatile_register, 402 .precious_reg = cy8c95x0_precious_register, 403 404 .cache_type = REGCACHE_FLAT, 405 .max_register = CY8C95X0_COMMAND, 406 }; 407 408 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, 409 unsigned long *val, unsigned long *mask) 410 { 411 DECLARE_BITMAP(tmask, MAX_LINE); 412 DECLARE_BITMAP(tval, MAX_LINE); 413 int write_val; 414 int ret = 0; 415 int i, off = 0; 416 u8 bits; 417 418 /* Add the 4 bit gap of Gport2 */ 419 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); 420 bitmap_shift_left(tmask, tmask, 4, MAX_LINE); 421 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); 422 423 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); 424 bitmap_shift_left(tval, tval, 4, MAX_LINE); 425 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); 426 427 mutex_lock(&chip->i2c_lock); 428 for (i = 0; i < chip->nport; i++) { 429 /* Skip over unused banks */ 430 bits = bitmap_get_value8(tmask, i * BANK_SZ); 431 if (!bits) 432 continue; 433 434 switch (reg) { 435 /* Muxed registers */ 436 case CY8C95X0_INTMASK: 437 case CY8C95X0_PWMSEL: 438 case CY8C95X0_INVERT: 439 case CY8C95X0_DIRECTION: 440 case CY8C95X0_DRV_PU: 441 case CY8C95X0_DRV_PD: 442 case CY8C95X0_DRV_ODH: 443 case CY8C95X0_DRV_ODL: 444 case CY8C95X0_DRV_PP_FAST: 445 case CY8C95X0_DRV_PP_SLOW: 446 case CY8C95X0_DRV_HIZ: 447 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i); 448 if (ret < 0) 449 goto out; 450 off = reg; 451 break; 452 /* Direct access registers */ 453 case CY8C95X0_INPUT: 454 case CY8C95X0_OUTPUT: 455 case CY8C95X0_INTSTATUS: 456 off = reg + i; 457 break; 458 default: 459 ret = -EINVAL; 460 goto out; 461 } 462 463 write_val = bitmap_get_value8(tval, i * BANK_SZ); 464 465 ret = regmap_update_bits(chip->regmap, off, bits, write_val); 466 if (ret < 0) 467 goto out; 468 } 469 out: 470 mutex_unlock(&chip->i2c_lock); 471 472 if (ret < 0) 473 dev_err(chip->dev, "failed writing register %d: err %d\n", off, ret); 474 475 return ret; 476 } 477 478 static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, 479 unsigned long *val, unsigned long *mask) 480 { 481 DECLARE_BITMAP(tmask, MAX_LINE); 482 DECLARE_BITMAP(tval, MAX_LINE); 483 DECLARE_BITMAP(tmp, MAX_LINE); 484 int read_val; 485 int ret = 0; 486 int i, off = 0; 487 u8 bits; 488 489 /* Add the 4 bit gap of Gport2 */ 490 bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); 491 bitmap_shift_left(tmask, tmask, 4, MAX_LINE); 492 bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); 493 494 bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); 495 bitmap_shift_left(tval, tval, 4, MAX_LINE); 496 bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); 497 498 mutex_lock(&chip->i2c_lock); 499 for (i = 0; i < chip->nport; i++) { 500 /* Skip over unused banks */ 501 bits = bitmap_get_value8(tmask, i * BANK_SZ); 502 if (!bits) 503 continue; 504 505 switch (reg) { 506 /* Muxed registers */ 507 case CY8C95X0_INTMASK: 508 case CY8C95X0_PWMSEL: 509 case CY8C95X0_INVERT: 510 case CY8C95X0_DIRECTION: 511 case CY8C95X0_DRV_PU: 512 case CY8C95X0_DRV_PD: 513 case CY8C95X0_DRV_ODH: 514 case CY8C95X0_DRV_ODL: 515 case CY8C95X0_DRV_PP_FAST: 516 case CY8C95X0_DRV_PP_SLOW: 517 case CY8C95X0_DRV_HIZ: 518 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i); 519 if (ret < 0) 520 goto out; 521 off = reg; 522 break; 523 /* Direct access registers */ 524 case CY8C95X0_INPUT: 525 case CY8C95X0_OUTPUT: 526 case CY8C95X0_INTSTATUS: 527 off = reg + i; 528 break; 529 default: 530 ret = -EINVAL; 531 goto out; 532 } 533 534 ret = regmap_read(chip->regmap, off, &read_val); 535 if (ret < 0) 536 goto out; 537 538 read_val &= bits; 539 read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits; 540 bitmap_set_value8(tval, read_val, i * BANK_SZ); 541 } 542 543 /* Fill the 4 bit gap of Gport2 */ 544 bitmap_shift_right(tmp, tval, 4, MAX_LINE); 545 bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE); 546 547 out: 548 mutex_unlock(&chip->i2c_lock); 549 550 if (ret < 0) 551 dev_err(chip->dev, "failed reading register %d: err %d\n", off, ret); 552 553 return ret; 554 } 555 556 static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off) 557 { 558 return pinctrl_gpio_direction_input(gc, off); 559 } 560 561 static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, 562 unsigned int off, int val) 563 { 564 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 565 u8 port = cypress_get_port(chip, off); 566 u8 outreg = CY8C95X0_OUTPUT_(port); 567 u8 bit = cypress_get_pin_mask(chip, off); 568 int ret; 569 570 /* Set output level */ 571 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 572 if (ret) 573 return ret; 574 575 return pinctrl_gpio_direction_output(gc, off); 576 } 577 578 static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) 579 { 580 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 581 u8 inreg = CY8C95X0_INPUT_(cypress_get_port(chip, off)); 582 u8 bit = cypress_get_pin_mask(chip, off); 583 u32 reg_val; 584 int ret; 585 586 ret = regmap_read(chip->regmap, inreg, ®_val); 587 if (ret < 0) { 588 /* 589 * NOTE: 590 * Diagnostic already emitted; that's all we should 591 * do unless gpio_*_value_cansleep() calls become different 592 * from their nonsleeping siblings (and report faults). 593 */ 594 return 0; 595 } 596 597 return !!(reg_val & bit); 598 } 599 600 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off, 601 int val) 602 { 603 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 604 u8 outreg = CY8C95X0_OUTPUT_(cypress_get_port(chip, off)); 605 u8 bit = cypress_get_pin_mask(chip, off); 606 607 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 608 } 609 610 static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off) 611 { 612 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 613 u8 port = cypress_get_port(chip, off); 614 u8 bit = cypress_get_pin_mask(chip, off); 615 u32 reg_val; 616 int ret; 617 618 mutex_lock(&chip->i2c_lock); 619 620 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 621 if (ret < 0) 622 goto out; 623 624 ret = regmap_read(chip->regmap, CY8C95X0_DIRECTION, ®_val); 625 if (ret < 0) 626 goto out; 627 628 mutex_unlock(&chip->i2c_lock); 629 630 if (reg_val & bit) 631 return GPIO_LINE_DIRECTION_IN; 632 633 return GPIO_LINE_DIRECTION_OUT; 634 out: 635 mutex_unlock(&chip->i2c_lock); 636 return ret; 637 } 638 639 static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, 640 unsigned int off, 641 unsigned long *config) 642 { 643 enum pin_config_param param = pinconf_to_config_param(*config); 644 u8 port = cypress_get_port(chip, off); 645 u8 bit = cypress_get_pin_mask(chip, off); 646 unsigned int reg; 647 u32 reg_val; 648 u16 arg = 0; 649 int ret; 650 651 mutex_lock(&chip->i2c_lock); 652 653 /* Select port */ 654 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 655 if (ret < 0) 656 goto out; 657 658 switch (param) { 659 case PIN_CONFIG_BIAS_PULL_UP: 660 reg = CY8C95X0_DRV_PU; 661 break; 662 case PIN_CONFIG_BIAS_PULL_DOWN: 663 reg = CY8C95X0_DRV_PD; 664 break; 665 case PIN_CONFIG_BIAS_DISABLE: 666 reg = CY8C95X0_DRV_HIZ; 667 break; 668 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 669 reg = CY8C95X0_DRV_ODL; 670 break; 671 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 672 reg = CY8C95X0_DRV_ODH; 673 break; 674 case PIN_CONFIG_DRIVE_PUSH_PULL: 675 reg = CY8C95X0_DRV_PP_FAST; 676 break; 677 case PIN_CONFIG_INPUT_ENABLE: 678 reg = CY8C95X0_DIRECTION; 679 break; 680 case PIN_CONFIG_MODE_PWM: 681 reg = CY8C95X0_PWMSEL; 682 break; 683 case PIN_CONFIG_OUTPUT: 684 reg = CY8C95X0_OUTPUT_(port); 685 break; 686 case PIN_CONFIG_OUTPUT_ENABLE: 687 reg = CY8C95X0_DIRECTION; 688 break; 689 690 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 691 case PIN_CONFIG_BIAS_BUS_HOLD: 692 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 693 case PIN_CONFIG_DRIVE_STRENGTH: 694 case PIN_CONFIG_DRIVE_STRENGTH_UA: 695 case PIN_CONFIG_INPUT_DEBOUNCE: 696 case PIN_CONFIG_INPUT_SCHMITT: 697 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 698 case PIN_CONFIG_MODE_LOW_POWER: 699 case PIN_CONFIG_PERSIST_STATE: 700 case PIN_CONFIG_POWER_SOURCE: 701 case PIN_CONFIG_SKEW_DELAY: 702 case PIN_CONFIG_SLEEP_HARDWARE_STATE: 703 case PIN_CONFIG_SLEW_RATE: 704 default: 705 ret = -ENOTSUPP; 706 goto out; 707 } 708 /* 709 * Writing 1 to one of the drive mode registers will automatically 710 * clear conflicting set bits in the other drive mode registers. 711 */ 712 ret = regmap_read(chip->regmap, reg, ®_val); 713 if (reg_val & bit) 714 arg = 1; 715 716 *config = pinconf_to_config_packed(param, (u16)arg); 717 out: 718 mutex_unlock(&chip->i2c_lock); 719 720 return ret; 721 } 722 723 static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip, 724 unsigned int off, 725 unsigned long config) 726 { 727 u8 port = cypress_get_port(chip, off); 728 u8 bit = cypress_get_pin_mask(chip, off); 729 unsigned long param = pinconf_to_config_param(config); 730 unsigned int reg; 731 int ret; 732 733 mutex_lock(&chip->i2c_lock); 734 735 /* Select port */ 736 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 737 if (ret < 0) 738 goto out; 739 740 switch (param) { 741 case PIN_CONFIG_BIAS_PULL_UP: 742 __clear_bit(off, chip->push_pull); 743 reg = CY8C95X0_DRV_PU; 744 break; 745 case PIN_CONFIG_BIAS_PULL_DOWN: 746 __clear_bit(off, chip->push_pull); 747 reg = CY8C95X0_DRV_PD; 748 break; 749 case PIN_CONFIG_BIAS_DISABLE: 750 __clear_bit(off, chip->push_pull); 751 reg = CY8C95X0_DRV_HIZ; 752 break; 753 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 754 __clear_bit(off, chip->push_pull); 755 reg = CY8C95X0_DRV_ODL; 756 break; 757 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 758 __clear_bit(off, chip->push_pull); 759 reg = CY8C95X0_DRV_ODH; 760 break; 761 case PIN_CONFIG_DRIVE_PUSH_PULL: 762 __set_bit(off, chip->push_pull); 763 reg = CY8C95X0_DRV_PP_FAST; 764 break; 765 case PIN_CONFIG_MODE_PWM: 766 reg = CY8C95X0_PWMSEL; 767 break; 768 default: 769 ret = -ENOTSUPP; 770 goto out; 771 } 772 /* 773 * Writing 1 to one of the drive mode registers will automatically 774 * clear conflicting set bits in the other drive mode registers. 775 */ 776 ret = regmap_write_bits(chip->regmap, reg, bit, bit); 777 778 out: 779 mutex_unlock(&chip->i2c_lock); 780 return ret; 781 } 782 783 static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc, 784 unsigned long *mask, unsigned long *bits) 785 { 786 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 787 788 return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask); 789 } 790 791 static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc, 792 unsigned long *mask, unsigned long *bits) 793 { 794 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 795 796 cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask); 797 } 798 799 static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc) 800 { 801 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 802 struct device *dev = chip->dev; 803 int ret; 804 805 ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin); 806 if (ret) 807 dev_err(dev, "failed to add GPIO pin range\n"); 808 809 return ret; 810 } 811 812 static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip) 813 { 814 struct gpio_chip *gc = &chip->gpio_chip; 815 816 gc->request = gpiochip_generic_request; 817 gc->free = gpiochip_generic_free; 818 gc->direction_input = cy8c95x0_gpio_direction_input; 819 gc->direction_output = cy8c95x0_gpio_direction_output; 820 gc->get = cy8c95x0_gpio_get_value; 821 gc->set = cy8c95x0_gpio_set_value; 822 gc->get_direction = cy8c95x0_gpio_get_direction; 823 gc->get_multiple = cy8c95x0_gpio_get_multiple; 824 gc->set_multiple = cy8c95x0_gpio_set_multiple; 825 gc->set_config = gpiochip_generic_config, 826 gc->can_sleep = true; 827 gc->add_pin_ranges = cy8c95x0_add_pin_ranges; 828 829 gc->base = -1; 830 gc->ngpio = chip->tpin; 831 832 gc->parent = chip->dev; 833 gc->owner = THIS_MODULE; 834 gc->names = NULL; 835 836 gc->label = dev_name(chip->dev); 837 838 return devm_gpiochip_add_data(chip->dev, gc, chip); 839 } 840 841 static void cy8c95x0_irq_mask(struct irq_data *d) 842 { 843 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 844 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 845 irq_hw_number_t hwirq = irqd_to_hwirq(d); 846 847 set_bit(hwirq, chip->irq_mask); 848 gpiochip_disable_irq(gc, hwirq); 849 } 850 851 static void cy8c95x0_irq_unmask(struct irq_data *d) 852 { 853 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 854 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 855 irq_hw_number_t hwirq = irqd_to_hwirq(d); 856 857 gpiochip_enable_irq(gc, hwirq); 858 clear_bit(hwirq, chip->irq_mask); 859 } 860 861 static void cy8c95x0_irq_bus_lock(struct irq_data *d) 862 { 863 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 864 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 865 866 mutex_lock(&chip->irq_lock); 867 } 868 869 static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d) 870 { 871 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 872 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 873 DECLARE_BITMAP(ones, MAX_LINE); 874 DECLARE_BITMAP(irq_mask, MAX_LINE); 875 DECLARE_BITMAP(reg_direction, MAX_LINE); 876 877 bitmap_fill(ones, MAX_LINE); 878 879 cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones); 880 881 /* Switch direction to input if needed */ 882 cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask); 883 bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE); 884 bitmap_complement(irq_mask, irq_mask, MAX_LINE); 885 886 /* Look for any newly setup interrupt */ 887 cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask); 888 889 mutex_unlock(&chip->irq_lock); 890 } 891 892 static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type) 893 { 894 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 895 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 896 irq_hw_number_t hwirq = irqd_to_hwirq(d); 897 unsigned int trig_type; 898 899 switch (type) { 900 case IRQ_TYPE_EDGE_RISING: 901 case IRQ_TYPE_EDGE_FALLING: 902 case IRQ_TYPE_EDGE_BOTH: 903 trig_type = type; 904 break; 905 case IRQ_TYPE_LEVEL_HIGH: 906 trig_type = IRQ_TYPE_EDGE_RISING; 907 break; 908 case IRQ_TYPE_LEVEL_LOW: 909 trig_type = IRQ_TYPE_EDGE_FALLING; 910 break; 911 default: 912 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type); 913 return -EINVAL; 914 } 915 916 assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING); 917 assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING); 918 assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW); 919 assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH); 920 921 return 0; 922 } 923 924 static void cy8c95x0_irq_shutdown(struct irq_data *d) 925 { 926 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 927 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 928 irq_hw_number_t hwirq = irqd_to_hwirq(d); 929 930 clear_bit(hwirq, chip->irq_trig_raise); 931 clear_bit(hwirq, chip->irq_trig_fall); 932 clear_bit(hwirq, chip->irq_trig_low); 933 clear_bit(hwirq, chip->irq_trig_high); 934 } 935 936 static const struct irq_chip cy8c95x0_irqchip = { 937 .name = "cy8c95x0-irq", 938 .irq_mask = cy8c95x0_irq_mask, 939 .irq_unmask = cy8c95x0_irq_unmask, 940 .irq_bus_lock = cy8c95x0_irq_bus_lock, 941 .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock, 942 .irq_set_type = cy8c95x0_irq_set_type, 943 .irq_shutdown = cy8c95x0_irq_shutdown, 944 .flags = IRQCHIP_IMMUTABLE, 945 GPIOCHIP_IRQ_RESOURCE_HELPERS, 946 }; 947 948 static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending) 949 { 950 DECLARE_BITMAP(ones, MAX_LINE); 951 DECLARE_BITMAP(cur_stat, MAX_LINE); 952 DECLARE_BITMAP(new_stat, MAX_LINE); 953 DECLARE_BITMAP(trigger, MAX_LINE); 954 955 bitmap_fill(ones, MAX_LINE); 956 957 /* Read the current interrupt status from the device */ 958 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones)) 959 return false; 960 961 /* Check latched inputs */ 962 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger)) 963 return false; 964 965 /* Apply filter for rising/falling edge selection */ 966 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, 967 cur_stat, MAX_LINE); 968 969 bitmap_and(pending, new_stat, trigger, MAX_LINE); 970 971 return !bitmap_empty(pending, MAX_LINE); 972 } 973 974 static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid) 975 { 976 struct cy8c95x0_pinctrl *chip = devid; 977 struct gpio_chip *gc = &chip->gpio_chip; 978 DECLARE_BITMAP(pending, MAX_LINE); 979 int nested_irq, level; 980 bool ret; 981 982 ret = cy8c95x0_irq_pending(chip, pending); 983 if (!ret) 984 return IRQ_RETVAL(0); 985 986 ret = 0; 987 for_each_set_bit(level, pending, MAX_LINE) { 988 /* Already accounted for 4bit gap in GPort2 */ 989 nested_irq = irq_find_mapping(gc->irq.domain, level); 990 991 if (unlikely(nested_irq <= 0)) { 992 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 993 continue; 994 } 995 996 if (test_bit(level, chip->irq_trig_low)) 997 while (!cy8c95x0_gpio_get_value(gc, level)) 998 handle_nested_irq(nested_irq); 999 else if (test_bit(level, chip->irq_trig_high)) 1000 while (cy8c95x0_gpio_get_value(gc, level)) 1001 handle_nested_irq(nested_irq); 1002 else 1003 handle_nested_irq(nested_irq); 1004 1005 ret = 1; 1006 } 1007 1008 return IRQ_RETVAL(ret); 1009 } 1010 1011 static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 1012 { 1013 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1014 1015 return chip->tpin; 1016 } 1017 1018 static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 1019 unsigned int group) 1020 { 1021 return cy8c95x0_groups[group]; 1022 } 1023 1024 static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 1025 unsigned int group, 1026 const unsigned int **pins, 1027 unsigned int *num_pins) 1028 { 1029 *pins = &cy8c9560_pins[group].number; 1030 *num_pins = 1; 1031 return 0; 1032 } 1033 1034 static const char *cy8c95x0_get_fname(unsigned int selector) 1035 { 1036 if (selector == 0) 1037 return "gpio"; 1038 else 1039 return "pwm"; 1040 } 1041 1042 static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1043 unsigned int pin) 1044 { 1045 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1046 DECLARE_BITMAP(mask, MAX_LINE); 1047 DECLARE_BITMAP(pwm, MAX_LINE); 1048 1049 bitmap_zero(mask, MAX_LINE); 1050 __set_bit(pin, mask); 1051 1052 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) { 1053 seq_puts(s, "not available"); 1054 return; 1055 } 1056 1057 seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm))); 1058 } 1059 1060 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = { 1061 .get_groups_count = cy8c95x0_pinctrl_get_groups_count, 1062 .get_group_name = cy8c95x0_pinctrl_get_group_name, 1063 .get_group_pins = cy8c95x0_pinctrl_get_group_pins, 1064 #ifdef CONFIG_OF 1065 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1066 .dt_free_map = pinconf_generic_dt_free_map, 1067 #endif 1068 .pin_dbg_show = cy8c95x0_pin_dbg_show, 1069 }; 1070 1071 static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector) 1072 { 1073 return cy8c95x0_get_fname(selector); 1074 } 1075 1076 static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev) 1077 { 1078 return 2; 1079 } 1080 1081 static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, 1082 const char * const **groups, 1083 unsigned int * const num_groups) 1084 { 1085 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1086 1087 *groups = cy8c95x0_groups; 1088 *num_groups = chip->tpin; 1089 return 0; 1090 } 1091 1092 static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode) 1093 { 1094 u8 port = cypress_get_port(chip, off); 1095 u8 bit = cypress_get_pin_mask(chip, off); 1096 int ret; 1097 1098 /* Select port */ 1099 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 1100 if (ret < 0) 1101 return ret; 1102 1103 return regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, mode ? bit : 0); 1104 } 1105 1106 static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, 1107 unsigned int selector, unsigned int group) 1108 { 1109 u8 port = cypress_get_port(chip, group); 1110 u8 bit = cypress_get_pin_mask(chip, group); 1111 int ret; 1112 1113 ret = cy8c95x0_set_mode(chip, group, selector); 1114 if (ret < 0) 1115 return ret; 1116 1117 if (selector == 0) 1118 return 0; 1119 1120 /* Set direction to output & set output to 1 so that PWM can work */ 1121 ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit); 1122 if (ret < 0) 1123 return ret; 1124 1125 return regmap_write_bits(chip->regmap, CY8C95X0_OUTPUT_(port), bit, bit); 1126 } 1127 1128 static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, 1129 unsigned int group) 1130 { 1131 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1132 int ret; 1133 1134 mutex_lock(&chip->i2c_lock); 1135 ret = cy8c95x0_pinmux_mode(chip, selector, group); 1136 mutex_unlock(&chip->i2c_lock); 1137 1138 return ret; 1139 } 1140 1141 static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, 1142 struct pinctrl_gpio_range *range, 1143 unsigned int pin) 1144 { 1145 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1146 int ret; 1147 1148 mutex_lock(&chip->i2c_lock); 1149 ret = cy8c95x0_set_mode(chip, pin, false); 1150 mutex_unlock(&chip->i2c_lock); 1151 1152 return ret; 1153 } 1154 1155 static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, 1156 unsigned int pin, bool input) 1157 { 1158 u8 port = cypress_get_port(chip, pin); 1159 u8 bit = cypress_get_pin_mask(chip, pin); 1160 int ret; 1161 1162 /* Select port... */ 1163 ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); 1164 if (ret) 1165 return ret; 1166 1167 /* ...then direction */ 1168 ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, input ? bit : 0); 1169 if (ret) 1170 return ret; 1171 1172 /* 1173 * Disable driving the pin by forcing it to HighZ. Only setting 1174 * the direction register isn't sufficient in Push-Pull mode. 1175 */ 1176 if (input && test_bit(pin, chip->push_pull)) { 1177 ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit); 1178 if (ret) 1179 return ret; 1180 1181 __clear_bit(pin, chip->push_pull); 1182 } 1183 1184 return 0; 1185 } 1186 1187 static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, 1188 struct pinctrl_gpio_range *range, 1189 unsigned int pin, bool input) 1190 { 1191 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1192 int ret; 1193 1194 mutex_lock(&chip->i2c_lock); 1195 ret = cy8c95x0_pinmux_direction(chip, pin, input); 1196 mutex_unlock(&chip->i2c_lock); 1197 1198 return ret; 1199 } 1200 1201 static const struct pinmux_ops cy8c95x0_pmxops = { 1202 .get_functions_count = cy8c95x0_get_functions_count, 1203 .get_function_name = cy8c95x0_get_function_name, 1204 .get_function_groups = cy8c95x0_get_function_groups, 1205 .set_mux = cy8c95x0_set_mux, 1206 .gpio_request_enable = cy8c95x0_gpio_request_enable, 1207 .gpio_set_direction = cy8c95x0_gpio_set_direction, 1208 .strict = true, 1209 }; 1210 1211 static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 1212 unsigned long *config) 1213 { 1214 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1215 1216 return cy8c95x0_gpio_get_pincfg(chip, pin, config); 1217 } 1218 1219 static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1220 unsigned long *configs, unsigned int num_configs) 1221 { 1222 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1223 int ret = 0; 1224 int i; 1225 1226 for (i = 0; i < num_configs; i++) { 1227 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]); 1228 if (ret) 1229 return ret; 1230 } 1231 1232 return ret; 1233 } 1234 1235 static const struct pinconf_ops cy8c95x0_pinconf_ops = { 1236 .pin_config_get = cy8c95x0_pinconf_get, 1237 .pin_config_set = cy8c95x0_pinconf_set, 1238 .is_generic = true, 1239 }; 1240 1241 static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) 1242 { 1243 struct gpio_irq_chip *girq = &chip->gpio_chip.irq; 1244 DECLARE_BITMAP(pending_irqs, MAX_LINE); 1245 int ret; 1246 1247 mutex_init(&chip->irq_lock); 1248 1249 bitmap_zero(pending_irqs, MAX_LINE); 1250 1251 /* Read IRQ status register to clear all pending interrupts */ 1252 ret = cy8c95x0_irq_pending(chip, pending_irqs); 1253 if (ret) { 1254 dev_err(chip->dev, "failed to clear irq status register\n"); 1255 return ret; 1256 } 1257 1258 /* Mask all interrupts */ 1259 bitmap_fill(chip->irq_mask, MAX_LINE); 1260 1261 gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip); 1262 1263 /* This will let us handle the parent IRQ in the driver */ 1264 girq->parent_handler = NULL; 1265 girq->num_parents = 0; 1266 girq->parents = NULL; 1267 girq->default_type = IRQ_TYPE_NONE; 1268 girq->handler = handle_simple_irq; 1269 girq->threaded = true; 1270 1271 ret = devm_request_threaded_irq(chip->dev, irq, 1272 NULL, cy8c95x0_irq_handler, 1273 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH, 1274 dev_name(chip->dev), chip); 1275 if (ret) { 1276 dev_err(chip->dev, "failed to request irq %d\n", irq); 1277 return ret; 1278 } 1279 dev_info(chip->dev, "Registered threaded IRQ\n"); 1280 1281 return 0; 1282 } 1283 1284 static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip) 1285 { 1286 struct pinctrl_desc *pd = &chip->pinctrl_desc; 1287 1288 pd->pctlops = &cy8c95x0_pinctrl_ops; 1289 pd->confops = &cy8c95x0_pinconf_ops; 1290 pd->pmxops = &cy8c95x0_pmxops; 1291 pd->name = dev_name(chip->dev); 1292 pd->pins = cy8c9560_pins; 1293 pd->npins = chip->tpin; 1294 pd->owner = THIS_MODULE; 1295 1296 chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip); 1297 if (IS_ERR(chip->pctldev)) 1298 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev), 1299 "can't register controller\n"); 1300 1301 return 0; 1302 } 1303 1304 static int cy8c95x0_detect(struct i2c_client *client, 1305 struct i2c_board_info *info) 1306 { 1307 struct i2c_adapter *adapter = client->adapter; 1308 int ret; 1309 const char *name; 1310 1311 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1312 return -ENODEV; 1313 1314 ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID); 1315 if (ret < 0) 1316 return ret; 1317 switch (ret & GENMASK(7, 4)) { 1318 case 0x20: 1319 name = cy8c95x0_id[0].name; 1320 break; 1321 case 0x40: 1322 name = cy8c95x0_id[1].name; 1323 break; 1324 case 0x60: 1325 name = cy8c95x0_id[2].name; 1326 break; 1327 default: 1328 return -ENODEV; 1329 } 1330 1331 dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr); 1332 strscpy(info->type, name, I2C_NAME_SIZE); 1333 1334 return 0; 1335 } 1336 1337 static int cy8c95x0_probe(struct i2c_client *client) 1338 { 1339 struct cy8c95x0_pinctrl *chip; 1340 struct regulator *reg; 1341 int ret; 1342 1343 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 1344 if (!chip) 1345 return -ENOMEM; 1346 1347 chip->dev = &client->dev; 1348 1349 /* Set the device type */ 1350 chip->driver_data = (uintptr_t)i2c_get_match_data(client); 1351 if (!chip->driver_data) 1352 return -ENODEV; 1353 1354 i2c_set_clientdata(client, chip); 1355 1356 chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK; 1357 chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ); 1358 1359 switch (chip->tpin) { 1360 case 20: 1361 strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE); 1362 break; 1363 case 40: 1364 strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE); 1365 break; 1366 case 60: 1367 strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE); 1368 break; 1369 default: 1370 return -ENODEV; 1371 } 1372 1373 reg = devm_regulator_get(&client->dev, "vdd"); 1374 if (IS_ERR(reg)) { 1375 if (PTR_ERR(reg) == -EPROBE_DEFER) 1376 return -EPROBE_DEFER; 1377 } else { 1378 ret = regulator_enable(reg); 1379 if (ret) { 1380 dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret); 1381 return ret; 1382 } 1383 chip->regulator = reg; 1384 } 1385 1386 /* bring the chip out of reset if reset pin is provided */ 1387 chip->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH); 1388 if (IS_ERR(chip->gpio_reset)) { 1389 ret = dev_err_probe(chip->dev, PTR_ERR(chip->gpio_reset), 1390 "Failed to get GPIO 'reset'\n"); 1391 goto err_exit; 1392 } else if (chip->gpio_reset) { 1393 usleep_range(1000, 2000); 1394 gpiod_set_value_cansleep(chip->gpio_reset, 0); 1395 usleep_range(250000, 300000); 1396 1397 gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET"); 1398 } 1399 1400 chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap); 1401 if (IS_ERR(chip->regmap)) { 1402 ret = PTR_ERR(chip->regmap); 1403 goto err_exit; 1404 } 1405 1406 bitmap_zero(chip->push_pull, MAX_LINE); 1407 bitmap_zero(chip->shiftmask, MAX_LINE); 1408 bitmap_set(chip->shiftmask, 0, 20); 1409 mutex_init(&chip->i2c_lock); 1410 1411 if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) { 1412 ret = cy8c95x0_acpi_get_irq(&client->dev); 1413 if (ret > 0) 1414 client->irq = ret; 1415 } 1416 1417 if (client->irq) { 1418 ret = cy8c95x0_irq_setup(chip, client->irq); 1419 if (ret) 1420 goto err_exit; 1421 } 1422 1423 ret = cy8c95x0_setup_pinctrl(chip); 1424 if (ret) 1425 goto err_exit; 1426 1427 ret = cy8c95x0_setup_gpiochip(chip); 1428 if (ret) 1429 goto err_exit; 1430 1431 return 0; 1432 1433 err_exit: 1434 if (!IS_ERR_OR_NULL(chip->regulator)) 1435 regulator_disable(chip->regulator); 1436 return ret; 1437 } 1438 1439 static void cy8c95x0_remove(struct i2c_client *client) 1440 { 1441 struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client); 1442 1443 if (!IS_ERR_OR_NULL(chip->regulator)) 1444 regulator_disable(chip->regulator); 1445 } 1446 1447 static const struct acpi_device_id cy8c95x0_acpi_ids[] = { 1448 { "INT3490", 40, }, 1449 { } 1450 }; 1451 MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids); 1452 1453 static struct i2c_driver cy8c95x0_driver = { 1454 .driver = { 1455 .name = "cy8c95x0-pinctrl", 1456 .of_match_table = cy8c95x0_dt_ids, 1457 .acpi_match_table = cy8c95x0_acpi_ids, 1458 }, 1459 .probe = cy8c95x0_probe, 1460 .remove = cy8c95x0_remove, 1461 .id_table = cy8c95x0_id, 1462 .detect = cy8c95x0_detect, 1463 }; 1464 module_i2c_driver(cy8c95x0_driver); 1465 1466 MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>"); 1467 MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>"); 1468 MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0"); 1469 MODULE_LICENSE("GPL"); 1470