1 /* 2 * at91 pinctrl driver based on at91 pinmux core 3 * 4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 5 * 6 * Under GPLv2 only 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/err.h> 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 #include <linux/slab.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/io.h> 22 #include <linux/gpio.h> 23 #include <linux/pinctrl/machine.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 /* Since we request GPIOs from ourself */ 28 #include <linux/pinctrl/consumer.h> 29 30 #include <asm/mach/irq.h> 31 32 #include <mach/hardware.h> 33 #include <mach/at91_pio.h> 34 35 #include "core.h" 36 37 #define MAX_NB_GPIO_PER_BANK 32 38 39 struct at91_pinctrl_mux_ops; 40 41 struct at91_gpio_chip { 42 struct gpio_chip chip; 43 struct pinctrl_gpio_range range; 44 struct at91_gpio_chip *next; /* Bank sharing same clock */ 45 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ 46 int pioc_virq; /* PIO bank Linux virtual interrupt */ 47 int pioc_idx; /* PIO bank index */ 48 void __iomem *regbase; /* PIO bank virtual address */ 49 struct clk *clock; /* associated clock */ 50 struct irq_domain *domain; /* associated irq domain */ 51 struct at91_pinctrl_mux_ops *ops; /* ops */ 52 }; 53 54 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) 55 56 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; 57 58 static int gpio_banks; 59 60 #define PULL_UP (1 << 0) 61 #define MULTI_DRIVE (1 << 1) 62 #define DEGLITCH (1 << 2) 63 #define PULL_DOWN (1 << 3) 64 #define DIS_SCHMIT (1 << 4) 65 #define DEBOUNCE (1 << 16) 66 #define DEBOUNCE_VAL_SHIFT 17 67 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) 68 69 /** 70 * struct at91_pmx_func - describes AT91 pinmux functions 71 * @name: the name of this specific function 72 * @groups: corresponding pin groups 73 * @ngroups: the number of groups 74 */ 75 struct at91_pmx_func { 76 const char *name; 77 const char **groups; 78 unsigned ngroups; 79 }; 80 81 enum at91_mux { 82 AT91_MUX_GPIO = 0, 83 AT91_MUX_PERIPH_A = 1, 84 AT91_MUX_PERIPH_B = 2, 85 AT91_MUX_PERIPH_C = 3, 86 AT91_MUX_PERIPH_D = 4, 87 }; 88 89 /** 90 * struct at91_pmx_pin - describes an At91 pin mux 91 * @bank: the bank of the pin 92 * @pin: the pin number in the @bank 93 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. 94 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... 95 */ 96 struct at91_pmx_pin { 97 uint32_t bank; 98 uint32_t pin; 99 enum at91_mux mux; 100 unsigned long conf; 101 }; 102 103 /** 104 * struct at91_pin_group - describes an At91 pin group 105 * @name: the name of this specific pin group 106 * @pins_conf: the mux mode for each pin in this group. The size of this 107 * array is the same as pins. 108 * @pins: an array of discrete physical pins used in this group, taken 109 * from the driver-local pin enumeration space 110 * @npins: the number of pins in this group array, i.e. the number of 111 * elements in .pins so we can iterate over that array 112 */ 113 struct at91_pin_group { 114 const char *name; 115 struct at91_pmx_pin *pins_conf; 116 unsigned int *pins; 117 unsigned npins; 118 }; 119 120 /** 121 * struct at91_pinctrl_mux_ops - describes an At91 mux ops group 122 * on new IP with support for periph C and D the way to mux in 123 * periph A and B has changed 124 * So provide the right call back 125 * if not present means the IP does not support it 126 * @get_periph: return the periph mode configured 127 * @mux_A_periph: mux as periph A 128 * @mux_B_periph: mux as periph B 129 * @mux_C_periph: mux as periph C 130 * @mux_D_periph: mux as periph D 131 * @get_deglitch: get deglitch status 132 * @set_deglitch: enable/disable deglitch 133 * @get_debounce: get debounce status 134 * @set_debounce: enable/disable debounce 135 * @get_pulldown: get pulldown status 136 * @set_pulldown: enable/disable pulldown 137 * @get_schmitt_trig: get schmitt trigger status 138 * @disable_schmitt_trig: disable schmitt trigger 139 * @irq_type: return irq type 140 */ 141 struct at91_pinctrl_mux_ops { 142 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); 143 void (*mux_A_periph)(void __iomem *pio, unsigned mask); 144 void (*mux_B_periph)(void __iomem *pio, unsigned mask); 145 void (*mux_C_periph)(void __iomem *pio, unsigned mask); 146 void (*mux_D_periph)(void __iomem *pio, unsigned mask); 147 bool (*get_deglitch)(void __iomem *pio, unsigned pin); 148 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on); 149 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); 150 void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div); 151 bool (*get_pulldown)(void __iomem *pio, unsigned pin); 152 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on); 153 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); 154 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); 155 /* irq */ 156 int (*irq_type)(struct irq_data *d, unsigned type); 157 }; 158 159 static int gpio_irq_type(struct irq_data *d, unsigned type); 160 static int alt_gpio_irq_type(struct irq_data *d, unsigned type); 161 162 struct at91_pinctrl { 163 struct device *dev; 164 struct pinctrl_dev *pctl; 165 166 int nbanks; 167 168 uint32_t *mux_mask; 169 int nmux; 170 171 struct at91_pmx_func *functions; 172 int nfunctions; 173 174 struct at91_pin_group *groups; 175 int ngroups; 176 177 struct at91_pinctrl_mux_ops *ops; 178 }; 179 180 static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name( 181 const struct at91_pinctrl *info, 182 const char *name) 183 { 184 const struct at91_pin_group *grp = NULL; 185 int i; 186 187 for (i = 0; i < info->ngroups; i++) { 188 if (strcmp(info->groups[i].name, name)) 189 continue; 190 191 grp = &info->groups[i]; 192 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); 193 break; 194 } 195 196 return grp; 197 } 198 199 static int at91_get_groups_count(struct pinctrl_dev *pctldev) 200 { 201 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 202 203 return info->ngroups; 204 } 205 206 static const char *at91_get_group_name(struct pinctrl_dev *pctldev, 207 unsigned selector) 208 { 209 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 210 211 return info->groups[selector].name; 212 } 213 214 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 215 const unsigned **pins, 216 unsigned *npins) 217 { 218 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 219 220 if (selector >= info->ngroups) 221 return -EINVAL; 222 223 *pins = info->groups[selector].pins; 224 *npins = info->groups[selector].npins; 225 226 return 0; 227 } 228 229 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 230 unsigned offset) 231 { 232 seq_printf(s, "%s", dev_name(pctldev->dev)); 233 } 234 235 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, 236 struct device_node *np, 237 struct pinctrl_map **map, unsigned *num_maps) 238 { 239 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 240 const struct at91_pin_group *grp; 241 struct pinctrl_map *new_map; 242 struct device_node *parent; 243 int map_num = 1; 244 int i; 245 246 /* 247 * first find the group of this node and check if we need create 248 * config maps for pins 249 */ 250 grp = at91_pinctrl_find_group_by_name(info, np->name); 251 if (!grp) { 252 dev_err(info->dev, "unable to find group for node %s\n", 253 np->name); 254 return -EINVAL; 255 } 256 257 map_num += grp->npins; 258 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL); 259 if (!new_map) 260 return -ENOMEM; 261 262 *map = new_map; 263 *num_maps = map_num; 264 265 /* create mux map */ 266 parent = of_get_parent(np); 267 if (!parent) { 268 devm_kfree(pctldev->dev, new_map); 269 return -EINVAL; 270 } 271 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 272 new_map[0].data.mux.function = parent->name; 273 new_map[0].data.mux.group = np->name; 274 of_node_put(parent); 275 276 /* create config map */ 277 new_map++; 278 for (i = 0; i < grp->npins; i++) { 279 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 280 new_map[i].data.configs.group_or_pin = 281 pin_get_name(pctldev, grp->pins[i]); 282 new_map[i].data.configs.configs = &grp->pins_conf[i].conf; 283 new_map[i].data.configs.num_configs = 1; 284 } 285 286 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 287 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 288 289 return 0; 290 } 291 292 static void at91_dt_free_map(struct pinctrl_dev *pctldev, 293 struct pinctrl_map *map, unsigned num_maps) 294 { 295 } 296 297 static struct pinctrl_ops at91_pctrl_ops = { 298 .get_groups_count = at91_get_groups_count, 299 .get_group_name = at91_get_group_name, 300 .get_group_pins = at91_get_group_pins, 301 .pin_dbg_show = at91_pin_dbg_show, 302 .dt_node_to_map = at91_dt_node_to_map, 303 .dt_free_map = at91_dt_free_map, 304 }; 305 306 static void __iomem * pin_to_controller(struct at91_pinctrl *info, 307 unsigned int bank) 308 { 309 return gpio_chips[bank]->regbase; 310 } 311 312 static inline int pin_to_bank(unsigned pin) 313 { 314 return pin /= MAX_NB_GPIO_PER_BANK; 315 } 316 317 static unsigned pin_to_mask(unsigned int pin) 318 { 319 return 1 << pin; 320 } 321 322 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) 323 { 324 writel_relaxed(mask, pio + PIO_IDR); 325 } 326 327 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) 328 { 329 return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1; 330 } 331 332 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) 333 { 334 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); 335 } 336 337 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) 338 { 339 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; 340 } 341 342 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) 343 { 344 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); 345 } 346 347 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) 348 { 349 writel_relaxed(mask, pio + PIO_ASR); 350 } 351 352 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) 353 { 354 writel_relaxed(mask, pio + PIO_BSR); 355 } 356 357 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) 358 { 359 360 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, 361 pio + PIO_ABCDSR1); 362 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 363 pio + PIO_ABCDSR2); 364 } 365 366 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) 367 { 368 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, 369 pio + PIO_ABCDSR1); 370 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, 371 pio + PIO_ABCDSR2); 372 } 373 374 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) 375 { 376 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); 377 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 378 } 379 380 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) 381 { 382 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); 383 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 384 } 385 386 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) 387 { 388 unsigned select; 389 390 if (readl_relaxed(pio + PIO_PSR) & mask) 391 return AT91_MUX_GPIO; 392 393 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); 394 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); 395 396 return select + 1; 397 } 398 399 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) 400 { 401 unsigned select; 402 403 if (readl_relaxed(pio + PIO_PSR) & mask) 404 return AT91_MUX_GPIO; 405 406 select = readl_relaxed(pio + PIO_ABSR) & mask; 407 408 return select + 1; 409 } 410 411 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) 412 { 413 return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1; 414 } 415 416 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 417 { 418 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 419 } 420 421 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 422 { 423 if (is_on) 424 __raw_writel(mask, pio + PIO_IFSCDR); 425 at91_mux_set_deglitch(pio, mask, is_on); 426 } 427 428 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) 429 { 430 *div = __raw_readl(pio + PIO_SCDR); 431 432 return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1; 433 } 434 435 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, 436 bool is_on, u32 div) 437 { 438 if (is_on) { 439 __raw_writel(mask, pio + PIO_IFSCER); 440 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); 441 __raw_writel(mask, pio + PIO_IFER); 442 } else { 443 __raw_writel(mask, pio + PIO_IFDR); 444 } 445 } 446 447 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) 448 { 449 return (__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1; 450 } 451 452 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) 453 { 454 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); 455 } 456 457 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) 458 { 459 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); 460 } 461 462 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) 463 { 464 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; 465 } 466 467 static struct at91_pinctrl_mux_ops at91rm9200_ops = { 468 .get_periph = at91_mux_get_periph, 469 .mux_A_periph = at91_mux_set_A_periph, 470 .mux_B_periph = at91_mux_set_B_periph, 471 .get_deglitch = at91_mux_get_deglitch, 472 .set_deglitch = at91_mux_set_deglitch, 473 .irq_type = gpio_irq_type, 474 }; 475 476 static struct at91_pinctrl_mux_ops at91sam9x5_ops = { 477 .get_periph = at91_mux_pio3_get_periph, 478 .mux_A_periph = at91_mux_pio3_set_A_periph, 479 .mux_B_periph = at91_mux_pio3_set_B_periph, 480 .mux_C_periph = at91_mux_pio3_set_C_periph, 481 .mux_D_periph = at91_mux_pio3_set_D_periph, 482 .get_deglitch = at91_mux_get_deglitch, 483 .set_deglitch = at91_mux_pio3_set_deglitch, 484 .get_debounce = at91_mux_pio3_get_debounce, 485 .set_debounce = at91_mux_pio3_set_debounce, 486 .get_pulldown = at91_mux_pio3_get_pulldown, 487 .set_pulldown = at91_mux_pio3_set_pulldown, 488 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 489 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 490 .irq_type = alt_gpio_irq_type, 491 }; 492 493 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) 494 { 495 if (pin->mux) { 496 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n", 497 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); 498 } else { 499 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n", 500 pin->bank + 'A', pin->pin, pin->conf); 501 } 502 } 503 504 static int pin_check_config(struct at91_pinctrl *info, const char* name, 505 int index, const struct at91_pmx_pin *pin) 506 { 507 int mux; 508 509 /* check if it's a valid config */ 510 if (pin->bank >= info->nbanks) { 511 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", 512 name, index, pin->bank, info->nbanks); 513 return -EINVAL; 514 } 515 516 if (pin->pin >= MAX_NB_GPIO_PER_BANK) { 517 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", 518 name, index, pin->pin, MAX_NB_GPIO_PER_BANK); 519 return -EINVAL; 520 } 521 522 if (!pin->mux) 523 return 0; 524 525 mux = pin->mux - 1; 526 527 if (mux >= info->nmux) { 528 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", 529 name, index, mux, info->nmux); 530 return -EINVAL; 531 } 532 533 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { 534 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", 535 name, index, mux, pin->bank + 'A', pin->pin); 536 return -EINVAL; 537 } 538 539 return 0; 540 } 541 542 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) 543 { 544 writel_relaxed(mask, pio + PIO_PDR); 545 } 546 547 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) 548 { 549 writel_relaxed(mask, pio + PIO_PER); 550 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); 551 } 552 553 static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 554 unsigned group) 555 { 556 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 557 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 558 const struct at91_pmx_pin *pin; 559 uint32_t npins = info->groups[group].npins; 560 int i, ret; 561 unsigned mask; 562 void __iomem *pio; 563 564 dev_dbg(info->dev, "enable function %s group %s\n", 565 info->functions[selector].name, info->groups[group].name); 566 567 /* first check that all the pins of the group are valid with a valid 568 * paramter */ 569 for (i = 0; i < npins; i++) { 570 pin = &pins_conf[i]; 571 ret = pin_check_config(info, info->groups[group].name, i, pin); 572 if (ret) 573 return ret; 574 } 575 576 for (i = 0; i < npins; i++) { 577 pin = &pins_conf[i]; 578 at91_pin_dbg(info->dev, pin); 579 pio = pin_to_controller(info, pin->bank); 580 mask = pin_to_mask(pin->pin); 581 at91_mux_disable_interrupt(pio, mask); 582 switch(pin->mux) { 583 case AT91_MUX_GPIO: 584 at91_mux_gpio_enable(pio, mask, 1); 585 break; 586 case AT91_MUX_PERIPH_A: 587 info->ops->mux_A_periph(pio, mask); 588 break; 589 case AT91_MUX_PERIPH_B: 590 info->ops->mux_B_periph(pio, mask); 591 break; 592 case AT91_MUX_PERIPH_C: 593 if (!info->ops->mux_C_periph) 594 return -EINVAL; 595 info->ops->mux_C_periph(pio, mask); 596 break; 597 case AT91_MUX_PERIPH_D: 598 if (!info->ops->mux_D_periph) 599 return -EINVAL; 600 info->ops->mux_D_periph(pio, mask); 601 break; 602 } 603 if (pin->mux) 604 at91_mux_gpio_disable(pio, mask); 605 } 606 607 return 0; 608 } 609 610 static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, 611 unsigned group) 612 { 613 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 614 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 615 const struct at91_pmx_pin *pin; 616 uint32_t npins = info->groups[group].npins; 617 int i; 618 unsigned mask; 619 void __iomem *pio; 620 621 for (i = 0; i < npins; i++) { 622 pin = &pins_conf[i]; 623 at91_pin_dbg(info->dev, pin); 624 pio = pin_to_controller(info, pin->bank); 625 mask = pin_to_mask(pin->pin); 626 at91_mux_gpio_enable(pio, mask, 1); 627 } 628 } 629 630 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 631 { 632 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 633 634 return info->nfunctions; 635 } 636 637 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, 638 unsigned selector) 639 { 640 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 641 642 return info->functions[selector].name; 643 } 644 645 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 646 const char * const **groups, 647 unsigned * const num_groups) 648 { 649 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 650 651 *groups = info->functions[selector].groups; 652 *num_groups = info->functions[selector].ngroups; 653 654 return 0; 655 } 656 657 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, 658 struct pinctrl_gpio_range *range, 659 unsigned offset) 660 { 661 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 662 struct at91_gpio_chip *at91_chip; 663 struct gpio_chip *chip; 664 unsigned mask; 665 666 if (!range) { 667 dev_err(npct->dev, "invalid range\n"); 668 return -EINVAL; 669 } 670 if (!range->gc) { 671 dev_err(npct->dev, "missing GPIO chip in range\n"); 672 return -EINVAL; 673 } 674 chip = range->gc; 675 at91_chip = container_of(chip, struct at91_gpio_chip, chip); 676 677 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 678 679 mask = 1 << (offset - chip->base); 680 681 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", 682 offset, 'A' + range->id, offset - chip->base, mask); 683 684 writel_relaxed(mask, at91_chip->regbase + PIO_PER); 685 686 return 0; 687 } 688 689 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, 690 struct pinctrl_gpio_range *range, 691 unsigned offset) 692 { 693 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 694 695 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 696 /* Set the pin to some default state, GPIO is usually default */ 697 } 698 699 static struct pinmux_ops at91_pmx_ops = { 700 .get_functions_count = at91_pmx_get_funcs_count, 701 .get_function_name = at91_pmx_get_func_name, 702 .get_function_groups = at91_pmx_get_groups, 703 .enable = at91_pmx_enable, 704 .disable = at91_pmx_disable, 705 .gpio_request_enable = at91_gpio_request_enable, 706 .gpio_disable_free = at91_gpio_disable_free, 707 }; 708 709 static int at91_pinconf_get(struct pinctrl_dev *pctldev, 710 unsigned pin_id, unsigned long *config) 711 { 712 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 713 void __iomem *pio; 714 unsigned pin; 715 int div; 716 717 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config); 718 pio = pin_to_controller(info, pin_to_bank(pin_id)); 719 pin = pin_id % MAX_NB_GPIO_PER_BANK; 720 721 if (at91_mux_get_multidrive(pio, pin)) 722 *config |= MULTI_DRIVE; 723 724 if (at91_mux_get_pullup(pio, pin)) 725 *config |= PULL_UP; 726 727 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) 728 *config |= DEGLITCH; 729 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) 730 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); 731 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) 732 *config |= PULL_DOWN; 733 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) 734 *config |= DIS_SCHMIT; 735 736 return 0; 737 } 738 739 static int at91_pinconf_set(struct pinctrl_dev *pctldev, 740 unsigned pin_id, unsigned long config) 741 { 742 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 743 unsigned mask; 744 void __iomem *pio; 745 746 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config); 747 pio = pin_to_controller(info, pin_to_bank(pin_id)); 748 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); 749 750 if (config & PULL_UP && config & PULL_DOWN) 751 return -EINVAL; 752 753 at91_mux_set_pullup(pio, mask, config & PULL_UP); 754 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); 755 if (info->ops->set_deglitch) 756 info->ops->set_deglitch(pio, mask, config & DEGLITCH); 757 if (info->ops->set_debounce) 758 info->ops->set_debounce(pio, mask, config & DEBOUNCE, 759 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); 760 if (info->ops->set_pulldown) 761 info->ops->set_pulldown(pio, mask, config & PULL_DOWN); 762 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) 763 info->ops->disable_schmitt_trig(pio, mask); 764 765 return 0; 766 } 767 768 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, 769 struct seq_file *s, unsigned pin_id) 770 { 771 772 } 773 774 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 775 struct seq_file *s, unsigned group) 776 { 777 } 778 779 static struct pinconf_ops at91_pinconf_ops = { 780 .pin_config_get = at91_pinconf_get, 781 .pin_config_set = at91_pinconf_set, 782 .pin_config_dbg_show = at91_pinconf_dbg_show, 783 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, 784 }; 785 786 static struct pinctrl_desc at91_pinctrl_desc = { 787 .pctlops = &at91_pctrl_ops, 788 .pmxops = &at91_pmx_ops, 789 .confops = &at91_pinconf_ops, 790 .owner = THIS_MODULE, 791 }; 792 793 static const char *gpio_compat = "atmel,at91rm9200-gpio"; 794 795 static void at91_pinctrl_child_count(struct at91_pinctrl *info, 796 struct device_node *np) 797 { 798 struct device_node *child; 799 800 for_each_child_of_node(np, child) { 801 if (of_device_is_compatible(child, gpio_compat)) { 802 info->nbanks++; 803 } else { 804 info->nfunctions++; 805 info->ngroups += of_get_child_count(child); 806 } 807 } 808 } 809 810 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, 811 struct device_node *np) 812 { 813 int ret = 0; 814 int size; 815 const const __be32 *list; 816 817 list = of_get_property(np, "atmel,mux-mask", &size); 818 if (!list) { 819 dev_err(info->dev, "can not read the mux-mask of %d\n", size); 820 return -EINVAL; 821 } 822 823 size /= sizeof(*list); 824 if (!size || size % info->nbanks) { 825 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks); 826 return -EINVAL; 827 } 828 info->nmux = size / info->nbanks; 829 830 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); 831 if (!info->mux_mask) { 832 dev_err(info->dev, "could not alloc mux_mask\n"); 833 return -ENOMEM; 834 } 835 836 ret = of_property_read_u32_array(np, "atmel,mux-mask", 837 info->mux_mask, size); 838 if (ret) 839 dev_err(info->dev, "can not read the mux-mask of %d\n", size); 840 return ret; 841 } 842 843 static int at91_pinctrl_parse_groups(struct device_node *np, 844 struct at91_pin_group *grp, 845 struct at91_pinctrl *info, u32 index) 846 { 847 struct at91_pmx_pin *pin; 848 int size; 849 const const __be32 *list; 850 int i, j; 851 852 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 853 854 /* Initialise group */ 855 grp->name = np->name; 856 857 /* 858 * the binding format is atmel,pins = <bank pin mux CONFIG ...>, 859 * do sanity check and calculate pins number 860 */ 861 list = of_get_property(np, "atmel,pins", &size); 862 /* we do not check return since it's safe node passed down */ 863 size /= sizeof(*list); 864 if (!size || size % 4) { 865 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 866 return -EINVAL; 867 } 868 869 grp->npins = size / 4; 870 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin), 871 GFP_KERNEL); 872 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 873 GFP_KERNEL); 874 if (!grp->pins_conf || !grp->pins) 875 return -ENOMEM; 876 877 for (i = 0, j = 0; i < size; i += 4, j++) { 878 pin->bank = be32_to_cpu(*list++); 879 pin->pin = be32_to_cpu(*list++); 880 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; 881 pin->mux = be32_to_cpu(*list++); 882 pin->conf = be32_to_cpu(*list++); 883 884 at91_pin_dbg(info->dev, pin); 885 pin++; 886 } 887 888 return 0; 889 } 890 891 static int at91_pinctrl_parse_functions(struct device_node *np, 892 struct at91_pinctrl *info, u32 index) 893 { 894 struct device_node *child; 895 struct at91_pmx_func *func; 896 struct at91_pin_group *grp; 897 int ret; 898 static u32 grp_index; 899 u32 i = 0; 900 901 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 902 903 func = &info->functions[index]; 904 905 /* Initialise function */ 906 func->name = np->name; 907 func->ngroups = of_get_child_count(np); 908 if (func->ngroups <= 0) { 909 dev_err(info->dev, "no groups defined\n"); 910 return -EINVAL; 911 } 912 func->groups = devm_kzalloc(info->dev, 913 func->ngroups * sizeof(char *), GFP_KERNEL); 914 if (!func->groups) 915 return -ENOMEM; 916 917 for_each_child_of_node(np, child) { 918 func->groups[i] = child->name; 919 grp = &info->groups[grp_index++]; 920 ret = at91_pinctrl_parse_groups(child, grp, info, i++); 921 if (ret) 922 return ret; 923 } 924 925 return 0; 926 } 927 928 static struct of_device_id at91_pinctrl_of_match[] = { 929 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, 930 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, 931 { /* sentinel */ } 932 }; 933 934 static int at91_pinctrl_probe_dt(struct platform_device *pdev, 935 struct at91_pinctrl *info) 936 { 937 int ret = 0; 938 int i, j; 939 uint32_t *tmp; 940 struct device_node *np = pdev->dev.of_node; 941 struct device_node *child; 942 943 if (!np) 944 return -ENODEV; 945 946 info->dev = &pdev->dev; 947 info->ops = (struct at91_pinctrl_mux_ops*) 948 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; 949 at91_pinctrl_child_count(info, np); 950 951 if (info->nbanks < 1) { 952 dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n"); 953 return -EINVAL; 954 } 955 956 ret = at91_pinctrl_mux_mask(info, np); 957 if (ret) 958 return ret; 959 960 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); 961 962 dev_dbg(&pdev->dev, "mux-mask\n"); 963 tmp = info->mux_mask; 964 for (i = 0; i < info->nbanks; i++) { 965 for (j = 0; j < info->nmux; j++, tmp++) { 966 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); 967 } 968 } 969 970 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 971 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 972 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func), 973 GFP_KERNEL); 974 if (!info->functions) 975 return -ENOMEM; 976 977 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group), 978 GFP_KERNEL); 979 if (!info->groups) 980 return -ENOMEM; 981 982 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks); 983 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 984 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 985 986 i = 0; 987 988 for_each_child_of_node(np, child) { 989 if (of_device_is_compatible(child, gpio_compat)) 990 continue; 991 ret = at91_pinctrl_parse_functions(child, info, i++); 992 if (ret) { 993 dev_err(&pdev->dev, "failed to parse function\n"); 994 return ret; 995 } 996 } 997 998 return 0; 999 } 1000 1001 static int at91_pinctrl_probe(struct platform_device *pdev) 1002 { 1003 struct at91_pinctrl *info; 1004 struct pinctrl_pin_desc *pdesc; 1005 int ret, i, j ,k; 1006 1007 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 1008 if (!info) 1009 return -ENOMEM; 1010 1011 ret = at91_pinctrl_probe_dt(pdev, info); 1012 if (ret) 1013 return ret; 1014 1015 /* 1016 * We need all the GPIO drivers to probe FIRST, or we will not be able 1017 * to obtain references to the struct gpio_chip * for them, and we 1018 * need this to proceed. 1019 */ 1020 for (i = 0; i < info->nbanks; i++) { 1021 if (!gpio_chips[i]) { 1022 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); 1023 devm_kfree(&pdev->dev, info); 1024 return -EPROBE_DEFER; 1025 } 1026 } 1027 1028 at91_pinctrl_desc.name = dev_name(&pdev->dev); 1029 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK; 1030 at91_pinctrl_desc.pins = pdesc = 1031 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL); 1032 1033 if (!at91_pinctrl_desc.pins) 1034 return -ENOMEM; 1035 1036 for (i = 0 , k = 0; i < info->nbanks; i++) { 1037 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { 1038 pdesc->number = k; 1039 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); 1040 pdesc++; 1041 } 1042 } 1043 1044 platform_set_drvdata(pdev, info); 1045 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info); 1046 1047 if (!info->pctl) { 1048 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); 1049 ret = -EINVAL; 1050 goto err; 1051 } 1052 1053 /* We will handle a range of GPIO pins */ 1054 for (i = 0; i < info->nbanks; i++) 1055 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); 1056 1057 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); 1058 1059 return 0; 1060 1061 err: 1062 return ret; 1063 } 1064 1065 static int at91_pinctrl_remove(struct platform_device *pdev) 1066 { 1067 struct at91_pinctrl *info = platform_get_drvdata(pdev); 1068 1069 pinctrl_unregister(info->pctl); 1070 1071 return 0; 1072 } 1073 1074 static int at91_gpio_request(struct gpio_chip *chip, unsigned offset) 1075 { 1076 /* 1077 * Map back to global GPIO space and request muxing, the direction 1078 * parameter does not matter for this controller. 1079 */ 1080 int gpio = chip->base + offset; 1081 int bank = chip->base / chip->ngpio; 1082 1083 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__, 1084 'A' + bank, offset, gpio); 1085 1086 return pinctrl_request_gpio(gpio); 1087 } 1088 1089 static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) 1090 { 1091 int gpio = chip->base + offset; 1092 1093 pinctrl_free_gpio(gpio); 1094 } 1095 1096 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1097 { 1098 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1099 void __iomem *pio = at91_gpio->regbase; 1100 unsigned mask = 1 << offset; 1101 1102 writel_relaxed(mask, pio + PIO_ODR); 1103 return 0; 1104 } 1105 1106 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) 1107 { 1108 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1109 void __iomem *pio = at91_gpio->regbase; 1110 unsigned mask = 1 << offset; 1111 u32 pdsr; 1112 1113 pdsr = readl_relaxed(pio + PIO_PDSR); 1114 return (pdsr & mask) != 0; 1115 } 1116 1117 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, 1118 int val) 1119 { 1120 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1121 void __iomem *pio = at91_gpio->regbase; 1122 unsigned mask = 1 << offset; 1123 1124 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 1125 } 1126 1127 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 1128 int val) 1129 { 1130 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1131 void __iomem *pio = at91_gpio->regbase; 1132 unsigned mask = 1 << offset; 1133 1134 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); 1135 writel_relaxed(mask, pio + PIO_OER); 1136 1137 return 0; 1138 } 1139 1140 static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 1141 { 1142 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1143 int virq; 1144 1145 if (offset < chip->ngpio) 1146 virq = irq_create_mapping(at91_gpio->domain, offset); 1147 else 1148 virq = -ENXIO; 1149 1150 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", 1151 chip->label, offset + chip->base, virq); 1152 return virq; 1153 } 1154 1155 #ifdef CONFIG_DEBUG_FS 1156 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1157 { 1158 enum at91_mux mode; 1159 int i; 1160 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 1161 void __iomem *pio = at91_gpio->regbase; 1162 1163 for (i = 0; i < chip->ngpio; i++) { 1164 unsigned pin = chip->base + i; 1165 unsigned mask = pin_to_mask(pin); 1166 const char *gpio_label; 1167 u32 pdsr; 1168 1169 gpio_label = gpiochip_is_requested(chip, i); 1170 if (!gpio_label) 1171 continue; 1172 mode = at91_gpio->ops->get_periph(pio, mask); 1173 seq_printf(s, "[%s] GPIO%s%d: ", 1174 gpio_label, chip->label, i); 1175 if (mode == AT91_MUX_GPIO) { 1176 pdsr = readl_relaxed(pio + PIO_PDSR); 1177 1178 seq_printf(s, "[gpio] %s\n", 1179 pdsr & mask ? 1180 "set" : "clear"); 1181 } else { 1182 seq_printf(s, "[periph %c]\n", 1183 mode + 'A' - 1); 1184 } 1185 } 1186 } 1187 #else 1188 #define at91_gpio_dbg_show NULL 1189 #endif 1190 1191 /* Several AIC controller irqs are dispatched through this GPIO handler. 1192 * To use any AT91_PIN_* as an externally triggered IRQ, first call 1193 * at91_set_gpio_input() then maybe enable its glitch filter. 1194 * Then just request_irq() with the pin ID; it works like any ARM IRQ 1195 * handler. 1196 * First implementation always triggers on rising and falling edges 1197 * whereas the newer PIO3 can be additionally configured to trigger on 1198 * level, edge with any polarity. 1199 * 1200 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after 1201 * configuring them with at91_set_a_periph() or at91_set_b_periph(). 1202 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. 1203 */ 1204 1205 static void gpio_irq_mask(struct irq_data *d) 1206 { 1207 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1208 void __iomem *pio = at91_gpio->regbase; 1209 unsigned mask = 1 << d->hwirq; 1210 1211 if (pio) 1212 writel_relaxed(mask, pio + PIO_IDR); 1213 } 1214 1215 static void gpio_irq_unmask(struct irq_data *d) 1216 { 1217 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1218 void __iomem *pio = at91_gpio->regbase; 1219 unsigned mask = 1 << d->hwirq; 1220 1221 if (pio) 1222 writel_relaxed(mask, pio + PIO_IER); 1223 } 1224 1225 static int gpio_irq_type(struct irq_data *d, unsigned type) 1226 { 1227 switch (type) { 1228 case IRQ_TYPE_NONE: 1229 case IRQ_TYPE_EDGE_BOTH: 1230 return 0; 1231 default: 1232 return -EINVAL; 1233 } 1234 } 1235 1236 /* Alternate irq type for PIO3 support */ 1237 static int alt_gpio_irq_type(struct irq_data *d, unsigned type) 1238 { 1239 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1240 void __iomem *pio = at91_gpio->regbase; 1241 unsigned mask = 1 << d->hwirq; 1242 1243 switch (type) { 1244 case IRQ_TYPE_EDGE_RISING: 1245 writel_relaxed(mask, pio + PIO_ESR); 1246 writel_relaxed(mask, pio + PIO_REHLSR); 1247 break; 1248 case IRQ_TYPE_EDGE_FALLING: 1249 writel_relaxed(mask, pio + PIO_ESR); 1250 writel_relaxed(mask, pio + PIO_FELLSR); 1251 break; 1252 case IRQ_TYPE_LEVEL_LOW: 1253 writel_relaxed(mask, pio + PIO_LSR); 1254 writel_relaxed(mask, pio + PIO_FELLSR); 1255 break; 1256 case IRQ_TYPE_LEVEL_HIGH: 1257 writel_relaxed(mask, pio + PIO_LSR); 1258 writel_relaxed(mask, pio + PIO_REHLSR); 1259 break; 1260 case IRQ_TYPE_EDGE_BOTH: 1261 /* 1262 * disable additional interrupt modes: 1263 * fall back to default behavior 1264 */ 1265 writel_relaxed(mask, pio + PIO_AIMDR); 1266 return 0; 1267 case IRQ_TYPE_NONE: 1268 default: 1269 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); 1270 return -EINVAL; 1271 } 1272 1273 /* enable additional interrupt modes */ 1274 writel_relaxed(mask, pio + PIO_AIMER); 1275 1276 return 0; 1277 } 1278 1279 #ifdef CONFIG_PM 1280 1281 static u32 wakeups[MAX_GPIO_BANKS]; 1282 static u32 backups[MAX_GPIO_BANKS]; 1283 1284 static int gpio_irq_set_wake(struct irq_data *d, unsigned state) 1285 { 1286 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 1287 unsigned bank = at91_gpio->pioc_idx; 1288 unsigned mask = 1 << d->hwirq; 1289 1290 if (unlikely(bank >= MAX_GPIO_BANKS)) 1291 return -EINVAL; 1292 1293 if (state) 1294 wakeups[bank] |= mask; 1295 else 1296 wakeups[bank] &= ~mask; 1297 1298 irq_set_irq_wake(at91_gpio->pioc_virq, state); 1299 1300 return 0; 1301 } 1302 1303 void at91_pinctrl_gpio_suspend(void) 1304 { 1305 int i; 1306 1307 for (i = 0; i < gpio_banks; i++) { 1308 void __iomem *pio; 1309 1310 if (!gpio_chips[i]) 1311 continue; 1312 1313 pio = gpio_chips[i]->regbase; 1314 1315 backups[i] = __raw_readl(pio + PIO_IMR); 1316 __raw_writel(backups[i], pio + PIO_IDR); 1317 __raw_writel(wakeups[i], pio + PIO_IER); 1318 1319 if (!wakeups[i]) { 1320 clk_unprepare(gpio_chips[i]->clock); 1321 clk_disable(gpio_chips[i]->clock); 1322 } else { 1323 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 1324 'A'+i, wakeups[i]); 1325 } 1326 } 1327 } 1328 1329 void at91_pinctrl_gpio_resume(void) 1330 { 1331 int i; 1332 1333 for (i = 0; i < gpio_banks; i++) { 1334 void __iomem *pio; 1335 1336 if (!gpio_chips[i]) 1337 continue; 1338 1339 pio = gpio_chips[i]->regbase; 1340 1341 if (!wakeups[i]) { 1342 if (clk_prepare(gpio_chips[i]->clock) == 0) 1343 clk_enable(gpio_chips[i]->clock); 1344 } 1345 1346 __raw_writel(wakeups[i], pio + PIO_IDR); 1347 __raw_writel(backups[i], pio + PIO_IER); 1348 } 1349 } 1350 1351 #else 1352 #define gpio_irq_set_wake NULL 1353 #endif /* CONFIG_PM */ 1354 1355 static struct irq_chip gpio_irqchip = { 1356 .name = "GPIO", 1357 .irq_disable = gpio_irq_mask, 1358 .irq_mask = gpio_irq_mask, 1359 .irq_unmask = gpio_irq_unmask, 1360 /* .irq_set_type is set dynamically */ 1361 .irq_set_wake = gpio_irq_set_wake, 1362 }; 1363 1364 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 1365 { 1366 struct irq_chip *chip = irq_desc_get_chip(desc); 1367 struct irq_data *idata = irq_desc_get_irq_data(desc); 1368 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); 1369 void __iomem *pio = at91_gpio->regbase; 1370 unsigned long isr; 1371 int n; 1372 1373 chained_irq_enter(chip, desc); 1374 for (;;) { 1375 /* Reading ISR acks pending (edge triggered) GPIO interrupts. 1376 * When there none are pending, we're finished unless we need 1377 * to process multiple banks (like ID_PIOCDE on sam9263). 1378 */ 1379 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); 1380 if (!isr) { 1381 if (!at91_gpio->next) 1382 break; 1383 at91_gpio = at91_gpio->next; 1384 pio = at91_gpio->regbase; 1385 continue; 1386 } 1387 1388 for_each_set_bit(n, &isr, BITS_PER_LONG) { 1389 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n)); 1390 } 1391 } 1392 chained_irq_exit(chip, desc); 1393 /* now it may re-trigger */ 1394 } 1395 1396 /* 1397 * This lock class tells lockdep that GPIO irqs are in a different 1398 * category than their parents, so it won't report false recursion. 1399 */ 1400 static struct lock_class_key gpio_lock_class; 1401 1402 static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq, 1403 irq_hw_number_t hw) 1404 { 1405 struct at91_gpio_chip *at91_gpio = h->host_data; 1406 1407 irq_set_lockdep_class(virq, &gpio_lock_class); 1408 1409 /* 1410 * Can use the "simple" and not "edge" handler since it's 1411 * shorter, and the AIC handles interrupts sanely. 1412 */ 1413 irq_set_chip_and_handler(virq, &gpio_irqchip, 1414 handle_simple_irq); 1415 set_irq_flags(virq, IRQF_VALID); 1416 irq_set_chip_data(virq, at91_gpio); 1417 1418 return 0; 1419 } 1420 1421 static int at91_gpio_irq_domain_xlate(struct irq_domain *d, 1422 struct device_node *ctrlr, 1423 const u32 *intspec, unsigned int intsize, 1424 irq_hw_number_t *out_hwirq, 1425 unsigned int *out_type) 1426 { 1427 struct at91_gpio_chip *at91_gpio = d->host_data; 1428 int ret; 1429 int pin = at91_gpio->chip.base + intspec[0]; 1430 1431 if (WARN_ON(intsize < 2)) 1432 return -EINVAL; 1433 *out_hwirq = intspec[0]; 1434 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; 1435 1436 ret = gpio_request(pin, ctrlr->full_name); 1437 if (ret) 1438 return ret; 1439 1440 ret = gpio_direction_input(pin); 1441 if (ret) 1442 return ret; 1443 1444 return 0; 1445 } 1446 1447 static struct irq_domain_ops at91_gpio_ops = { 1448 .map = at91_gpio_irq_map, 1449 .xlate = at91_gpio_irq_domain_xlate, 1450 }; 1451 1452 static int at91_gpio_of_irq_setup(struct device_node *node, 1453 struct at91_gpio_chip *at91_gpio) 1454 { 1455 struct at91_gpio_chip *prev = NULL; 1456 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); 1457 1458 at91_gpio->pioc_hwirq = irqd_to_hwirq(d); 1459 1460 /* Setup proper .irq_set_type function */ 1461 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type; 1462 1463 /* Disable irqs of this PIO controller */ 1464 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); 1465 1466 /* Setup irq domain */ 1467 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio, 1468 &at91_gpio_ops, at91_gpio); 1469 if (!at91_gpio->domain) 1470 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", 1471 at91_gpio->pioc_idx); 1472 1473 /* Setup chained handler */ 1474 if (at91_gpio->pioc_idx) 1475 prev = gpio_chips[at91_gpio->pioc_idx - 1]; 1476 1477 /* The toplevel handler handles one bank of GPIOs, except 1478 * on some SoC it can handles up to three... 1479 * We only set up the handler for the first of the list. 1480 */ 1481 if (prev && prev->next == at91_gpio) 1482 return 0; 1483 1484 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio); 1485 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler); 1486 1487 return 0; 1488 } 1489 1490 /* This structure is replicated for each GPIO block allocated at probe time */ 1491 static struct gpio_chip at91_gpio_template = { 1492 .request = at91_gpio_request, 1493 .free = at91_gpio_free, 1494 .direction_input = at91_gpio_direction_input, 1495 .get = at91_gpio_get, 1496 .direction_output = at91_gpio_direction_output, 1497 .set = at91_gpio_set, 1498 .to_irq = at91_gpio_to_irq, 1499 .dbg_show = at91_gpio_dbg_show, 1500 .can_sleep = 0, 1501 .ngpio = MAX_NB_GPIO_PER_BANK, 1502 }; 1503 1504 static void at91_gpio_probe_fixup(void) 1505 { 1506 unsigned i; 1507 struct at91_gpio_chip *at91_gpio, *last = NULL; 1508 1509 for (i = 0; i < gpio_banks; i++) { 1510 at91_gpio = gpio_chips[i]; 1511 1512 /* 1513 * GPIO controller are grouped on some SoC: 1514 * PIOC, PIOD and PIOE can share the same IRQ line 1515 */ 1516 if (last && last->pioc_virq == at91_gpio->pioc_virq) 1517 last->next = at91_gpio; 1518 last = at91_gpio; 1519 } 1520 } 1521 1522 static struct of_device_id at91_gpio_of_match[] = { 1523 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, 1524 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, 1525 { /* sentinel */ } 1526 }; 1527 1528 static int at91_gpio_probe(struct platform_device *pdev) 1529 { 1530 struct device_node *np = pdev->dev.of_node; 1531 struct resource *res; 1532 struct at91_gpio_chip *at91_chip = NULL; 1533 struct gpio_chip *chip; 1534 struct pinctrl_gpio_range *range; 1535 int ret = 0; 1536 int irq, i; 1537 int alias_idx = of_alias_get_id(np, "gpio"); 1538 uint32_t ngpio; 1539 char **names; 1540 1541 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); 1542 if (gpio_chips[alias_idx]) { 1543 ret = -EBUSY; 1544 goto err; 1545 } 1546 1547 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1548 if (!res) { 1549 ret = -ENOENT; 1550 goto err; 1551 } 1552 1553 irq = platform_get_irq(pdev, 0); 1554 if (irq < 0) { 1555 ret = irq; 1556 goto err; 1557 } 1558 1559 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); 1560 if (!at91_chip) { 1561 ret = -ENOMEM; 1562 goto err; 1563 } 1564 1565 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res); 1566 if (IS_ERR(at91_chip->regbase)) { 1567 ret = PTR_ERR(at91_chip->regbase); 1568 goto err; 1569 } 1570 1571 at91_chip->ops = (struct at91_pinctrl_mux_ops*) 1572 of_match_device(at91_gpio_of_match, &pdev->dev)->data; 1573 at91_chip->pioc_virq = irq; 1574 at91_chip->pioc_idx = alias_idx; 1575 1576 at91_chip->clock = clk_get(&pdev->dev, NULL); 1577 if (IS_ERR(at91_chip->clock)) { 1578 dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); 1579 goto err; 1580 } 1581 1582 if (clk_prepare(at91_chip->clock)) 1583 goto clk_prep_err; 1584 1585 /* enable PIO controller's clock */ 1586 if (clk_enable(at91_chip->clock)) { 1587 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); 1588 goto clk_err; 1589 } 1590 1591 at91_chip->chip = at91_gpio_template; 1592 1593 chip = &at91_chip->chip; 1594 chip->of_node = np; 1595 chip->label = dev_name(&pdev->dev); 1596 chip->dev = &pdev->dev; 1597 chip->owner = THIS_MODULE; 1598 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; 1599 1600 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { 1601 if (ngpio >= MAX_NB_GPIO_PER_BANK) 1602 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", 1603 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); 1604 else 1605 chip->ngpio = ngpio; 1606 } 1607 1608 names = devm_kzalloc(&pdev->dev, sizeof(char*) * chip->ngpio, GFP_KERNEL); 1609 1610 if (!names) { 1611 ret = -ENOMEM; 1612 goto clk_err; 1613 } 1614 1615 for (i = 0; i < chip->ngpio; i++) 1616 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); 1617 1618 chip->names = (const char*const*)names; 1619 1620 range = &at91_chip->range; 1621 range->name = chip->label; 1622 range->id = alias_idx; 1623 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; 1624 1625 range->npins = chip->ngpio; 1626 range->gc = chip; 1627 1628 ret = gpiochip_add(chip); 1629 if (ret) 1630 goto clk_err; 1631 1632 gpio_chips[alias_idx] = at91_chip; 1633 gpio_banks = max(gpio_banks, alias_idx + 1); 1634 1635 at91_gpio_probe_fixup(); 1636 1637 at91_gpio_of_irq_setup(np, at91_chip); 1638 1639 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); 1640 1641 return 0; 1642 1643 clk_err: 1644 clk_unprepare(at91_chip->clock); 1645 clk_prep_err: 1646 clk_put(at91_chip->clock); 1647 err: 1648 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); 1649 1650 return ret; 1651 } 1652 1653 static struct platform_driver at91_gpio_driver = { 1654 .driver = { 1655 .name = "gpio-at91", 1656 .owner = THIS_MODULE, 1657 .of_match_table = of_match_ptr(at91_gpio_of_match), 1658 }, 1659 .probe = at91_gpio_probe, 1660 }; 1661 1662 static struct platform_driver at91_pinctrl_driver = { 1663 .driver = { 1664 .name = "pinctrl-at91", 1665 .owner = THIS_MODULE, 1666 .of_match_table = of_match_ptr(at91_pinctrl_of_match), 1667 }, 1668 .probe = at91_pinctrl_probe, 1669 .remove = at91_pinctrl_remove, 1670 }; 1671 1672 static int __init at91_pinctrl_init(void) 1673 { 1674 int ret; 1675 1676 ret = platform_driver_register(&at91_gpio_driver); 1677 if (ret) 1678 return ret; 1679 return platform_driver_register(&at91_pinctrl_driver); 1680 } 1681 arch_initcall(at91_pinctrl_init); 1682 1683 static void __exit at91_pinctrl_exit(void) 1684 { 1685 platform_driver_unregister(&at91_pinctrl_driver); 1686 } 1687 1688 module_exit(at91_pinctrl_exit); 1689 MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>"); 1690 MODULE_DESCRIPTION("Atmel AT91 pinctrl driver"); 1691 MODULE_LICENSE("GPL v2"); 1692