1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ams AS3722 pin control and GPIO driver. 4 * 5 * Copyright (c) 2013, NVIDIA Corporation. 6 * 7 * Author: Laxman Dewangan <ldewangan@nvidia.com> 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mfd/as3722.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm.h> 17 #include <linux/property.h> 18 #include <linux/slab.h> 19 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinmux.h> 26 27 #include "core.h" 28 #include "pinconf.h" 29 #include "pinctrl-utils.h" 30 31 #define AS3722_PIN_GPIO0 0 32 #define AS3722_PIN_GPIO1 1 33 #define AS3722_PIN_GPIO2 2 34 #define AS3722_PIN_GPIO3 3 35 #define AS3722_PIN_GPIO4 4 36 #define AS3722_PIN_GPIO5 5 37 #define AS3722_PIN_GPIO6 6 38 #define AS3722_PIN_GPIO7 7 39 #define AS3722_PIN_NUM (AS3722_PIN_GPIO7 + 1) 40 41 #define AS3722_GPIO_MODE_PULL_UP BIT(PIN_CONFIG_BIAS_PULL_UP) 42 #define AS3722_GPIO_MODE_PULL_DOWN BIT(PIN_CONFIG_BIAS_PULL_DOWN) 43 #define AS3722_GPIO_MODE_HIGH_IMPED BIT(PIN_CONFIG_BIAS_HIGH_IMPEDANCE) 44 #define AS3722_GPIO_MODE_OPEN_DRAIN BIT(PIN_CONFIG_DRIVE_OPEN_DRAIN) 45 46 struct as3722_pin_function { 47 const char *name; 48 const char * const *groups; 49 unsigned ngroups; 50 int mux_option; 51 }; 52 53 struct as3722_gpio_pin_control { 54 unsigned mode_prop; 55 int io_function; 56 }; 57 58 struct as3722_pingroup { 59 const char *name; 60 const unsigned pins[1]; 61 unsigned npins; 62 }; 63 64 struct as3722_pctrl_info { 65 struct device *dev; 66 struct pinctrl_dev *pctl; 67 struct as3722 *as3722; 68 struct gpio_chip gpio_chip; 69 int pins_current_opt[AS3722_PIN_NUM]; 70 const struct as3722_pin_function *functions; 71 unsigned num_functions; 72 const struct as3722_pingroup *pin_groups; 73 int num_pin_groups; 74 const struct pinctrl_pin_desc *pins; 75 unsigned num_pins; 76 struct as3722_gpio_pin_control gpio_control[AS3722_PIN_NUM]; 77 }; 78 79 static const struct pinctrl_pin_desc as3722_pins_desc[] = { 80 PINCTRL_PIN(AS3722_PIN_GPIO0, "gpio0"), 81 PINCTRL_PIN(AS3722_PIN_GPIO1, "gpio1"), 82 PINCTRL_PIN(AS3722_PIN_GPIO2, "gpio2"), 83 PINCTRL_PIN(AS3722_PIN_GPIO3, "gpio3"), 84 PINCTRL_PIN(AS3722_PIN_GPIO4, "gpio4"), 85 PINCTRL_PIN(AS3722_PIN_GPIO5, "gpio5"), 86 PINCTRL_PIN(AS3722_PIN_GPIO6, "gpio6"), 87 PINCTRL_PIN(AS3722_PIN_GPIO7, "gpio7"), 88 }; 89 90 static const char * const gpio_groups[] = { 91 "gpio0", 92 "gpio1", 93 "gpio2", 94 "gpio3", 95 "gpio4", 96 "gpio5", 97 "gpio6", 98 "gpio7", 99 }; 100 101 enum as3722_pinmux_option { 102 AS3722_PINMUX_GPIO = 0, 103 AS3722_PINMUX_INTERRUPT_OUT = 1, 104 AS3722_PINMUX_VSUB_VBAT_UNDEB_LOW_OUT = 2, 105 AS3722_PINMUX_GPIO_INTERRUPT = 3, 106 AS3722_PINMUX_PWM_INPUT = 4, 107 AS3722_PINMUX_VOLTAGE_IN_STBY = 5, 108 AS3722_PINMUX_OC_PG_SD0 = 6, 109 AS3722_PINMUX_PG_OUT = 7, 110 AS3722_PINMUX_CLK32K_OUT = 8, 111 AS3722_PINMUX_WATCHDOG_INPUT = 9, 112 AS3722_PINMUX_SOFT_RESET_IN = 11, 113 AS3722_PINMUX_PWM_OUTPUT = 12, 114 AS3722_PINMUX_VSUB_VBAT_LOW_DEB_OUT = 13, 115 AS3722_PINMUX_OC_PG_SD6 = 14, 116 }; 117 118 #define FUNCTION_GROUP(fname, mux) \ 119 { \ 120 .name = #fname, \ 121 .groups = gpio_groups, \ 122 .ngroups = ARRAY_SIZE(gpio_groups), \ 123 .mux_option = AS3722_PINMUX_##mux, \ 124 } 125 126 static const struct as3722_pin_function as3722_pin_function[] = { 127 FUNCTION_GROUP(gpio, GPIO), 128 FUNCTION_GROUP(interrupt-out, INTERRUPT_OUT), 129 FUNCTION_GROUP(gpio-in-interrupt, GPIO_INTERRUPT), 130 FUNCTION_GROUP(vsup-vbat-low-undebounce-out, VSUB_VBAT_UNDEB_LOW_OUT), 131 FUNCTION_GROUP(vsup-vbat-low-debounce-out, VSUB_VBAT_LOW_DEB_OUT), 132 FUNCTION_GROUP(voltage-in-standby, VOLTAGE_IN_STBY), 133 FUNCTION_GROUP(oc-pg-sd0, OC_PG_SD0), 134 FUNCTION_GROUP(oc-pg-sd6, OC_PG_SD6), 135 FUNCTION_GROUP(powergood-out, PG_OUT), 136 FUNCTION_GROUP(pwm-in, PWM_INPUT), 137 FUNCTION_GROUP(pwm-out, PWM_OUTPUT), 138 FUNCTION_GROUP(clk32k-out, CLK32K_OUT), 139 FUNCTION_GROUP(watchdog-in, WATCHDOG_INPUT), 140 FUNCTION_GROUP(soft-reset-in, SOFT_RESET_IN), 141 }; 142 143 #define AS3722_PINGROUP(pg_name, pin_id) \ 144 { \ 145 .name = #pg_name, \ 146 .pins = {AS3722_PIN_##pin_id}, \ 147 .npins = 1, \ 148 } 149 150 static const struct as3722_pingroup as3722_pingroups[] = { 151 AS3722_PINGROUP(gpio0, GPIO0), 152 AS3722_PINGROUP(gpio1, GPIO1), 153 AS3722_PINGROUP(gpio2, GPIO2), 154 AS3722_PINGROUP(gpio3, GPIO3), 155 AS3722_PINGROUP(gpio4, GPIO4), 156 AS3722_PINGROUP(gpio5, GPIO5), 157 AS3722_PINGROUP(gpio6, GPIO6), 158 AS3722_PINGROUP(gpio7, GPIO7), 159 }; 160 161 static int as3722_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 162 { 163 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 164 165 return as_pci->num_pin_groups; 166 } 167 168 static const char *as3722_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 169 unsigned group) 170 { 171 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 172 173 return as_pci->pin_groups[group].name; 174 } 175 176 static int as3722_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 177 unsigned group, const unsigned **pins, unsigned *num_pins) 178 { 179 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 180 181 *pins = as_pci->pin_groups[group].pins; 182 *num_pins = as_pci->pin_groups[group].npins; 183 return 0; 184 } 185 186 static const struct pinctrl_ops as3722_pinctrl_ops = { 187 .get_groups_count = as3722_pinctrl_get_groups_count, 188 .get_group_name = as3722_pinctrl_get_group_name, 189 .get_group_pins = as3722_pinctrl_get_group_pins, 190 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 191 .dt_free_map = pinctrl_utils_free_map, 192 }; 193 194 static int as3722_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) 195 { 196 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 197 198 return as_pci->num_functions; 199 } 200 201 static const char *as3722_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 202 unsigned function) 203 { 204 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 205 206 return as_pci->functions[function].name; 207 } 208 209 static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, 210 unsigned function, const char * const **groups, 211 unsigned * const num_groups) 212 { 213 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 214 215 *groups = as_pci->functions[function].groups; 216 *num_groups = as_pci->functions[function].ngroups; 217 return 0; 218 } 219 220 static int as3722_pinctrl_set(struct pinctrl_dev *pctldev, unsigned function, 221 unsigned group) 222 { 223 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 224 int gpio_cntr_reg = AS3722_GPIOn_CONTROL_REG(group); 225 u8 val = AS3722_GPIO_IOSF_VAL(as_pci->functions[function].mux_option); 226 int ret; 227 228 dev_dbg(as_pci->dev, "%s(): GPIO %u pin to function %u and val %u\n", 229 __func__, group, function, val); 230 231 ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg, 232 AS3722_GPIO_IOSF_MASK, val); 233 if (ret < 0) { 234 dev_err(as_pci->dev, "GPIO%d_CTRL_REG update failed %d\n", 235 group, ret); 236 return ret; 237 } 238 as_pci->gpio_control[group].io_function = function; 239 240 switch (val) { 241 case AS3722_GPIO_IOSF_SD0_OUT: 242 case AS3722_GPIO_IOSF_PWR_GOOD_OUT: 243 case AS3722_GPIO_IOSF_Q32K_OUT: 244 case AS3722_GPIO_IOSF_PWM_OUT: 245 case AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW: 246 ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg, 247 AS3722_GPIO_MODE_MASK, AS3722_GPIO_MODE_OUTPUT_VDDH); 248 if (ret < 0) { 249 dev_err(as_pci->dev, "GPIO%d_CTRL update failed %d\n", 250 group, ret); 251 return ret; 252 } 253 as_pci->gpio_control[group].mode_prop = 254 AS3722_GPIO_MODE_OUTPUT_VDDH; 255 break; 256 default: 257 break; 258 } 259 return ret; 260 } 261 262 static int as3722_pinctrl_gpio_get_mode(unsigned gpio_mode_prop, bool input) 263 { 264 if (gpio_mode_prop & AS3722_GPIO_MODE_HIGH_IMPED) 265 return -EINVAL; 266 267 if (gpio_mode_prop & AS3722_GPIO_MODE_OPEN_DRAIN) { 268 if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP) 269 return AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP; 270 return AS3722_GPIO_MODE_IO_OPEN_DRAIN; 271 } 272 if (input) { 273 if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP) 274 return AS3722_GPIO_MODE_INPUT_PULL_UP; 275 else if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN) 276 return AS3722_GPIO_MODE_INPUT_PULL_DOWN; 277 return AS3722_GPIO_MODE_INPUT; 278 } 279 if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN) 280 return AS3722_GPIO_MODE_OUTPUT_VDDL; 281 return AS3722_GPIO_MODE_OUTPUT_VDDH; 282 } 283 284 static int as3722_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, 285 struct pinctrl_gpio_range *range, unsigned offset) 286 { 287 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 288 289 if (as_pci->gpio_control[offset].io_function) 290 return -EBUSY; 291 return 0; 292 } 293 294 static int as3722_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev, 295 struct pinctrl_gpio_range *range, unsigned offset, bool input) 296 { 297 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 298 struct as3722 *as3722 = as_pci->as3722; 299 int mode; 300 301 mode = as3722_pinctrl_gpio_get_mode( 302 as_pci->gpio_control[offset].mode_prop, input); 303 if (mode < 0) { 304 dev_err(as_pci->dev, "%s direction for GPIO %d not supported\n", 305 (input) ? "Input" : "Output", offset); 306 return mode; 307 } 308 309 return as3722_update_bits(as3722, AS3722_GPIOn_CONTROL_REG(offset), 310 AS3722_GPIO_MODE_MASK, mode); 311 } 312 313 static const struct pinmux_ops as3722_pinmux_ops = { 314 .get_functions_count = as3722_pinctrl_get_funcs_count, 315 .get_function_name = as3722_pinctrl_get_func_name, 316 .get_function_groups = as3722_pinctrl_get_func_groups, 317 .set_mux = as3722_pinctrl_set, 318 .gpio_request_enable = as3722_pinctrl_gpio_request_enable, 319 .gpio_set_direction = as3722_pinctrl_gpio_set_direction, 320 }; 321 322 static int as3722_pinconf_get(struct pinctrl_dev *pctldev, 323 unsigned pin, unsigned long *config) 324 { 325 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 326 enum pin_config_param param = pinconf_to_config_param(*config); 327 int arg = 0; 328 u16 prop; 329 330 switch (param) { 331 case PIN_CONFIG_BIAS_DISABLE: 332 prop = AS3722_GPIO_MODE_PULL_UP | 333 AS3722_GPIO_MODE_PULL_DOWN; 334 if (!(as_pci->gpio_control[pin].mode_prop & prop)) 335 arg = 1; 336 prop = 0; 337 break; 338 339 case PIN_CONFIG_BIAS_PULL_UP: 340 prop = AS3722_GPIO_MODE_PULL_UP; 341 break; 342 343 case PIN_CONFIG_BIAS_PULL_DOWN: 344 prop = AS3722_GPIO_MODE_PULL_DOWN; 345 break; 346 347 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 348 prop = AS3722_GPIO_MODE_OPEN_DRAIN; 349 break; 350 351 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 352 prop = AS3722_GPIO_MODE_HIGH_IMPED; 353 break; 354 355 default: 356 dev_err(as_pci->dev, "Properties not supported\n"); 357 return -ENOTSUPP; 358 } 359 360 if (as_pci->gpio_control[pin].mode_prop & prop) 361 arg = 1; 362 363 *config = pinconf_to_config_packed(param, (u16)arg); 364 return 0; 365 } 366 367 static int as3722_pinconf_set(struct pinctrl_dev *pctldev, 368 unsigned pin, unsigned long *configs, 369 unsigned num_configs) 370 { 371 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 372 enum pin_config_param param; 373 int mode_prop; 374 int i; 375 376 for (i = 0; i < num_configs; i++) { 377 param = pinconf_to_config_param(configs[i]); 378 mode_prop = as_pci->gpio_control[pin].mode_prop; 379 380 switch (param) { 381 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 382 break; 383 384 case PIN_CONFIG_BIAS_DISABLE: 385 mode_prop &= ~(AS3722_GPIO_MODE_PULL_UP | 386 AS3722_GPIO_MODE_PULL_DOWN); 387 break; 388 case PIN_CONFIG_BIAS_PULL_UP: 389 mode_prop |= AS3722_GPIO_MODE_PULL_UP; 390 break; 391 392 case PIN_CONFIG_BIAS_PULL_DOWN: 393 mode_prop |= AS3722_GPIO_MODE_PULL_DOWN; 394 break; 395 396 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 397 mode_prop |= AS3722_GPIO_MODE_HIGH_IMPED; 398 break; 399 400 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 401 mode_prop |= AS3722_GPIO_MODE_OPEN_DRAIN; 402 break; 403 404 default: 405 dev_err(as_pci->dev, "Properties not supported\n"); 406 return -ENOTSUPP; 407 } 408 409 as_pci->gpio_control[pin].mode_prop = mode_prop; 410 } 411 return 0; 412 } 413 414 static const struct pinconf_ops as3722_pinconf_ops = { 415 .pin_config_get = as3722_pinconf_get, 416 .pin_config_set = as3722_pinconf_set, 417 }; 418 419 static struct pinctrl_desc as3722_pinctrl_desc = { 420 .pctlops = &as3722_pinctrl_ops, 421 .pmxops = &as3722_pinmux_ops, 422 .confops = &as3722_pinconf_ops, 423 .owner = THIS_MODULE, 424 .pins = as3722_pins_desc, 425 .npins = ARRAY_SIZE(as3722_pins_desc), 426 }; 427 428 static int as3722_gpio_get(struct gpio_chip *chip, unsigned offset) 429 { 430 struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip); 431 struct as3722 *as3722 = as_pci->as3722; 432 int ret; 433 u32 reg; 434 u32 control; 435 u32 val; 436 int mode; 437 int invert_enable; 438 439 ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &control); 440 if (ret < 0) { 441 dev_err(as_pci->dev, 442 "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret); 443 return ret; 444 } 445 446 invert_enable = !!(control & AS3722_GPIO_INV); 447 mode = control & AS3722_GPIO_MODE_MASK; 448 switch (mode) { 449 case AS3722_GPIO_MODE_INPUT: 450 case AS3722_GPIO_MODE_INPUT_PULL_UP: 451 case AS3722_GPIO_MODE_INPUT_PULL_DOWN: 452 case AS3722_GPIO_MODE_IO_OPEN_DRAIN: 453 case AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP: 454 reg = AS3722_GPIO_SIGNAL_IN_REG; 455 break; 456 case AS3722_GPIO_MODE_OUTPUT_VDDH: 457 case AS3722_GPIO_MODE_OUTPUT_VDDL: 458 reg = AS3722_GPIO_SIGNAL_OUT_REG; 459 break; 460 default: 461 return -EINVAL; 462 } 463 464 ret = as3722_read(as3722, reg, &val); 465 if (ret < 0) { 466 dev_err(as_pci->dev, 467 "GPIO_SIGNAL_IN_REG read failed: %d\n", ret); 468 return ret; 469 } 470 471 val = !!(val & AS3722_GPIOn_SIGNAL(offset)); 472 return (invert_enable) ? !val : val; 473 } 474 475 static int as3722_gpio_set(struct gpio_chip *chip, unsigned int offset, 476 int value) 477 { 478 struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip); 479 struct as3722 *as3722 = as_pci->as3722; 480 int en_invert; 481 u32 val; 482 int ret; 483 484 ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &val); 485 if (ret < 0) { 486 dev_err(as_pci->dev, 487 "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret); 488 return ret; 489 } 490 en_invert = !!(val & AS3722_GPIO_INV); 491 492 if (value) 493 val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset); 494 else 495 val = (en_invert) ? AS3722_GPIOn_SIGNAL(offset) : 0; 496 497 ret = as3722_update_bits(as3722, AS3722_GPIO_SIGNAL_OUT_REG, 498 AS3722_GPIOn_SIGNAL(offset), val); 499 if (ret < 0) 500 dev_err(as_pci->dev, 501 "GPIO_SIGNAL_OUT_REG update failed: %d\n", ret); 502 503 return ret; 504 } 505 506 static int as3722_gpio_direction_output(struct gpio_chip *chip, 507 unsigned int offset, int value) 508 { 509 int ret; 510 511 ret = as3722_gpio_set(chip, offset, value); 512 if (ret) 513 return ret; 514 515 return pinctrl_gpio_direction_output(chip, offset); 516 } 517 518 static int as3722_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 519 { 520 struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip); 521 522 return as3722_irq_get_virq(as_pci->as3722, offset); 523 } 524 525 static const struct gpio_chip as3722_gpio_chip = { 526 .label = "as3722-gpio", 527 .owner = THIS_MODULE, 528 .request = gpiochip_generic_request, 529 .free = gpiochip_generic_free, 530 .get = as3722_gpio_get, 531 .set = as3722_gpio_set, 532 .direction_input = pinctrl_gpio_direction_input, 533 .direction_output = as3722_gpio_direction_output, 534 .to_irq = as3722_gpio_to_irq, 535 .can_sleep = true, 536 .ngpio = AS3722_PIN_NUM, 537 .base = -1, 538 }; 539 540 static int as3722_pinctrl_probe(struct platform_device *pdev) 541 { 542 struct as3722_pctrl_info *as_pci; 543 int ret; 544 545 device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent)); 546 547 as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL); 548 if (!as_pci) 549 return -ENOMEM; 550 551 as_pci->dev = &pdev->dev; 552 as_pci->as3722 = dev_get_drvdata(pdev->dev.parent); 553 554 as_pci->pins = as3722_pins_desc; 555 as_pci->num_pins = ARRAY_SIZE(as3722_pins_desc); 556 as_pci->functions = as3722_pin_function; 557 as_pci->num_functions = ARRAY_SIZE(as3722_pin_function); 558 as_pci->pin_groups = as3722_pingroups; 559 as_pci->num_pin_groups = ARRAY_SIZE(as3722_pingroups); 560 as3722_pinctrl_desc.name = dev_name(&pdev->dev); 561 as_pci->pctl = devm_pinctrl_register(&pdev->dev, &as3722_pinctrl_desc, 562 as_pci); 563 if (IS_ERR(as_pci->pctl)) { 564 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 565 return PTR_ERR(as_pci->pctl); 566 } 567 568 as_pci->gpio_chip = as3722_gpio_chip; 569 as_pci->gpio_chip.parent = &pdev->dev; 570 ret = devm_gpiochip_add_data(&pdev->dev, &as_pci->gpio_chip, as_pci); 571 if (ret < 0) { 572 dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret); 573 return ret; 574 } 575 576 ret = gpiochip_add_pin_range(&as_pci->gpio_chip, dev_name(&pdev->dev), 577 0, 0, AS3722_PIN_NUM); 578 if (ret < 0) { 579 dev_err(&pdev->dev, "Couldn't add pin range, %d\n", ret); 580 return ret; 581 } 582 583 return 0; 584 } 585 586 static const struct of_device_id as3722_pinctrl_of_match[] = { 587 { .compatible = "ams,as3722-pinctrl", }, 588 { }, 589 }; 590 MODULE_DEVICE_TABLE(of, as3722_pinctrl_of_match); 591 592 static struct platform_driver as3722_pinctrl_driver = { 593 .driver = { 594 .name = "as3722-pinctrl", 595 .of_match_table = as3722_pinctrl_of_match, 596 }, 597 .probe = as3722_pinctrl_probe, 598 }; 599 module_platform_driver(as3722_pinctrl_driver); 600 601 MODULE_ALIAS("platform:as3722-pinctrl"); 602 MODULE_DESCRIPTION("AS3722 pin control and GPIO driver"); 603 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>"); 604 MODULE_LICENSE("GPL v2"); 605