1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Apple SoC pinctrl+GPIO+external IRQ driver 4 * 5 * Copyright (C) The Asahi Linux Contributors 6 * Copyright (C) 2020 Corellium LLC 7 * 8 * Based on: pinctrl-pistachio.c 9 * Copyright (C) 2014 Imagination Technologies Ltd. 10 * Copyright (C) 2014 Google, Inc. 11 */ 12 13 #include <dt-bindings/pinctrl/apple.h> 14 15 #include <linux/bitfield.h> 16 #include <linux/bits.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinmux.h> 28 29 #include "pinctrl-utils.h" 30 #include "core.h" 31 #include "pinmux.h" 32 33 struct apple_gpio_pinctrl { 34 struct device *dev; 35 struct pinctrl_dev *pctldev; 36 37 void __iomem *base; 38 struct regmap *map; 39 40 struct pinctrl_desc pinctrl_desc; 41 struct gpio_chip gpio_chip; 42 u8 irqgrps[]; 43 }; 44 45 #define REG_GPIO(x) (4 * (x)) 46 #define REG_GPIOx_DATA BIT(0) 47 #define REG_GPIOx_MODE GENMASK(3, 1) 48 #define REG_GPIOx_OUT 1 49 #define REG_GPIOx_IN_IRQ_HI 2 50 #define REG_GPIOx_IN_IRQ_LO 3 51 #define REG_GPIOx_IN_IRQ_UP 4 52 #define REG_GPIOx_IN_IRQ_DN 5 53 #define REG_GPIOx_IN_IRQ_ANY 6 54 #define REG_GPIOx_IN_IRQ_OFF 7 55 #define REG_GPIOx_PERIPH GENMASK(6, 5) 56 #define REG_GPIOx_PULL GENMASK(8, 7) 57 #define REG_GPIOx_PULL_OFF 0 58 #define REG_GPIOx_PULL_DOWN 1 59 #define REG_GPIOx_PULL_UP_STRONG 2 60 #define REG_GPIOx_PULL_UP 3 61 #define REG_GPIOx_INPUT_ENABLE BIT(9) 62 #define REG_GPIOx_DRIVE_STRENGTH0 GENMASK(11, 10) 63 #define REG_GPIOx_SCHMITT BIT(15) 64 #define REG_GPIOx_GRP GENMASK(18, 16) 65 #define REG_GPIOx_LOCK BIT(21) 66 #define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22) 67 #define REG_IRQ(g, x) (0x800 + 0x40 * (g) + 4 * ((x) >> 5)) 68 69 static const struct regmap_config regmap_config = { 70 .reg_bits = 32, 71 .val_bits = 32, 72 .reg_stride = 4, 73 .cache_type = REGCACHE_FLAT, 74 .max_register = 512 * sizeof(u32), 75 .num_reg_defaults_raw = 512, 76 .use_relaxed_mmio = true, 77 .use_raw_spinlock = true, 78 }; 79 80 /* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */ 81 static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl, 82 unsigned int pin, u32 mask, u32 value) 83 { 84 regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value); 85 } 86 87 static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl, 88 unsigned int pin) 89 { 90 int ret; 91 u32 val; 92 93 ret = regmap_read(pctl->map, REG_GPIO(pin), &val); 94 if (ret) 95 return 0; 96 97 return val; 98 } 99 100 /* Pin controller functions */ 101 102 static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev, 103 struct device_node *node, 104 struct pinctrl_map **map, 105 unsigned int *num_maps) 106 { 107 unsigned int reserved_maps; 108 struct apple_gpio_pinctrl *pctl; 109 u32 pinfunc, pin, func; 110 int num_pins, i, ret; 111 const char *group_name; 112 const char *function_name; 113 114 *map = NULL; 115 *num_maps = 0; 116 reserved_maps = 0; 117 118 pctl = pinctrl_dev_get_drvdata(pctldev); 119 120 ret = of_property_count_u32_elems(node, "pinmux"); 121 if (ret <= 0) { 122 dev_err(pctl->dev, 123 "missing or empty pinmux property in node %pOFn.\n", 124 node); 125 return ret ? ret : -EINVAL; 126 } 127 128 num_pins = ret; 129 130 ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, num_pins); 131 if (ret) 132 return ret; 133 134 for (i = 0; i < num_pins; i++) { 135 ret = of_property_read_u32_index(node, "pinmux", i, &pinfunc); 136 if (ret) 137 goto free_map; 138 139 pin = APPLE_PIN(pinfunc); 140 func = APPLE_FUNC(pinfunc); 141 142 if (func >= pinmux_generic_get_function_count(pctldev)) { 143 ret = -EINVAL; 144 goto free_map; 145 } 146 147 group_name = pinctrl_generic_get_group_name(pctldev, pin); 148 function_name = pinmux_generic_get_function_name(pctl->pctldev, func); 149 ret = pinctrl_utils_add_map_mux(pctl->pctldev, map, 150 &reserved_maps, num_maps, 151 group_name, function_name); 152 if (ret) 153 goto free_map; 154 } 155 156 free_map: 157 if (ret < 0) 158 pinctrl_utils_free_map(pctldev, *map, *num_maps); 159 160 return ret; 161 } 162 163 static const struct pinctrl_ops apple_gpio_pinctrl_ops = { 164 .get_groups_count = pinctrl_generic_get_group_count, 165 .get_group_name = pinctrl_generic_get_group_name, 166 .get_group_pins = pinctrl_generic_get_group_pins, 167 .dt_node_to_map = apple_gpio_dt_node_to_map, 168 .dt_free_map = pinctrl_utils_free_map, 169 }; 170 171 /* Pin multiplexer functions */ 172 173 static bool apple_gpio_pinmux_func_is_gpio(struct pinctrl_dev *pctldev, 174 unsigned int selector) 175 { 176 /* Function selector 0 is always the GPIO mode */ 177 return (selector == 0); 178 } 179 180 static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned int func, 181 unsigned int group) 182 { 183 struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 184 185 apple_gpio_set_reg( 186 pctl, group, REG_GPIOx_PERIPH | REG_GPIOx_INPUT_ENABLE, 187 FIELD_PREP(REG_GPIOx_PERIPH, func) | REG_GPIOx_INPUT_ENABLE); 188 189 return 0; 190 } 191 192 static const struct pinmux_ops apple_gpio_pinmux_ops = { 193 .get_functions_count = pinmux_generic_get_function_count, 194 .get_function_name = pinmux_generic_get_function_name, 195 .get_function_groups = pinmux_generic_get_function_groups, 196 .function_is_gpio = apple_gpio_pinmux_func_is_gpio, 197 .set_mux = apple_gpio_pinmux_set, 198 .strict = true, 199 }; 200 201 /* GPIO chip functions */ 202 203 static int apple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 204 { 205 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 206 unsigned int reg = apple_gpio_get_reg(pctl, offset); 207 208 if (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT) 209 return GPIO_LINE_DIRECTION_OUT; 210 return GPIO_LINE_DIRECTION_IN; 211 } 212 213 static int apple_gpio_get(struct gpio_chip *chip, unsigned int offset) 214 { 215 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 216 unsigned int reg = apple_gpio_get_reg(pctl, offset); 217 218 /* 219 * If this is an input GPIO, read the actual value (not the 220 * cached regmap value) 221 */ 222 if (FIELD_GET(REG_GPIOx_MODE, reg) != REG_GPIOx_OUT) 223 reg = readl_relaxed(pctl->base + REG_GPIO(offset)); 224 225 return !!(reg & REG_GPIOx_DATA); 226 } 227 228 static int apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 229 { 230 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 231 232 apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, value ? REG_GPIOx_DATA : 0); 233 234 return 0; 235 } 236 237 static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 238 { 239 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 240 241 apple_gpio_set_reg(pctl, offset, 242 REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA | 243 REG_GPIOx_INPUT_ENABLE, 244 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF) | 245 REG_GPIOx_INPUT_ENABLE); 246 return 0; 247 } 248 249 static int apple_gpio_direction_output(struct gpio_chip *chip, 250 unsigned int offset, int value) 251 { 252 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 253 254 apple_gpio_set_reg(pctl, offset, 255 REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA, 256 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_OUT) | 257 (value ? REG_GPIOx_DATA : 0)); 258 return 0; 259 } 260 261 /* IRQ chip functions */ 262 263 static void apple_gpio_irq_ack(struct irq_data *data) 264 { 265 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data)); 266 unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq)); 267 268 writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq)); 269 } 270 271 static unsigned int apple_gpio_irq_type(unsigned int type) 272 { 273 switch (type & IRQ_TYPE_SENSE_MASK) { 274 case IRQ_TYPE_EDGE_RISING: 275 return REG_GPIOx_IN_IRQ_UP; 276 case IRQ_TYPE_EDGE_FALLING: 277 return REG_GPIOx_IN_IRQ_DN; 278 case IRQ_TYPE_EDGE_BOTH: 279 return REG_GPIOx_IN_IRQ_ANY; 280 case IRQ_TYPE_LEVEL_HIGH: 281 return REG_GPIOx_IN_IRQ_HI; 282 case IRQ_TYPE_LEVEL_LOW: 283 return REG_GPIOx_IN_IRQ_LO; 284 default: 285 return REG_GPIOx_IN_IRQ_OFF; 286 } 287 } 288 289 static void apple_gpio_irq_mask(struct irq_data *data) 290 { 291 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 292 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc); 293 294 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, 295 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF)); 296 gpiochip_disable_irq(gc, data->hwirq); 297 } 298 299 static void apple_gpio_irq_unmask(struct irq_data *data) 300 { 301 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 302 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc); 303 unsigned int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data)); 304 305 gpiochip_enable_irq(gc, data->hwirq); 306 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, 307 FIELD_PREP(REG_GPIOx_MODE, irqtype)); 308 } 309 310 static unsigned int apple_gpio_irq_startup(struct irq_data *data) 311 { 312 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 313 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); 314 315 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP, 316 FIELD_PREP(REG_GPIOx_GRP, 0)); 317 318 apple_gpio_direction_input(chip, data->hwirq); 319 apple_gpio_irq_unmask(data); 320 321 return 0; 322 } 323 324 static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type) 325 { 326 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data)); 327 unsigned int irqtype = apple_gpio_irq_type(type); 328 329 if (irqtype == REG_GPIOx_IN_IRQ_OFF) 330 return -EINVAL; 331 332 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, 333 FIELD_PREP(REG_GPIOx_MODE, irqtype)); 334 335 if (type & IRQ_TYPE_LEVEL_MASK) 336 irq_set_handler_locked(data, handle_level_irq); 337 else 338 irq_set_handler_locked(data, handle_edge_irq); 339 return 0; 340 } 341 342 static void apple_gpio_irq_handler(struct irq_desc *desc) 343 { 344 struct irq_chip *chip = irq_desc_get_chip(desc); 345 u8 *grpp = irq_desc_get_handler_data(desc); 346 struct apple_gpio_pinctrl *pctl; 347 unsigned int pinh, pinl; 348 unsigned long pending; 349 struct gpio_chip *gc; 350 351 pctl = container_of(grpp - *grpp, typeof(*pctl), irqgrps[0]); 352 gc = &pctl->gpio_chip; 353 354 chained_irq_enter(chip, desc); 355 for (pinh = 0; pinh < gc->ngpio; pinh += 32) { 356 pending = readl_relaxed(pctl->base + REG_IRQ(*grpp, pinh)); 357 for_each_set_bit(pinl, &pending, 32) 358 generic_handle_domain_irq(gc->irq.domain, pinh + pinl); 359 } 360 chained_irq_exit(chip, desc); 361 } 362 363 static const struct irq_chip apple_gpio_irqchip = { 364 .name = "Apple-GPIO", 365 .irq_startup = apple_gpio_irq_startup, 366 .irq_ack = apple_gpio_irq_ack, 367 .irq_mask = apple_gpio_irq_mask, 368 .irq_unmask = apple_gpio_irq_unmask, 369 .irq_set_type = apple_gpio_irq_set_type, 370 .flags = IRQCHIP_IMMUTABLE, 371 GPIOCHIP_IRQ_RESOURCE_HELPERS, 372 }; 373 374 /* Probe & register */ 375 376 static int apple_gpio_register(struct apple_gpio_pinctrl *pctl) 377 { 378 struct gpio_irq_chip *girq = &pctl->gpio_chip.irq; 379 void **irq_data = NULL; 380 int ret; 381 382 pctl->gpio_chip.label = dev_name(pctl->dev); 383 pctl->gpio_chip.request = gpiochip_generic_request; 384 pctl->gpio_chip.free = gpiochip_generic_free; 385 pctl->gpio_chip.get_direction = apple_gpio_get_direction; 386 pctl->gpio_chip.direction_input = apple_gpio_direction_input; 387 pctl->gpio_chip.direction_output = apple_gpio_direction_output; 388 pctl->gpio_chip.get = apple_gpio_get; 389 pctl->gpio_chip.set = apple_gpio_set; 390 pctl->gpio_chip.base = -1; 391 pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins; 392 pctl->gpio_chip.parent = pctl->dev; 393 394 if (girq->num_parents) { 395 int i; 396 397 gpio_irq_chip_set_chip(girq, &apple_gpio_irqchip); 398 girq->parent_handler = apple_gpio_irq_handler; 399 400 girq->parents = kmalloc_array(girq->num_parents, 401 sizeof(*girq->parents), 402 GFP_KERNEL); 403 irq_data = kmalloc_objs(*irq_data, girq->num_parents); 404 if (!girq->parents || !irq_data) { 405 ret = -ENOMEM; 406 goto out_free_irq_data; 407 } 408 409 for (i = 0; i < girq->num_parents; i++) { 410 ret = platform_get_irq(to_platform_device(pctl->dev), i); 411 if (ret < 0) 412 goto out_free_irq_data; 413 414 girq->parents[i] = ret; 415 pctl->irqgrps[i] = i; 416 irq_data[i] = &pctl->irqgrps[i]; 417 } 418 419 girq->parent_handler_data_array = irq_data; 420 girq->per_parent_data = true; 421 girq->default_type = IRQ_TYPE_NONE; 422 girq->handler = handle_level_irq; 423 } 424 425 ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl); 426 427 out_free_irq_data: 428 kfree(girq->parents); 429 kfree(irq_data); 430 431 return ret; 432 } 433 434 static int apple_gpio_pinctrl_probe(struct platform_device *pdev) 435 { 436 struct apple_gpio_pinctrl *pctl; 437 struct pinctrl_pin_desc *pins; 438 unsigned int npins; 439 const char **pin_names; 440 unsigned int *pin_nums; 441 static const char *pinmux_functions[] = { 442 "gpio", "periph1", "periph2", "periph3" 443 }; 444 unsigned int i, nirqs = 0; 445 int res; 446 447 if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) { 448 res = platform_irq_count(pdev); 449 if (res > 0) 450 nirqs = res; 451 } 452 453 pctl = devm_kzalloc(&pdev->dev, struct_size(pctl, irqgrps, nirqs), 454 GFP_KERNEL); 455 if (!pctl) 456 return -ENOMEM; 457 pctl->dev = &pdev->dev; 458 pctl->gpio_chip.irq.num_parents = nirqs; 459 dev_set_drvdata(&pdev->dev, pctl); 460 461 if (of_property_read_u32(pdev->dev.of_node, "apple,npins", &npins)) 462 return dev_err_probe(&pdev->dev, -EINVAL, 463 "apple,npins property not found\n"); 464 465 pins = devm_kmalloc_array(&pdev->dev, npins, sizeof(pins[0]), 466 GFP_KERNEL); 467 pin_names = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_names[0]), 468 GFP_KERNEL); 469 pin_nums = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_nums[0]), 470 GFP_KERNEL); 471 if (!pins || !pin_names || !pin_nums) 472 return -ENOMEM; 473 474 pctl->base = devm_platform_ioremap_resource(pdev, 0); 475 if (IS_ERR(pctl->base)) 476 return PTR_ERR(pctl->base); 477 478 pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, ®map_config); 479 if (IS_ERR(pctl->map)) 480 return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map), 481 "Failed to create regmap\n"); 482 483 for (i = 0; i < npins; i++) { 484 pins[i].number = i; 485 pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "PIN%u", i); 486 if (!pins[i].name) 487 return -ENOMEM; 488 489 pins[i].drv_data = pctl; 490 pin_names[i] = pins[i].name; 491 pin_nums[i] = i; 492 } 493 494 pctl->pinctrl_desc.name = dev_name(pctl->dev); 495 pctl->pinctrl_desc.pins = pins; 496 pctl->pinctrl_desc.npins = npins; 497 pctl->pinctrl_desc.pctlops = &apple_gpio_pinctrl_ops; 498 pctl->pinctrl_desc.pmxops = &apple_gpio_pinmux_ops; 499 500 pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pctl->pinctrl_desc, pctl); 501 if (IS_ERR(pctl->pctldev)) 502 return dev_err_probe(&pdev->dev, PTR_ERR(pctl->pctldev), 503 "Failed to register pinctrl device.\n"); 504 505 for (i = 0; i < npins; i++) { 506 res = pinctrl_generic_add_group(pctl->pctldev, pins[i].name, 507 pin_nums + i, 1, pctl); 508 if (res < 0) 509 return dev_err_probe(pctl->dev, res, 510 "Failed to register group"); 511 } 512 513 for (i = 0; i < ARRAY_SIZE(pinmux_functions); ++i) { 514 res = pinmux_generic_add_function(pctl->pctldev, pinmux_functions[i], 515 pin_names, npins, pctl); 516 if (res < 0) 517 return dev_err_probe(pctl->dev, res, 518 "Failed to register function."); 519 } 520 521 return apple_gpio_register(pctl); 522 } 523 524 static const struct of_device_id apple_gpio_pinctrl_of_match[] = { 525 { .compatible = "apple,t8103-pinctrl", }, 526 { .compatible = "apple,pinctrl", }, 527 { } 528 }; 529 MODULE_DEVICE_TABLE(of, apple_gpio_pinctrl_of_match); 530 531 static struct platform_driver apple_gpio_pinctrl_driver = { 532 .driver = { 533 .name = "apple-gpio-pinctrl", 534 .of_match_table = apple_gpio_pinctrl_of_match, 535 .suppress_bind_attrs = true, 536 }, 537 .probe = apple_gpio_pinctrl_probe, 538 }; 539 module_platform_driver(apple_gpio_pinctrl_driver); 540 541 MODULE_DESCRIPTION("Apple pinctrl/GPIO driver"); 542 MODULE_AUTHOR("Stan Skowronek <stan@corellium.com>"); 543 MODULE_AUTHOR("Joey Gouly <joey.gouly@arm.com>"); 544 MODULE_LICENSE("GPL v2"); 545