1 /* 2 * GPIO driver for AMD 3 * 4 * Copyright (c) 2014,2015 AMD Corporation. 5 * Authors: Ken Xue <Ken.Xue@amd.com> 6 * Wu, Jeff <Jeff.Wu@amd.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> 13 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 14 * 15 */ 16 17 #include <linux/err.h> 18 #include <linux/bug.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/spinlock.h> 22 #include <linux/compiler.h> 23 #include <linux/types.h> 24 #include <linux/errno.h> 25 #include <linux/log2.h> 26 #include <linux/io.h> 27 #include <linux/gpio.h> 28 #include <linux/slab.h> 29 #include <linux/platform_device.h> 30 #include <linux/mutex.h> 31 #include <linux/acpi.h> 32 #include <linux/seq_file.h> 33 #include <linux/interrupt.h> 34 #include <linux/list.h> 35 #include <linux/bitops.h> 36 #include <linux/pinctrl/pinconf.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 39 #include "core.h" 40 #include "pinctrl-utils.h" 41 #include "pinctrl-amd.h" 42 43 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 44 { 45 unsigned long flags; 46 u32 pin_reg; 47 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 48 49 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 50 pin_reg = readl(gpio_dev->base + offset * 4); 51 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 52 53 return !(pin_reg & BIT(OUTPUT_ENABLE_OFF)); 54 } 55 56 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 57 { 58 unsigned long flags; 59 u32 pin_reg; 60 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 61 62 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 63 pin_reg = readl(gpio_dev->base + offset * 4); 64 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 65 writel(pin_reg, gpio_dev->base + offset * 4); 66 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 67 68 return 0; 69 } 70 71 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 72 int value) 73 { 74 u32 pin_reg; 75 unsigned long flags; 76 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 77 78 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 79 pin_reg = readl(gpio_dev->base + offset * 4); 80 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 81 if (value) 82 pin_reg |= BIT(OUTPUT_VALUE_OFF); 83 else 84 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 85 writel(pin_reg, gpio_dev->base + offset * 4); 86 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 87 88 return 0; 89 } 90 91 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 92 { 93 u32 pin_reg; 94 unsigned long flags; 95 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 96 97 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 98 pin_reg = readl(gpio_dev->base + offset * 4); 99 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 100 101 return !!(pin_reg & BIT(PIN_STS_OFF)); 102 } 103 104 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 105 { 106 u32 pin_reg; 107 unsigned long flags; 108 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 109 110 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 111 pin_reg = readl(gpio_dev->base + offset * 4); 112 if (value) 113 pin_reg |= BIT(OUTPUT_VALUE_OFF); 114 else 115 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 116 writel(pin_reg, gpio_dev->base + offset * 4); 117 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 118 } 119 120 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 121 unsigned debounce) 122 { 123 u32 time; 124 u32 pin_reg; 125 int ret = 0; 126 unsigned long flags; 127 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 128 129 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 130 pin_reg = readl(gpio_dev->base + offset * 4); 131 132 if (debounce) { 133 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 134 pin_reg &= ~DB_TMR_OUT_MASK; 135 /* 136 Debounce Debounce Timer Max 137 TmrLarge TmrOutUnit Unit Debounce 138 Time 139 0 0 61 usec (2 RtcClk) 976 usec 140 0 1 244 usec (8 RtcClk) 3.9 msec 141 1 0 15.6 msec (512 RtcClk) 250 msec 142 1 1 62.5 msec (2048 RtcClk) 1 sec 143 */ 144 145 if (debounce < 61) { 146 pin_reg |= 1; 147 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 148 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 149 } else if (debounce < 976) { 150 time = debounce / 61; 151 pin_reg |= time & DB_TMR_OUT_MASK; 152 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 153 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 154 } else if (debounce < 3900) { 155 time = debounce / 244; 156 pin_reg |= time & DB_TMR_OUT_MASK; 157 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 158 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 159 } else if (debounce < 250000) { 160 time = debounce / 15600; 161 pin_reg |= time & DB_TMR_OUT_MASK; 162 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 163 pin_reg |= BIT(DB_TMR_LARGE_OFF); 164 } else if (debounce < 1000000) { 165 time = debounce / 62500; 166 pin_reg |= time & DB_TMR_OUT_MASK; 167 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 168 pin_reg |= BIT(DB_TMR_LARGE_OFF); 169 } else { 170 pin_reg &= ~DB_CNTRl_MASK; 171 ret = -EINVAL; 172 } 173 } else { 174 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 175 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 176 pin_reg &= ~DB_TMR_OUT_MASK; 177 pin_reg &= ~DB_CNTRl_MASK; 178 } 179 writel(pin_reg, gpio_dev->base + offset * 4); 180 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 181 182 return ret; 183 } 184 185 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 186 unsigned long config) 187 { 188 u32 debounce; 189 190 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 191 return -ENOTSUPP; 192 193 debounce = pinconf_to_config_argument(config); 194 return amd_gpio_set_debounce(gc, offset, debounce); 195 } 196 197 #ifdef CONFIG_DEBUG_FS 198 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 199 { 200 u32 pin_reg; 201 unsigned long flags; 202 unsigned int bank, i, pin_num; 203 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 204 205 char *level_trig; 206 char *active_level; 207 char *interrupt_enable; 208 char *interrupt_mask; 209 char *wake_cntrl0; 210 char *wake_cntrl1; 211 char *wake_cntrl2; 212 char *pin_sts; 213 char *pull_up_sel; 214 char *pull_up_enable; 215 char *pull_down_enable; 216 char *output_value; 217 char *output_enable; 218 219 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 220 seq_printf(s, "GPIO bank%d\t", bank); 221 222 switch (bank) { 223 case 0: 224 i = 0; 225 pin_num = AMD_GPIO_PINS_BANK0; 226 break; 227 case 1: 228 i = 64; 229 pin_num = AMD_GPIO_PINS_BANK1 + i; 230 break; 231 case 2: 232 i = 128; 233 pin_num = AMD_GPIO_PINS_BANK2 + i; 234 break; 235 case 3: 236 i = 192; 237 pin_num = AMD_GPIO_PINS_BANK3 + i; 238 break; 239 default: 240 /* Illegal bank number, ignore */ 241 continue; 242 } 243 for (; i < pin_num; i++) { 244 seq_printf(s, "pin%d\t", i); 245 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 246 pin_reg = readl(gpio_dev->base + i * 4); 247 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 248 249 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 250 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 251 ACTIVE_LEVEL_MASK; 252 interrupt_enable = "interrupt is enabled|"; 253 254 if (level == ACTIVE_LEVEL_HIGH) 255 active_level = "Active high|"; 256 else if (level == ACTIVE_LEVEL_LOW) 257 active_level = "Active low|"; 258 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 259 level == ACTIVE_LEVEL_BOTH) 260 active_level = "Active on both|"; 261 else 262 active_level = "Unknown Active level|"; 263 264 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 265 level_trig = "Level trigger|"; 266 else 267 level_trig = "Edge trigger|"; 268 269 } else { 270 interrupt_enable = 271 "interrupt is disabled|"; 272 active_level = " "; 273 level_trig = " "; 274 } 275 276 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 277 interrupt_mask = 278 "interrupt is unmasked|"; 279 else 280 interrupt_mask = 281 "interrupt is masked|"; 282 283 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 284 wake_cntrl0 = "enable wakeup in S0i3 state|"; 285 else 286 wake_cntrl0 = "disable wakeup in S0i3 state|"; 287 288 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 289 wake_cntrl1 = "enable wakeup in S3 state|"; 290 else 291 wake_cntrl1 = "disable wakeup in S3 state|"; 292 293 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 294 wake_cntrl2 = "enable wakeup in S4/S5 state|"; 295 else 296 wake_cntrl2 = "disable wakeup in S4/S5 state|"; 297 298 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 299 pull_up_enable = "pull-up is enabled|"; 300 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 301 pull_up_sel = "8k pull-up|"; 302 else 303 pull_up_sel = "4k pull-up|"; 304 } else { 305 pull_up_enable = "pull-up is disabled|"; 306 pull_up_sel = " "; 307 } 308 309 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 310 pull_down_enable = "pull-down is enabled|"; 311 else 312 pull_down_enable = "Pull-down is disabled|"; 313 314 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 315 pin_sts = " "; 316 output_enable = "output is enabled|"; 317 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 318 output_value = "output is high|"; 319 else 320 output_value = "output is low|"; 321 } else { 322 output_enable = "output is disabled|"; 323 output_value = " "; 324 325 if (pin_reg & BIT(PIN_STS_OFF)) 326 pin_sts = "input is high|"; 327 else 328 pin_sts = "input is low|"; 329 } 330 331 seq_printf(s, "%s %s %s %s %s %s\n" 332 " %s %s %s %s %s %s %s 0x%x\n", 333 level_trig, active_level, interrupt_enable, 334 interrupt_mask, wake_cntrl0, wake_cntrl1, 335 wake_cntrl2, pin_sts, pull_up_sel, 336 pull_up_enable, pull_down_enable, 337 output_value, output_enable, pin_reg); 338 } 339 } 340 } 341 #else 342 #define amd_gpio_dbg_show NULL 343 #endif 344 345 static void amd_gpio_irq_enable(struct irq_data *d) 346 { 347 u32 pin_reg; 348 unsigned long flags; 349 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 350 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 351 u32 mask = BIT(INTERRUPT_ENABLE_OFF) | BIT(INTERRUPT_MASK_OFF); 352 353 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 354 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 355 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 356 pin_reg |= BIT(INTERRUPT_MASK_OFF); 357 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 358 /* 359 * When debounce logic is enabled it takes ~900 us before interrupts 360 * can be enabled. During this "debounce warm up" period the 361 * "INTERRUPT_ENABLE" bit will read as 0. Poll the bit here until it 362 * reads back as 1, signaling that interrupts are now enabled. 363 */ 364 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 365 continue; 366 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 367 } 368 369 static void amd_gpio_irq_disable(struct irq_data *d) 370 { 371 u32 pin_reg; 372 unsigned long flags; 373 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 374 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 375 376 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 377 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 378 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 379 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 380 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 381 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 382 } 383 384 static void amd_gpio_irq_mask(struct irq_data *d) 385 { 386 u32 pin_reg; 387 unsigned long flags; 388 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 389 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 390 391 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 392 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 393 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 394 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 395 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 396 } 397 398 static void amd_gpio_irq_unmask(struct irq_data *d) 399 { 400 u32 pin_reg; 401 unsigned long flags; 402 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 403 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 404 405 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 406 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 407 pin_reg |= BIT(INTERRUPT_MASK_OFF); 408 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 409 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 410 } 411 412 static void amd_gpio_irq_eoi(struct irq_data *d) 413 { 414 u32 reg; 415 unsigned long flags; 416 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 417 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 418 419 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 420 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 421 reg |= EOI_MASK; 422 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 423 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 424 } 425 426 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 427 { 428 int ret = 0; 429 u32 pin_reg; 430 unsigned long flags, irq_flags; 431 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 432 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 433 434 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 435 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 436 437 /* Ignore the settings coming from the client and 438 * read the values from the ACPI tables 439 * while setting the trigger type 440 */ 441 442 irq_flags = irq_get_trigger_type(d->irq); 443 if (irq_flags != IRQ_TYPE_NONE) 444 type = irq_flags; 445 446 switch (type & IRQ_TYPE_SENSE_MASK) { 447 case IRQ_TYPE_EDGE_RISING: 448 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 449 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 450 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 451 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 452 irq_set_handler_locked(d, handle_edge_irq); 453 break; 454 455 case IRQ_TYPE_EDGE_FALLING: 456 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 457 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 458 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 459 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 460 irq_set_handler_locked(d, handle_edge_irq); 461 break; 462 463 case IRQ_TYPE_EDGE_BOTH: 464 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 465 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 466 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 467 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 468 irq_set_handler_locked(d, handle_edge_irq); 469 break; 470 471 case IRQ_TYPE_LEVEL_HIGH: 472 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 473 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 474 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 475 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 476 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; 477 irq_set_handler_locked(d, handle_level_irq); 478 break; 479 480 case IRQ_TYPE_LEVEL_LOW: 481 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 482 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 483 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 484 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 485 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; 486 irq_set_handler_locked(d, handle_level_irq); 487 break; 488 489 case IRQ_TYPE_NONE: 490 break; 491 492 default: 493 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 494 ret = -EINVAL; 495 } 496 497 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 498 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 499 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 500 501 return ret; 502 } 503 504 static void amd_irq_ack(struct irq_data *d) 505 { 506 /* 507 * based on HW design,there is no need to ack HW 508 * before handle current irq. But this routine is 509 * necessary for handle_edge_irq 510 */ 511 } 512 513 static struct irq_chip amd_gpio_irqchip = { 514 .name = "amd_gpio", 515 .irq_ack = amd_irq_ack, 516 .irq_enable = amd_gpio_irq_enable, 517 .irq_disable = amd_gpio_irq_disable, 518 .irq_mask = amd_gpio_irq_mask, 519 .irq_unmask = amd_gpio_irq_unmask, 520 .irq_eoi = amd_gpio_irq_eoi, 521 .irq_set_type = amd_gpio_irq_set_type, 522 .flags = IRQCHIP_SKIP_SET_WAKE, 523 }; 524 525 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 526 527 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 528 { 529 struct amd_gpio *gpio_dev = dev_id; 530 struct gpio_chip *gc = &gpio_dev->gc; 531 irqreturn_t ret = IRQ_NONE; 532 unsigned int i, irqnr; 533 unsigned long flags; 534 u32 *regs, regval; 535 u64 status, mask; 536 537 /* Read the wake status */ 538 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 539 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 540 status <<= 32; 541 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 542 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 543 544 /* Bit 0-45 contain the relevant status bits */ 545 status &= (1ULL << 46) - 1; 546 regs = gpio_dev->base; 547 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 548 if (!(status & mask)) 549 continue; 550 status &= ~mask; 551 552 /* Each status bit covers four pins */ 553 for (i = 0; i < 4; i++) { 554 regval = readl(regs + i); 555 if (!(regval & PIN_IRQ_PENDING) || 556 !(regval & BIT(INTERRUPT_MASK_OFF))) 557 continue; 558 irq = irq_find_mapping(gc->irq.domain, irqnr + i); 559 generic_handle_irq(irq); 560 561 /* Clear interrupt. 562 * We must read the pin register again, in case the 563 * value was changed while executing 564 * generic_handle_irq() above. 565 */ 566 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 567 regval = readl(regs + i); 568 writel(regval, regs + i); 569 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 570 ret = IRQ_HANDLED; 571 } 572 } 573 574 /* Signal EOI to the GPIO unit */ 575 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 576 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 577 regval |= EOI_MASK; 578 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 579 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 580 581 return ret; 582 } 583 584 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 585 { 586 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 587 588 return gpio_dev->ngroups; 589 } 590 591 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 592 unsigned group) 593 { 594 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 595 596 return gpio_dev->groups[group].name; 597 } 598 599 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 600 unsigned group, 601 const unsigned **pins, 602 unsigned *num_pins) 603 { 604 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 605 606 *pins = gpio_dev->groups[group].pins; 607 *num_pins = gpio_dev->groups[group].npins; 608 return 0; 609 } 610 611 static const struct pinctrl_ops amd_pinctrl_ops = { 612 .get_groups_count = amd_get_groups_count, 613 .get_group_name = amd_get_group_name, 614 .get_group_pins = amd_get_group_pins, 615 #ifdef CONFIG_OF 616 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 617 .dt_free_map = pinctrl_utils_free_map, 618 #endif 619 }; 620 621 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 622 unsigned int pin, 623 unsigned long *config) 624 { 625 u32 pin_reg; 626 unsigned arg; 627 unsigned long flags; 628 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 629 enum pin_config_param param = pinconf_to_config_param(*config); 630 631 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 632 pin_reg = readl(gpio_dev->base + pin*4); 633 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 634 switch (param) { 635 case PIN_CONFIG_INPUT_DEBOUNCE: 636 arg = pin_reg & DB_TMR_OUT_MASK; 637 break; 638 639 case PIN_CONFIG_BIAS_PULL_DOWN: 640 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 641 break; 642 643 case PIN_CONFIG_BIAS_PULL_UP: 644 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 645 break; 646 647 case PIN_CONFIG_DRIVE_STRENGTH: 648 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 649 break; 650 651 default: 652 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 653 param); 654 return -ENOTSUPP; 655 } 656 657 *config = pinconf_to_config_packed(param, arg); 658 659 return 0; 660 } 661 662 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 663 unsigned long *configs, unsigned num_configs) 664 { 665 int i; 666 u32 arg; 667 int ret = 0; 668 u32 pin_reg; 669 unsigned long flags; 670 enum pin_config_param param; 671 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 672 673 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 674 for (i = 0; i < num_configs; i++) { 675 param = pinconf_to_config_param(configs[i]); 676 arg = pinconf_to_config_argument(configs[i]); 677 pin_reg = readl(gpio_dev->base + pin*4); 678 679 switch (param) { 680 case PIN_CONFIG_INPUT_DEBOUNCE: 681 pin_reg &= ~DB_TMR_OUT_MASK; 682 pin_reg |= arg & DB_TMR_OUT_MASK; 683 break; 684 685 case PIN_CONFIG_BIAS_PULL_DOWN: 686 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 687 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 688 break; 689 690 case PIN_CONFIG_BIAS_PULL_UP: 691 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 692 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 693 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 694 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 695 break; 696 697 case PIN_CONFIG_DRIVE_STRENGTH: 698 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 699 << DRV_STRENGTH_SEL_OFF); 700 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 701 << DRV_STRENGTH_SEL_OFF; 702 break; 703 704 default: 705 dev_err(&gpio_dev->pdev->dev, 706 "Invalid config param %04x\n", param); 707 ret = -ENOTSUPP; 708 } 709 710 writel(pin_reg, gpio_dev->base + pin*4); 711 } 712 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 713 714 return ret; 715 } 716 717 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 718 unsigned int group, 719 unsigned long *config) 720 { 721 const unsigned *pins; 722 unsigned npins; 723 int ret; 724 725 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 726 if (ret) 727 return ret; 728 729 if (amd_pinconf_get(pctldev, pins[0], config)) 730 return -ENOTSUPP; 731 732 return 0; 733 } 734 735 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 736 unsigned group, unsigned long *configs, 737 unsigned num_configs) 738 { 739 const unsigned *pins; 740 unsigned npins; 741 int i, ret; 742 743 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 744 if (ret) 745 return ret; 746 for (i = 0; i < npins; i++) { 747 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 748 return -ENOTSUPP; 749 } 750 return 0; 751 } 752 753 static const struct pinconf_ops amd_pinconf_ops = { 754 .pin_config_get = amd_pinconf_get, 755 .pin_config_set = amd_pinconf_set, 756 .pin_config_group_get = amd_pinconf_group_get, 757 .pin_config_group_set = amd_pinconf_group_set, 758 }; 759 760 #ifdef CONFIG_PM_SLEEP 761 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 762 { 763 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 764 765 if (!pd) 766 return false; 767 768 /* 769 * Only restore the pin if it is actually in use by the kernel (or 770 * by userspace). 771 */ 772 if (pd->mux_owner || pd->gpio_owner || 773 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 774 return true; 775 776 return false; 777 } 778 779 static int amd_gpio_suspend(struct device *dev) 780 { 781 struct platform_device *pdev = to_platform_device(dev); 782 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); 783 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 784 int i; 785 786 for (i = 0; i < desc->npins; i++) { 787 int pin = desc->pins[i].number; 788 789 if (!amd_gpio_should_save(gpio_dev, pin)) 790 continue; 791 792 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4); 793 } 794 795 return 0; 796 } 797 798 static int amd_gpio_resume(struct device *dev) 799 { 800 struct platform_device *pdev = to_platform_device(dev); 801 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); 802 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 803 int i; 804 805 for (i = 0; i < desc->npins; i++) { 806 int pin = desc->pins[i].number; 807 808 if (!amd_gpio_should_save(gpio_dev, pin)) 809 continue; 810 811 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4); 812 } 813 814 return 0; 815 } 816 817 static const struct dev_pm_ops amd_gpio_pm_ops = { 818 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 819 amd_gpio_resume) 820 }; 821 #endif 822 823 static struct pinctrl_desc amd_pinctrl_desc = { 824 .pins = kerncz_pins, 825 .npins = ARRAY_SIZE(kerncz_pins), 826 .pctlops = &amd_pinctrl_ops, 827 .confops = &amd_pinconf_ops, 828 .owner = THIS_MODULE, 829 }; 830 831 static int amd_gpio_probe(struct platform_device *pdev) 832 { 833 int ret = 0; 834 int irq_base; 835 struct resource *res; 836 struct amd_gpio *gpio_dev; 837 838 gpio_dev = devm_kzalloc(&pdev->dev, 839 sizeof(struct amd_gpio), GFP_KERNEL); 840 if (!gpio_dev) 841 return -ENOMEM; 842 843 raw_spin_lock_init(&gpio_dev->lock); 844 845 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 846 if (!res) { 847 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 848 return -EINVAL; 849 } 850 851 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, 852 resource_size(res)); 853 if (!gpio_dev->base) 854 return -ENOMEM; 855 856 irq_base = platform_get_irq(pdev, 0); 857 if (irq_base < 0) { 858 dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base); 859 return irq_base; 860 } 861 862 #ifdef CONFIG_PM_SLEEP 863 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 864 sizeof(*gpio_dev->saved_regs), 865 GFP_KERNEL); 866 if (!gpio_dev->saved_regs) 867 return -ENOMEM; 868 #endif 869 870 gpio_dev->pdev = pdev; 871 gpio_dev->gc.get_direction = amd_gpio_get_direction; 872 gpio_dev->gc.direction_input = amd_gpio_direction_input; 873 gpio_dev->gc.direction_output = amd_gpio_direction_output; 874 gpio_dev->gc.get = amd_gpio_get_value; 875 gpio_dev->gc.set = amd_gpio_set_value; 876 gpio_dev->gc.set_config = amd_gpio_set_config; 877 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 878 879 gpio_dev->gc.base = -1; 880 gpio_dev->gc.label = pdev->name; 881 gpio_dev->gc.owner = THIS_MODULE; 882 gpio_dev->gc.parent = &pdev->dev; 883 gpio_dev->gc.ngpio = resource_size(res) / 4; 884 #if defined(CONFIG_OF_GPIO) 885 gpio_dev->gc.of_node = pdev->dev.of_node; 886 #endif 887 888 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 889 gpio_dev->groups = kerncz_groups; 890 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 891 892 amd_pinctrl_desc.name = dev_name(&pdev->dev); 893 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 894 gpio_dev); 895 if (IS_ERR(gpio_dev->pctrl)) { 896 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 897 return PTR_ERR(gpio_dev->pctrl); 898 } 899 900 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 901 if (ret) 902 return ret; 903 904 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 905 0, 0, gpio_dev->gc.ngpio); 906 if (ret) { 907 dev_err(&pdev->dev, "Failed to add pin range\n"); 908 goto out2; 909 } 910 911 ret = gpiochip_irqchip_add(&gpio_dev->gc, 912 &amd_gpio_irqchip, 913 0, 914 handle_simple_irq, 915 IRQ_TYPE_NONE); 916 if (ret) { 917 dev_err(&pdev->dev, "could not add irqchip\n"); 918 ret = -ENODEV; 919 goto out2; 920 } 921 922 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0, 923 KBUILD_MODNAME, gpio_dev); 924 if (ret) 925 goto out2; 926 927 platform_set_drvdata(pdev, gpio_dev); 928 929 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 930 return ret; 931 932 out2: 933 gpiochip_remove(&gpio_dev->gc); 934 935 return ret; 936 } 937 938 static int amd_gpio_remove(struct platform_device *pdev) 939 { 940 struct amd_gpio *gpio_dev; 941 942 gpio_dev = platform_get_drvdata(pdev); 943 944 gpiochip_remove(&gpio_dev->gc); 945 946 return 0; 947 } 948 949 static const struct acpi_device_id amd_gpio_acpi_match[] = { 950 { "AMD0030", 0 }, 951 { "AMDI0030", 0}, 952 { }, 953 }; 954 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 955 956 static struct platform_driver amd_gpio_driver = { 957 .driver = { 958 .name = "amd_gpio", 959 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 960 #ifdef CONFIG_PM_SLEEP 961 .pm = &amd_gpio_pm_ops, 962 #endif 963 }, 964 .probe = amd_gpio_probe, 965 .remove = amd_gpio_remove, 966 }; 967 968 module_platform_driver(amd_gpio_driver); 969 970 MODULE_LICENSE("GPL v2"); 971 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 972 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 973