xref: /linux/drivers/pinctrl/pinctrl-amd.c (revision dd5b2498d845f925904cb2afabb6ba11bfc317c5)
1 /*
2  * GPIO driver for AMD
3  *
4  * Copyright (c) 2014,2015 AMD Corporation.
5  * Authors: Ken Xue <Ken.Xue@amd.com>
6  *      Wu, Jeff <Jeff.Wu@amd.com>
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2, as published by the Free Software Foundation.
11  *
12  * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
13  *			Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
14  *
15  */
16 
17 #include <linux/err.h>
18 #include <linux/bug.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/compiler.h>
23 #include <linux/types.h>
24 #include <linux/errno.h>
25 #include <linux/log2.h>
26 #include <linux/io.h>
27 #include <linux/gpio/driver.h>
28 #include <linux/slab.h>
29 #include <linux/platform_device.h>
30 #include <linux/mutex.h>
31 #include <linux/acpi.h>
32 #include <linux/seq_file.h>
33 #include <linux/interrupt.h>
34 #include <linux/list.h>
35 #include <linux/bitops.h>
36 #include <linux/pinctrl/pinconf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 
39 #include "core.h"
40 #include "pinctrl-utils.h"
41 #include "pinctrl-amd.h"
42 
43 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
44 {
45 	unsigned long flags;
46 	u32 pin_reg;
47 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
48 
49 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
50 	pin_reg = readl(gpio_dev->base + offset * 4);
51 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
52 
53 	return !(pin_reg & BIT(OUTPUT_ENABLE_OFF));
54 }
55 
56 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
57 {
58 	unsigned long flags;
59 	u32 pin_reg;
60 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
61 
62 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
63 	pin_reg = readl(gpio_dev->base + offset * 4);
64 	pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
65 	writel(pin_reg, gpio_dev->base + offset * 4);
66 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
67 
68 	return 0;
69 }
70 
71 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
72 		int value)
73 {
74 	u32 pin_reg;
75 	unsigned long flags;
76 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
77 
78 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
79 	pin_reg = readl(gpio_dev->base + offset * 4);
80 	pin_reg |= BIT(OUTPUT_ENABLE_OFF);
81 	if (value)
82 		pin_reg |= BIT(OUTPUT_VALUE_OFF);
83 	else
84 		pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
85 	writel(pin_reg, gpio_dev->base + offset * 4);
86 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
87 
88 	return 0;
89 }
90 
91 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
92 {
93 	u32 pin_reg;
94 	unsigned long flags;
95 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
96 
97 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
98 	pin_reg = readl(gpio_dev->base + offset * 4);
99 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
100 
101 	return !!(pin_reg & BIT(PIN_STS_OFF));
102 }
103 
104 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
105 {
106 	u32 pin_reg;
107 	unsigned long flags;
108 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
109 
110 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
111 	pin_reg = readl(gpio_dev->base + offset * 4);
112 	if (value)
113 		pin_reg |= BIT(OUTPUT_VALUE_OFF);
114 	else
115 		pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
116 	writel(pin_reg, gpio_dev->base + offset * 4);
117 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
118 }
119 
120 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
121 		unsigned debounce)
122 {
123 	u32 time;
124 	u32 pin_reg;
125 	int ret = 0;
126 	unsigned long flags;
127 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
128 
129 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
130 	pin_reg = readl(gpio_dev->base + offset * 4);
131 
132 	if (debounce) {
133 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
134 		pin_reg &= ~DB_TMR_OUT_MASK;
135 		/*
136 		Debounce	Debounce	Timer	Max
137 		TmrLarge	TmrOutUnit	Unit	Debounce
138 							Time
139 		0	0	61 usec (2 RtcClk)	976 usec
140 		0	1	244 usec (8 RtcClk)	3.9 msec
141 		1	0	15.6 msec (512 RtcClk)	250 msec
142 		1	1	62.5 msec (2048 RtcClk)	1 sec
143 		*/
144 
145 		if (debounce < 61) {
146 			pin_reg |= 1;
147 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
148 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
149 		} else if (debounce < 976) {
150 			time = debounce / 61;
151 			pin_reg |= time & DB_TMR_OUT_MASK;
152 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
153 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
154 		} else if (debounce < 3900) {
155 			time = debounce / 244;
156 			pin_reg |= time & DB_TMR_OUT_MASK;
157 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
158 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
159 		} else if (debounce < 250000) {
160 			time = debounce / 15600;
161 			pin_reg |= time & DB_TMR_OUT_MASK;
162 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
163 			pin_reg |= BIT(DB_TMR_LARGE_OFF);
164 		} else if (debounce < 1000000) {
165 			time = debounce / 62500;
166 			pin_reg |= time & DB_TMR_OUT_MASK;
167 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
168 			pin_reg |= BIT(DB_TMR_LARGE_OFF);
169 		} else {
170 			pin_reg &= ~DB_CNTRl_MASK;
171 			ret = -EINVAL;
172 		}
173 	} else {
174 		pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
175 		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
176 		pin_reg &= ~DB_TMR_OUT_MASK;
177 		pin_reg &= ~DB_CNTRl_MASK;
178 	}
179 	writel(pin_reg, gpio_dev->base + offset * 4);
180 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
181 
182 	return ret;
183 }
184 
185 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
186 			       unsigned long config)
187 {
188 	u32 debounce;
189 
190 	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
191 		return -ENOTSUPP;
192 
193 	debounce = pinconf_to_config_argument(config);
194 	return amd_gpio_set_debounce(gc, offset, debounce);
195 }
196 
197 #ifdef CONFIG_DEBUG_FS
198 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
199 {
200 	u32 pin_reg;
201 	unsigned long flags;
202 	unsigned int bank, i, pin_num;
203 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
204 
205 	char *level_trig;
206 	char *active_level;
207 	char *interrupt_enable;
208 	char *interrupt_mask;
209 	char *wake_cntrl0;
210 	char *wake_cntrl1;
211 	char *wake_cntrl2;
212 	char *pin_sts;
213 	char *pull_up_sel;
214 	char *pull_up_enable;
215 	char *pull_down_enable;
216 	char *output_value;
217 	char *output_enable;
218 
219 	for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
220 		seq_printf(s, "GPIO bank%d\t", bank);
221 
222 		switch (bank) {
223 		case 0:
224 			i = 0;
225 			pin_num = AMD_GPIO_PINS_BANK0;
226 			break;
227 		case 1:
228 			i = 64;
229 			pin_num = AMD_GPIO_PINS_BANK1 + i;
230 			break;
231 		case 2:
232 			i = 128;
233 			pin_num = AMD_GPIO_PINS_BANK2 + i;
234 			break;
235 		case 3:
236 			i = 192;
237 			pin_num = AMD_GPIO_PINS_BANK3 + i;
238 			break;
239 		default:
240 			/* Illegal bank number, ignore */
241 			continue;
242 		}
243 		for (; i < pin_num; i++) {
244 			seq_printf(s, "pin%d\t", i);
245 			raw_spin_lock_irqsave(&gpio_dev->lock, flags);
246 			pin_reg = readl(gpio_dev->base + i * 4);
247 			raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
248 
249 			if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
250 				u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
251 						ACTIVE_LEVEL_MASK;
252 				interrupt_enable = "interrupt is enabled|";
253 
254 				if (level == ACTIVE_LEVEL_HIGH)
255 					active_level = "Active high|";
256 				else if (level == ACTIVE_LEVEL_LOW)
257 					active_level = "Active low|";
258 				else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
259 					 level == ACTIVE_LEVEL_BOTH)
260 					active_level = "Active on both|";
261 				else
262 					active_level = "Unknown Active level|";
263 
264 				if (pin_reg & BIT(LEVEL_TRIG_OFF))
265 					level_trig = "Level trigger|";
266 				else
267 					level_trig = "Edge trigger|";
268 
269 			} else {
270 				interrupt_enable =
271 					"interrupt is disabled|";
272 				active_level = " ";
273 				level_trig = " ";
274 			}
275 
276 			if (pin_reg & BIT(INTERRUPT_MASK_OFF))
277 				interrupt_mask =
278 					"interrupt is unmasked|";
279 			else
280 				interrupt_mask =
281 					"interrupt is masked|";
282 
283 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
284 				wake_cntrl0 = "enable wakeup in S0i3 state|";
285 			else
286 				wake_cntrl0 = "disable wakeup in S0i3 state|";
287 
288 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
289 				wake_cntrl1 = "enable wakeup in S3 state|";
290 			else
291 				wake_cntrl1 = "disable wakeup in S3 state|";
292 
293 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
294 				wake_cntrl2 = "enable wakeup in S4/S5 state|";
295 			else
296 				wake_cntrl2 = "disable wakeup in S4/S5 state|";
297 
298 			if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
299 				pull_up_enable = "pull-up is enabled|";
300 				if (pin_reg & BIT(PULL_UP_SEL_OFF))
301 					pull_up_sel = "8k pull-up|";
302 				else
303 					pull_up_sel = "4k pull-up|";
304 			} else {
305 				pull_up_enable = "pull-up is disabled|";
306 				pull_up_sel = " ";
307 			}
308 
309 			if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
310 				pull_down_enable = "pull-down is enabled|";
311 			else
312 				pull_down_enable = "Pull-down is disabled|";
313 
314 			if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
315 				pin_sts = " ";
316 				output_enable = "output is enabled|";
317 				if (pin_reg & BIT(OUTPUT_VALUE_OFF))
318 					output_value = "output is high|";
319 				else
320 					output_value = "output is low|";
321 			} else {
322 				output_enable = "output is disabled|";
323 				output_value = " ";
324 
325 				if (pin_reg & BIT(PIN_STS_OFF))
326 					pin_sts = "input is high|";
327 				else
328 					pin_sts = "input is low|";
329 			}
330 
331 			seq_printf(s, "%s %s %s %s %s %s\n"
332 				" %s %s %s %s %s %s %s 0x%x\n",
333 				level_trig, active_level, interrupt_enable,
334 				interrupt_mask, wake_cntrl0, wake_cntrl1,
335 				wake_cntrl2, pin_sts, pull_up_sel,
336 				pull_up_enable, pull_down_enable,
337 				output_value, output_enable, pin_reg);
338 		}
339 	}
340 }
341 #else
342 #define amd_gpio_dbg_show NULL
343 #endif
344 
345 static void amd_gpio_irq_enable(struct irq_data *d)
346 {
347 	u32 pin_reg;
348 	unsigned long flags;
349 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
350 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
351 
352 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
353 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
354 	pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
355 	pin_reg |= BIT(INTERRUPT_MASK_OFF);
356 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
357 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
358 }
359 
360 static void amd_gpio_irq_disable(struct irq_data *d)
361 {
362 	u32 pin_reg;
363 	unsigned long flags;
364 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
365 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
366 
367 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
368 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
369 	pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
370 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
371 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
372 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
373 }
374 
375 static void amd_gpio_irq_mask(struct irq_data *d)
376 {
377 	u32 pin_reg;
378 	unsigned long flags;
379 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
380 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
381 
382 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
383 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
384 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
385 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
386 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
387 }
388 
389 static void amd_gpio_irq_unmask(struct irq_data *d)
390 {
391 	u32 pin_reg;
392 	unsigned long flags;
393 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
394 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
395 
396 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
397 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
398 	pin_reg |= BIT(INTERRUPT_MASK_OFF);
399 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
400 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
401 }
402 
403 static void amd_gpio_irq_eoi(struct irq_data *d)
404 {
405 	u32 reg;
406 	unsigned long flags;
407 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
408 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
409 
410 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
411 	reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
412 	reg |= EOI_MASK;
413 	writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
414 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
415 }
416 
417 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
418 {
419 	int ret = 0;
420 	u32 pin_reg, pin_reg_irq_en, mask;
421 	unsigned long flags, irq_flags;
422 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
423 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
424 
425 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
426 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
427 
428 	/* Ignore the settings coming from the client and
429 	 * read the values from the ACPI tables
430 	 * while setting the trigger type
431 	 */
432 
433 	irq_flags = irq_get_trigger_type(d->irq);
434 	if (irq_flags != IRQ_TYPE_NONE)
435 		type = irq_flags;
436 
437 	switch (type & IRQ_TYPE_SENSE_MASK) {
438 	case IRQ_TYPE_EDGE_RISING:
439 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
440 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
441 		pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
442 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
443 		irq_set_handler_locked(d, handle_edge_irq);
444 		break;
445 
446 	case IRQ_TYPE_EDGE_FALLING:
447 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
448 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
449 		pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
450 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
451 		irq_set_handler_locked(d, handle_edge_irq);
452 		break;
453 
454 	case IRQ_TYPE_EDGE_BOTH:
455 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
456 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
457 		pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
458 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
459 		irq_set_handler_locked(d, handle_edge_irq);
460 		break;
461 
462 	case IRQ_TYPE_LEVEL_HIGH:
463 		pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
464 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
465 		pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
466 		pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
467 		pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
468 		irq_set_handler_locked(d, handle_level_irq);
469 		break;
470 
471 	case IRQ_TYPE_LEVEL_LOW:
472 		pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
473 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
474 		pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
475 		pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
476 		pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
477 		irq_set_handler_locked(d, handle_level_irq);
478 		break;
479 
480 	case IRQ_TYPE_NONE:
481 		break;
482 
483 	default:
484 		dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
485 		ret = -EINVAL;
486 	}
487 
488 	pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
489 	/*
490 	 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
491 	 * debounce registers of any GPIO will block wake/interrupt status
492 	 * generation for *all* GPIOs for a length of time that depends on
493 	 * WAKE_INT_MASTER_REG.MaskStsLength[11:0].  During this period the
494 	 * INTERRUPT_ENABLE bit will read as 0.
495 	 *
496 	 * We temporarily enable irq for the GPIO whose configuration is
497 	 * changing, and then wait for it to read back as 1 to know when
498 	 * debounce has settled and then disable the irq again.
499 	 * We do this polling with the spinlock held to ensure other GPIO
500 	 * access routines do not read an incorrect value for the irq enable
501 	 * bit of other GPIOs.  We keep the GPIO masked while polling to avoid
502 	 * spurious irqs, and disable the irq again after polling.
503 	 */
504 	mask = BIT(INTERRUPT_ENABLE_OFF);
505 	pin_reg_irq_en = pin_reg;
506 	pin_reg_irq_en |= mask;
507 	pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
508 	writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
509 	while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
510 		continue;
511 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
512 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
513 
514 	return ret;
515 }
516 
517 static void amd_irq_ack(struct irq_data *d)
518 {
519 	/*
520 	 * based on HW design,there is no need to ack HW
521 	 * before handle current irq. But this routine is
522 	 * necessary for handle_edge_irq
523 	*/
524 }
525 
526 static struct irq_chip amd_gpio_irqchip = {
527 	.name         = "amd_gpio",
528 	.irq_ack      = amd_irq_ack,
529 	.irq_enable   = amd_gpio_irq_enable,
530 	.irq_disable  = amd_gpio_irq_disable,
531 	.irq_mask     = amd_gpio_irq_mask,
532 	.irq_unmask   = amd_gpio_irq_unmask,
533 	.irq_eoi      = amd_gpio_irq_eoi,
534 	.irq_set_type = amd_gpio_irq_set_type,
535 	.flags        = IRQCHIP_SKIP_SET_WAKE,
536 };
537 
538 #define PIN_IRQ_PENDING	(BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
539 
540 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
541 {
542 	struct amd_gpio *gpio_dev = dev_id;
543 	struct gpio_chip *gc = &gpio_dev->gc;
544 	irqreturn_t ret = IRQ_NONE;
545 	unsigned int i, irqnr;
546 	unsigned long flags;
547 	u32 *regs, regval;
548 	u64 status, mask;
549 
550 	/* Read the wake status */
551 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
552 	status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
553 	status <<= 32;
554 	status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
555 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
556 
557 	/* Bit 0-45 contain the relevant status bits */
558 	status &= (1ULL << 46) - 1;
559 	regs = gpio_dev->base;
560 	for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
561 		if (!(status & mask))
562 			continue;
563 		status &= ~mask;
564 
565 		/* Each status bit covers four pins */
566 		for (i = 0; i < 4; i++) {
567 			regval = readl(regs + i);
568 			if (!(regval & PIN_IRQ_PENDING) ||
569 			    !(regval & BIT(INTERRUPT_MASK_OFF)))
570 				continue;
571 			irq = irq_find_mapping(gc->irq.domain, irqnr + i);
572 			generic_handle_irq(irq);
573 
574 			/* Clear interrupt.
575 			 * We must read the pin register again, in case the
576 			 * value was changed while executing
577 			 * generic_handle_irq() above.
578 			 */
579 			raw_spin_lock_irqsave(&gpio_dev->lock, flags);
580 			regval = readl(regs + i);
581 			writel(regval, regs + i);
582 			raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
583 			ret = IRQ_HANDLED;
584 		}
585 	}
586 
587 	/* Signal EOI to the GPIO unit */
588 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
589 	regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
590 	regval |= EOI_MASK;
591 	writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
592 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
593 
594 	return ret;
595 }
596 
597 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
598 {
599 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
600 
601 	return gpio_dev->ngroups;
602 }
603 
604 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
605 				      unsigned group)
606 {
607 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
608 
609 	return gpio_dev->groups[group].name;
610 }
611 
612 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
613 			      unsigned group,
614 			      const unsigned **pins,
615 			      unsigned *num_pins)
616 {
617 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
618 
619 	*pins = gpio_dev->groups[group].pins;
620 	*num_pins = gpio_dev->groups[group].npins;
621 	return 0;
622 }
623 
624 static const struct pinctrl_ops amd_pinctrl_ops = {
625 	.get_groups_count	= amd_get_groups_count,
626 	.get_group_name		= amd_get_group_name,
627 	.get_group_pins		= amd_get_group_pins,
628 #ifdef CONFIG_OF
629 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
630 	.dt_free_map		= pinctrl_utils_free_map,
631 #endif
632 };
633 
634 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
635 			  unsigned int pin,
636 			  unsigned long *config)
637 {
638 	u32 pin_reg;
639 	unsigned arg;
640 	unsigned long flags;
641 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
642 	enum pin_config_param param = pinconf_to_config_param(*config);
643 
644 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
645 	pin_reg = readl(gpio_dev->base + pin*4);
646 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
647 	switch (param) {
648 	case PIN_CONFIG_INPUT_DEBOUNCE:
649 		arg = pin_reg & DB_TMR_OUT_MASK;
650 		break;
651 
652 	case PIN_CONFIG_BIAS_PULL_DOWN:
653 		arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
654 		break;
655 
656 	case PIN_CONFIG_BIAS_PULL_UP:
657 		arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
658 		break;
659 
660 	case PIN_CONFIG_DRIVE_STRENGTH:
661 		arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
662 		break;
663 
664 	default:
665 		dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
666 			param);
667 		return -ENOTSUPP;
668 	}
669 
670 	*config = pinconf_to_config_packed(param, arg);
671 
672 	return 0;
673 }
674 
675 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
676 				unsigned long *configs, unsigned num_configs)
677 {
678 	int i;
679 	u32 arg;
680 	int ret = 0;
681 	u32 pin_reg;
682 	unsigned long flags;
683 	enum pin_config_param param;
684 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
685 
686 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
687 	for (i = 0; i < num_configs; i++) {
688 		param = pinconf_to_config_param(configs[i]);
689 		arg = pinconf_to_config_argument(configs[i]);
690 		pin_reg = readl(gpio_dev->base + pin*4);
691 
692 		switch (param) {
693 		case PIN_CONFIG_INPUT_DEBOUNCE:
694 			pin_reg &= ~DB_TMR_OUT_MASK;
695 			pin_reg |= arg & DB_TMR_OUT_MASK;
696 			break;
697 
698 		case PIN_CONFIG_BIAS_PULL_DOWN:
699 			pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
700 			pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
701 			break;
702 
703 		case PIN_CONFIG_BIAS_PULL_UP:
704 			pin_reg &= ~BIT(PULL_UP_SEL_OFF);
705 			pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
706 			pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
707 			pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
708 			break;
709 
710 		case PIN_CONFIG_DRIVE_STRENGTH:
711 			pin_reg &= ~(DRV_STRENGTH_SEL_MASK
712 					<< DRV_STRENGTH_SEL_OFF);
713 			pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
714 					<< DRV_STRENGTH_SEL_OFF;
715 			break;
716 
717 		default:
718 			dev_err(&gpio_dev->pdev->dev,
719 				"Invalid config param %04x\n", param);
720 			ret = -ENOTSUPP;
721 		}
722 
723 		writel(pin_reg, gpio_dev->base + pin*4);
724 	}
725 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
726 
727 	return ret;
728 }
729 
730 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
731 				unsigned int group,
732 				unsigned long *config)
733 {
734 	const unsigned *pins;
735 	unsigned npins;
736 	int ret;
737 
738 	ret = amd_get_group_pins(pctldev, group, &pins, &npins);
739 	if (ret)
740 		return ret;
741 
742 	if (amd_pinconf_get(pctldev, pins[0], config))
743 			return -ENOTSUPP;
744 
745 	return 0;
746 }
747 
748 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
749 				unsigned group, unsigned long *configs,
750 				unsigned num_configs)
751 {
752 	const unsigned *pins;
753 	unsigned npins;
754 	int i, ret;
755 
756 	ret = amd_get_group_pins(pctldev, group, &pins, &npins);
757 	if (ret)
758 		return ret;
759 	for (i = 0; i < npins; i++) {
760 		if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
761 			return -ENOTSUPP;
762 	}
763 	return 0;
764 }
765 
766 static const struct pinconf_ops amd_pinconf_ops = {
767 	.pin_config_get		= amd_pinconf_get,
768 	.pin_config_set		= amd_pinconf_set,
769 	.pin_config_group_get = amd_pinconf_group_get,
770 	.pin_config_group_set = amd_pinconf_group_set,
771 };
772 
773 #ifdef CONFIG_PM_SLEEP
774 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
775 {
776 	const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
777 
778 	if (!pd)
779 		return false;
780 
781 	/*
782 	 * Only restore the pin if it is actually in use by the kernel (or
783 	 * by userspace).
784 	 */
785 	if (pd->mux_owner || pd->gpio_owner ||
786 	    gpiochip_line_is_irq(&gpio_dev->gc, pin))
787 		return true;
788 
789 	return false;
790 }
791 
792 static int amd_gpio_suspend(struct device *dev)
793 {
794 	struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
795 	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
796 	int i;
797 
798 	for (i = 0; i < desc->npins; i++) {
799 		int pin = desc->pins[i].number;
800 
801 		if (!amd_gpio_should_save(gpio_dev, pin))
802 			continue;
803 
804 		gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
805 	}
806 
807 	return 0;
808 }
809 
810 static int amd_gpio_resume(struct device *dev)
811 {
812 	struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
813 	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
814 	int i;
815 
816 	for (i = 0; i < desc->npins; i++) {
817 		int pin = desc->pins[i].number;
818 
819 		if (!amd_gpio_should_save(gpio_dev, pin))
820 			continue;
821 
822 		writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
823 	}
824 
825 	return 0;
826 }
827 
828 static const struct dev_pm_ops amd_gpio_pm_ops = {
829 	SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
830 				     amd_gpio_resume)
831 };
832 #endif
833 
834 static struct pinctrl_desc amd_pinctrl_desc = {
835 	.pins	= kerncz_pins,
836 	.npins = ARRAY_SIZE(kerncz_pins),
837 	.pctlops = &amd_pinctrl_ops,
838 	.confops = &amd_pinconf_ops,
839 	.owner = THIS_MODULE,
840 };
841 
842 static int amd_gpio_probe(struct platform_device *pdev)
843 {
844 	int ret = 0;
845 	int irq_base;
846 	struct resource *res;
847 	struct amd_gpio *gpio_dev;
848 
849 	gpio_dev = devm_kzalloc(&pdev->dev,
850 				sizeof(struct amd_gpio), GFP_KERNEL);
851 	if (!gpio_dev)
852 		return -ENOMEM;
853 
854 	raw_spin_lock_init(&gpio_dev->lock);
855 
856 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
857 	if (!res) {
858 		dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
859 		return -EINVAL;
860 	}
861 
862 	gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
863 						resource_size(res));
864 	if (!gpio_dev->base)
865 		return -ENOMEM;
866 
867 	irq_base = platform_get_irq(pdev, 0);
868 	if (irq_base < 0) {
869 		dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base);
870 		return irq_base;
871 	}
872 
873 #ifdef CONFIG_PM_SLEEP
874 	gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
875 					    sizeof(*gpio_dev->saved_regs),
876 					    GFP_KERNEL);
877 	if (!gpio_dev->saved_regs)
878 		return -ENOMEM;
879 #endif
880 
881 	gpio_dev->pdev = pdev;
882 	gpio_dev->gc.get_direction	= amd_gpio_get_direction;
883 	gpio_dev->gc.direction_input	= amd_gpio_direction_input;
884 	gpio_dev->gc.direction_output	= amd_gpio_direction_output;
885 	gpio_dev->gc.get			= amd_gpio_get_value;
886 	gpio_dev->gc.set			= amd_gpio_set_value;
887 	gpio_dev->gc.set_config		= amd_gpio_set_config;
888 	gpio_dev->gc.dbg_show		= amd_gpio_dbg_show;
889 
890 	gpio_dev->gc.base		= -1;
891 	gpio_dev->gc.label			= pdev->name;
892 	gpio_dev->gc.owner			= THIS_MODULE;
893 	gpio_dev->gc.parent			= &pdev->dev;
894 	gpio_dev->gc.ngpio			= resource_size(res) / 4;
895 #if defined(CONFIG_OF_GPIO)
896 	gpio_dev->gc.of_node			= pdev->dev.of_node;
897 #endif
898 
899 	gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
900 	gpio_dev->groups = kerncz_groups;
901 	gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
902 
903 	amd_pinctrl_desc.name = dev_name(&pdev->dev);
904 	gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
905 						gpio_dev);
906 	if (IS_ERR(gpio_dev->pctrl)) {
907 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
908 		return PTR_ERR(gpio_dev->pctrl);
909 	}
910 
911 	ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
912 	if (ret)
913 		return ret;
914 
915 	ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
916 				0, 0, gpio_dev->gc.ngpio);
917 	if (ret) {
918 		dev_err(&pdev->dev, "Failed to add pin range\n");
919 		goto out2;
920 	}
921 
922 	ret = gpiochip_irqchip_add(&gpio_dev->gc,
923 				&amd_gpio_irqchip,
924 				0,
925 				handle_simple_irq,
926 				IRQ_TYPE_NONE);
927 	if (ret) {
928 		dev_err(&pdev->dev, "could not add irqchip\n");
929 		ret = -ENODEV;
930 		goto out2;
931 	}
932 
933 	ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0,
934 			       KBUILD_MODNAME, gpio_dev);
935 	if (ret)
936 		goto out2;
937 
938 	platform_set_drvdata(pdev, gpio_dev);
939 
940 	dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
941 	return ret;
942 
943 out2:
944 	gpiochip_remove(&gpio_dev->gc);
945 
946 	return ret;
947 }
948 
949 static int amd_gpio_remove(struct platform_device *pdev)
950 {
951 	struct amd_gpio *gpio_dev;
952 
953 	gpio_dev = platform_get_drvdata(pdev);
954 
955 	gpiochip_remove(&gpio_dev->gc);
956 
957 	return 0;
958 }
959 
960 static const struct acpi_device_id amd_gpio_acpi_match[] = {
961 	{ "AMD0030", 0 },
962 	{ "AMDI0030", 0},
963 	{ },
964 };
965 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
966 
967 static struct platform_driver amd_gpio_driver = {
968 	.driver		= {
969 		.name	= "amd_gpio",
970 		.acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
971 #ifdef CONFIG_PM_SLEEP
972 		.pm	= &amd_gpio_pm_ops,
973 #endif
974 	},
975 	.probe		= amd_gpio_probe,
976 	.remove		= amd_gpio_remove,
977 };
978 
979 module_platform_driver(amd_gpio_driver);
980 
981 MODULE_LICENSE("GPL v2");
982 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
983 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
984