1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 */ 10 11 #include <linux/err.h> 12 #include <linux/bug.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/compiler.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/log2.h> 20 #include <linux/io.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/slab.h> 23 #include <linux/platform_device.h> 24 #include <linux/acpi.h> 25 #include <linux/seq_file.h> 26 #include <linux/interrupt.h> 27 #include <linux/bitops.h> 28 #include <linux/pinctrl/pinconf.h> 29 #include <linux/dmi.h> 30 #include <linux/pinctrl/pinconf-generic.h> 31 #include <linux/pinctrl/pinmux.h> 32 #include <linux/string_choices.h> 33 #include <linux/suspend.h> 34 35 #include "core.h" 36 #include "pinctrl-utils.h" 37 #include "pinctrl-amd.h" 38 39 #ifdef CONFIG_SUSPEND 40 static struct amd_gpio *pinctrl_dev; 41 #endif 42 43 static const struct dmi_system_id amd_gpio_quirk_yoga7_14agp11[] = { 44 { 45 .matches = { 46 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 47 DMI_MATCH(DMI_PRODUCT_NAME, "83TD"), 48 DMI_MATCH(DMI_BOARD_NAME, "LNVNB161216"), 49 }, 50 }, 51 { } 52 }; 53 54 static void amd_gpio_apply_quirks(struct amd_gpio *gpio_dev) 55 { 56 const unsigned int pin = 157; /* WACF2200 GpioInt per ACPI _CRS */ 57 unsigned long flags; 58 u32 reg; 59 60 if (!dmi_check_system(amd_gpio_quirk_yoga7_14agp11)) 61 return; 62 if (pin >= gpio_dev->gc.ngpio) 63 return; 64 65 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 66 reg = readl(gpio_dev->base + pin * 4); 67 reg |= BIT(INTERRUPT_ENABLE_OFF) | BIT(INTERRUPT_MASK_OFF); 68 writel(reg, gpio_dev->base + pin * 4); 69 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 70 71 dev_info(&gpio_dev->pdev->dev, 72 "Enabled IRQ for GPIO %u (Yoga 7 14AGP11 touchscreen)\n", 73 pin); 74 } 75 76 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 77 { 78 unsigned long flags; 79 u32 pin_reg; 80 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 81 82 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 83 pin_reg = readl(gpio_dev->base + offset * 4); 84 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 85 86 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 87 return GPIO_LINE_DIRECTION_OUT; 88 89 return GPIO_LINE_DIRECTION_IN; 90 } 91 92 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 93 { 94 unsigned long flags; 95 u32 pin_reg; 96 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 97 98 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 99 pin_reg = readl(gpio_dev->base + offset * 4); 100 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 101 writel(pin_reg, gpio_dev->base + offset * 4); 102 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 103 104 return 0; 105 } 106 107 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 108 int value) 109 { 110 u32 pin_reg; 111 unsigned long flags; 112 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 113 114 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 115 pin_reg = readl(gpio_dev->base + offset * 4); 116 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 117 if (value) 118 pin_reg |= BIT(OUTPUT_VALUE_OFF); 119 else 120 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 121 writel(pin_reg, gpio_dev->base + offset * 4); 122 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 123 124 return 0; 125 } 126 127 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 128 { 129 u32 pin_reg; 130 unsigned long flags; 131 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 132 133 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 134 pin_reg = readl(gpio_dev->base + offset * 4); 135 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 136 137 return !!(pin_reg & BIT(PIN_STS_OFF)); 138 } 139 140 static int amd_gpio_set_value(struct gpio_chip *gc, unsigned int offset, 141 int value) 142 { 143 u32 pin_reg; 144 unsigned long flags; 145 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 146 147 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 148 pin_reg = readl(gpio_dev->base + offset * 4); 149 if (value) 150 pin_reg |= BIT(OUTPUT_VALUE_OFF); 151 else 152 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 153 writel(pin_reg, gpio_dev->base + offset * 4); 154 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 155 156 return 0; 157 } 158 159 static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset, 160 unsigned int debounce) 161 { 162 u32 time; 163 u32 pin_reg; 164 int ret = 0; 165 166 /* Use special handling for Pin0 debounce */ 167 if (offset == 0) { 168 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 169 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) 170 debounce = 0; 171 } 172 173 pin_reg = readl(gpio_dev->base + offset * 4); 174 175 if (debounce) { 176 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 177 pin_reg &= ~DB_TMR_OUT_MASK; 178 /* 179 Debounce Debounce Timer Max 180 TmrLarge TmrOutUnit Unit Debounce 181 Time 182 0 0 61 usec (2 RtcClk) 976 usec 183 0 1 244 usec (8 RtcClk) 3.9 msec 184 1 0 15.6 msec (512 RtcClk) 250 msec 185 1 1 62.5 msec (2048 RtcClk) 1 sec 186 */ 187 188 if (debounce < 61) { 189 pin_reg |= 1; 190 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 191 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 192 } else if (debounce < 976) { 193 time = debounce / 61; 194 pin_reg |= time & DB_TMR_OUT_MASK; 195 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 196 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 197 } else if (debounce < 3900) { 198 time = debounce / 244; 199 pin_reg |= time & DB_TMR_OUT_MASK; 200 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 201 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 202 } else if (debounce < 250000) { 203 time = debounce / 15625; 204 pin_reg |= time & DB_TMR_OUT_MASK; 205 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 206 pin_reg |= BIT(DB_TMR_LARGE_OFF); 207 } else if (debounce < 1000000) { 208 time = debounce / 62500; 209 pin_reg |= time & DB_TMR_OUT_MASK; 210 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 211 pin_reg |= BIT(DB_TMR_LARGE_OFF); 212 } else { 213 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 214 ret = -EINVAL; 215 } 216 } else { 217 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 218 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 219 pin_reg &= ~DB_TMR_OUT_MASK; 220 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 221 } 222 writel(pin_reg, gpio_dev->base + offset * 4); 223 224 return ret; 225 } 226 227 #ifdef CONFIG_DEBUG_FS 228 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 229 { 230 u32 pin_reg; 231 u32 db_cntrl; 232 unsigned long flags; 233 unsigned int bank, i, pin_num; 234 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 235 236 bool tmr_out_unit; 237 bool tmr_large; 238 239 char *level_trig; 240 char *active_level; 241 char *interrupt_mask; 242 char *wake_cntrl0; 243 char *wake_cntrl1; 244 char *wake_cntrl2; 245 char *pin_sts; 246 char *interrupt_sts; 247 char *wake_sts; 248 char *orientation; 249 char debounce_value[40]; 250 char *debounce_enable; 251 char *wake_cntrlz; 252 253 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG)); 254 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 255 unsigned int time = 0; 256 unsigned int unit = 0; 257 258 switch (bank) { 259 case 0: 260 i = 0; 261 pin_num = AMD_GPIO_PINS_BANK0; 262 break; 263 case 1: 264 i = 64; 265 pin_num = AMD_GPIO_PINS_BANK1 + i; 266 break; 267 case 2: 268 i = 128; 269 pin_num = AMD_GPIO_PINS_BANK2 + i; 270 break; 271 case 3: 272 i = 192; 273 pin_num = AMD_GPIO_PINS_BANK3 + i; 274 break; 275 default: 276 /* Illegal bank number, ignore */ 277 continue; 278 } 279 seq_printf(s, "GPIO bank%d\n", bank); 280 seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n"); 281 for (; i < pin_num; i++) { 282 seq_printf(s, "#%d\t", i); 283 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 284 pin_reg = readl(gpio_dev->base + i * 4); 285 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 286 287 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 288 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 289 ACTIVE_LEVEL_MASK; 290 291 if (level == ACTIVE_LEVEL_HIGH) 292 active_level = "↑"; 293 else if (level == ACTIVE_LEVEL_LOW) 294 active_level = "↓"; 295 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 296 level == ACTIVE_LEVEL_BOTH) 297 active_level = "b"; 298 else 299 active_level = "?"; 300 301 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 302 level_trig = "level"; 303 else 304 level_trig = " edge"; 305 306 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 307 interrupt_mask = "��"; 308 else 309 interrupt_mask = "��"; 310 311 if (pin_reg & BIT(INTERRUPT_STS_OFF)) 312 interrupt_sts = "��"; 313 else 314 interrupt_sts = " "; 315 316 seq_printf(s, "%s %s| %s| %s|", 317 interrupt_sts, 318 interrupt_mask, 319 active_level, 320 level_trig); 321 } else 322 seq_puts(s, " ∅| | |"); 323 324 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 325 wake_cntrl0 = "⏰"; 326 else 327 wake_cntrl0 = " "; 328 seq_printf(s, " %s| ", wake_cntrl0); 329 330 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 331 wake_cntrl1 = "⏰"; 332 else 333 wake_cntrl1 = " "; 334 seq_printf(s, "%s|", wake_cntrl1); 335 336 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 337 wake_cntrl2 = "⏰"; 338 else 339 wake_cntrl2 = " "; 340 seq_printf(s, " %s|", wake_cntrl2); 341 342 if (pin_reg & BIT(WAKECNTRL_Z_OFF)) 343 wake_cntrlz = "⏰"; 344 else 345 wake_cntrlz = " "; 346 seq_printf(s, "%s|", wake_cntrlz); 347 348 if (pin_reg & BIT(WAKE_STS_OFF)) 349 wake_sts = "��"; 350 else 351 wake_sts = " "; 352 seq_printf(s, " %s|", wake_sts); 353 354 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 355 seq_puts(s, " ↑ |"); 356 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) { 357 seq_puts(s, " ↓ |"); 358 } else { 359 seq_puts(s, " |"); 360 } 361 362 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 363 pin_sts = "output"; 364 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 365 orientation = "↑"; 366 else 367 orientation = "↓"; 368 } else { 369 pin_sts = "input "; 370 if (pin_reg & BIT(PIN_STS_OFF)) 371 orientation = "↑"; 372 else 373 orientation = "↓"; 374 } 375 seq_printf(s, "%s %s|", pin_sts, orientation); 376 377 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 378 if (db_cntrl) { 379 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 380 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 381 time = pin_reg & DB_TMR_OUT_MASK; 382 if (tmr_large) { 383 if (tmr_out_unit) 384 unit = 62500; 385 else 386 unit = 15625; 387 } else { 388 if (tmr_out_unit) 389 unit = 244; 390 else 391 unit = 61; 392 } 393 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 394 debounce_enable = "b"; 395 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 396 debounce_enable = "↓"; 397 else 398 debounce_enable = "↑"; 399 snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit); 400 seq_printf(s, "%s (�� %sus)|", debounce_enable, debounce_value); 401 } else { 402 seq_puts(s, " |"); 403 } 404 seq_printf(s, "0x%x\n", pin_reg); 405 } 406 } 407 } 408 #else 409 #define amd_gpio_dbg_show NULL 410 #endif 411 412 static void amd_gpio_irq_enable(struct irq_data *d) 413 { 414 u32 pin_reg; 415 unsigned long flags; 416 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 417 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 418 irq_hw_number_t hwirq = irqd_to_hwirq(d); 419 420 gpiochip_enable_irq(gc, hwirq); 421 422 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 423 pin_reg = readl(gpio_dev->base + hwirq * 4); 424 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 425 pin_reg |= BIT(INTERRUPT_MASK_OFF); 426 writel(pin_reg, gpio_dev->base + hwirq * 4); 427 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 428 } 429 430 static void amd_gpio_irq_disable(struct irq_data *d) 431 { 432 u32 pin_reg; 433 unsigned long flags; 434 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 435 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 436 irq_hw_number_t hwirq = irqd_to_hwirq(d); 437 438 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 439 pin_reg = readl(gpio_dev->base + hwirq * 4); 440 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 441 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 442 writel(pin_reg, gpio_dev->base + hwirq * 4); 443 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 444 445 gpiochip_disable_irq(gc, hwirq); 446 } 447 448 static void amd_gpio_irq_mask(struct irq_data *d) 449 { 450 u32 pin_reg; 451 unsigned long flags; 452 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 453 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 454 irq_hw_number_t hwirq = irqd_to_hwirq(d); 455 456 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 457 pin_reg = readl(gpio_dev->base + hwirq * 4); 458 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 459 writel(pin_reg, gpio_dev->base + hwirq * 4); 460 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 461 } 462 463 static void amd_gpio_irq_unmask(struct irq_data *d) 464 { 465 u32 pin_reg; 466 unsigned long flags; 467 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 468 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 469 irq_hw_number_t hwirq = irqd_to_hwirq(d); 470 471 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 472 pin_reg = readl(gpio_dev->base + hwirq * 4); 473 pin_reg |= BIT(INTERRUPT_MASK_OFF); 474 writel(pin_reg, gpio_dev->base + hwirq * 4); 475 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 476 } 477 478 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 479 { 480 u32 pin_reg; 481 unsigned long flags; 482 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 483 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 484 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 485 irq_hw_number_t hwirq = irqd_to_hwirq(d); 486 int err; 487 488 pm_pr_dbg("Setting wake for GPIO %lu to %s\n", 489 hwirq, str_enable_disable(on)); 490 491 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 492 pin_reg = readl(gpio_dev->base + hwirq * 4); 493 494 if (on) 495 pin_reg |= wake_mask; 496 else 497 pin_reg &= ~wake_mask; 498 499 writel(pin_reg, gpio_dev->base + hwirq * 4); 500 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 501 502 if (on) 503 err = enable_irq_wake(gpio_dev->irq); 504 else 505 err = disable_irq_wake(gpio_dev->irq); 506 507 if (err) 508 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", 509 str_enable_disable(on)); 510 511 return 0; 512 } 513 514 static void amd_gpio_irq_eoi(struct irq_data *d) 515 { 516 u32 reg; 517 unsigned long flags; 518 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 519 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 520 521 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 522 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 523 reg |= EOI_MASK; 524 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 525 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 526 } 527 528 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 529 { 530 int ret = 0; 531 u32 pin_reg, pin_reg_irq_en, mask; 532 unsigned long flags; 533 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 534 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 535 irq_hw_number_t hwirq = irqd_to_hwirq(d); 536 537 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 538 pin_reg = readl(gpio_dev->base + hwirq * 4); 539 540 switch (type & IRQ_TYPE_SENSE_MASK) { 541 case IRQ_TYPE_EDGE_RISING: 542 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 543 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 544 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 545 irq_set_handler_locked(d, handle_edge_irq); 546 break; 547 548 case IRQ_TYPE_EDGE_FALLING: 549 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 550 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 551 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 552 irq_set_handler_locked(d, handle_edge_irq); 553 break; 554 555 case IRQ_TYPE_EDGE_BOTH: 556 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 557 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 558 pin_reg |= BOTH_EDGES << ACTIVE_LEVEL_OFF; 559 irq_set_handler_locked(d, handle_edge_irq); 560 break; 561 562 case IRQ_TYPE_LEVEL_HIGH: 563 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 564 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 565 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 566 irq_set_handler_locked(d, handle_level_irq); 567 break; 568 569 case IRQ_TYPE_LEVEL_LOW: 570 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 571 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 572 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 573 irq_set_handler_locked(d, handle_level_irq); 574 break; 575 576 case IRQ_TYPE_NONE: 577 break; 578 579 default: 580 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 581 ret = -EINVAL; 582 } 583 584 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 585 /* 586 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 587 * debounce registers of any GPIO will block wake/interrupt status 588 * generation for *all* GPIOs for a length of time that depends on 589 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 590 * INTERRUPT_ENABLE bit will read as 0. 591 * 592 * We temporarily enable irq for the GPIO whose configuration is 593 * changing, and then wait for it to read back as 1 to know when 594 * debounce has settled and then disable the irq again. 595 * We do this polling with the spinlock held to ensure other GPIO 596 * access routines do not read an incorrect value for the irq enable 597 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 598 * spurious irqs, and disable the irq again after polling. 599 */ 600 mask = BIT(INTERRUPT_ENABLE_OFF); 601 pin_reg_irq_en = pin_reg; 602 pin_reg_irq_en |= mask; 603 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 604 writel(pin_reg_irq_en, gpio_dev->base + hwirq * 4); 605 while ((readl(gpio_dev->base + hwirq * 4) & mask) != mask) 606 continue; 607 writel(pin_reg, gpio_dev->base + hwirq * 4); 608 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 609 610 return ret; 611 } 612 613 static void amd_irq_ack(struct irq_data *d) 614 { 615 /* 616 * based on HW design,there is no need to ack HW 617 * before handle current irq. But this routine is 618 * necessary for handle_edge_irq 619 */ 620 } 621 622 static const struct irq_chip amd_gpio_irqchip = { 623 .name = "amd_gpio", 624 .irq_ack = amd_irq_ack, 625 .irq_enable = amd_gpio_irq_enable, 626 .irq_disable = amd_gpio_irq_disable, 627 .irq_mask = amd_gpio_irq_mask, 628 .irq_unmask = amd_gpio_irq_unmask, 629 .irq_set_wake = amd_gpio_irq_set_wake, 630 .irq_eoi = amd_gpio_irq_eoi, 631 .irq_set_type = amd_gpio_irq_set_type, 632 /* 633 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 634 * also generates an IRQ. We need the IRQ so the irq_handler can clear 635 * the wake event. Otherwise the wake event will never clear and 636 * prevent the system from suspending. 637 */ 638 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE, 639 GPIOCHIP_IRQ_RESOURCE_HELPERS, 640 }; 641 642 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 643 644 static bool do_amd_gpio_irq_handler(int irq, void *dev_id) 645 { 646 struct amd_gpio *gpio_dev = dev_id; 647 struct gpio_chip *gc = &gpio_dev->gc; 648 unsigned int i, irqnr; 649 unsigned long flags; 650 u32 __iomem *regs; 651 bool ret = false; 652 u32 regval; 653 u64 status, mask; 654 655 /* Read the wake status */ 656 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 657 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 658 status <<= 32; 659 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 660 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 661 662 /* Bit 0-45 contain the relevant status bits */ 663 status &= (1ULL << 46) - 1; 664 regs = gpio_dev->base; 665 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 666 if (!(status & mask)) 667 continue; 668 status &= ~mask; 669 670 /* Each status bit covers four pins */ 671 for (i = 0; i < 4; i++) { 672 regval = readl(regs + i); 673 674 if (regval & PIN_IRQ_PENDING) 675 pm_pr_dbg("GPIO %d is active: 0x%x", 676 irqnr + i, regval); 677 678 /* caused wake on resume context for shared IRQ */ 679 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) 680 return true; 681 682 if (!(regval & PIN_IRQ_PENDING) || 683 !(regval & BIT(INTERRUPT_MASK_OFF))) 684 continue; 685 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i); 686 687 /* Clear interrupt. 688 * We must read the pin register again, in case the 689 * value was changed while executing 690 * generic_handle_domain_irq() above. 691 * If the line is not an irq, disable it in order to 692 * avoid a system hang caused by an interrupt storm. 693 */ 694 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 695 regval = readl(regs + i); 696 if (!gpiochip_line_is_irq(gc, irqnr + i)) { 697 regval &= ~BIT(INTERRUPT_MASK_OFF); 698 dev_dbg(&gpio_dev->pdev->dev, 699 "Disabling spurious GPIO IRQ %d\n", 700 irqnr + i); 701 } else { 702 ret = true; 703 } 704 writel(regval, regs + i); 705 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 706 } 707 } 708 /* did not cause wake on resume context for shared IRQ */ 709 if (irq < 0) 710 return false; 711 712 /* Signal EOI to the GPIO unit */ 713 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 714 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 715 regval |= EOI_MASK; 716 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 717 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 718 719 return ret; 720 } 721 722 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 723 { 724 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id)); 725 } 726 727 static bool __maybe_unused amd_gpio_check_wake(void *dev_id) 728 { 729 return do_amd_gpio_irq_handler(-1, dev_id); 730 } 731 732 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 733 { 734 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 735 736 return gpio_dev->ngroups; 737 } 738 739 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 740 unsigned group) 741 { 742 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 743 744 return gpio_dev->groups[group].name; 745 } 746 747 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 748 unsigned group, 749 const unsigned **pins, 750 unsigned *num_pins) 751 { 752 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 753 754 *pins = gpio_dev->groups[group].pins; 755 *num_pins = gpio_dev->groups[group].npins; 756 return 0; 757 } 758 759 static const struct pinctrl_ops amd_pinctrl_ops = { 760 .get_groups_count = amd_get_groups_count, 761 .get_group_name = amd_get_group_name, 762 .get_group_pins = amd_get_group_pins, 763 #ifdef CONFIG_OF 764 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 765 .dt_free_map = pinctrl_utils_free_map, 766 #endif 767 }; 768 769 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 770 unsigned int pin, 771 unsigned long *config) 772 { 773 u32 pin_reg; 774 unsigned arg; 775 unsigned long flags; 776 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 777 enum pin_config_param param = pinconf_to_config_param(*config); 778 779 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 780 pin_reg = readl(gpio_dev->base + pin*4); 781 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 782 switch (param) { 783 case PIN_CONFIG_INPUT_DEBOUNCE: 784 arg = pin_reg & DB_TMR_OUT_MASK; 785 break; 786 787 case PIN_CONFIG_BIAS_PULL_DOWN: 788 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 789 break; 790 791 case PIN_CONFIG_BIAS_PULL_UP: 792 arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0); 793 break; 794 795 case PIN_CONFIG_DRIVE_STRENGTH: 796 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 797 break; 798 799 default: 800 dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 801 param); 802 return -ENOTSUPP; 803 } 804 805 *config = pinconf_to_config_packed(param, arg); 806 807 return 0; 808 } 809 810 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 811 unsigned long *configs, unsigned int num_configs) 812 { 813 int i; 814 u32 arg; 815 int ret = 0; 816 u32 pin_reg; 817 unsigned long flags; 818 enum pin_config_param param; 819 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 820 821 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 822 for (i = 0; i < num_configs; i++) { 823 param = pinconf_to_config_param(configs[i]); 824 arg = pinconf_to_config_argument(configs[i]); 825 pin_reg = readl(gpio_dev->base + pin*4); 826 827 switch (param) { 828 case PIN_CONFIG_INPUT_DEBOUNCE: 829 ret = amd_gpio_set_debounce(gpio_dev, pin, arg); 830 goto out_unlock; 831 832 case PIN_CONFIG_BIAS_PULL_DOWN: 833 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 834 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 835 break; 836 837 case PIN_CONFIG_BIAS_PULL_UP: 838 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 839 pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF; 840 break; 841 842 case PIN_CONFIG_DRIVE_STRENGTH: 843 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 844 << DRV_STRENGTH_SEL_OFF); 845 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 846 << DRV_STRENGTH_SEL_OFF; 847 break; 848 849 default: 850 dev_dbg(&gpio_dev->pdev->dev, 851 "Invalid config param %04x\n", param); 852 ret = -ENOTSUPP; 853 } 854 855 writel(pin_reg, gpio_dev->base + pin*4); 856 } 857 out_unlock: 858 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 859 860 return ret; 861 } 862 863 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 864 unsigned int group, 865 unsigned long *config) 866 { 867 const unsigned *pins; 868 unsigned npins; 869 int ret; 870 871 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 872 if (ret) 873 return ret; 874 875 if (amd_pinconf_get(pctldev, pins[0], config)) 876 return -ENOTSUPP; 877 878 return 0; 879 } 880 881 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 882 unsigned group, unsigned long *configs, 883 unsigned num_configs) 884 { 885 const unsigned *pins; 886 unsigned npins; 887 int i, ret; 888 889 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 890 if (ret) 891 return ret; 892 for (i = 0; i < npins; i++) { 893 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 894 return -ENOTSUPP; 895 } 896 return 0; 897 } 898 899 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin, 900 unsigned long config) 901 { 902 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 903 904 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1); 905 } 906 907 static const struct pinconf_ops amd_pinconf_ops = { 908 .pin_config_get = amd_pinconf_get, 909 .pin_config_set = amd_pinconf_set, 910 .pin_config_group_get = amd_pinconf_group_get, 911 .pin_config_group_set = amd_pinconf_group_set, 912 }; 913 914 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 915 { 916 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 917 unsigned long flags; 918 u32 pin_reg, mask; 919 int i; 920 921 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 922 BIT(WAKE_CNTRL_OFF_S4); 923 924 for (i = 0; i < desc->npins; i++) { 925 int pin = desc->pins[i].number; 926 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 927 928 if (!pd) 929 continue; 930 931 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 932 933 pin_reg = readl(gpio_dev->base + pin * 4); 934 pin_reg &= ~mask; 935 writel(pin_reg, gpio_dev->base + pin * 4); 936 937 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 938 } 939 } 940 941 #if defined(CONFIG_SUSPEND) && defined(CONFIG_ACPI) 942 static void amd_gpio_check_pending(void) 943 { 944 struct amd_gpio *gpio_dev = pinctrl_dev; 945 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 946 int i; 947 948 if (!pm_debug_messages_on) 949 return; 950 951 for (i = 0; i < desc->npins; i++) { 952 int pin = desc->pins[i].number; 953 u32 tmp; 954 955 tmp = readl(gpio_dev->base + pin * 4); 956 if (tmp & PIN_IRQ_PENDING) 957 pm_pr_dbg("%s: GPIO %d is active: 0x%x.\n", __func__, pin, tmp); 958 } 959 } 960 961 static struct acpi_s2idle_dev_ops pinctrl_amd_s2idle_dev_ops = { 962 .check = amd_gpio_check_pending, 963 }; 964 965 static void amd_gpio_register_s2idle_ops(void) 966 { 967 acpi_register_lps0_dev(&pinctrl_amd_s2idle_dev_ops); 968 } 969 970 static void amd_gpio_unregister_s2idle_ops(void) 971 { 972 acpi_unregister_lps0_dev(&pinctrl_amd_s2idle_dev_ops); 973 } 974 #else 975 static inline void amd_gpio_register_s2idle_ops(void) {} 976 static inline void amd_gpio_unregister_s2idle_ops(void) {} 977 #endif 978 979 #ifdef CONFIG_PM_SLEEP 980 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 981 { 982 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 983 984 if (!pd) 985 return false; 986 987 /* 988 * Only restore the pin if it is actually in use by the kernel (or 989 * by userspace). 990 */ 991 if (pd->mux_owner || pd->gpio_owner || 992 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 993 return true; 994 995 return false; 996 } 997 998 static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend) 999 { 1000 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 1001 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 1002 unsigned long flags; 1003 int i; 1004 u32 wake_mask = is_suspend ? WAKE_SOURCE_SUSPEND : WAKE_SOURCE_HIBERNATE; 1005 1006 for (i = 0; i < desc->npins; i++) { 1007 int pin = desc->pins[i].number; 1008 1009 if (!amd_gpio_should_save(gpio_dev, pin)) 1010 continue; 1011 1012 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 1013 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; 1014 1015 /* mask any interrupts not intended to be a wake source */ 1016 if (!(gpio_dev->saved_regs[i] & wake_mask)) { 1017 writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF), 1018 gpio_dev->base + pin * 4); 1019 pm_pr_dbg("Disabling GPIO #%d interrupt for %s.\n", 1020 pin, is_suspend ? "suspend" : "hibernate"); 1021 } 1022 1023 /* 1024 * debounce enabled over suspend has shown issues with a GPIO 1025 * being unable to wake the system, as we're only interested in 1026 * the actual wakeup event, clear it. 1027 */ 1028 if (gpio_dev->saved_regs[i] & (DB_CNTRl_MASK << DB_CNTRL_OFF)) { 1029 amd_gpio_set_debounce(gpio_dev, pin, 0); 1030 pm_pr_dbg("Clearing debounce for GPIO #%d during %s.\n", 1031 pin, is_suspend ? "suspend" : "hibernate"); 1032 } 1033 1034 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 1035 } 1036 1037 return 0; 1038 } 1039 1040 static int amd_gpio_suspend(struct device *dev) 1041 { 1042 #ifdef CONFIG_SUSPEND 1043 pinctrl_dev = dev_get_drvdata(dev); 1044 #endif 1045 return amd_gpio_suspend_hibernate_common(dev, true); 1046 } 1047 1048 static int amd_gpio_hibernate(struct device *dev) 1049 { 1050 return amd_gpio_suspend_hibernate_common(dev, false); 1051 } 1052 1053 static int amd_gpio_resume(struct device *dev) 1054 { 1055 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 1056 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 1057 unsigned long flags; 1058 int i; 1059 1060 for (i = 0; i < desc->npins; i++) { 1061 int pin = desc->pins[i].number; 1062 1063 if (!amd_gpio_should_save(gpio_dev, pin)) 1064 continue; 1065 1066 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 1067 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; 1068 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); 1069 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 1070 } 1071 1072 return 0; 1073 } 1074 1075 static const struct dev_pm_ops amd_gpio_pm_ops = { 1076 .suspend_late = amd_gpio_suspend, 1077 .resume_early = amd_gpio_resume, 1078 .freeze_late = amd_gpio_hibernate, 1079 .thaw_early = amd_gpio_resume, 1080 .poweroff_late = amd_gpio_hibernate, 1081 .restore_early = amd_gpio_resume, 1082 }; 1083 #endif 1084 1085 static int amd_get_functions_count(struct pinctrl_dev *pctldev) 1086 { 1087 return ARRAY_SIZE(pmx_functions); 1088 } 1089 1090 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector) 1091 { 1092 return pmx_functions[selector].name; 1093 } 1094 1095 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, 1096 const char * const **groups, 1097 unsigned int * const num_groups) 1098 { 1099 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 1100 1101 if (!gpio_dev->iomux_base) { 1102 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); 1103 return -EINVAL; 1104 } 1105 1106 *groups = pmx_functions[selector].groups; 1107 *num_groups = pmx_functions[selector].ngroups; 1108 return 0; 1109 } 1110 1111 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group) 1112 { 1113 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 1114 struct device *dev = &gpio_dev->pdev->dev; 1115 struct pin_desc *pd; 1116 int ind, index; 1117 1118 if (!gpio_dev->iomux_base) 1119 return -EINVAL; 1120 1121 for (index = 0; index < NSELECTS; index++) { 1122 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index])) 1123 continue; 1124 1125 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) == 1126 FUNCTION_INVALID) { 1127 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1128 pmx_functions[function].index); 1129 return -EINVAL; 1130 } 1131 1132 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index); 1133 1134 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) & 1135 FUNCTION_MASK)) { 1136 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1137 pmx_functions[function].index); 1138 return -EINVAL; 1139 } 1140 1141 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { 1142 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F"))) 1143 continue; 1144 1145 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); 1146 pd->mux_owner = gpio_dev->groups[group].name; 1147 } 1148 break; 1149 } 1150 1151 return 0; 1152 } 1153 1154 static const struct pinmux_ops amd_pmxops = { 1155 .get_functions_count = amd_get_functions_count, 1156 .get_function_name = amd_get_fname, 1157 .get_function_groups = amd_get_groups, 1158 .set_mux = amd_set_mux, 1159 }; 1160 1161 static struct pinctrl_desc amd_pinctrl_desc = { 1162 .pins = kerncz_pins, 1163 .npins = ARRAY_SIZE(kerncz_pins), 1164 .pctlops = &amd_pinctrl_ops, 1165 .pmxops = &amd_pmxops, 1166 .confops = &amd_pinconf_ops, 1167 .owner = THIS_MODULE, 1168 }; 1169 1170 static void amd_get_iomux_res(struct amd_gpio *gpio_dev) 1171 { 1172 struct pinctrl_desc *desc = &amd_pinctrl_desc; 1173 struct device *dev = &gpio_dev->pdev->dev; 1174 int index; 1175 1176 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux"); 1177 if (index < 0) { 1178 dev_dbg(dev, "iomux not supported\n"); 1179 goto out_no_pinmux; 1180 } 1181 1182 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index); 1183 if (IS_ERR(gpio_dev->iomux_base)) { 1184 dev_dbg(dev, "iomux not supported %d io resource\n", index); 1185 goto out_no_pinmux; 1186 } 1187 1188 return; 1189 1190 out_no_pinmux: 1191 desc->pmxops = NULL; 1192 } 1193 1194 static int amd_gpio_probe(struct platform_device *pdev) 1195 { 1196 int ret = 0; 1197 struct resource *res; 1198 struct amd_gpio *gpio_dev; 1199 struct gpio_irq_chip *girq; 1200 1201 gpio_dev = devm_kzalloc(&pdev->dev, 1202 sizeof(struct amd_gpio), GFP_KERNEL); 1203 if (!gpio_dev) 1204 return -ENOMEM; 1205 1206 raw_spin_lock_init(&gpio_dev->lock); 1207 1208 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1209 if (IS_ERR(gpio_dev->base)) { 1210 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 1211 return PTR_ERR(gpio_dev->base); 1212 } 1213 1214 gpio_dev->irq = platform_get_irq(pdev, 0); 1215 if (gpio_dev->irq < 0) 1216 return gpio_dev->irq; 1217 1218 #ifdef CONFIG_SUSPEND 1219 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 1220 sizeof(*gpio_dev->saved_regs), 1221 GFP_KERNEL); 1222 if (!gpio_dev->saved_regs) 1223 return -ENOMEM; 1224 #endif 1225 1226 gpio_dev->pdev = pdev; 1227 gpio_dev->gc.get_direction = amd_gpio_get_direction; 1228 gpio_dev->gc.direction_input = amd_gpio_direction_input; 1229 gpio_dev->gc.direction_output = amd_gpio_direction_output; 1230 gpio_dev->gc.get = amd_gpio_get_value; 1231 gpio_dev->gc.set = amd_gpio_set_value; 1232 gpio_dev->gc.set_config = amd_gpio_set_config; 1233 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 1234 1235 gpio_dev->gc.base = -1; 1236 gpio_dev->gc.label = pdev->name; 1237 gpio_dev->gc.owner = THIS_MODULE; 1238 gpio_dev->gc.parent = &pdev->dev; 1239 gpio_dev->gc.ngpio = resource_size(res) / 4; 1240 1241 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 1242 gpio_dev->groups = kerncz_groups; 1243 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 1244 1245 amd_pinctrl_desc.name = dev_name(&pdev->dev); 1246 amd_get_iomux_res(gpio_dev); 1247 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 1248 gpio_dev); 1249 if (IS_ERR(gpio_dev->pctrl)) { 1250 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1251 return PTR_ERR(gpio_dev->pctrl); 1252 } 1253 1254 /* Disable and mask interrupts */ 1255 amd_gpio_irq_init(gpio_dev); 1256 amd_gpio_apply_quirks(gpio_dev); 1257 1258 girq = &gpio_dev->gc.irq; 1259 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); 1260 /* This will let us handle the parent IRQ in the driver */ 1261 girq->parent_handler = NULL; 1262 girq->num_parents = 0; 1263 girq->parents = NULL; 1264 girq->default_type = IRQ_TYPE_NONE; 1265 girq->handler = handle_simple_irq; 1266 1267 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 1268 if (ret) 1269 return ret; 1270 1271 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 1272 0, 0, gpio_dev->gc.ngpio); 1273 if (ret) { 1274 dev_err(&pdev->dev, "Failed to add pin range\n"); 1275 goto out2; 1276 } 1277 1278 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, 1279 IRQF_SHARED | IRQF_COND_ONESHOT, KBUILD_MODNAME, gpio_dev); 1280 if (ret) 1281 goto out2; 1282 1283 platform_set_drvdata(pdev, gpio_dev); 1284 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); 1285 amd_gpio_register_s2idle_ops(); 1286 1287 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1288 return ret; 1289 1290 out2: 1291 gpiochip_remove(&gpio_dev->gc); 1292 1293 return ret; 1294 } 1295 1296 static void amd_gpio_remove(struct platform_device *pdev) 1297 { 1298 struct amd_gpio *gpio_dev; 1299 1300 gpio_dev = platform_get_drvdata(pdev); 1301 1302 gpiochip_remove(&gpio_dev->gc); 1303 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); 1304 amd_gpio_unregister_s2idle_ops(); 1305 } 1306 1307 #ifdef CONFIG_ACPI 1308 static const struct acpi_device_id amd_gpio_acpi_match[] = { 1309 { "AMD0030", 0 }, 1310 { "AMDI0030", 0}, 1311 { "AMDI0031", 0}, 1312 { "AMDI0033", 0}, 1313 { }, 1314 }; 1315 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1316 #endif 1317 1318 static struct platform_driver amd_gpio_driver = { 1319 .driver = { 1320 .name = "amd_gpio", 1321 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1322 #ifdef CONFIG_PM_SLEEP 1323 .pm = &amd_gpio_pm_ops, 1324 #endif 1325 }, 1326 .probe = amd_gpio_probe, 1327 .remove = amd_gpio_remove, 1328 }; 1329 1330 module_platform_driver(amd_gpio_driver); 1331 1332 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1333 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1334