xref: /linux/drivers/pinctrl/pinctrl-amd.c (revision af50e4ba34f4c45e92535364133d4deb5931c1c5)
1 /*
2  * GPIO driver for AMD
3  *
4  * Copyright (c) 2014,2015 AMD Corporation.
5  * Authors: Ken Xue <Ken.Xue@amd.com>
6  *      Wu, Jeff <Jeff.Wu@amd.com>
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2, as published by the Free Software Foundation.
11  *
12  * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
13  *			Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
14  *
15  */
16 
17 #include <linux/err.h>
18 #include <linux/bug.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/compiler.h>
23 #include <linux/types.h>
24 #include <linux/errno.h>
25 #include <linux/log2.h>
26 #include <linux/io.h>
27 #include <linux/gpio.h>
28 #include <linux/slab.h>
29 #include <linux/platform_device.h>
30 #include <linux/mutex.h>
31 #include <linux/acpi.h>
32 #include <linux/seq_file.h>
33 #include <linux/interrupt.h>
34 #include <linux/list.h>
35 #include <linux/bitops.h>
36 #include <linux/pinctrl/pinconf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 
39 #include "core.h"
40 #include "pinctrl-utils.h"
41 #include "pinctrl-amd.h"
42 
43 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
44 {
45 	unsigned long flags;
46 	u32 pin_reg;
47 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
48 
49 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
50 	pin_reg = readl(gpio_dev->base + offset * 4);
51 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
52 
53 	return !(pin_reg & BIT(OUTPUT_ENABLE_OFF));
54 }
55 
56 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
57 {
58 	unsigned long flags;
59 	u32 pin_reg;
60 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
61 
62 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
63 	pin_reg = readl(gpio_dev->base + offset * 4);
64 	pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
65 	writel(pin_reg, gpio_dev->base + offset * 4);
66 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
67 
68 	return 0;
69 }
70 
71 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
72 		int value)
73 {
74 	u32 pin_reg;
75 	unsigned long flags;
76 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
77 
78 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
79 	pin_reg = readl(gpio_dev->base + offset * 4);
80 	pin_reg |= BIT(OUTPUT_ENABLE_OFF);
81 	if (value)
82 		pin_reg |= BIT(OUTPUT_VALUE_OFF);
83 	else
84 		pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
85 	writel(pin_reg, gpio_dev->base + offset * 4);
86 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
87 
88 	return 0;
89 }
90 
91 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
92 {
93 	u32 pin_reg;
94 	unsigned long flags;
95 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
96 
97 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
98 	pin_reg = readl(gpio_dev->base + offset * 4);
99 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
100 
101 	return !!(pin_reg & BIT(PIN_STS_OFF));
102 }
103 
104 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
105 {
106 	u32 pin_reg;
107 	unsigned long flags;
108 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
109 
110 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
111 	pin_reg = readl(gpio_dev->base + offset * 4);
112 	if (value)
113 		pin_reg |= BIT(OUTPUT_VALUE_OFF);
114 	else
115 		pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
116 	writel(pin_reg, gpio_dev->base + offset * 4);
117 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
118 }
119 
120 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
121 		unsigned debounce)
122 {
123 	u32 time;
124 	u32 pin_reg;
125 	int ret = 0;
126 	unsigned long flags;
127 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
128 
129 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
130 	pin_reg = readl(gpio_dev->base + offset * 4);
131 
132 	if (debounce) {
133 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
134 		pin_reg &= ~DB_TMR_OUT_MASK;
135 		/*
136 		Debounce	Debounce	Timer	Max
137 		TmrLarge	TmrOutUnit	Unit	Debounce
138 							Time
139 		0	0	61 usec (2 RtcClk)	976 usec
140 		0	1	244 usec (8 RtcClk)	3.9 msec
141 		1	0	15.6 msec (512 RtcClk)	250 msec
142 		1	1	62.5 msec (2048 RtcClk)	1 sec
143 		*/
144 
145 		if (debounce < 61) {
146 			pin_reg |= 1;
147 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
148 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
149 		} else if (debounce < 976) {
150 			time = debounce / 61;
151 			pin_reg |= time & DB_TMR_OUT_MASK;
152 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
153 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
154 		} else if (debounce < 3900) {
155 			time = debounce / 244;
156 			pin_reg |= time & DB_TMR_OUT_MASK;
157 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
158 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
159 		} else if (debounce < 250000) {
160 			time = debounce / 15600;
161 			pin_reg |= time & DB_TMR_OUT_MASK;
162 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
163 			pin_reg |= BIT(DB_TMR_LARGE_OFF);
164 		} else if (debounce < 1000000) {
165 			time = debounce / 62500;
166 			pin_reg |= time & DB_TMR_OUT_MASK;
167 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
168 			pin_reg |= BIT(DB_TMR_LARGE_OFF);
169 		} else {
170 			pin_reg &= ~DB_CNTRl_MASK;
171 			ret = -EINVAL;
172 		}
173 	} else {
174 		pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
175 		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
176 		pin_reg &= ~DB_TMR_OUT_MASK;
177 		pin_reg &= ~DB_CNTRl_MASK;
178 	}
179 	writel(pin_reg, gpio_dev->base + offset * 4);
180 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
181 
182 	return ret;
183 }
184 
185 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
186 			       unsigned long config)
187 {
188 	u32 debounce;
189 
190 	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
191 		return -ENOTSUPP;
192 
193 	debounce = pinconf_to_config_argument(config);
194 	return amd_gpio_set_debounce(gc, offset, debounce);
195 }
196 
197 #ifdef CONFIG_DEBUG_FS
198 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
199 {
200 	u32 pin_reg;
201 	unsigned long flags;
202 	unsigned int bank, i, pin_num;
203 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
204 
205 	char *level_trig;
206 	char *active_level;
207 	char *interrupt_enable;
208 	char *interrupt_mask;
209 	char *wake_cntrl0;
210 	char *wake_cntrl1;
211 	char *wake_cntrl2;
212 	char *pin_sts;
213 	char *pull_up_sel;
214 	char *pull_up_enable;
215 	char *pull_down_enable;
216 	char *output_value;
217 	char *output_enable;
218 
219 	for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
220 		seq_printf(s, "GPIO bank%d\t", bank);
221 
222 		switch (bank) {
223 		case 0:
224 			i = 0;
225 			pin_num = AMD_GPIO_PINS_BANK0;
226 			break;
227 		case 1:
228 			i = 64;
229 			pin_num = AMD_GPIO_PINS_BANK1 + i;
230 			break;
231 		case 2:
232 			i = 128;
233 			pin_num = AMD_GPIO_PINS_BANK2 + i;
234 			break;
235 		case 3:
236 			i = 192;
237 			pin_num = AMD_GPIO_PINS_BANK3 + i;
238 			break;
239 		default:
240 			/* Illegal bank number, ignore */
241 			continue;
242 		}
243 		for (; i < pin_num; i++) {
244 			seq_printf(s, "pin%d\t", i);
245 			raw_spin_lock_irqsave(&gpio_dev->lock, flags);
246 			pin_reg = readl(gpio_dev->base + i * 4);
247 			raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
248 
249 			if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
250 				interrupt_enable = "interrupt is enabled|";
251 
252 				if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&
253 				    !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))
254 					active_level = "Active low|";
255 				else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) &&
256 					 !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))
257 					active_level = "Active high|";
258 				else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&
259 					 pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))
260 					active_level = "Active on both|";
261 				else
262 					active_level = "Unknown Active level|";
263 
264 				if (pin_reg & BIT(LEVEL_TRIG_OFF))
265 					level_trig = "Level trigger|";
266 				else
267 					level_trig = "Edge trigger|";
268 
269 			} else {
270 				interrupt_enable =
271 					"interrupt is disabled|";
272 				active_level = " ";
273 				level_trig = " ";
274 			}
275 
276 			if (pin_reg & BIT(INTERRUPT_MASK_OFF))
277 				interrupt_mask =
278 					"interrupt is unmasked|";
279 			else
280 				interrupt_mask =
281 					"interrupt is masked|";
282 
283 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
284 				wake_cntrl0 = "enable wakeup in S0i3 state|";
285 			else
286 				wake_cntrl0 = "disable wakeup in S0i3 state|";
287 
288 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
289 				wake_cntrl1 = "enable wakeup in S3 state|";
290 			else
291 				wake_cntrl1 = "disable wakeup in S3 state|";
292 
293 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
294 				wake_cntrl2 = "enable wakeup in S4/S5 state|";
295 			else
296 				wake_cntrl2 = "disable wakeup in S4/S5 state|";
297 
298 			if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
299 				pull_up_enable = "pull-up is enabled|";
300 				if (pin_reg & BIT(PULL_UP_SEL_OFF))
301 					pull_up_sel = "8k pull-up|";
302 				else
303 					pull_up_sel = "4k pull-up|";
304 			} else {
305 				pull_up_enable = "pull-up is disabled|";
306 				pull_up_sel = " ";
307 			}
308 
309 			if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
310 				pull_down_enable = "pull-down is enabled|";
311 			else
312 				pull_down_enable = "Pull-down is disabled|";
313 
314 			if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
315 				pin_sts = " ";
316 				output_enable = "output is enabled|";
317 				if (pin_reg & BIT(OUTPUT_VALUE_OFF))
318 					output_value = "output is high|";
319 				else
320 					output_value = "output is low|";
321 			} else {
322 				output_enable = "output is disabled|";
323 				output_value = " ";
324 
325 				if (pin_reg & BIT(PIN_STS_OFF))
326 					pin_sts = "input is high|";
327 				else
328 					pin_sts = "input is low|";
329 			}
330 
331 			seq_printf(s, "%s %s %s %s %s %s\n"
332 				" %s %s %s %s %s %s %s 0x%x\n",
333 				level_trig, active_level, interrupt_enable,
334 				interrupt_mask, wake_cntrl0, wake_cntrl1,
335 				wake_cntrl2, pin_sts, pull_up_sel,
336 				pull_up_enable, pull_down_enable,
337 				output_value, output_enable, pin_reg);
338 		}
339 	}
340 }
341 #else
342 #define amd_gpio_dbg_show NULL
343 #endif
344 
345 static void amd_gpio_irq_enable(struct irq_data *d)
346 {
347 	u32 pin_reg;
348 	unsigned long flags;
349 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
350 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
351 	u32 mask = BIT(INTERRUPT_ENABLE_OFF) | BIT(INTERRUPT_MASK_OFF);
352 
353 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
354 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
355 	pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
356 	pin_reg |= BIT(INTERRUPT_MASK_OFF);
357 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
358 	/*
359 	 * When debounce logic is enabled it takes ~900 us before interrupts
360 	 * can be enabled.  During this "debounce warm up" period the
361 	 * "INTERRUPT_ENABLE" bit will read as 0. Poll the bit here until it
362 	 * reads back as 1, signaling that interrupts are now enabled.
363 	 */
364 	while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
365 		continue;
366 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
367 }
368 
369 static void amd_gpio_irq_disable(struct irq_data *d)
370 {
371 	u32 pin_reg;
372 	unsigned long flags;
373 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
374 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
375 
376 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
377 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
378 	pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
379 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
380 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
381 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
382 }
383 
384 static void amd_gpio_irq_mask(struct irq_data *d)
385 {
386 	u32 pin_reg;
387 	unsigned long flags;
388 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
389 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
390 
391 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
392 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
393 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
394 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
395 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
396 }
397 
398 static void amd_gpio_irq_unmask(struct irq_data *d)
399 {
400 	u32 pin_reg;
401 	unsigned long flags;
402 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
403 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
404 
405 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
406 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
407 	pin_reg |= BIT(INTERRUPT_MASK_OFF);
408 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
409 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
410 }
411 
412 static void amd_gpio_irq_eoi(struct irq_data *d)
413 {
414 	u32 reg;
415 	unsigned long flags;
416 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
417 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
418 
419 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
420 	reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
421 	reg |= EOI_MASK;
422 	writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
423 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
424 }
425 
426 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
427 {
428 	int ret = 0;
429 	u32 pin_reg;
430 	unsigned long flags, irq_flags;
431 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
432 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
433 
434 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
435 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
436 
437 	/* Ignore the settings coming from the client and
438 	 * read the values from the ACPI tables
439 	 * while setting the trigger type
440 	 */
441 
442 	irq_flags = irq_get_trigger_type(d->irq);
443 	if (irq_flags != IRQ_TYPE_NONE)
444 		type = irq_flags;
445 
446 	switch (type & IRQ_TYPE_SENSE_MASK) {
447 	case IRQ_TYPE_EDGE_RISING:
448 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
449 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
450 		pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
451 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
452 		irq_set_handler_locked(d, handle_edge_irq);
453 		break;
454 
455 	case IRQ_TYPE_EDGE_FALLING:
456 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
457 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
458 		pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
459 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
460 		irq_set_handler_locked(d, handle_edge_irq);
461 		break;
462 
463 	case IRQ_TYPE_EDGE_BOTH:
464 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
465 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
466 		pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
467 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
468 		irq_set_handler_locked(d, handle_edge_irq);
469 		break;
470 
471 	case IRQ_TYPE_LEVEL_HIGH:
472 		pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
473 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
474 		pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
475 		pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
476 		pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
477 		irq_set_handler_locked(d, handle_level_irq);
478 		break;
479 
480 	case IRQ_TYPE_LEVEL_LOW:
481 		pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
482 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
483 		pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
484 		pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
485 		pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
486 		irq_set_handler_locked(d, handle_level_irq);
487 		break;
488 
489 	case IRQ_TYPE_NONE:
490 		break;
491 
492 	default:
493 		dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
494 		ret = -EINVAL;
495 	}
496 
497 	pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
498 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
499 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
500 
501 	return ret;
502 }
503 
504 static void amd_irq_ack(struct irq_data *d)
505 {
506 	/*
507 	 * based on HW design,there is no need to ack HW
508 	 * before handle current irq. But this routine is
509 	 * necessary for handle_edge_irq
510 	*/
511 }
512 
513 static struct irq_chip amd_gpio_irqchip = {
514 	.name         = "amd_gpio",
515 	.irq_ack      = amd_irq_ack,
516 	.irq_enable   = amd_gpio_irq_enable,
517 	.irq_disable  = amd_gpio_irq_disable,
518 	.irq_mask     = amd_gpio_irq_mask,
519 	.irq_unmask   = amd_gpio_irq_unmask,
520 	.irq_eoi      = amd_gpio_irq_eoi,
521 	.irq_set_type = amd_gpio_irq_set_type,
522 	.flags        = IRQCHIP_SKIP_SET_WAKE,
523 };
524 
525 #define PIN_IRQ_PENDING	(BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
526 
527 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
528 {
529 	struct amd_gpio *gpio_dev = dev_id;
530 	struct gpio_chip *gc = &gpio_dev->gc;
531 	irqreturn_t ret = IRQ_NONE;
532 	unsigned int i, irqnr;
533 	unsigned long flags;
534 	u32 *regs, regval;
535 	u64 status, mask;
536 
537 	/* Read the wake status */
538 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
539 	status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
540 	status <<= 32;
541 	status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
542 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
543 
544 	/* Bit 0-45 contain the relevant status bits */
545 	status &= (1ULL << 46) - 1;
546 	regs = gpio_dev->base;
547 	for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
548 		if (!(status & mask))
549 			continue;
550 		status &= ~mask;
551 
552 		/* Each status bit covers four pins */
553 		for (i = 0; i < 4; i++) {
554 			regval = readl(regs + i);
555 			if (!(regval & PIN_IRQ_PENDING))
556 				continue;
557 			irq = irq_find_mapping(gc->irq.domain, irqnr + i);
558 			generic_handle_irq(irq);
559 
560 			/* Clear interrupt.
561 			 * We must read the pin register again, in case the
562 			 * value was changed while executing
563 			 * generic_handle_irq() above.
564 			 */
565 			raw_spin_lock_irqsave(&gpio_dev->lock, flags);
566 			regval = readl(regs + i);
567 			writel(regval, regs + i);
568 			raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
569 			ret = IRQ_HANDLED;
570 		}
571 	}
572 
573 	/* Signal EOI to the GPIO unit */
574 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
575 	regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
576 	regval |= EOI_MASK;
577 	writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
578 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
579 
580 	return ret;
581 }
582 
583 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
584 {
585 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
586 
587 	return gpio_dev->ngroups;
588 }
589 
590 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
591 				      unsigned group)
592 {
593 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
594 
595 	return gpio_dev->groups[group].name;
596 }
597 
598 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
599 			      unsigned group,
600 			      const unsigned **pins,
601 			      unsigned *num_pins)
602 {
603 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
604 
605 	*pins = gpio_dev->groups[group].pins;
606 	*num_pins = gpio_dev->groups[group].npins;
607 	return 0;
608 }
609 
610 static const struct pinctrl_ops amd_pinctrl_ops = {
611 	.get_groups_count	= amd_get_groups_count,
612 	.get_group_name		= amd_get_group_name,
613 	.get_group_pins		= amd_get_group_pins,
614 #ifdef CONFIG_OF
615 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
616 	.dt_free_map		= pinctrl_utils_free_map,
617 #endif
618 };
619 
620 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
621 			  unsigned int pin,
622 			  unsigned long *config)
623 {
624 	u32 pin_reg;
625 	unsigned arg;
626 	unsigned long flags;
627 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
628 	enum pin_config_param param = pinconf_to_config_param(*config);
629 
630 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
631 	pin_reg = readl(gpio_dev->base + pin*4);
632 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
633 	switch (param) {
634 	case PIN_CONFIG_INPUT_DEBOUNCE:
635 		arg = pin_reg & DB_TMR_OUT_MASK;
636 		break;
637 
638 	case PIN_CONFIG_BIAS_PULL_DOWN:
639 		arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
640 		break;
641 
642 	case PIN_CONFIG_BIAS_PULL_UP:
643 		arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
644 		break;
645 
646 	case PIN_CONFIG_DRIVE_STRENGTH:
647 		arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
648 		break;
649 
650 	default:
651 		dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
652 			param);
653 		return -ENOTSUPP;
654 	}
655 
656 	*config = pinconf_to_config_packed(param, arg);
657 
658 	return 0;
659 }
660 
661 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
662 				unsigned long *configs, unsigned num_configs)
663 {
664 	int i;
665 	u32 arg;
666 	int ret = 0;
667 	u32 pin_reg;
668 	unsigned long flags;
669 	enum pin_config_param param;
670 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
671 
672 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
673 	for (i = 0; i < num_configs; i++) {
674 		param = pinconf_to_config_param(configs[i]);
675 		arg = pinconf_to_config_argument(configs[i]);
676 		pin_reg = readl(gpio_dev->base + pin*4);
677 
678 		switch (param) {
679 		case PIN_CONFIG_INPUT_DEBOUNCE:
680 			pin_reg &= ~DB_TMR_OUT_MASK;
681 			pin_reg |= arg & DB_TMR_OUT_MASK;
682 			break;
683 
684 		case PIN_CONFIG_BIAS_PULL_DOWN:
685 			pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
686 			pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
687 			break;
688 
689 		case PIN_CONFIG_BIAS_PULL_UP:
690 			pin_reg &= ~BIT(PULL_UP_SEL_OFF);
691 			pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
692 			pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
693 			pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
694 			break;
695 
696 		case PIN_CONFIG_DRIVE_STRENGTH:
697 			pin_reg &= ~(DRV_STRENGTH_SEL_MASK
698 					<< DRV_STRENGTH_SEL_OFF);
699 			pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
700 					<< DRV_STRENGTH_SEL_OFF;
701 			break;
702 
703 		default:
704 			dev_err(&gpio_dev->pdev->dev,
705 				"Invalid config param %04x\n", param);
706 			ret = -ENOTSUPP;
707 		}
708 
709 		writel(pin_reg, gpio_dev->base + pin*4);
710 	}
711 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
712 
713 	return ret;
714 }
715 
716 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
717 				unsigned int group,
718 				unsigned long *config)
719 {
720 	const unsigned *pins;
721 	unsigned npins;
722 	int ret;
723 
724 	ret = amd_get_group_pins(pctldev, group, &pins, &npins);
725 	if (ret)
726 		return ret;
727 
728 	if (amd_pinconf_get(pctldev, pins[0], config))
729 			return -ENOTSUPP;
730 
731 	return 0;
732 }
733 
734 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
735 				unsigned group, unsigned long *configs,
736 				unsigned num_configs)
737 {
738 	const unsigned *pins;
739 	unsigned npins;
740 	int i, ret;
741 
742 	ret = amd_get_group_pins(pctldev, group, &pins, &npins);
743 	if (ret)
744 		return ret;
745 	for (i = 0; i < npins; i++) {
746 		if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
747 			return -ENOTSUPP;
748 	}
749 	return 0;
750 }
751 
752 static const struct pinconf_ops amd_pinconf_ops = {
753 	.pin_config_get		= amd_pinconf_get,
754 	.pin_config_set		= amd_pinconf_set,
755 	.pin_config_group_get = amd_pinconf_group_get,
756 	.pin_config_group_set = amd_pinconf_group_set,
757 };
758 
759 #ifdef CONFIG_PM_SLEEP
760 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
761 {
762 	const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
763 
764 	if (!pd)
765 		return false;
766 
767 	/*
768 	 * Only restore the pin if it is actually in use by the kernel (or
769 	 * by userspace).
770 	 */
771 	if (pd->mux_owner || pd->gpio_owner ||
772 	    gpiochip_line_is_irq(&gpio_dev->gc, pin))
773 		return true;
774 
775 	return false;
776 }
777 
778 static int amd_gpio_suspend(struct device *dev)
779 {
780 	struct platform_device *pdev = to_platform_device(dev);
781 	struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
782 	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
783 	int i;
784 
785 	for (i = 0; i < desc->npins; i++) {
786 		int pin = desc->pins[i].number;
787 
788 		if (!amd_gpio_should_save(gpio_dev, pin))
789 			continue;
790 
791 		gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
792 	}
793 
794 	return 0;
795 }
796 
797 static int amd_gpio_resume(struct device *dev)
798 {
799 	struct platform_device *pdev = to_platform_device(dev);
800 	struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
801 	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
802 	int i;
803 
804 	for (i = 0; i < desc->npins; i++) {
805 		int pin = desc->pins[i].number;
806 
807 		if (!amd_gpio_should_save(gpio_dev, pin))
808 			continue;
809 
810 		writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
811 	}
812 
813 	return 0;
814 }
815 
816 static const struct dev_pm_ops amd_gpio_pm_ops = {
817 	SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
818 				     amd_gpio_resume)
819 };
820 #endif
821 
822 static struct pinctrl_desc amd_pinctrl_desc = {
823 	.pins	= kerncz_pins,
824 	.npins = ARRAY_SIZE(kerncz_pins),
825 	.pctlops = &amd_pinctrl_ops,
826 	.confops = &amd_pinconf_ops,
827 	.owner = THIS_MODULE,
828 };
829 
830 static int amd_gpio_probe(struct platform_device *pdev)
831 {
832 	int ret = 0;
833 	int irq_base;
834 	struct resource *res;
835 	struct amd_gpio *gpio_dev;
836 
837 	gpio_dev = devm_kzalloc(&pdev->dev,
838 				sizeof(struct amd_gpio), GFP_KERNEL);
839 	if (!gpio_dev)
840 		return -ENOMEM;
841 
842 	raw_spin_lock_init(&gpio_dev->lock);
843 
844 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
845 	if (!res) {
846 		dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
847 		return -EINVAL;
848 	}
849 
850 	gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
851 						resource_size(res));
852 	if (!gpio_dev->base)
853 		return -ENOMEM;
854 
855 	irq_base = platform_get_irq(pdev, 0);
856 	if (irq_base < 0) {
857 		dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base);
858 		return irq_base;
859 	}
860 
861 #ifdef CONFIG_PM_SLEEP
862 	gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
863 					    sizeof(*gpio_dev->saved_regs),
864 					    GFP_KERNEL);
865 	if (!gpio_dev->saved_regs)
866 		return -ENOMEM;
867 #endif
868 
869 	gpio_dev->pdev = pdev;
870 	gpio_dev->gc.get_direction	= amd_gpio_get_direction;
871 	gpio_dev->gc.direction_input	= amd_gpio_direction_input;
872 	gpio_dev->gc.direction_output	= amd_gpio_direction_output;
873 	gpio_dev->gc.get			= amd_gpio_get_value;
874 	gpio_dev->gc.set			= amd_gpio_set_value;
875 	gpio_dev->gc.set_config		= amd_gpio_set_config;
876 	gpio_dev->gc.dbg_show		= amd_gpio_dbg_show;
877 
878 	gpio_dev->gc.base		= -1;
879 	gpio_dev->gc.label			= pdev->name;
880 	gpio_dev->gc.owner			= THIS_MODULE;
881 	gpio_dev->gc.parent			= &pdev->dev;
882 	gpio_dev->gc.ngpio			= resource_size(res) / 4;
883 #if defined(CONFIG_OF_GPIO)
884 	gpio_dev->gc.of_node			= pdev->dev.of_node;
885 #endif
886 
887 	gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
888 	gpio_dev->groups = kerncz_groups;
889 	gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
890 
891 	amd_pinctrl_desc.name = dev_name(&pdev->dev);
892 	gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
893 						gpio_dev);
894 	if (IS_ERR(gpio_dev->pctrl)) {
895 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
896 		return PTR_ERR(gpio_dev->pctrl);
897 	}
898 
899 	ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
900 	if (ret)
901 		return ret;
902 
903 	ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
904 				0, 0, gpio_dev->gc.ngpio);
905 	if (ret) {
906 		dev_err(&pdev->dev, "Failed to add pin range\n");
907 		goto out2;
908 	}
909 
910 	ret = gpiochip_irqchip_add(&gpio_dev->gc,
911 				&amd_gpio_irqchip,
912 				0,
913 				handle_simple_irq,
914 				IRQ_TYPE_NONE);
915 	if (ret) {
916 		dev_err(&pdev->dev, "could not add irqchip\n");
917 		ret = -ENODEV;
918 		goto out2;
919 	}
920 
921 	ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0,
922 			       KBUILD_MODNAME, gpio_dev);
923 	if (ret)
924 		goto out2;
925 
926 	platform_set_drvdata(pdev, gpio_dev);
927 
928 	dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
929 	return ret;
930 
931 out2:
932 	gpiochip_remove(&gpio_dev->gc);
933 
934 	return ret;
935 }
936 
937 static int amd_gpio_remove(struct platform_device *pdev)
938 {
939 	struct amd_gpio *gpio_dev;
940 
941 	gpio_dev = platform_get_drvdata(pdev);
942 
943 	gpiochip_remove(&gpio_dev->gc);
944 
945 	return 0;
946 }
947 
948 static const struct acpi_device_id amd_gpio_acpi_match[] = {
949 	{ "AMD0030", 0 },
950 	{ "AMDI0030", 0},
951 	{ },
952 };
953 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
954 
955 static struct platform_driver amd_gpio_driver = {
956 	.driver		= {
957 		.name	= "amd_gpio",
958 		.acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
959 #ifdef CONFIG_PM_SLEEP
960 		.pm	= &amd_gpio_pm_ops,
961 #endif
962 	},
963 	.probe		= amd_gpio_probe,
964 	.remove		= amd_gpio_remove,
965 };
966 
967 module_platform_driver(amd_gpio_driver);
968 
969 MODULE_LICENSE("GPL v2");
970 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
971 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
972